1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L Pin Control and GPIO driver core
5 * Copyright (C) 2021 Renesas Electronics Corporation.
8 #include <linux/bitops.h>
10 #include <linux/gpio/driver.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/pinctrl/pinconf-generic.h>
15 #include <linux/pinctrl/pinconf.h>
16 #include <linux/pinctrl/pinctrl.h>
17 #include <linux/pinctrl/pinmux.h>
18 #include <linux/spinlock.h>
20 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
23 #include "../pinconf.h"
24 #include "../pinmux.h"
26 #define DRV_NAME "pinctrl-rzg2l"
29 * Use 16 lower bits [15:0] for pin identifier
30 * Use 16 higher bits [31:16] for pin mux function
32 #define MUX_PIN_ID_MASK GENMASK(15, 0)
33 #define MUX_FUNC_MASK GENMASK(31, 16)
34 #define MUX_FUNC_OFFS 16
35 #define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
37 /* PIN capabilities */
38 #define PIN_CFG_IOLH_A BIT(0)
39 #define PIN_CFG_IOLH_B BIT(1)
40 #define PIN_CFG_SR BIT(2)
41 #define PIN_CFG_IEN BIT(3)
42 #define PIN_CFG_PUPD BIT(4)
43 #define PIN_CFG_IO_VMC_SD0 BIT(5)
44 #define PIN_CFG_IO_VMC_SD1 BIT(6)
45 #define PIN_CFG_IO_VMC_QSPI BIT(7)
46 #define PIN_CFG_IO_VMC_ETH0 BIT(8)
47 #define PIN_CFG_IO_VMC_ETH1 BIT(9)
48 #define PIN_CFG_FILONOFF BIT(10)
49 #define PIN_CFG_FILNUM BIT(11)
50 #define PIN_CFG_FILCLKSEL BIT(12)
52 #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \
59 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
65 * n indicates number of pins in the port, a is the register index
66 * and f is pin configuration capabilities supported.
68 #define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f))
69 #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28)
70 #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20)
71 #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0))
74 * BIT(31) indicates dedicated pin, p is the register index while
75 * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits
76 * (b * 8) and f is the pin configuration capabilities supported.
78 #define RZG2L_SINGLE_PIN BIT(31)
79 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
80 ((p) << 24) | ((b) << 20) | (f))
81 #define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24)
82 #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20)
83 #define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0))
85 #define P(n) (0x0000 + 0x10 + (n))
86 #define PM(n) (0x0100 + 0x20 + (n) * 2)
87 #define PMC(n) (0x0200 + 0x10 + (n))
88 #define PFC(n) (0x0400 + 0x40 + (n) * 4)
89 #define PIN(n) (0x0800 + 0x10 + (n))
90 #define IOLH(n) (0x1000 + (n) * 8)
91 #define IEN(n) (0x1800 + (n) * 8)
93 #define SD_CH(n) (0x3000 + (n) * 4)
96 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
97 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
99 #define PWPR_B0WI BIT(7) /* Bit Write Disable */
100 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
103 #define PVDD_MASK 0x01
104 #define PFC_MASK 0x07
105 #define IEN_MASK 0x01
106 #define IOLH_MASK 0x03
109 #define PM_OUTPUT 0x2
111 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT)
112 #define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10)
113 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT)
115 struct rzg2l_dedicated_configs {
120 struct rzg2l_pinctrl_data {
121 const char * const *port_pins;
122 const u32 *port_pin_configs;
123 struct rzg2l_dedicated_configs *dedicated_pins;
124 unsigned int n_port_pins;
125 unsigned int n_dedicated_pins;
128 struct rzg2l_pinctrl {
129 struct pinctrl_dev *pctl;
130 struct pinctrl_desc desc;
131 struct pinctrl_pin_desc *pins;
133 const struct rzg2l_pinctrl_data *data;
138 struct gpio_chip gpio_chip;
139 struct pinctrl_gpio_range gpio_range;
144 static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 };
145 static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 };
147 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
148 u8 port, u8 pin, u8 func)
153 spin_lock_irqsave(&pctrl->lock, flags);
155 /* Set pin to 'Non-use (Hi-Z input protection)' */
156 reg = readw(pctrl->base + PM(port));
157 reg &= ~(PM_MASK << (pin * 2));
158 writew(reg, pctrl->base + PM(port));
160 /* Temporarily switch to GPIO mode with PMC register */
161 reg = readb(pctrl->base + PMC(port));
162 writeb(reg & ~BIT(pin), pctrl->base + PMC(port));
164 /* Set the PWPR register to allow PFC register to write */
165 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */
166 writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */
168 /* Select Pin function mode with PFC register */
169 reg = readl(pctrl->base + PFC(port));
170 reg &= ~(PFC_MASK << (pin * 4));
171 writel(reg | (func << (pin * 4)), pctrl->base + PFC(port));
173 /* Set the PWPR register to be write-protected */
174 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */
175 writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */
177 /* Switch to Peripheral pin function with PMC register */
178 reg = readb(pctrl->base + PMC(port));
179 writeb(reg | BIT(pin), pctrl->base + PMC(port));
181 spin_unlock_irqrestore(&pctrl->lock, flags);
184 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
185 unsigned int func_selector,
186 unsigned int group_selector)
188 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
189 struct function_desc *func;
190 unsigned int i, *psel_val;
191 struct group_desc *group;
194 func = pinmux_generic_get_function(pctldev, func_selector);
197 group = pinctrl_generic_get_group(pctldev, group_selector);
201 psel_val = func->data;
204 for (i = 0; i < group->num_pins; i++) {
205 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
206 RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]),
208 rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]),
209 RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]);
215 static int rzg2l_map_add_config(struct pinctrl_map *map,
216 const char *group_or_pin,
217 enum pinctrl_map_type type,
218 unsigned long *configs,
219 unsigned int num_configs)
223 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
229 map->data.configs.group_or_pin = group_or_pin;
230 map->data.configs.configs = cfgs;
231 map->data.configs.num_configs = num_configs;
236 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
237 struct device_node *np,
238 struct pinctrl_map **map,
239 unsigned int *num_maps,
242 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
243 struct pinctrl_map *maps = *map;
244 unsigned int nmaps = *num_maps;
245 unsigned long *configs = NULL;
246 unsigned int *pins, *psel_val;
247 unsigned int num_pinmux = 0;
248 unsigned int idx = *index;
249 unsigned int num_pins, i;
250 unsigned int num_configs;
251 struct property *pinmux;
252 struct property *prop;
257 pinmux = of_find_property(np, "pinmux", NULL);
259 num_pinmux = pinmux->length / sizeof(u32);
261 ret = of_property_count_strings(np, "pins");
262 if (ret == -EINVAL) {
264 } else if (ret < 0) {
265 dev_err(pctrl->dev, "Invalid pins list in DT\n");
271 if (!num_pinmux && !num_pins)
274 if (num_pinmux && num_pins) {
276 "DT node must contain either a pinmux or pins and not both\n");
280 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
284 if (num_pins && !num_configs) {
285 dev_err(pctrl->dev, "DT node must contain a config\n");
296 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);
305 of_property_for_each_string(np, "pins", prop, pin) {
306 ret = rzg2l_map_add_config(&maps[idx], pin,
307 PIN_MAP_TYPE_CONFIGS_PIN,
308 configs, num_configs);
318 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
319 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
321 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
322 if (!pins || !psel_val || !pin_fn) {
327 /* Collect pin locations and mux settings from DT properties */
328 for (i = 0; i < num_pinmux; ++i) {
331 ret = of_property_read_u32_index(np, "pinmux", i, &value);
334 pins[i] = value & MUX_PIN_ID_MASK;
335 psel_val[i] = MUX_FUNC(value);
338 /* Register a single pin group listing all the pins we read from DT */
339 gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
346 * Register a single group function where the 'data' is an array PSEL
347 * register values read from DT.
349 pin_fn[0] = np->name;
350 fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
357 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
358 maps[idx].data.mux.group = np->name;
359 maps[idx].data.mux.function = np->name;
362 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
367 pinctrl_generic_remove_group(pctldev, gsel);
374 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev,
375 struct pinctrl_map *map,
376 unsigned int num_maps)
383 for (i = 0; i < num_maps; ++i) {
384 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
385 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
386 kfree(map[i].data.configs.configs);
391 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
392 struct device_node *np,
393 struct pinctrl_map **map,
394 unsigned int *num_maps)
396 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
397 struct device_node *child;
405 for_each_child_of_node(np, child) {
406 ret = rzg2l_dt_subnode_to_map(pctldev, child, map,
414 if (*num_maps == 0) {
415 ret = rzg2l_dt_subnode_to_map(pctldev, np, map,
424 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
429 rzg2l_dt_free_map(pctldev, *map, *num_maps);
434 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
435 u32 cfg, u32 port, u8 bit)
437 u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg);
438 u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg);
441 if (bit >= pincount || port >= pctrl->data->n_port_pins)
444 data = pctrl->data->port_pin_configs[port];
445 if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data))
451 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
454 void __iomem *addr = pctrl->base + offset;
456 /* handle _L/_H for 32-bit register read/write */
462 return (readl(addr) >> (bit * 8)) & mask;
465 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
466 u8 bit, u32 mask, u32 val)
468 void __iomem *addr = pctrl->base + offset;
472 /* handle _L/_H for 32-bit register read/write */
478 spin_lock_irqsave(&pctrl->lock, flags);
479 reg = readl(addr) & ~(mask << (bit * 8));
480 writel(reg | (val << (bit * 8)), addr);
481 spin_unlock_irqrestore(&pctrl->lock, flags);
484 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
486 unsigned long *config)
488 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
489 enum pin_config_param param = pinconf_to_config_param(*config);
490 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
491 unsigned int *pin_data = pin->drv_data;
492 unsigned int arg = 0;
502 if (*pin_data & RZG2L_SINGLE_PIN) {
503 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);
504 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
505 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
507 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);
508 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
509 bit = RZG2L_PIN_ID_TO_PIN(_pin);
511 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
516 case PIN_CONFIG_INPUT_ENABLE:
517 if (!(cfg & PIN_CFG_IEN))
519 arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK);
522 case PIN_CONFIG_POWER_SOURCE: {
525 if (cfg & PIN_CFG_IO_VMC_SD0)
527 else if (cfg & PIN_CFG_IO_VMC_SD1)
529 else if (cfg & PIN_CFG_IO_VMC_QSPI)
534 spin_lock_irqsave(&pctrl->lock, flags);
535 addr = pctrl->base + pwr_reg;
536 arg = (readl(addr) & PVDD_MASK) ? 1800 : 3300;
537 spin_unlock_irqrestore(&pctrl->lock, flags);
541 case PIN_CONFIG_DRIVE_STRENGTH: {
544 if (!(cfg & PIN_CFG_IOLH_A))
547 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK);
548 arg = iolh_groupa_mA[index];
552 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
555 if (!(cfg & PIN_CFG_IOLH_B))
558 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK);
559 arg = iolh_groupb_oi[index];
567 *config = pinconf_to_config_packed(param, arg);
572 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
574 unsigned long *_configs,
575 unsigned int num_configs)
577 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
578 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
579 unsigned int *pin_data = pin->drv_data;
580 enum pin_config_param param;
591 if (*pin_data & RZG2L_SINGLE_PIN) {
592 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);
593 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
594 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
596 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);
597 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
598 bit = RZG2L_PIN_ID_TO_PIN(_pin);
600 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
604 for (i = 0; i < num_configs; i++) {
605 param = pinconf_to_config_param(_configs[i]);
607 case PIN_CONFIG_INPUT_ENABLE: {
609 pinconf_to_config_argument(_configs[i]);
611 if (!(cfg & PIN_CFG_IEN))
614 rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg);
618 case PIN_CONFIG_POWER_SOURCE: {
619 unsigned int mV = pinconf_to_config_argument(_configs[i]);
622 if (mV != 1800 && mV != 3300)
625 if (cfg & PIN_CFG_IO_VMC_SD0)
627 else if (cfg & PIN_CFG_IO_VMC_SD1)
629 else if (cfg & PIN_CFG_IO_VMC_QSPI)
634 addr = pctrl->base + pwr_reg;
635 spin_lock_irqsave(&pctrl->lock, flags);
636 writel((mV == 1800) ? PVDD_1800 : PVDD_3300, addr);
637 spin_unlock_irqrestore(&pctrl->lock, flags);
641 case PIN_CONFIG_DRIVE_STRENGTH: {
642 unsigned int arg = pinconf_to_config_argument(_configs[i]);
645 if (!(cfg & PIN_CFG_IOLH_A))
648 for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) {
649 if (arg == iolh_groupa_mA[index])
652 if (index >= ARRAY_SIZE(iolh_groupa_mA))
655 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index);
659 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
660 unsigned int arg = pinconf_to_config_argument(_configs[i]);
663 if (!(cfg & PIN_CFG_IOLH_B))
666 for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) {
667 if (arg == iolh_groupb_oi[index])
670 if (index >= ARRAY_SIZE(iolh_groupb_oi))
673 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index);
685 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
687 unsigned long *configs,
688 unsigned int num_configs)
690 const unsigned int *pins;
691 unsigned int i, npins;
694 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
698 for (i = 0; i < npins; i++) {
699 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs,
708 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
710 unsigned long *config)
712 const unsigned int *pins;
713 unsigned int i, npins, prev_config = 0;
716 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
720 for (i = 0; i < npins; i++) {
721 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config);
725 /* Check config matching between to pin */
726 if (i && prev_config != *config)
729 prev_config = *config;
735 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = {
736 .get_groups_count = pinctrl_generic_get_group_count,
737 .get_group_name = pinctrl_generic_get_group_name,
738 .get_group_pins = pinctrl_generic_get_group_pins,
739 .dt_node_to_map = rzg2l_dt_node_to_map,
740 .dt_free_map = rzg2l_dt_free_map,
743 static const struct pinmux_ops rzg2l_pinctrl_pmxops = {
744 .get_functions_count = pinmux_generic_get_function_count,
745 .get_function_name = pinmux_generic_get_function_name,
746 .get_function_groups = pinmux_generic_get_function_groups,
747 .set_mux = rzg2l_pinctrl_set_mux,
751 static const struct pinconf_ops rzg2l_pinctrl_confops = {
753 .pin_config_get = rzg2l_pinctrl_pinconf_get,
754 .pin_config_set = rzg2l_pinctrl_pinconf_set,
755 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set,
756 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get,
757 .pin_config_config_dbg_show = pinconf_generic_dump_config,
760 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
762 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
763 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
764 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
769 ret = pinctrl_gpio_request(chip->base + offset);
773 spin_lock_irqsave(&pctrl->lock, flags);
775 /* Select GPIO mode in PMC Register */
776 reg8 = readb(pctrl->base + PMC(port));
778 writeb(reg8, pctrl->base + PMC(port));
780 spin_unlock_irqrestore(&pctrl->lock, flags);
785 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port,
791 spin_lock_irqsave(&pctrl->lock, flags);
793 reg16 = readw(pctrl->base + PM(port));
794 reg16 &= ~(PM_MASK << (bit * 2));
796 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2);
797 writew(reg16, pctrl->base + PM(port));
799 spin_unlock_irqrestore(&pctrl->lock, flags);
802 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
804 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
805 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
806 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
808 if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) {
811 reg16 = readw(pctrl->base + PM(port));
812 reg16 = (reg16 >> (bit * 2)) & PM_MASK;
813 if (reg16 == PM_OUTPUT)
814 return GPIO_LINE_DIRECTION_OUT;
817 return GPIO_LINE_DIRECTION_IN;
820 static int rzg2l_gpio_direction_input(struct gpio_chip *chip,
823 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
824 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
825 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
827 rzg2l_gpio_set_direction(pctrl, port, bit, false);
832 static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
835 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
836 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
837 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
841 spin_lock_irqsave(&pctrl->lock, flags);
843 reg8 = readb(pctrl->base + P(port));
846 writeb(reg8 | BIT(bit), pctrl->base + P(port));
848 writeb(reg8 & ~BIT(bit), pctrl->base + P(port));
850 spin_unlock_irqrestore(&pctrl->lock, flags);
853 static int rzg2l_gpio_direction_output(struct gpio_chip *chip,
854 unsigned int offset, int value)
856 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
857 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
858 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
860 rzg2l_gpio_set(chip, offset, value);
861 rzg2l_gpio_set_direction(pctrl, port, bit, true);
866 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)
868 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
869 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
870 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
873 reg16 = readw(pctrl->base + PM(port));
874 reg16 = (reg16 >> (bit * 2)) & PM_MASK;
876 if (reg16 == PM_INPUT)
877 return !!(readb(pctrl->base + PIN(port)) & BIT(bit));
878 else if (reg16 == PM_OUTPUT)
879 return !!(readb(pctrl->base + P(port)) & BIT(bit));
884 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
886 pinctrl_gpio_free(chip->base + offset);
889 * Set the GPIO as an input to ensure that the next GPIO request won't
890 * drive the GPIO pin as an output.
892 rzg2l_gpio_direction_input(chip, offset);
895 static const char * const rzg2l_gpio_names[] = {
896 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
897 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
898 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
899 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
900 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
901 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
902 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
903 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
904 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
905 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
906 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
907 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
908 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
909 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
910 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
911 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
912 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
913 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
914 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
915 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
916 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
917 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
918 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7",
919 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7",
920 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7",
921 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7",
922 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7",
923 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7",
924 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7",
925 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7",
926 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7",
927 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7",
928 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7",
929 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7",
930 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7",
931 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",
932 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7",
933 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7",
934 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7",
935 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7",
936 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7",
937 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7",
938 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7",
939 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7",
940 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7",
941 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7",
942 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7",
943 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7",
944 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",
947 static const u32 rzg2l_gpio_configs[] = {
948 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
949 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
950 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
951 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS),
952 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS),
953 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS),
954 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS),
955 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS),
956 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS),
957 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS),
958 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
959 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
960 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
961 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
962 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
963 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
964 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
965 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
966 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
967 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
968 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
969 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
970 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
971 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
972 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
973 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
974 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
975 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
976 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
977 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
978 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
979 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
980 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
981 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
982 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
983 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
984 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
985 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
986 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
987 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
988 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
989 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS),
990 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
991 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
992 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
993 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
994 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
995 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
996 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
999 static const u32 r9a07g043_gpio_configs[] = {
1000 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
1001 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1002 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1003 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1004 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1005 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
1006 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
1007 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1008 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1009 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1010 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1011 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
1012 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
1013 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
1014 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
1015 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
1016 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
1017 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
1018 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
1022 struct rzg2l_dedicated_configs common[35];
1023 struct rzg2l_dedicated_configs rzg2l_pins[7];
1024 } rzg2l_dedicated_pins = {
1026 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
1027 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
1028 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
1029 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
1030 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
1031 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
1032 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
1033 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
1034 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
1035 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
1036 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
1037 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1038 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
1039 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
1040 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
1041 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1042 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
1043 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1044 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
1045 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1046 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
1047 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1048 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
1049 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1050 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
1051 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1052 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
1053 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1054 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
1055 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
1056 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
1057 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
1058 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
1059 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1060 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
1061 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1062 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
1063 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1064 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
1065 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1066 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
1067 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
1068 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
1069 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1070 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
1071 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1072 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
1073 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1074 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
1075 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1076 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
1077 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1078 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
1079 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1080 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
1081 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1082 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
1083 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1084 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
1085 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
1086 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
1087 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
1088 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
1091 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1092 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
1093 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1094 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
1095 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1096 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
1097 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1098 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
1099 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1100 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
1101 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1102 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
1103 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
1107 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
1109 struct device_node *np = pctrl->dev->of_node;
1110 struct gpio_chip *chip = &pctrl->gpio_chip;
1111 const char *name = dev_name(pctrl->dev);
1112 struct of_phandle_args of_args;
1115 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
1117 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
1121 if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
1122 of_args.args[2] != pctrl->data->n_port_pins) {
1123 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
1127 chip->names = pctrl->data->port_pins;
1128 chip->request = rzg2l_gpio_request;
1129 chip->free = rzg2l_gpio_free;
1130 chip->get_direction = rzg2l_gpio_get_direction;
1131 chip->direction_input = rzg2l_gpio_direction_input;
1132 chip->direction_output = rzg2l_gpio_direction_output;
1133 chip->get = rzg2l_gpio_get;
1134 chip->set = rzg2l_gpio_set;
1136 chip->parent = pctrl->dev;
1137 chip->owner = THIS_MODULE;
1139 chip->ngpio = of_args.args[2];
1141 pctrl->gpio_range.id = 0;
1142 pctrl->gpio_range.pin_base = 0;
1143 pctrl->gpio_range.base = 0;
1144 pctrl->gpio_range.npins = chip->ngpio;
1145 pctrl->gpio_range.name = chip->label;
1146 pctrl->gpio_range.gc = chip;
1147 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1149 dev_err(pctrl->dev, "failed to add GPIO controller\n");
1153 dev_dbg(pctrl->dev, "Registered gpio controller\n");
1158 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
1160 struct pinctrl_pin_desc *pins;
1165 pctrl->desc.name = DRV_NAME;
1166 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
1167 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops;
1168 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops;
1169 pctrl->desc.confops = &rzg2l_pinctrl_confops;
1170 pctrl->desc.owner = THIS_MODULE;
1172 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
1176 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,
1177 sizeof(*pin_data), GFP_KERNEL);
1182 pctrl->desc.pins = pins;
1184 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
1186 pins[i].name = pctrl->data->port_pins[i];
1187 if (i && !(i % RZG2L_PINS_PER_PORT))
1189 pin_data[i] = pctrl->data->port_pin_configs[j];
1190 pins[i].drv_data = &pin_data[i];
1193 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
1194 unsigned int index = pctrl->data->n_port_pins + i;
1196 pins[index].number = index;
1197 pins[index].name = pctrl->data->dedicated_pins[i].name;
1198 pin_data[index] = pctrl->data->dedicated_pins[i].config;
1199 pins[index].drv_data = &pin_data[index];
1202 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
1205 dev_err(pctrl->dev, "pinctrl registration failed\n");
1209 ret = pinctrl_enable(pctrl->pctl);
1211 dev_err(pctrl->dev, "pinctrl enable failed\n");
1215 ret = rzg2l_gpio_register(pctrl);
1217 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
1224 static void rzg2l_pinctrl_clk_disable(void *data)
1226 clk_disable_unprepare(data);
1229 static int rzg2l_pinctrl_probe(struct platform_device *pdev)
1231 struct rzg2l_pinctrl *pctrl;
1234 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1238 pctrl->dev = &pdev->dev;
1240 pctrl->data = of_device_get_match_data(&pdev->dev);
1244 pctrl->base = devm_platform_ioremap_resource(pdev, 0);
1245 if (IS_ERR(pctrl->base))
1246 return PTR_ERR(pctrl->base);
1248 pctrl->clk = devm_clk_get(pctrl->dev, NULL);
1249 if (IS_ERR(pctrl->clk)) {
1250 ret = PTR_ERR(pctrl->clk);
1251 dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret);
1255 spin_lock_init(&pctrl->lock);
1257 platform_set_drvdata(pdev, pctrl);
1259 ret = clk_prepare_enable(pctrl->clk);
1261 dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret);
1265 ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable,
1269 "failed to register GPIO clk disable action, %i\n",
1274 ret = rzg2l_pinctrl_register(pctrl);
1278 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);
1282 static struct rzg2l_pinctrl_data r9a07g043_data = {
1283 .port_pins = rzg2l_gpio_names,
1284 .port_pin_configs = r9a07g043_gpio_configs,
1285 .dedicated_pins = rzg2l_dedicated_pins.common,
1286 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
1287 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
1290 static struct rzg2l_pinctrl_data r9a07g044_data = {
1291 .port_pins = rzg2l_gpio_names,
1292 .port_pin_configs = rzg2l_gpio_configs,
1293 .dedicated_pins = rzg2l_dedicated_pins.common,
1294 .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names),
1295 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
1296 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
1299 static const struct of_device_id rzg2l_pinctrl_of_table[] = {
1301 .compatible = "renesas,r9a07g043-pinctrl",
1302 .data = &r9a07g043_data,
1305 .compatible = "renesas,r9a07g044-pinctrl",
1306 .data = &r9a07g044_data,
1311 static struct platform_driver rzg2l_pinctrl_driver = {
1314 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table),
1316 .probe = rzg2l_pinctrl_probe,
1319 static int __init rzg2l_pinctrl_init(void)
1321 return platform_driver_register(&rzg2l_pinctrl_driver);
1323 core_initcall(rzg2l_pinctrl_init);
1325 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
1326 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");
1327 MODULE_LICENSE("GPL v2");