drivers/pinctrl/renesas/pfc-sh73a0.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * sh73a0 processor support - PFC hardware block
   4  *
   5  * Copyright (C) 2010 Renesas Solutions Corp.
   6  * Copyright (C) 2010 NISHIMOTO Hiroki
   7  */
   8 #include <linux/io.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/pinctrl/pinconf-generic.h>
  12 #include <linux/regulator/driver.h>
  13 #include <linux/regulator/machine.h>
  14 #include <linux/slab.h>
  15
  16 #include "sh_pfc.h"
  17
  18 #define CPU_ALL_PORT(fn, pfx, sfx)                                      \
  19         PORT_10(0,  fn, pfx, sfx), PORT_90(0, fn, pfx, sfx),            \
  20         PORT_10(100, fn, pfx##10, sfx),                                 \
  21         PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
  22         PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
  23         PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
  24         PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \
  25         PORT_1(118, fn, pfx##118, sfx),                                 \
  26         PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
  27         PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \
  28         PORT_10(150, fn, pfx##15, sfx),                                 \
  29         PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \
  30         PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \
  31         PORT_1(164, fn, pfx##164, sfx),                                 \
  32         PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
  33         PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
  34         PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
  35         PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
  36         PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \
  37         PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \
  38         PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \
  39         PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \
  40         PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
  41         PORT_1(282, fn, pfx##282, sfx),                                 \
  42         PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
  43         PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
  44
  45 #define CPU_ALL_NOGP(fn)        \
  46         PIN_NOGP(A11, "F26", fn)
  47
  48 enum {
  49         PINMUX_RESERVED = 0,
  50
  51         PINMUX_DATA_BEGIN,
  52         PORT_ALL(DATA),                 /* PORT0_DATA -> PORT309_DATA */
  53         PINMUX_DATA_END,
  54
  55         PINMUX_INPUT_BEGIN,
  56         PORT_ALL(IN),                   /* PORT0_IN -> PORT309_IN */
  57         PINMUX_INPUT_END,
  58
  59         PINMUX_OUTPUT_BEGIN,
  60         PORT_ALL(OUT),                  /* PORT0_OUT -> PORT309_OUT */
  61         PINMUX_OUTPUT_END,
  62
  63         PINMUX_FUNCTION_BEGIN,
  64         PORT_ALL(FN_IN),                /* PORT0_FN_IN -> PORT309_FN_IN */
  65         PORT_ALL(FN_OUT),               /* PORT0_FN_OUT -> PORT309_FN_OUT */
  66         PORT_ALL(FN0),                  /* PORT0_FN0 -> PORT309_FN0 */
  67         PORT_ALL(FN1),                  /* PORT0_FN1 -> PORT309_FN1 */
  68         PORT_ALL(FN2),                  /* PORT0_FN2 -> PORT309_FN2 */
  69         PORT_ALL(FN3),                  /* PORT0_FN3 -> PORT309_FN3 */
  70         PORT_ALL(FN4),                  /* PORT0_FN4 -> PORT309_FN4 */
  71         PORT_ALL(FN5),                  /* PORT0_FN5 -> PORT309_FN5 */
  72         PORT_ALL(FN6),                  /* PORT0_FN6 -> PORT309_FN6 */
  73         PORT_ALL(FN7),                  /* PORT0_FN7 -> PORT309_FN7 */
  74
  75         MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
  76         MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
  77         MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
  78         MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
  79         MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
  80         MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
  81         MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
  82         MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
  83         MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
  84         MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
  85         MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
  86         MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
  87         MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
  88         MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
  89         MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
  90         MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
  91         MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
  92         MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
  93         MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
  94         MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
  95         MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
  96         MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
  97         MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
  98         MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
  99         MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
 100         MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
 101         MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
 102         MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
 103         MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
 104         MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
 105         MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
 106         MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
 107         MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
 108         MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
 109         MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
 110         MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
 111         MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
 112         MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
 113         MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
 114         MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
 115         MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
 116         MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
 117         PINMUX_FUNCTION_END,
 118
 119         PINMUX_MARK_BEGIN,
 120         /* Hardware manual Table 25-1 (Function 0-7) */
 121         VBUS_0_MARK,
 122         GPI0_MARK,
 123         GPI1_MARK,
 124         GPI2_MARK,
 125         GPI3_MARK,
 126         GPI4_MARK,
 127         GPI5_MARK,
 128         GPI6_MARK,
 129         GPI7_MARK,
 130         SCIFA7_RXD_MARK,
 131         SCIFA7_CTS__MARK,
 132         GPO7_MARK, MFG0_OUT2_MARK,
 133         GPO6_MARK, MFG1_OUT2_MARK,
 134         GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
 135         SCIFA0_TXD_MARK,
 136         SCIFA7_TXD_MARK,
 137         SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
 138         GPO0_MARK,
 139         GPO1_MARK,
 140         GPO2_MARK, STATUS0_MARK,
 141         GPO3_MARK, STATUS1_MARK,
 142         GPO4_MARK, STATUS2_MARK,
 143         VINT_MARK,
 144         TCKON_MARK,
 145         XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
 146         MFG0_OUT1_MARK, PORT27_IROUT_MARK,
 147         XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
 148         PORT28_TPU1TO1_MARK,
 149         SIM_RST_MARK, PORT29_TPU1TO1_MARK,
 150         SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
 151         SIM_D_MARK, PORT31_IROUT_MARK,
 152         SCIFA4_TXD_MARK,
 153         SCIFA4_RXD_MARK, XWUP_MARK,
 154         SCIFA4_RTS__MARK,
 155         SCIFA4_CTS__MARK,
 156         FSIBOBT_MARK, FSIBIBT_MARK,
 157         FSIBOLR_MARK, FSIBILR_MARK,
 158         FSIBOSLD_MARK,
 159         FSIBISLD_MARK,
 160         VACK_MARK,
 161         XTAL1L_MARK,
 162         SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
 163         SCIFA0_RXD_MARK,
 164         SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
 165         FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
 166         FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
 167         FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
 168         FSICISLD_MARK, FSIDISLD_MARK,
 169         FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
 170         FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
 171
 172         FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
 173         FSIAOSLD_MARK, BBIF2_TXD2_MARK,
 174         FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
 175         PORT53_FSICSPDIF_MARK,
 176         FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
 177         FSICCK_MARK, FSICOMC_MARK,
 178         FSIAISLD_MARK, TPU0TO0_MARK,
 179         A0_MARK, BS__MARK,
 180         A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
 181         A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
 182         A14_MARK, KEYOUT5_MARK,
 183         A15_MARK, KEYOUT4_MARK,
 184         A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
 185         A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
 186         A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
 187         A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
 188         A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
 189         A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
 190         A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
 191         A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
 192         A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
 193         A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
 194         A26_MARK, KEYIN6_MARK,
 195         KEYIN7_MARK,
 196         D0_NAF0_MARK,
 197         D1_NAF1_MARK,
 198         D2_NAF2_MARK,
 199         D3_NAF3_MARK,
 200         D4_NAF4_MARK,
 201         D5_NAF5_MARK,
 202         D6_NAF6_MARK,
 203         D7_NAF7_MARK,
 204         D8_NAF8_MARK,
 205         D9_NAF9_MARK,
 206         D10_NAF10_MARK,
 207         D11_NAF11_MARK,
 208         D12_NAF12_MARK,
 209         D13_NAF13_MARK,
 210         D14_NAF14_MARK,
 211         D15_NAF15_MARK,
 212         CS4__MARK,
 213         CS5A__MARK, PORT91_RDWR_MARK,
 214         CS5B__MARK, FCE1__MARK,
 215         CS6B__MARK, DACK0_MARK,
 216         FCE0__MARK, CS6A__MARK,
 217         WAIT__MARK, DREQ0_MARK,
 218         RD__FSC_MARK,
 219         WE0__FWE_MARK, RDWR_FWE_MARK,
 220         WE1__MARK,
 221         FRB_MARK,
 222         CKO_MARK,
 223         NBRSTOUT__MARK,
 224         NBRST__MARK,
 225         BBIF2_TXD_MARK,
 226         BBIF2_RXD_MARK,
 227         BBIF2_SYNC_MARK,
 228         BBIF2_SCK_MARK,
 229         SCIFA3_CTS__MARK, MFG3_IN2_MARK,
 230         SCIFA3_RXD_MARK, MFG3_IN1_MARK,
 231         BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
 232         SCIFA3_TXD_MARK,
 233         HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
 234         HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
 235         HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
 236         HSI_TX_READY_MARK, BBIF1_TXD_MARK,
 237         HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
 238         PORT115_I2C_SCL3_MARK,
 239         HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
 240         PORT116_I2C_SDA3_MARK,
 241         HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
 242         HSI_TX_FLAG_MARK,
 243         VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
 244
 245         VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
 246         VIO2_HD_MARK, LCD2D1_MARK,
 247         VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
 248         VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
 249         PORT131_KEYOUT11_MARK, LCD2D11_MARK,
 250         VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
 251         PORT132_KEYOUT10_MARK, LCD2D12_MARK,
 252         VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
 253         VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
 254         VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
 255         VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
 256         VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
 257         VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
 258         VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
 259         VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
 260         VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
 261         VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
 262         VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
 263         VIO2_D5_MARK, LCD2D3_MARK,
 264         VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
 265         VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
 266         PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
 267         VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
 268         LCD2D18_MARK,
 269         VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
 270         VIO_CKO_MARK,
 271         A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
 272         MFG0_IN2_MARK,
 273         TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
 274         TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
 275         TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
 276         SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
 277         SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
 278         SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
 279         SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
 280         DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
 281         PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
 282         PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
 283         PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
 284         PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
 285         PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
 286         LCDD0_MARK,
 287         LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
 288         LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
 289         LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
 290         LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
 291         LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
 292         LCDD6_MARK,
 293         LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
 294         LCDD8_MARK, D16_MARK,
 295         LCDD9_MARK, D17_MARK,
 296         LCDD10_MARK, D18_MARK,
 297         LCDD11_MARK, D19_MARK,
 298         LCDD12_MARK, D20_MARK,
 299         LCDD13_MARK, D21_MARK,
 300         LCDD14_MARK, D22_MARK,
 301         LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
 302         LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
 303         LCDD17_MARK, D25_MARK,
 304         LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
 305         LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
 306         LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
 307         LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
 308         LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
 309         LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
 310         LCDDCK_MARK, LCDWR__MARK,
 311         LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
 312         VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
 313         LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
 314         PORT218_VIO_CKOR_MARK,
 315         LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
 316         MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
 317         LCDVSYN_MARK, LCDVSYN2_MARK,
 318         LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
 319         MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
 320         LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
 321         VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
 322
 323         SCIFA1_TXD_MARK, OVCN2_MARK,
 324         EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
 325         SCIFA1_RTS__MARK, IDIN_MARK,
 326         SCIFA1_RXD_MARK,
 327         SCIFA1_CTS__MARK, MFG1_IN1_MARK,
 328         MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
 329         MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
 330         MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
 331         MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
 332         MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
 333         MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
 334         MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
 335         MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
 336         MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
 337         MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
 338         SCIFA6_TXD_MARK,
 339         PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
 340         PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
 341         PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
 342         PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
 343         MSIOF2R_RXD_MARK,
 344         PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
 345         MSIOF2R_TXD_MARK,
 346         PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
 347         TPU1TO0_MARK,
 348         PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
 349         TPU3TO1_MARK,
 350         PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
 351         TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
 352         PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
 353         MSIOF2R_TSYNC_MARK,
 354         SDHICLK0_MARK,
 355         SDHICD0_MARK,
 356         SDHID0_0_MARK,
 357         SDHID0_1_MARK,
 358         SDHID0_2_MARK,
 359         SDHID0_3_MARK,
 360         SDHICMD0_MARK,
 361         SDHIWP0_MARK,
 362         SDHICLK1_MARK,
 363         SDHID1_0_MARK, TS_SPSYNC2_MARK,
 364         SDHID1_1_MARK, TS_SDAT2_MARK,
 365         SDHID1_2_MARK, TS_SDEN2_MARK,
 366         SDHID1_3_MARK, TS_SCK2_MARK,
 367         SDHICMD1_MARK,
 368         SDHICLK2_MARK,
 369         SDHID2_0_MARK, TS_SPSYNC4_MARK,
 370         SDHID2_1_MARK, TS_SDAT4_MARK,
 371         SDHID2_2_MARK, TS_SDEN4_MARK,
 372         SDHID2_3_MARK, TS_SCK4_MARK,
 373         SDHICMD2_MARK,
 374         MMCCLK0_MARK,
 375         MMCD0_0_MARK,
 376         MMCD0_1_MARK,
 377         MMCD0_2_MARK,
 378         MMCD0_3_MARK,
 379         MMCD0_4_MARK, TS_SPSYNC5_MARK,
 380         MMCD0_5_MARK, TS_SDAT5_MARK,
 381         MMCD0_6_MARK, TS_SDEN5_MARK,
 382         MMCD0_7_MARK, TS_SCK5_MARK,
 383         MMCCMD0_MARK,
 384         RESETOUTS__MARK, EXTAL2OUT_MARK,
 385         MCP_WAIT__MCP_FRB_MARK,
 386         MCP_CKO_MARK, MMCCLK1_MARK,
 387         MCP_D15_MCP_NAF15_MARK,
 388         MCP_D14_MCP_NAF14_MARK,
 389         MCP_D13_MCP_NAF13_MARK,
 390         MCP_D12_MCP_NAF12_MARK,
 391         MCP_D11_MCP_NAF11_MARK,
 392         MCP_D10_MCP_NAF10_MARK,
 393         MCP_D9_MCP_NAF9_MARK,
 394         MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
 395         MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
 396
 397         MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
 398         MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
 399         MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
 400         MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
 401         MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
 402         MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
 403         MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
 404         MCP_NBRSTOUT__MARK,
 405         MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
 406
 407         /* MSEL2 special cases */
 408         TSIF2_TS_XX1_MARK,
 409         TSIF2_TS_XX2_MARK,
 410         TSIF2_TS_XX3_MARK,
 411         TSIF2_TS_XX4_MARK,
 412         TSIF2_TS_XX5_MARK,
 413         TSIF1_TS_XX1_MARK,
 414         TSIF1_TS_XX2_MARK,
 415         TSIF1_TS_XX3_MARK,
 416         TSIF1_TS_XX4_MARK,
 417         TSIF1_TS_XX5_MARK,
 418         TSIF0_TS_XX1_MARK,
 419         TSIF0_TS_XX2_MARK,
 420         TSIF0_TS_XX3_MARK,
 421         TSIF0_TS_XX4_MARK,
 422         TSIF0_TS_XX5_MARK,
 423         MST1_TS_XX1_MARK,
 424         MST1_TS_XX2_MARK,
 425         MST1_TS_XX3_MARK,
 426         MST1_TS_XX4_MARK,
 427         MST1_TS_XX5_MARK,
 428         MST0_TS_XX1_MARK,
 429         MST0_TS_XX2_MARK,
 430         MST0_TS_XX3_MARK,
 431         MST0_TS_XX4_MARK,
 432         MST0_TS_XX5_MARK,
 433
 434         /* MSEL3 special cases */
 435         SDHI0_VCCQ_MC0_ON_MARK,
 436         SDHI0_VCCQ_MC0_OFF_MARK,
 437         DEBUG_MON_VIO_MARK,
 438         DEBUG_MON_LCDD_MARK,
 439         LCDC_LCDC0_MARK,
 440         LCDC_LCDC1_MARK,
 441
 442         /* MSEL4 special cases */
 443         IRQ9_MEM_INT_MARK,
 444         IRQ9_MCP_INT_MARK,
 445         A11_MARK,
 446         KEYOUT8_MARK,
 447         TPU4TO3_MARK,
 448         RESETA_N_PU_ON_MARK,
 449         RESETA_N_PU_OFF_MARK,
 450         EDBGREQ_PD_MARK,
 451         EDBGREQ_PU_MARK,
 452
 453         PINMUX_MARK_END,
 454 };
 455
 456 static const u16 pinmux_data[] = {
 457         /* specify valid pin states for each pin in GPIO mode */
 458         PINMUX_DATA_ALL(),
 459
 460         /* Table 25-1 (Function 0-7) */
 461         PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
 462         PINMUX_DATA(GPI0_MARK, PORT1_FN1),
 463         PINMUX_DATA(GPI1_MARK, PORT2_FN1),
 464         PINMUX_DATA(GPI2_MARK, PORT3_FN1),
 465         PINMUX_DATA(GPI3_MARK, PORT4_FN1),
 466         PINMUX_DATA(GPI4_MARK, PORT5_FN1),
 467         PINMUX_DATA(GPI5_MARK, PORT6_FN1),
 468         PINMUX_DATA(GPI6_MARK, PORT7_FN1),
 469         PINMUX_DATA(GPI7_MARK, PORT8_FN1),
 470         PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
 471         PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
 472         PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
 473         PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
 474         PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
 475         PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
 476         PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
 477         PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
 478         PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
 479         PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
 480         PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
 481         PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
 482         PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
 483         PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
 484         PINMUX_DATA(GPO0_MARK, PORT20_FN1),
 485         PINMUX_DATA(GPO1_MARK, PORT21_FN1),
 486         PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
 487         PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
 488         PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
 489         PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
 490         PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
 491         PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
 492         PINMUX_DATA(VINT_MARK, PORT25_FN1),
 493         PINMUX_DATA(TCKON_MARK, PORT26_FN1),
 494         PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
 495         PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
 496                 MSEL2CR_MSEL16_1), \
 497         PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
 498                 MSEL2CR_MSEL18_1), \
 499         PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
 500         PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
 501         PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
 502         PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
 503                 MSEL2CR_MSEL16_1), \
 504         PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
 505                 MSEL2CR_MSEL18_1), \
 506         PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
 507         PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
 508         PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
 509         PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
 510         PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
 511         PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
 512         PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
 513         PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
 514         PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
 515         PINMUX_DATA(XWUP_MARK, PORT33_FN3),
 516         PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
 517         PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
 518         PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
 519         PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
 520         PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
 521         PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
 522         PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
 523         PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
 524         PINMUX_DATA(VACK_MARK, PORT40_FN1),
 525         PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
 526         PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
 527         PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
 528         PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
 529         PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
 530         PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
 531         PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
 532         PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
 533         PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
 534         PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
 535         PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
 536         PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
 537         PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
 538         PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
 539         PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
 540         PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
 541         PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
 542         PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
 543         PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
 544         PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
 545         PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
 546         PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
 547         PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
 548         PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
 549         PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
 550         PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
 551
 552         PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
 553         PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
 554         PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
 555         PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
 556         PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
 557         PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
 558         PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
 559         PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
 560         PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
 561         PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
 562         PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
 563         PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
 564         PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
 565         PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
 566         PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
 567         PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
 568         PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
 569         PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
 570         PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
 571         PINMUX_DATA(A0_MARK, PORT57_FN1), \
 572         PINMUX_DATA(BS__MARK, PORT57_FN2),
 573         PINMUX_DATA(A12_MARK, PORT58_FN1), \
 574         PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
 575         PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
 576         PINMUX_DATA(A13_MARK, PORT59_FN1), \
 577         PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
 578         PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
 579         PINMUX_DATA(A14_MARK, PORT60_FN1), \
 580         PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
 581         PINMUX_DATA(A15_MARK, PORT61_FN1), \
 582         PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
 583         PINMUX_DATA(A16_MARK, PORT62_FN1), \
 584         PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
 585         PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
 586         PINMUX_DATA(A17_MARK, PORT63_FN1), \
 587         PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
 588         PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
 589         PINMUX_DATA(A18_MARK, PORT64_FN1), \
 590         PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
 591         PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
 592         PINMUX_DATA(A19_MARK, PORT65_FN1), \
 593         PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
 594         PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
 595         PINMUX_DATA(A20_MARK, PORT66_FN1), \
 596         PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
 597         PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
 598         PINMUX_DATA(A21_MARK, PORT67_FN1), \
 599         PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
 600         PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
 601         PINMUX_DATA(A22_MARK, PORT68_FN1), \
 602         PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
 603         PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
 604         PINMUX_DATA(A23_MARK, PORT69_FN1), \
 605         PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
 606         PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
 607         PINMUX_DATA(A24_MARK, PORT70_FN1), \
 608         PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
 609         PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
 610         PINMUX_DATA(A25_MARK, PORT71_FN1), \
 611         PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
 612         PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
 613         PINMUX_DATA(A26_MARK, PORT72_FN1), \
 614         PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
 615         PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
 616         PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
 617         PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
 618         PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
 619         PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
 620         PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
 621         PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
 622         PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
 623         PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
 624         PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
 625         PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
 626         PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
 627         PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
 628         PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
 629         PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
 630         PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
 631         PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
 632         PINMUX_DATA(CS4__MARK, PORT90_FN1),
 633         PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
 634         PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
 635         PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
 636         PINMUX_DATA(FCE1__MARK, PORT92_FN2),
 637         PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
 638         PINMUX_DATA(DACK0_MARK, PORT93_FN4),
 639         PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
 640         PINMUX_DATA(CS6A__MARK, PORT94_FN2),
 641         PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
 642         PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
 643         PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
 644         PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
 645         PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
 646         PINMUX_DATA(WE1__MARK, PORT98_FN1),
 647         PINMUX_DATA(FRB_MARK, PORT99_FN1),
 648         PINMUX_DATA(CKO_MARK, PORT100_FN1),
 649         PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
 650         PINMUX_DATA(NBRST__MARK, PORT102_FN1),
 651         PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
 652         PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
 653         PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
 654         PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
 655         PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
 656         PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
 657         PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
 658         PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
 659         PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
 660         PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
 661         PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
 662         PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
 663         PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
 664         PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
 665         PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
 666         PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
 667         PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
 668         PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
 669         PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
 670         PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
 671         PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
 672         PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
 673         PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
 674         PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
 675         PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
 676         PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
 677         PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
 678         PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
 679         PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
 680         PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
 681         PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
 682         PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
 683         PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
 684         PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
 685         PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
 686         PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
 687
 688         PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
 689         PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
 690         PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
 691         PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
 692         PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
 693         PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
 694         PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
 695                 MSEL4CR_MSEL10_1), \
 696         PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
 697         PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
 698         PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
 699         PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
 700         PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
 701         PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
 702         PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
 703         PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
 704         PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
 705         PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
 706         PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
 707         PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
 708         PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
 709         PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
 710         PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
 711         PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
 712         PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
 713         PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
 714         PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
 715         PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
 716         PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
 717         PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
 718         PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
 719         PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
 720         PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
 721         PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
 722         PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
 723         PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
 724         PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
 725         PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
 726         PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
 727         PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
 728         PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
 729         PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
 730         PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
 731         PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
 732         PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
 733         PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
 734         PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
 735         PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
 736         PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
 737         PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
 738         PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
 739         PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
 740         PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
 741         PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
 742         PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
 743         PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
 744         PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
 745         PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
 746         PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
 747         PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
 748         PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
 749         PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
 750         PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
 751         PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
 752         PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
 753         PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
 754         PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
 755         PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
 756         PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
 757         PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
 758         PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
 759         PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
 760         PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
 761         PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
 762         PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
 763         PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
 764         PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
 765         PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
 766         PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
 767         PINMUX_DATA(A27_MARK, PORT149_FN1), \
 768         PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
 769         PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
 770         PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
 771         PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
 772         PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
 773         PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
 774         PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
 775         PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
 776         PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
 777         PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
 778         PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
 779         PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
 780         PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
 781         PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
 782         PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
 783         PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
 784         PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
 785         PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
 786         PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
 787                 MSEL4CR_MSEL10_0),
 788         PINMUX_DATA(DINT__MARK, PORT158_FN1), \
 789         PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
 790         PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
 791         PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
 792         PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
 793         PINMUX_DATA(NMI_MARK, PORT159_FN3),
 794         PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
 795         PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
 796         PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
 797         PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
 798         PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
 799         PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
 800         PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
 801         PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
 802         PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
 803         PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
 804         PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
 805         PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
 806                 MSEL4CR_MSEL20_1), \
 807         PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
 808         PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
 809         PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
 810                 MSEL4CR_MSEL20_1), \
 811         PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
 812         PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
 813         PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
 814                 MSEL4CR_MSEL20_1), \
 815         PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
 816         PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
 817         PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
 818                 MSEL4CR_MSEL20_1),
 819         PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
 820         PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
 821                 MSEL4CR_MSEL20_1), \
 822         PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
 823         PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
 824         PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
 825         PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
 826         PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
 827         PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
 828         PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
 829         PINMUX_DATA(D16_MARK, PORT200_FN6),
 830         PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
 831         PINMUX_DATA(D17_MARK, PORT201_FN6),
 832         PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
 833         PINMUX_DATA(D18_MARK, PORT202_FN6),
 834         PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
 835         PINMUX_DATA(D19_MARK, PORT203_FN6),
 836         PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
 837         PINMUX_DATA(D20_MARK, PORT204_FN6),
 838         PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
 839         PINMUX_DATA(D21_MARK, PORT205_FN6),
 840         PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
 841         PINMUX_DATA(D22_MARK, PORT206_FN6),
 842         PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
 843         PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
 844         PINMUX_DATA(D23_MARK, PORT207_FN6),
 845         PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
 846         PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
 847         PINMUX_DATA(D24_MARK, PORT208_FN6),
 848         PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
 849         PINMUX_DATA(D25_MARK, PORT209_FN6),
 850         PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
 851         PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
 852         PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
 853         PINMUX_DATA(D26_MARK, PORT210_FN6),
 854         PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
 855         PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
 856         PINMUX_DATA(D27_MARK, PORT211_FN6),
 857         PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
 858         PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
 859         PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
 860         PINMUX_DATA(D28_MARK, PORT212_FN6),
 861         PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
 862         PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
 863         PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
 864         PINMUX_DATA(D29_MARK, PORT213_FN6),
 865         PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
 866         PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
 867         PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
 868         PINMUX_DATA(D30_MARK, PORT214_FN6),
 869         PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
 870         PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
 871         PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
 872         PINMUX_DATA(D31_MARK, PORT215_FN6),
 873         PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
 874         PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
 875         PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
 876         PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
 877         PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
 878         PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
 879         PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
 880                 MSEL4CR_MSEL26_1), \
 881         PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
 882         PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
 883         PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
 884         PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
 885         PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
 886         PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
 887         PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
 888         PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
 889         PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
 890         PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
 891         PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
 892         PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
 893                 MSEL4CR_MSEL26_1), \
 894         PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
 895         PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
 896         PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
 897         PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
 898         PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
 899         PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
 900         PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
 901         PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
 902         PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
 903                 MSEL4CR_MSEL26_1), \
 904         PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
 905         PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
 906         PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
 907         PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
 908         PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
 909         PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
 910         PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
 911                 MSEL4CR_MSEL26_1), \
 912         PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
 913
 914         PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
 915         PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
 916         PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
 917         PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
 918         PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
 919         PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
 920         PINMUX_DATA(IDIN_MARK, PORT227_FN4),
 921         PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
 922         PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
 923         PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
 924         PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
 925         PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
 926         PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
 927         PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
 928         PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
 929         PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
 930         PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
 931         PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
 932         PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
 933         PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
 934         PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
 935                 MSEL4CR_MSEL26_0), \
 936         PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
 937         PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
 938         PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
 939         PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
 940                 MSEL4CR_MSEL26_0), \
 941         PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
 942         PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
 943         PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
 944                 MSEL2CR_MSEL16_0),
 945         PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
 946         PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
 947                 MSEL2CR_MSEL16_0),
 948         PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
 949         PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
 950                 MSEL4CR_MSEL26_0), \
 951         PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
 952         PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
 953         PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
 954                 MSEL4CR_MSEL26_0), \
 955         PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
 956         PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
 957         PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
 958         PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
 959         PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
 960         PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
 961         PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
 962         PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
 963         PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
 964         PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
 965         PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
 966                 MSEL4CR_MSEL20_0), \
 967         PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
 968         PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
 969         PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
 970         PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
 971                 MSEL4CR_MSEL20_0), \
 972         PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
 973         PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
 974         PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
 975         PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
 976                 MSEL4CR_MSEL20_0), \
 977         PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
 978         PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
 979         PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
 980         PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
 981                 MSEL4CR_MSEL20_0), \
 982         PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
 983         PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
 984         PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
 985         PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
 986                 MSEL4CR_MSEL20_0), \
 987         PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
 988         PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
 989         PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
 990         PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
 991                 MSEL2CR_MSEL18_0), \
 992         PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
 993         PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
 994         PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
 995         PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
 996                 MSEL2CR_MSEL18_0), \
 997         PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
 998         PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
 999         PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
1000         PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
1001         PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
1002         PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
1003         PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
1004         PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
1005         PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
1006         PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
1007         PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
1008         PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
1009         PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
1010         PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
1011         PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
1012         PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
1013         PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
1014         PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
1015         PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
1016         PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
1017         PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
1018         PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
1019         PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
1020         PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
1021         PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
1022         PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
1023         PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
1024         PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1025         PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1026         PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
1027         PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
1028         PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
1029         PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
1030         PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
1031         PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
1032         PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
1033         PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
1034         PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
1035         PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
1036         PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
1037         PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
1038         PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
1039         PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
1040         PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1041         PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1042         PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
1043         PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
1044         PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
1045         PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
1046         PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
1047         PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
1048         PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
1049         PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
1050         PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
1051         PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
1052         PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
1053         PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
1054         PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
1055         PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
1056
1057         PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
1058         PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
1059         PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
1060         PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
1061         PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
1062         PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
1063         PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
1064         PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
1065         PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
1066         PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
1067         PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
1068         PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
1069         PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
1070         PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
1071         PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
1072         PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
1073         PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
1074
1075         /* MSEL2 special cases */
1076         PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1077                 MSEL2CR_MSEL12_0),
1078         PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1079                 MSEL2CR_MSEL12_1),
1080         PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1081                 MSEL2CR_MSEL12_0),
1082         PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1083                 MSEL2CR_MSEL12_1),
1084         PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
1085                 MSEL2CR_MSEL12_0),
1086         PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1087                 MSEL2CR_MSEL9_0),
1088         PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1089                 MSEL2CR_MSEL9_1),
1090         PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1091                 MSEL2CR_MSEL9_0),
1092         PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1093                 MSEL2CR_MSEL9_1),
1094         PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
1095                 MSEL2CR_MSEL9_0),
1096         PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1097                 MSEL2CR_MSEL6_0),
1098         PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1099                 MSEL2CR_MSEL6_1),
1100         PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1101                 MSEL2CR_MSEL6_0),
1102         PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1103                 MSEL2CR_MSEL6_1),
1104         PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
1105                 MSEL2CR_MSEL6_0),
1106         PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1107                 MSEL2CR_MSEL3_0),
1108         PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1109                 MSEL2CR_MSEL3_1),
1110         PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1111                 MSEL2CR_MSEL3_0),
1112         PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1113                 MSEL2CR_MSEL3_1),
1114         PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
1115                 MSEL2CR_MSEL3_0),
1116         PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1117                 MSEL2CR_MSEL0_0),
1118         PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1119                 MSEL2CR_MSEL0_1),
1120         PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1121                 MSEL2CR_MSEL0_0),
1122         PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1123                 MSEL2CR_MSEL0_1),
1124         PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
1125                 MSEL2CR_MSEL0_0),
1126
1127         /* MSEL3 special cases */
1128         PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
1129         PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
1130         PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
1131         PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
1132         PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
1133         PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
1134
1135         /* MSEL4 special cases */
1136         PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
1137         PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
1138         PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
1139         PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
1140         PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
1141         PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
1142         PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
1143         PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
1144         PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
1145 };
1146
1147 #define __I             (SH_PFC_PIN_CFG_INPUT)
1148 #define __O             (SH_PFC_PIN_CFG_OUTPUT)
1149 #define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1150 #define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
1151 #define __PU            (SH_PFC_PIN_CFG_PULL_UP)
1152 #define __PUD           (SH_PFC_PIN_CFG_PULL_UP_DOWN)
1153
1154 #define SH73A0_PIN_I_PD(pin)            SH_PFC_PIN_CFG(pin, __I | __PD)
1155 #define SH73A0_PIN_I_PU(pin)            SH_PFC_PIN_CFG(pin, __I | __PU)
1156 #define SH73A0_PIN_I_PU_PD(pin)         SH_PFC_PIN_CFG(pin, __I | __PUD)
1157 #define SH73A0_PIN_IO(pin)              SH_PFC_PIN_CFG(pin, __IO)
1158 #define SH73A0_PIN_IO_PD(pin)           SH_PFC_PIN_CFG(pin, __IO | __PD)
1159 #define SH73A0_PIN_IO_PU(pin)           SH_PFC_PIN_CFG(pin, __IO | __PU)
1160 #define SH73A0_PIN_IO_PU_PD(pin)        SH_PFC_PIN_CFG(pin, __IO | __PUD)
1161 #define SH73A0_PIN_O(pin)               SH_PFC_PIN_CFG(pin, __O)
1162
1163 /*
1164  * Pins not associated with a GPIO port.
1165  */
1166 enum {
1167         PORT_ASSIGN_LAST(),
1168         NOGP_ALL(),
1169 };
1170
1171 static const struct sh_pfc_pin pinmux_pins[] = {
1172         /* Table 25-1 (I/O and Pull U/D) */
1173         SH73A0_PIN_I_PD(0),
1174         SH73A0_PIN_I_PU(1),
1175         SH73A0_PIN_I_PU(2),
1176         SH73A0_PIN_I_PU(3),
1177         SH73A0_PIN_I_PU(4),
1178         SH73A0_PIN_I_PU(5),
1179         SH73A0_PIN_I_PU(6),
1180         SH73A0_PIN_I_PU(7),
1181         SH73A0_PIN_I_PU(8),
1182         SH73A0_PIN_I_PD(9),
1183         SH73A0_PIN_I_PD(10),
1184         SH73A0_PIN_I_PU_PD(11),
1185         SH73A0_PIN_IO_PU_PD(12),
1186         SH73A0_PIN_IO_PU_PD(13),
1187         SH73A0_PIN_IO_PU_PD(14),
1188         SH73A0_PIN_IO_PU_PD(15),
1189         SH73A0_PIN_IO_PD(16),
1190         SH73A0_PIN_IO_PD(17),
1191         SH73A0_PIN_IO_PU(18),
1192         SH73A0_PIN_IO_PU(19),
1193         SH73A0_PIN_O(20),
1194         SH73A0_PIN_O(21),
1195         SH73A0_PIN_O(22),
1196         SH73A0_PIN_O(23),
1197         SH73A0_PIN_O(24),
1198         SH73A0_PIN_I_PD(25),
1199         SH73A0_PIN_I_PD(26),
1200         SH73A0_PIN_IO_PU(27),
1201         SH73A0_PIN_IO_PU(28),
1202         SH73A0_PIN_IO_PD(29),
1203         SH73A0_PIN_IO_PD(30),
1204         SH73A0_PIN_IO_PU(31),
1205         SH73A0_PIN_IO_PD(32),
1206         SH73A0_PIN_I_PU_PD(33),
1207         SH73A0_PIN_IO_PD(34),
1208         SH73A0_PIN_I_PU_PD(35),
1209         SH73A0_PIN_IO_PD(36),
1210         SH73A0_PIN_IO(37),
1211         SH73A0_PIN_O(38),
1212         SH73A0_PIN_I_PU(39),
1213         SH73A0_PIN_I_PU_PD(40),
1214         SH73A0_PIN_O(41),
1215         SH73A0_PIN_IO_PD(42),
1216         SH73A0_PIN_IO_PU_PD(43),
1217         SH73A0_PIN_IO_PU_PD(44),
1218         SH73A0_PIN_IO_PD(45),
1219         SH73A0_PIN_IO_PD(46),
1220         SH73A0_PIN_IO_PD(47),
1221         SH73A0_PIN_I_PD(48),
1222         SH73A0_PIN_IO_PU_PD(49),
1223         SH73A0_PIN_IO_PD(50),
1224         SH73A0_PIN_IO_PD(51),
1225         SH73A0_PIN_O(52),
1226         SH73A0_PIN_IO_PU_PD(53),
1227         SH73A0_PIN_IO_PU_PD(54),
1228         SH73A0_PIN_IO_PD(55),
1229         SH73A0_PIN_I_PU_PD(56),
1230         SH73A0_PIN_IO(57),
1231         SH73A0_PIN_IO(58),
1232         SH73A0_PIN_IO(59),
1233         SH73A0_PIN_IO(60),
1234         SH73A0_PIN_IO(61),
1235         SH73A0_PIN_IO_PD(62),
1236         SH73A0_PIN_IO_PD(63),
1237         SH73A0_PIN_IO_PU_PD(64),
1238         SH73A0_PIN_IO_PD(65),
1239         SH73A0_PIN_IO_PU_PD(66),
1240         SH73A0_PIN_IO_PU_PD(67),
1241         SH73A0_PIN_IO_PU_PD(68),
1242         SH73A0_PIN_IO_PU_PD(69),
1243         SH73A0_PIN_IO_PU_PD(70),
1244         SH73A0_PIN_IO_PU_PD(71),
1245         SH73A0_PIN_IO_PU_PD(72),
1246         SH73A0_PIN_I_PU_PD(73),
1247         SH73A0_PIN_IO_PU(74),
1248         SH73A0_PIN_IO_PU(75),
1249         SH73A0_PIN_IO_PU(76),
1250         SH73A0_PIN_IO_PU(77),
1251         SH73A0_PIN_IO_PU(78),
1252         SH73A0_PIN_IO_PU(79),
1253         SH73A0_PIN_IO_PU(80),
1254         SH73A0_PIN_IO_PU(81),
1255         SH73A0_PIN_IO_PU(82),
1256         SH73A0_PIN_IO_PU(83),
1257         SH73A0_PIN_IO_PU(84),
1258         SH73A0_PIN_IO_PU(85),
1259         SH73A0_PIN_IO_PU(86),
1260         SH73A0_PIN_IO_PU(87),
1261         SH73A0_PIN_IO_PU(88),
1262         SH73A0_PIN_IO_PU(89),
1263         SH73A0_PIN_O(90),
1264         SH73A0_PIN_IO_PU(91),
1265         SH73A0_PIN_O(92),
1266         SH73A0_PIN_IO_PU(93),
1267         SH73A0_PIN_O(94),
1268         SH73A0_PIN_I_PU_PD(95),
1269         SH73A0_PIN_IO(96),
1270         SH73A0_PIN_IO(97),
1271         SH73A0_PIN_IO(98),
1272         SH73A0_PIN_I_PU(99),
1273         SH73A0_PIN_O(100),
1274         SH73A0_PIN_O(101),
1275         SH73A0_PIN_I_PU(102),
1276         SH73A0_PIN_IO_PD(103),
1277         SH73A0_PIN_I_PU_PD(104),
1278         SH73A0_PIN_I_PD(105),
1279         SH73A0_PIN_I_PD(106),
1280         SH73A0_PIN_I_PU_PD(107),
1281         SH73A0_PIN_I_PU_PD(108),
1282         SH73A0_PIN_IO_PD(109),
1283         SH73A0_PIN_IO_PD(110),
1284         SH73A0_PIN_IO_PU_PD(111),
1285         SH73A0_PIN_IO_PU_PD(112),
1286         SH73A0_PIN_IO_PU_PD(113),
1287         SH73A0_PIN_IO_PD(114),
1288         SH73A0_PIN_IO_PU(115),
1289         SH73A0_PIN_IO_PU(116),
1290         SH73A0_PIN_IO_PU_PD(117),
1291         SH73A0_PIN_IO_PU_PD(118),
1292         SH73A0_PIN_IO_PD(128),
1293         SH73A0_PIN_IO_PD(129),
1294         SH73A0_PIN_IO_PU_PD(130),
1295         SH73A0_PIN_IO_PD(131),
1296         SH73A0_PIN_IO_PD(132),
1297         SH73A0_PIN_IO_PD(133),
1298         SH73A0_PIN_IO_PU_PD(134),
1299         SH73A0_PIN_IO_PU_PD(135),
1300         SH73A0_PIN_IO_PU_PD(136),
1301         SH73A0_PIN_IO_PU_PD(137),
1302         SH73A0_PIN_IO_PD(138),
1303         SH73A0_PIN_IO_PD(139),
1304         SH73A0_PIN_IO_PD(140),
1305         SH73A0_PIN_IO_PD(141),
1306         SH73A0_PIN_IO_PD(142),
1307         SH73A0_PIN_IO_PD(143),
1308         SH73A0_PIN_IO_PU_PD(144),
1309         SH73A0_PIN_IO_PD(145),
1310         SH73A0_PIN_IO_PU_PD(146),
1311         SH73A0_PIN_IO_PU_PD(147),
1312         SH73A0_PIN_IO_PU_PD(148),
1313         SH73A0_PIN_IO_PU_PD(149),
1314         SH73A0_PIN_I_PU_PD(150),
1315         SH73A0_PIN_IO_PU_PD(151),
1316         SH73A0_PIN_IO_PU_PD(152),
1317         SH73A0_PIN_IO_PD(153),
1318         SH73A0_PIN_IO_PD(154),
1319         SH73A0_PIN_I_PU_PD(155),
1320         SH73A0_PIN_IO_PU_PD(156),
1321         SH73A0_PIN_I_PD(157),
1322         SH73A0_PIN_IO_PD(158),
1323         SH73A0_PIN_IO_PU_PD(159),
1324         SH73A0_PIN_IO_PU_PD(160),
1325         SH73A0_PIN_I_PU_PD(161),
1326         SH73A0_PIN_I_PU_PD(162),
1327         SH73A0_PIN_IO_PU_PD(163),
1328         SH73A0_PIN_I_PU_PD(164),
1329         SH73A0_PIN_IO_PD(192),
1330         SH73A0_PIN_IO_PU_PD(193),
1331         SH73A0_PIN_IO_PD(194),
1332         SH73A0_PIN_IO_PU_PD(195),
1333         SH73A0_PIN_IO_PD(196),
1334         SH73A0_PIN_IO_PD(197),
1335         SH73A0_PIN_IO_PD(198),
1336         SH73A0_PIN_IO_PD(199),
1337         SH73A0_PIN_IO_PU_PD(200),
1338         SH73A0_PIN_IO_PU_PD(201),
1339         SH73A0_PIN_IO_PU_PD(202),
1340         SH73A0_PIN_IO_PU_PD(203),
1341         SH73A0_PIN_IO_PU_PD(204),
1342         SH73A0_PIN_IO_PU_PD(205),
1343         SH73A0_PIN_IO_PU_PD(206),
1344         SH73A0_PIN_IO_PD(207),
1345         SH73A0_PIN_IO_PD(208),
1346         SH73A0_PIN_IO_PD(209),
1347         SH73A0_PIN_IO_PD(210),
1348         SH73A0_PIN_IO_PD(211),
1349         SH73A0_PIN_IO_PD(212),
1350         SH73A0_PIN_IO_PD(213),
1351         SH73A0_PIN_IO_PU_PD(214),
1352         SH73A0_PIN_IO_PU_PD(215),
1353         SH73A0_PIN_IO_PD(216),
1354         SH73A0_PIN_IO_PD(217),
1355         SH73A0_PIN_O(218),
1356         SH73A0_PIN_IO_PD(219),
1357         SH73A0_PIN_IO_PD(220),
1358         SH73A0_PIN_IO_PU_PD(221),
1359         SH73A0_PIN_IO_PU_PD(222),
1360         SH73A0_PIN_I_PU_PD(223),
1361         SH73A0_PIN_I_PU_PD(224),
1362         SH73A0_PIN_IO_PU_PD(225),
1363         SH73A0_PIN_O(226),
1364         SH73A0_PIN_IO_PU_PD(227),
1365         SH73A0_PIN_I_PU_PD(228),
1366         SH73A0_PIN_I_PD(229),
1367         SH73A0_PIN_IO(230),
1368         SH73A0_PIN_IO_PU_PD(231),
1369         SH73A0_PIN_IO_PU_PD(232),
1370         SH73A0_PIN_I_PU_PD(233),
1371         SH73A0_PIN_IO_PU_PD(234),
1372         SH73A0_PIN_IO_PU_PD(235),
1373         SH73A0_PIN_IO_PU_PD(236),
1374         SH73A0_PIN_IO_PD(237),
1375         SH73A0_PIN_IO_PU_PD(238),
1376         SH73A0_PIN_IO_PU_PD(239),
1377         SH73A0_PIN_IO_PU_PD(240),
1378         SH73A0_PIN_O(241),
1379         SH73A0_PIN_I_PD(242),
1380         SH73A0_PIN_IO_PU_PD(243),
1381         SH73A0_PIN_IO_PU_PD(244),
1382         SH73A0_PIN_IO_PU_PD(245),
1383         SH73A0_PIN_IO_PU_PD(246),
1384         SH73A0_PIN_IO_PU_PD(247),
1385         SH73A0_PIN_IO_PU_PD(248),
1386         SH73A0_PIN_IO_PU_PD(249),
1387         SH73A0_PIN_IO_PU_PD(250),
1388         SH73A0_PIN_IO_PU_PD(251),
1389         SH73A0_PIN_IO_PU_PD(252),
1390         SH73A0_PIN_IO_PU_PD(253),
1391         SH73A0_PIN_IO_PU_PD(254),
1392         SH73A0_PIN_IO_PU_PD(255),
1393         SH73A0_PIN_IO_PU_PD(256),
1394         SH73A0_PIN_IO_PU_PD(257),
1395         SH73A0_PIN_IO_PU_PD(258),
1396         SH73A0_PIN_IO_PU_PD(259),
1397         SH73A0_PIN_IO_PU_PD(260),
1398         SH73A0_PIN_IO_PU_PD(261),
1399         SH73A0_PIN_IO_PU_PD(262),
1400         SH73A0_PIN_IO_PU_PD(263),
1401         SH73A0_PIN_IO_PU_PD(264),
1402         SH73A0_PIN_IO_PU_PD(265),
1403         SH73A0_PIN_IO_PU_PD(266),
1404         SH73A0_PIN_IO_PU_PD(267),
1405         SH73A0_PIN_IO_PU_PD(268),
1406         SH73A0_PIN_IO_PU_PD(269),
1407         SH73A0_PIN_IO_PU_PD(270),
1408         SH73A0_PIN_IO_PU_PD(271),
1409         SH73A0_PIN_IO_PU_PD(272),
1410         SH73A0_PIN_IO_PU_PD(273),
1411         SH73A0_PIN_IO_PU_PD(274),
1412         SH73A0_PIN_IO_PU_PD(275),
1413         SH73A0_PIN_IO_PU_PD(276),
1414         SH73A0_PIN_IO_PU_PD(277),
1415         SH73A0_PIN_IO_PU_PD(278),
1416         SH73A0_PIN_IO_PU_PD(279),
1417         SH73A0_PIN_IO_PU_PD(280),
1418         SH73A0_PIN_O(281),
1419         SH73A0_PIN_O(282),
1420         SH73A0_PIN_I_PU(288),
1421         SH73A0_PIN_IO_PU_PD(289),
1422         SH73A0_PIN_IO_PU_PD(290),
1423         SH73A0_PIN_IO_PU_PD(291),
1424         SH73A0_PIN_IO_PU_PD(292),
1425         SH73A0_PIN_IO_PU_PD(293),
1426         SH73A0_PIN_IO_PU_PD(294),
1427         SH73A0_PIN_IO_PU_PD(295),
1428         SH73A0_PIN_IO_PU_PD(296),
1429         SH73A0_PIN_IO_PU_PD(297),
1430         SH73A0_PIN_IO_PU_PD(298),
1431         SH73A0_PIN_IO_PU_PD(299),
1432         SH73A0_PIN_IO_PU_PD(300),
1433         SH73A0_PIN_IO_PU_PD(301),
1434         SH73A0_PIN_IO_PU_PD(302),
1435         SH73A0_PIN_IO_PU_PD(303),
1436         SH73A0_PIN_IO_PU_PD(304),
1437         SH73A0_PIN_IO_PU_PD(305),
1438         SH73A0_PIN_O(306),
1439         SH73A0_PIN_O(307),
1440         SH73A0_PIN_I_PU(308),
1441         SH73A0_PIN_O(309),
1442
1443         /* Pins not associated with a GPIO port */
1444         PINMUX_NOGP_ALL(),
1445 };
1446
1447 /* - BSC -------------------------------------------------------------------- */
1448 static const unsigned int bsc_data_0_7_pins[] = {
1449         /* D[0:7] */
1450         74, 75, 76, 77, 78, 79, 80, 81,
1451 };
1452 static const unsigned int bsc_data_0_7_mux[] = {
1453         D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1454         D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1455 };
1456 static const unsigned int bsc_data_8_15_pins[] = {
1457         /* D[8:15] */
1458         82, 83, 84, 85, 86, 87, 88, 89,
1459 };
1460 static const unsigned int bsc_data_8_15_mux[] = {
1461         D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1462         D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1463 };
1464 static const unsigned int bsc_cs4_pins[] = {
1465         /* CS */
1466         90,
1467 };
1468 static const unsigned int bsc_cs4_mux[] = {
1469         CS4__MARK,
1470 };
1471 static const unsigned int bsc_cs5_a_pins[] = {
1472         /* CS */
1473         91,
1474 };
1475 static const unsigned int bsc_cs5_a_mux[] = {
1476         CS5A__MARK,
1477 };
1478 static const unsigned int bsc_cs5_b_pins[] = {
1479         /* CS */
1480         92,
1481 };
1482 static const unsigned int bsc_cs5_b_mux[] = {
1483         CS5B__MARK,
1484 };
1485 static const unsigned int bsc_cs6_a_pins[] = {
1486         /* CS */
1487         94,
1488 };
1489 static const unsigned int bsc_cs6_a_mux[] = {
1490         CS6A__MARK,
1491 };
1492 static const unsigned int bsc_cs6_b_pins[] = {
1493         /* CS */
1494         93,
1495 };
1496 static const unsigned int bsc_cs6_b_mux[] = {
1497         CS6B__MARK,
1498 };
1499 static const unsigned int bsc_rd_pins[] = {
1500         /* RD */
1501         96,
1502 };
1503 static const unsigned int bsc_rd_mux[] = {
1504         RD__FSC_MARK,
1505 };
1506 static const unsigned int bsc_rdwr_0_pins[] = {
1507         /* RDWR */
1508         91,
1509 };
1510 static const unsigned int bsc_rdwr_0_mux[] = {
1511         PORT91_RDWR_MARK,
1512 };
1513 static const unsigned int bsc_rdwr_1_pins[] = {
1514         /* RDWR */
1515         97,
1516 };
1517 static const unsigned int bsc_rdwr_1_mux[] = {
1518         RDWR_FWE_MARK,
1519 };
1520 static const unsigned int bsc_rdwr_2_pins[] = {
1521         /* RDWR */
1522         149,
1523 };
1524 static const unsigned int bsc_rdwr_2_mux[] = {
1525         PORT149_RDWR_MARK,
1526 };
1527 static const unsigned int bsc_we0_pins[] = {
1528         /* WE0 */
1529         97,
1530 };
1531 static const unsigned int bsc_we0_mux[] = {
1532         WE0__FWE_MARK,
1533 };
1534 static const unsigned int bsc_we1_pins[] = {
1535         /* WE1 */
1536         98,
1537 };
1538 static const unsigned int bsc_we1_mux[] = {
1539         WE1__MARK,
1540 };
1541 /* - FSIA ------------------------------------------------------------------- */
1542 static const unsigned int fsia_mclk_in_pins[] = {
1543         /* CK */
1544         49,
1545 };
1546 static const unsigned int fsia_mclk_in_mux[] = {
1547         FSIACK_MARK,
1548 };
1549 static const unsigned int fsia_mclk_out_pins[] = {
1550         /* OMC */
1551         49,
1552 };
1553 static const unsigned int fsia_mclk_out_mux[] = {
1554         FSIAOMC_MARK,
1555 };
1556 static const unsigned int fsia_sclk_in_pins[] = {
1557         /* ILR, IBT */
1558         50, 51,
1559 };
1560 static const unsigned int fsia_sclk_in_mux[] = {
1561         FSIAILR_MARK, FSIAIBT_MARK,
1562 };
1563 static const unsigned int fsia_sclk_out_pins[] = {
1564         /* OLR, OBT */
1565         50, 51,
1566 };
1567 static const unsigned int fsia_sclk_out_mux[] = {
1568         FSIAOLR_MARK, FSIAOBT_MARK,
1569 };
1570 static const unsigned int fsia_data_in_pins[] = {
1571         /* ISLD */
1572         55,
1573 };
1574 static const unsigned int fsia_data_in_mux[] = {
1575         FSIAISLD_MARK,
1576 };
1577 static const unsigned int fsia_data_out_pins[] = {
1578         /* OSLD */
1579         52,
1580 };
1581 static const unsigned int fsia_data_out_mux[] = {
1582         FSIAOSLD_MARK,
1583 };
1584 static const unsigned int fsia_spdif_pins[] = {
1585         /* SPDIF */
1586         53,
1587 };
1588 static const unsigned int fsia_spdif_mux[] = {
1589         FSIASPDIF_MARK,
1590 };
1591 /* - FSIB ------------------------------------------------------------------- */
1592 static const unsigned int fsib_mclk_in_pins[] = {
1593         /* CK */
1594         54,
1595 };
1596 static const unsigned int fsib_mclk_in_mux[] = {
1597         FSIBCK_MARK,
1598 };
1599 static const unsigned int fsib_mclk_out_pins[] = {
1600         /* OMC */
1601         54,
1602 };
1603 static const unsigned int fsib_mclk_out_mux[] = {
1604         FSIBOMC_MARK,
1605 };
1606 static const unsigned int fsib_sclk_in_pins[] = {
1607         /* ILR, IBT */
1608         37, 36,
1609 };
1610 static const unsigned int fsib_sclk_in_mux[] = {
1611         FSIBILR_MARK, FSIBIBT_MARK,
1612 };
1613 static const unsigned int fsib_sclk_out_pins[] = {
1614         /* OLR, OBT */
1615         37, 36,
1616 };
1617 static const unsigned int fsib_sclk_out_mux[] = {
1618         FSIBOLR_MARK, FSIBOBT_MARK,
1619 };
1620 static const unsigned int fsib_data_in_pins[] = {
1621         /* ISLD */
1622         39,
1623 };
1624 static const unsigned int fsib_data_in_mux[] = {
1625         FSIBISLD_MARK,
1626 };
1627 static const unsigned int fsib_data_out_pins[] = {
1628         /* OSLD */
1629         38,
1630 };
1631 static const unsigned int fsib_data_out_mux[] = {
1632         FSIBOSLD_MARK,
1633 };
1634 static const unsigned int fsib_spdif_pins[] = {
1635         /* SPDIF */
1636         53,
1637 };
1638 static const unsigned int fsib_spdif_mux[] = {
1639         FSIBSPDIF_MARK,
1640 };
1641 /* - FSIC ------------------------------------------------------------------- */
1642 static const unsigned int fsic_mclk_in_pins[] = {
1643         /* CK */
1644         54,
1645 };
1646 static const unsigned int fsic_mclk_in_mux[] = {
1647         FSICCK_MARK,
1648 };
1649 static const unsigned int fsic_mclk_out_pins[] = {
1650         /* OMC */
1651         54,
1652 };
1653 static const unsigned int fsic_mclk_out_mux[] = {
1654         FSICOMC_MARK,
1655 };
1656 static const unsigned int fsic_sclk_in_pins[] = {
1657         /* ILR, IBT */
1658         46, 45,
1659 };
1660 static const unsigned int fsic_sclk_in_mux[] = {
1661         FSICILR_MARK, FSICIBT_MARK,
1662 };
1663 static const unsigned int fsic_sclk_out_pins[] = {
1664         /* OLR, OBT */
1665         46, 45,
1666 };
1667 static const unsigned int fsic_sclk_out_mux[] = {
1668         FSICOLR_MARK, FSICOBT_MARK,
1669 };
1670 static const unsigned int fsic_data_in_pins[] = {
1671         /* ISLD */
1672         48,
1673 };
1674 static const unsigned int fsic_data_in_mux[] = {
1675         FSICISLD_MARK,
1676 };
1677 static const unsigned int fsic_data_out_pins[] = {
1678         /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
1679         47, 44, 42, 16,
1680 };
1681 static const unsigned int fsic_data_out_mux[] = {
1682         FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
1683 };
1684 static const unsigned int fsic_spdif_0_pins[] = {
1685         /* SPDIF */
1686         53,
1687 };
1688 static const unsigned int fsic_spdif_0_mux[] = {
1689         PORT53_FSICSPDIF_MARK,
1690 };
1691 static const unsigned int fsic_spdif_1_pins[] = {
1692         /* SPDIF */
1693         47,
1694 };
1695 static const unsigned int fsic_spdif_1_mux[] = {
1696         PORT47_FSICSPDIF_MARK,
1697 };
1698 /* - FSID ------------------------------------------------------------------- */
1699 static const unsigned int fsid_sclk_in_pins[] = {
1700         /* ILR, IBT */
1701         46, 45,
1702 };
1703 static const unsigned int fsid_sclk_in_mux[] = {
1704         FSIDILR_MARK, FSIDIBT_MARK,
1705 };
1706 static const unsigned int fsid_sclk_out_pins[] = {
1707         /* OLR, OBT */
1708         46, 45,
1709 };
1710 static const unsigned int fsid_sclk_out_mux[] = {
1711         FSIDOLR_MARK, FSIDOBT_MARK,
1712 };
1713 static const unsigned int fsid_data_in_pins[] = {
1714         /* ISLD */
1715         48,
1716 };
1717 static const unsigned int fsid_data_in_mux[] = {
1718         FSIDISLD_MARK,
1719 };
1720 /* - I2C2 ------------------------------------------------------------------- */
1721 static const unsigned int i2c2_0_pins[] = {
1722         /* SCL, SDA */
1723         237, 236,
1724 };
1725 static const unsigned int i2c2_0_mux[] = {
1726         PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
1727 };
1728 static const unsigned int i2c2_1_pins[] = {
1729         /* SCL, SDA */
1730         27, 28,
1731 };
1732 static const unsigned int i2c2_1_mux[] = {
1733         PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
1734 };
1735 static const unsigned int i2c2_2_pins[] = {
1736         /* SCL, SDA */
1737         115, 116,
1738 };
1739 static const unsigned int i2c2_2_mux[] = {
1740         PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
1741 };
1742 /* - I2C3 ------------------------------------------------------------------- */
1743 static const unsigned int i2c3_0_pins[] = {
1744         /* SCL, SDA */
1745         248, 249,
1746 };
1747 static const unsigned int i2c3_0_mux[] = {
1748         PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
1749 };
1750 static const unsigned int i2c3_1_pins[] = {
1751         /* SCL, SDA */
1752         27, 28,
1753 };
1754 static const unsigned int i2c3_1_mux[] = {
1755         PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
1756 };
1757 static const unsigned int i2c3_2_pins[] = {
1758         /* SCL, SDA */
1759         115, 116,
1760 };
1761 static const unsigned int i2c3_2_mux[] = {
1762         PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
1763 };
1764 /* - IrDA ------------------------------------------------------------------- */
1765 static const unsigned int irda_0_pins[] = {
1766         /* OUT, IN, FIRSEL */
1767         241, 242, 243,
1768 };
1769 static const unsigned int irda_0_mux[] = {
1770         PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
1771 };
1772 static const unsigned int irda_1_pins[] = {
1773         /* OUT, IN, FIRSEL */
1774         49, 53, 54,
1775 };
1776 static const unsigned int irda_1_mux[] = {
1777         PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
1778 };
1779 /* - KEYSC ------------------------------------------------------------------ */
1780 static const unsigned int keysc_in5_pins[] = {
1781         /* KEYIN[0:4] */
1782         66, 67, 68, 69, 70,
1783 };
1784 static const unsigned int keysc_in5_mux[] = {
1785         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1786         KEYIN4_MARK,
1787 };
1788 static const unsigned int keysc_in6_pins[] = {
1789         /* KEYIN[0:5] */
1790         66, 67, 68, 69, 70, 71,
1791 };
1792 static const unsigned int keysc_in6_mux[] = {
1793         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1794         KEYIN4_MARK, KEYIN5_MARK,
1795 };
1796 static const unsigned int keysc_in7_pins[] = {
1797         /* KEYIN[0:6] */
1798         66, 67, 68, 69, 70, 71, 72,
1799 };
1800 static const unsigned int keysc_in7_mux[] = {
1801         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1802         KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
1803 };
1804 static const unsigned int keysc_in8_pins[] = {
1805         /* KEYIN[0:7] */
1806         66, 67, 68, 69, 70, 71, 72, 73,
1807 };
1808 static const unsigned int keysc_in8_mux[] = {
1809         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1810         KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
1811 };
1812 static const unsigned int keysc_out04_pins[] = {
1813         /* KEYOUT[0:4] */
1814         65, 64, 63, 62, 61,
1815 };
1816 static const unsigned int keysc_out04_mux[] = {
1817         KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
1818 };
1819 static const unsigned int keysc_out5_pins[] = {
1820         /* KEYOUT5 */
1821         60,
1822 };
1823 static const unsigned int keysc_out5_mux[] = {
1824         KEYOUT5_MARK,
1825 };
1826 static const unsigned int keysc_out6_0_pins[] = {
1827         /* KEYOUT6 */
1828         59,
1829 };
1830 static const unsigned int keysc_out6_0_mux[] = {
1831         PORT59_KEYOUT6_MARK,
1832 };
1833 static const unsigned int keysc_out6_1_pins[] = {
1834         /* KEYOUT6 */
1835         131,
1836 };
1837 static const unsigned int keysc_out6_1_mux[] = {
1838         PORT131_KEYOUT6_MARK,
1839 };
1840 static const unsigned int keysc_out6_2_pins[] = {
1841         /* KEYOUT6 */
1842         143,
1843 };
1844 static const unsigned int keysc_out6_2_mux[] = {
1845         PORT143_KEYOUT6_MARK,
1846 };
1847 static const unsigned int keysc_out7_0_pins[] = {
1848         /* KEYOUT7 */
1849         58,
1850 };
1851 static const unsigned int keysc_out7_0_mux[] = {
1852         PORT58_KEYOUT7_MARK,
1853 };
1854 static const unsigned int keysc_out7_1_pins[] = {
1855         /* KEYOUT7 */
1856         132,
1857 };
1858 static const unsigned int keysc_out7_1_mux[] = {
1859         PORT132_KEYOUT7_MARK,
1860 };
1861 static const unsigned int keysc_out7_2_pins[] = {
1862         /* KEYOUT7 */
1863         144,
1864 };
1865 static const unsigned int keysc_out7_2_mux[] = {
1866         PORT144_KEYOUT7_MARK,
1867 };
1868 static const unsigned int keysc_out8_0_pins[] = {
1869         /* KEYOUT8 */
1870         PIN_A11,
1871 };
1872 static const unsigned int keysc_out8_0_mux[] = {
1873         KEYOUT8_MARK,
1874 };
1875 static const unsigned int keysc_out8_1_pins[] = {
1876         /* KEYOUT8 */
1877         136,
1878 };
1879 static const unsigned int keysc_out8_1_mux[] = {
1880         PORT136_KEYOUT8_MARK,
1881 };
1882 static const unsigned int keysc_out8_2_pins[] = {
1883         /* KEYOUT8 */
1884         138,
1885 };
1886 static const unsigned int keysc_out8_2_mux[] = {
1887         PORT138_KEYOUT8_MARK,
1888 };
1889 static const unsigned int keysc_out9_0_pins[] = {
1890         /* KEYOUT9 */
1891         137,
1892 };
1893 static const unsigned int keysc_out9_0_mux[] = {
1894         PORT137_KEYOUT9_MARK,
1895 };
1896 static const unsigned int keysc_out9_1_pins[] = {
1897         /* KEYOUT9 */
1898         139,
1899 };
1900 static const unsigned int keysc_out9_1_mux[] = {
1901         PORT139_KEYOUT9_MARK,
1902 };
1903 static const unsigned int keysc_out9_2_pins[] = {
1904         /* KEYOUT9 */
1905         149,
1906 };
1907 static const unsigned int keysc_out9_2_mux[] = {
1908         PORT149_KEYOUT9_MARK,
1909 };
1910 static const unsigned int keysc_out10_0_pins[] = {
1911         /* KEYOUT10 */
1912         132,
1913 };
1914 static const unsigned int keysc_out10_0_mux[] = {
1915         PORT132_KEYOUT10_MARK,
1916 };
1917 static const unsigned int keysc_out10_1_pins[] = {
1918         /* KEYOUT10 */
1919         142,
1920 };
1921 static const unsigned int keysc_out10_1_mux[] = {
1922         PORT142_KEYOUT10_MARK,
1923 };
1924 static const unsigned int keysc_out11_0_pins[] = {
1925         /* KEYOUT11 */
1926         131,
1927 };
1928 static const unsigned int keysc_out11_0_mux[] = {
1929         PORT131_KEYOUT11_MARK,
1930 };
1931 static const unsigned int keysc_out11_1_pins[] = {
1932         /* KEYOUT11 */
1933         143,
1934 };
1935 static const unsigned int keysc_out11_1_mux[] = {
1936         PORT143_KEYOUT11_MARK,
1937 };
1938 /* - LCD -------------------------------------------------------------------- */
1939 static const unsigned int lcd_data8_pins[] = {
1940         /* D[0:7] */
1941         192, 193, 194, 195, 196, 197, 198, 199,
1942 };
1943 static const unsigned int lcd_data8_mux[] = {
1944         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1945         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1946 };
1947 static const unsigned int lcd_data9_pins[] = {
1948         /* D[0:8] */
1949         192, 193, 194, 195, 196, 197, 198, 199,
1950         200,
1951 };
1952 static const unsigned int lcd_data9_mux[] = {
1953         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1954         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1955         LCDD8_MARK,
1956 };
1957 static const unsigned int lcd_data12_pins[] = {
1958         /* D[0:11] */
1959         192, 193, 194, 195, 196, 197, 198, 199,
1960         200, 201, 202, 203,
1961 };
1962 static const unsigned int lcd_data12_mux[] = {
1963         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1964         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1965         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1966 };
1967 static const unsigned int lcd_data16_pins[] = {
1968         /* D[0:15] */
1969         192, 193, 194, 195, 196, 197, 198, 199,
1970         200, 201, 202, 203, 204, 205, 206, 207,
1971 };
1972 static const unsigned int lcd_data16_mux[] = {
1973         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1974         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1975         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1976         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1977 };
1978 static const unsigned int lcd_data18_pins[] = {
1979         /* D[0:17] */
1980         192, 193, 194, 195, 196, 197, 198, 199,
1981         200, 201, 202, 203, 204, 205, 206, 207,
1982         208, 209,
1983 };
1984 static const unsigned int lcd_data18_mux[] = {
1985         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1986         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1987         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1988         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1989         LCDD16_MARK, LCDD17_MARK,
1990 };
1991 static const unsigned int lcd_data24_pins[] = {
1992         /* D[0:23] */
1993         192, 193, 194, 195, 196, 197, 198, 199,
1994         200, 201, 202, 203, 204, 205, 206, 207,
1995         208, 209, 210, 211, 212, 213, 214, 215
1996 };
1997 static const unsigned int lcd_data24_mux[] = {
1998         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1999         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2000         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2001         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2002         LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
2003         LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
2004 };
2005 static const unsigned int lcd_display_pins[] = {
2006         /* DON */
2007         222,
2008 };
2009 static const unsigned int lcd_display_mux[] = {
2010         LCDDON_MARK,
2011 };
2012 static const unsigned int lcd_lclk_pins[] = {
2013         /* LCLK */
2014         221,
2015 };
2016 static const unsigned int lcd_lclk_mux[] = {
2017         LCDLCLK_MARK,
2018 };
2019 static const unsigned int lcd_sync_pins[] = {
2020         /* VSYN, HSYN, DCK, DISP */
2021         220, 218, 216, 219,
2022 };
2023 static const unsigned int lcd_sync_mux[] = {
2024         LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
2025 };
2026 static const unsigned int lcd_sys_pins[] = {
2027         /* CS, WR, RD, RS */
2028         218, 216, 217, 219,
2029 };
2030 static const unsigned int lcd_sys_mux[] = {
2031         LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
2032 };
2033 /* - LCD2 ------------------------------------------------------------------- */
2034 static const unsigned int lcd2_data8_pins[] = {
2035         /* D[0:7] */
2036         128, 129, 142, 143, 144, 145, 138, 139,
2037 };
2038 static const unsigned int lcd2_data8_mux[] = {
2039         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2040         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2041 };
2042 static const unsigned int lcd2_data9_pins[] = {
2043         /* D[0:8] */
2044         128, 129, 142, 143, 144, 145, 138, 139,
2045         140,
2046 };
2047 static const unsigned int lcd2_data9_mux[] = {
2048         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2049         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2050         LCD2D8_MARK,
2051 };
2052 static const unsigned int lcd2_data12_pins[] = {
2053         /* D[0:11] */
2054         128, 129, 142, 143, 144, 145, 138, 139,
2055         140, 141, 130, 131,
2056 };
2057 static const unsigned int lcd2_data12_mux[] = {
2058         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2059         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2060         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2061 };
2062 static const unsigned int lcd2_data16_pins[] = {
2063         /* D[0:15] */
2064         128, 129, 142, 143, 144, 145, 138, 139,
2065         140, 141, 130, 131, 132, 133, 134, 135,
2066 };
2067 static const unsigned int lcd2_data16_mux[] = {
2068         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2069         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2070         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2071         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2072 };
2073 static const unsigned int lcd2_data18_pins[] = {
2074         /* D[0:17] */
2075         128, 129, 142, 143, 144, 145, 138, 139,
2076         140, 141, 130, 131, 132, 133, 134, 135,
2077         136, 137,
2078 };
2079 static const unsigned int lcd2_data18_mux[] = {
2080         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2081         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2082         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2083         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2084         LCD2D16_MARK, LCD2D17_MARK,
2085 };
2086 static const unsigned int lcd2_data24_pins[] = {
2087         /* D[0:23] */
2088         128, 129, 142, 143, 144, 145, 138, 139,
2089         140, 141, 130, 131, 132, 133, 134, 135,
2090         136, 137, 146, 147, 234, 235, 238, 239
2091 };
2092 static const unsigned int lcd2_data24_mux[] = {
2093         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2094         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2095         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2096         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2097         LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
2098         LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
2099 };
2100 static const unsigned int lcd2_sync_0_pins[] = {
2101         /* VSYN, HSYN, DCK, DISP */
2102         128, 129, 146, 145,
2103 };
2104 static const unsigned int lcd2_sync_0_mux[] = {
2105         PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
2106         LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
2107 };
2108 static const unsigned int lcd2_sync_1_pins[] = {
2109         /* VSYN, HSYN, DCK, DISP */
2110         222, 221, 219, 217,
2111 };
2112 static const unsigned int lcd2_sync_1_mux[] = {
2113         PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
2114         LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
2115 };
2116 static const unsigned int lcd2_sys_0_pins[] = {
2117         /* CS, WR, RD, RS */
2118         129, 146, 147, 145,
2119 };
2120 static const unsigned int lcd2_sys_0_mux[] = {
2121         PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
2122         LCD2RD__MARK, PORT145_LCD2RS_MARK,
2123 };
2124 static const unsigned int lcd2_sys_1_pins[] = {
2125         /* CS, WR, RD, RS */
2126         221, 219, 147, 217,
2127 };
2128 static const unsigned int lcd2_sys_1_mux[] = {
2129         PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
2130         LCD2RD__MARK, PORT217_LCD2RS_MARK,
2131 };
2132 /* - MMCIF ------------------------------------------------------------------ */
2133 static const unsigned int mmc0_data1_0_pins[] = {
2134         /* D[0] */
2135         271,
2136 };
2137 static const unsigned int mmc0_data1_0_mux[] = {
2138         MMCD0_0_MARK,
2139 };
2140 static const unsigned int mmc0_data4_0_pins[] = {
2141         /* D[0:3] */
2142         271, 272, 273, 274,
2143 };
2144 static const unsigned int mmc0_data4_0_mux[] = {
2145         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2146 };
2147 static const unsigned int mmc0_data8_0_pins[] = {
2148         /* D[0:7] */
2149         271, 272, 273, 274, 275, 276, 277, 278,
2150 };
2151 static const unsigned int mmc0_data8_0_mux[] = {
2152         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2153         MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
2154 };
2155 static const unsigned int mmc0_ctrl_0_pins[] = {
2156         /* CMD, CLK */
2157         279, 270,
2158 };
2159 static const unsigned int mmc0_ctrl_0_mux[] = {
2160         MMCCMD0_MARK, MMCCLK0_MARK,
2161 };
2162
2163 static const unsigned int mmc0_data1_1_pins[] = {
2164         /* D[0] */
2165         305,
2166 };
2167 static const unsigned int mmc0_data1_1_mux[] = {
2168         MMCD1_0_MARK,
2169 };
2170 static const unsigned int mmc0_data4_1_pins[] = {
2171         /* D[0:3] */
2172         305, 304, 303, 302,
2173 };
2174 static const unsigned int mmc0_data4_1_mux[] = {
2175         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2176 };
2177 static const unsigned int mmc0_data8_1_pins[] = {
2178         /* D[0:7] */
2179         305, 304, 303, 302, 301, 300, 299, 298,
2180 };
2181 static const unsigned int mmc0_data8_1_mux[] = {
2182         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2183         MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
2184 };
2185 static const unsigned int mmc0_ctrl_1_pins[] = {
2186         /* CMD, CLK */
2187         297, 289,
2188 };
2189 static const unsigned int mmc0_ctrl_1_mux[] = {
2190         MMCCMD1_MARK, MMCCLK1_MARK,
2191 };
2192 /* - MSIOF0 ----------------------------------------------------------------- */
2193 static const unsigned int msiof0_rsck_pins[] = {
2194         /* RSCK */
2195         66,
2196 };
2197 static const unsigned int msiof0_rsck_mux[] = {
2198         MSIOF0_RSCK_MARK,
2199 };
2200 static const unsigned int msiof0_tsck_pins[] = {
2201         /* TSCK */
2202         64,
2203 };
2204 static const unsigned int msiof0_tsck_mux[] = {
2205         MSIOF0_TSCK_MARK,
2206 };
2207 static const unsigned int msiof0_rsync_pins[] = {
2208         /* RSYNC */
2209         67,
2210 };
2211 static const unsigned int msiof0_rsync_mux[] = {
2212         MSIOF0_RSYNC_MARK,
2213 };
2214 static const unsigned int msiof0_tsync_pins[] = {
2215         /* TSYNC */
2216         63,
2217 };
2218 static const unsigned int msiof0_tsync_mux[] = {
2219         MSIOF0_TSYNC_MARK,
2220 };
2221 static const unsigned int msiof0_ss1_pins[] = {
2222         /* SS1 */
2223         62,
2224 };
2225 static const unsigned int msiof0_ss1_mux[] = {
2226         MSIOF0_SS1_MARK,
2227 };
2228 static const unsigned int msiof0_ss2_pins[] = {
2229         /* SS2 */
2230         71,
2231 };
2232 static const unsigned int msiof0_ss2_mux[] = {
2233         MSIOF0_SS2_MARK,
2234 };
2235 static const unsigned int msiof0_rxd_pins[] = {
2236         /* RXD */
2237         70,
2238 };
2239 static const unsigned int msiof0_rxd_mux[] = {
2240         MSIOF0_RXD_MARK,
2241 };
2242 static const unsigned int msiof0_txd_pins[] = {
2243         /* TXD */
2244         65,
2245 };
2246 static const unsigned int msiof0_txd_mux[] = {
2247         MSIOF0_TXD_MARK,
2248 };
2249 static const unsigned int msiof0_mck0_pins[] = {
2250         /* MSCK0 */
2251         68,
2252 };
2253 static const unsigned int msiof0_mck0_mux[] = {
2254         MSIOF0_MCK0_MARK,
2255 };
2256
2257 static const unsigned int msiof0_mck1_pins[] = {
2258         /* MSCK1 */
2259         69,
2260 };
2261 static const unsigned int msiof0_mck1_mux[] = {
2262         MSIOF0_MCK1_MARK,
2263 };
2264
2265 static const unsigned int msiof0l_rsck_pins[] = {
2266         /* RSCK */
2267         214,
2268 };
2269 static const unsigned int msiof0l_rsck_mux[] = {
2270         MSIOF0L_RSCK_MARK,
2271 };
2272 static const unsigned int msiof0l_tsck_pins[] = {
2273         /* TSCK */
2274         219,
2275 };
2276 static const unsigned int msiof0l_tsck_mux[] = {
2277         MSIOF0L_TSCK_MARK,
2278 };
2279 static const unsigned int msiof0l_rsync_pins[] = {
2280         /* RSYNC */
2281         215,
2282 };
2283 static const unsigned int msiof0l_rsync_mux[] = {
2284         MSIOF0L_RSYNC_MARK,
2285 };
2286 static const unsigned int msiof0l_tsync_pins[] = {
2287         /* TSYNC */
2288         217,
2289 };
2290 static const unsigned int msiof0l_tsync_mux[] = {
2291         MSIOF0L_TSYNC_MARK,
2292 };
2293 static const unsigned int msiof0l_ss1_a_pins[] = {
2294         /* SS1 */
2295         207,
2296 };
2297 static const unsigned int msiof0l_ss1_a_mux[] = {
2298         PORT207_MSIOF0L_SS1_MARK,
2299 };
2300 static const unsigned int msiof0l_ss1_b_pins[] = {
2301         /* SS1 */
2302         210,
2303 };
2304 static const unsigned int msiof0l_ss1_b_mux[] = {
2305         PORT210_MSIOF0L_SS1_MARK,
2306 };
2307 static const unsigned int msiof0l_ss2_a_pins[] = {
2308         /* SS2 */
2309         208,
2310 };
2311 static const unsigned int msiof0l_ss2_a_mux[] = {
2312         PORT208_MSIOF0L_SS2_MARK,
2313 };
2314 static const unsigned int msiof0l_ss2_b_pins[] = {
2315         /* SS2 */
2316         211,
2317 };
2318 static const unsigned int msiof0l_ss2_b_mux[] = {
2319         PORT211_MSIOF0L_SS2_MARK,
2320 };
2321 static const unsigned int msiof0l_rxd_pins[] = {
2322         /* RXD */
2323         221,
2324 };
2325 static const unsigned int msiof0l_rxd_mux[] = {
2326         MSIOF0L_RXD_MARK,
2327 };
2328 static const unsigned int msiof0l_txd_pins[] = {
2329         /* TXD */
2330         222,
2331 };
2332 static const unsigned int msiof0l_txd_mux[] = {
2333         MSIOF0L_TXD_MARK,
2334 };
2335 static const unsigned int msiof0l_mck0_pins[] = {
2336         /* MSCK0 */
2337         212,
2338 };
2339 static const unsigned int msiof0l_mck0_mux[] = {
2340         MSIOF0L_MCK0_MARK,
2341 };
2342 static const unsigned int msiof0l_mck1_pins[] = {
2343         /* MSCK1 */
2344         213,
2345 };
2346 static const unsigned int msiof0l_mck1_mux[] = {
2347         MSIOF0L_MCK1_MARK,
2348 };
2349 /* - MSIOF1 ----------------------------------------------------------------- */
2350 static const unsigned int msiof1_rsck_pins[] = {
2351         /* RSCK */
2352         234,
2353 };
2354 static const unsigned int msiof1_rsck_mux[] = {
2355         MSIOF1_RSCK_MARK,
2356 };
2357 static const unsigned int msiof1_tsck_pins[] = {
2358         /* TSCK */
2359         232,
2360 };
2361 static const unsigned int msiof1_tsck_mux[] = {
2362         MSIOF1_TSCK_MARK,
2363 };
2364 static const unsigned int msiof1_rsync_pins[] = {
2365         /* RSYNC */
2366         235,
2367 };
2368 static const unsigned int msiof1_rsync_mux[] = {
2369         MSIOF1_RSYNC_MARK,
2370 };
2371 static const unsigned int msiof1_tsync_pins[] = {
2372         /* TSYNC */
2373         231,
2374 };
2375 static const unsigned int msiof1_tsync_mux[] = {
2376         MSIOF1_TSYNC_MARK,
2377 };
2378 static const unsigned int msiof1_ss1_pins[] = {
2379         /* SS1 */
2380         238,
2381 };
2382 static const unsigned int msiof1_ss1_mux[] = {
2383         MSIOF1_SS1_MARK,
2384 };
2385 static const unsigned int msiof1_ss2_pins[] = {
2386         /* SS2 */
2387         239,
2388 };
2389 static const unsigned int msiof1_ss2_mux[] = {
2390         MSIOF1_SS2_MARK,
2391 };
2392 static const unsigned int msiof1_rxd_pins[] = {
2393         /* RXD */
2394         233,
2395 };
2396 static const unsigned int msiof1_rxd_mux[] = {
2397         MSIOF1_RXD_MARK,
2398 };
2399 static const unsigned int msiof1_txd_pins[] = {
2400         /* TXD */
2401         230,
2402 };
2403 static const unsigned int msiof1_txd_mux[] = {
2404         MSIOF1_TXD_MARK,
2405 };
2406 static const unsigned int msiof1_mck0_pins[] = {
2407         /* MSCK0 */
2408         236,
2409 };
2410 static const unsigned int msiof1_mck0_mux[] = {
2411         MSIOF1_MCK0_MARK,
2412 };
2413 static const unsigned int msiof1_mck1_pins[] = {
2414         /* MSCK1 */
2415         237,
2416 };
2417 static const unsigned int msiof1_mck1_mux[] = {
2418         MSIOF1_MCK1_MARK,
2419 };
2420 /* - MSIOF2 ----------------------------------------------------------------- */
2421 static const unsigned int msiof2_rsck_pins[] = {
2422         /* RSCK */
2423         151,
2424 };
2425 static const unsigned int msiof2_rsck_mux[] = {
2426         MSIOF2_RSCK_MARK,
2427 };
2428 static const unsigned int msiof2_tsck_pins[] = {
2429         /* TSCK */
2430         135,
2431 };
2432 static const unsigned int msiof2_tsck_mux[] = {
2433         MSIOF2_TSCK_MARK,
2434 };
2435 static const unsigned int msiof2_rsync_pins[] = {
2436         /* RSYNC */
2437         152,
2438 };
2439 static const unsigned int msiof2_rsync_mux[] = {
2440         MSIOF2_RSYNC_MARK,
2441 };
2442 static const unsigned int msiof2_tsync_pins[] = {
2443         /* TSYNC */
2444         133,
2445 };
2446 static const unsigned int msiof2_tsync_mux[] = {
2447         MSIOF2_TSYNC_MARK,
2448 };
2449 static const unsigned int msiof2_ss1_a_pins[] = {
2450         /* SS1 */
2451         131,
2452 };
2453 static const unsigned int msiof2_ss1_a_mux[] = {
2454         PORT131_MSIOF2_SS1_MARK,
2455 };
2456 static const unsigned int msiof2_ss1_b_pins[] = {
2457         /* SS1 */
2458         153,
2459 };
2460 static const unsigned int msiof2_ss1_b_mux[] = {
2461         PORT153_MSIOF2_SS1_MARK,
2462 };
2463 static const unsigned int msiof2_ss2_a_pins[] = {
2464         /* SS2 */
2465         132,
2466 };
2467 static const unsigned int msiof2_ss2_a_mux[] = {
2468         PORT132_MSIOF2_SS2_MARK,
2469 };
2470 static const unsigned int msiof2_ss2_b_pins[] = {
2471         /* SS2 */
2472         156,
2473 };
2474 static const unsigned int msiof2_ss2_b_mux[] = {
2475         PORT156_MSIOF2_SS2_MARK,
2476 };
2477 static const unsigned int msiof2_rxd_a_pins[] = {
2478         /* RXD */
2479         130,
2480 };
2481 static const unsigned int msiof2_rxd_a_mux[] = {
2482         PORT130_MSIOF2_RXD_MARK,
2483 };
2484 static const unsigned int msiof2_rxd_b_pins[] = {
2485         /* RXD */
2486         157,
2487 };
2488 static const unsigned int msiof2_rxd_b_mux[] = {
2489         PORT157_MSIOF2_RXD_MARK,
2490 };
2491 static const unsigned int msiof2_txd_pins[] = {
2492         /* TXD */
2493         134,
2494 };
2495 static const unsigned int msiof2_txd_mux[] = {
2496         MSIOF2_TXD_MARK,
2497 };
2498 static const unsigned int msiof2_mck0_pins[] = {
2499         /* MSCK0 */
2500         154,
2501 };
2502 static const unsigned int msiof2_mck0_mux[] = {
2503         MSIOF2_MCK0_MARK,
2504 };
2505 static const unsigned int msiof2_mck1_pins[] = {
2506         /* MSCK1 */
2507         155,
2508 };
2509 static const unsigned int msiof2_mck1_mux[] = {
2510         MSIOF2_MCK1_MARK,
2511 };
2512
2513 static const unsigned int msiof2r_tsck_pins[] = {
2514         /* TSCK */
2515         248,
2516 };
2517 static const unsigned int msiof2r_tsck_mux[] = {
2518         MSIOF2R_TSCK_MARK,
2519 };
2520 static const unsigned int msiof2r_tsync_pins[] = {
2521         /* TSYNC */
2522         249,
2523 };
2524 static const unsigned int msiof2r_tsync_mux[] = {
2525         MSIOF2R_TSYNC_MARK,
2526 };
2527 static const unsigned int msiof2r_rxd_pins[] = {
2528         /* RXD */
2529         244,
2530 };
2531 static const unsigned int msiof2r_rxd_mux[] = {
2532         MSIOF2R_RXD_MARK,
2533 };
2534 static const unsigned int msiof2r_txd_pins[] = {
2535         /* TXD */
2536         245,
2537 };
2538 static const unsigned int msiof2r_txd_mux[] = {
2539         MSIOF2R_TXD_MARK,
2540 };
2541 /* - MSIOF3 (Pin function name of MSIOF3 is named BBIF1) -------------------- */
2542 static const unsigned int msiof3_rsck_pins[] = {
2543         /* RSCK */
2544         115,
2545 };
2546 static const unsigned int msiof3_rsck_mux[] = {
2547         BBIF1_RSCK_MARK,
2548 };
2549 static const unsigned int msiof3_tsck_pins[] = {
2550         /* TSCK */
2551         112,
2552 };
2553 static const unsigned int msiof3_tsck_mux[] = {
2554         BBIF1_TSCK_MARK,
2555 };
2556 static const unsigned int msiof3_rsync_pins[] = {
2557         /* RSYNC */
2558         116,
2559 };
2560 static const unsigned int msiof3_rsync_mux[] = {
2561         BBIF1_RSYNC_MARK,
2562 };
2563 static const unsigned int msiof3_tsync_pins[] = {
2564         /* TSYNC */
2565         113,
2566 };
2567 static const unsigned int msiof3_tsync_mux[] = {
2568         BBIF1_TSYNC_MARK,
2569 };
2570 static const unsigned int msiof3_ss1_pins[] = {
2571         /* SS1 */
2572         117,
2573 };
2574 static const unsigned int msiof3_ss1_mux[] = {
2575         BBIF1_SS1_MARK,
2576 };
2577 static const unsigned int msiof3_ss2_pins[] = {
2578         /* SS2 */
2579         109,
2580 };
2581 static const unsigned int msiof3_ss2_mux[] = {
2582         BBIF1_SS2_MARK,
2583 };
2584 static const unsigned int msiof3_rxd_pins[] = {
2585         /* RXD */
2586         111,
2587 };
2588 static const unsigned int msiof3_rxd_mux[] = {
2589         BBIF1_RXD_MARK,
2590 };
2591 static const unsigned int msiof3_txd_pins[] = {
2592         /* TXD */
2593         114,
2594 };
2595 static const unsigned int msiof3_txd_mux[] = {
2596         BBIF1_TXD_MARK,
2597 };
2598 static const unsigned int msiof3_flow_pins[] = {
2599         /* FLOW */
2600         117,
2601 };
2602 static const unsigned int msiof3_flow_mux[] = {
2603         BBIF1_FLOW_MARK,
2604 };
2605
2606 /* - SCIFA0 ----------------------------------------------------------------- */
2607 static const unsigned int scifa0_data_pins[] = {
2608         /* RXD, TXD */
2609         43, 17,
2610 };
2611 static const unsigned int scifa0_data_mux[] = {
2612         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2613 };
2614 static const unsigned int scifa0_clk_pins[] = {
2615         /* SCK */
2616         16,
2617 };
2618 static const unsigned int scifa0_clk_mux[] = {
2619         SCIFA0_SCK_MARK,
2620 };
2621 static const unsigned int scifa0_ctrl_pins[] = {
2622         /* RTS, CTS */
2623         42, 44,
2624 };
2625 static const unsigned int scifa0_ctrl_mux[] = {
2626         SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
2627 };
2628 /* - SCIFA1 ----------------------------------------------------------------- */
2629 static const unsigned int scifa1_data_pins[] = {
2630         /* RXD, TXD */
2631         228, 225,
2632 };
2633 static const unsigned int scifa1_data_mux[] = {
2634         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2635 };
2636 static const unsigned int scifa1_clk_pins[] = {
2637         /* SCK */
2638         226,
2639 };
2640 static const unsigned int scifa1_clk_mux[] = {
2641         SCIFA1_SCK_MARK,
2642 };
2643 static const unsigned int scifa1_ctrl_pins[] = {
2644         /* RTS, CTS */
2645         227, 229,
2646 };
2647 static const unsigned int scifa1_ctrl_mux[] = {
2648         SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
2649 };
2650 /* - SCIFA2 ----------------------------------------------------------------- */
2651 static const unsigned int scifa2_data_0_pins[] = {
2652         /* RXD, TXD */
2653         155, 154,
2654 };
2655 static const unsigned int scifa2_data_0_mux[] = {
2656         SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
2657 };
2658 static const unsigned int scifa2_clk_0_pins[] = {
2659         /* SCK */
2660         158,
2661 };
2662 static const unsigned int scifa2_clk_0_mux[] = {
2663         SCIFA2_SCK1_MARK,
2664 };
2665 static const unsigned int scifa2_ctrl_0_pins[] = {
2666         /* RTS, CTS */
2667         156, 157,
2668 };
2669 static const unsigned int scifa2_ctrl_0_mux[] = {
2670         SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
2671 };
2672 static const unsigned int scifa2_data_1_pins[] = {
2673         /* RXD, TXD */
2674         233, 230,
2675 };
2676 static const unsigned int scifa2_data_1_mux[] = {
2677         SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
2678 };
2679 static const unsigned int scifa2_clk_1_pins[] = {
2680         /* SCK */
2681         232,
2682 };
2683 static const unsigned int scifa2_clk_1_mux[] = {
2684         SCIFA2_SCK2_MARK,
2685 };
2686 static const unsigned int scifa2_ctrl_1_pins[] = {
2687         /* RTS, CTS */
2688         234, 231,
2689 };
2690 static const unsigned int scifa2_ctrl_1_mux[] = {
2691         SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
2692 };
2693 /* - SCIFA3 ----------------------------------------------------------------- */
2694 static const unsigned int scifa3_data_pins[] = {
2695         /* RXD, TXD */
2696         108, 110,
2697 };
2698 static const unsigned int scifa3_data_mux[] = {
2699         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2700 };
2701 static const unsigned int scifa3_ctrl_pins[] = {
2702         /* RTS, CTS */
2703         109, 107,
2704 };
2705 static const unsigned int scifa3_ctrl_mux[] = {
2706         SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
2707 };
2708 /* - SCIFA4 ----------------------------------------------------------------- */
2709 static const unsigned int scifa4_data_pins[] = {
2710         /* RXD, TXD */
2711         33, 32,
2712 };
2713 static const unsigned int scifa4_data_mux[] = {
2714         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2715 };
2716 static const unsigned int scifa4_ctrl_pins[] = {
2717         /* RTS, CTS */
2718         34, 35,
2719 };
2720 static const unsigned int scifa4_ctrl_mux[] = {
2721         SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
2722 };
2723 /* - SCIFA5 ----------------------------------------------------------------- */
2724 static const unsigned int scifa5_data_0_pins[] = {
2725         /* RXD, TXD */
2726         246, 247,
2727 };
2728 static const unsigned int scifa5_data_0_mux[] = {
2729         PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
2730 };
2731 static const unsigned int scifa5_clk_0_pins[] = {
2732         /* SCK */
2733         248,
2734 };
2735 static const unsigned int scifa5_clk_0_mux[] = {
2736         PORT248_SCIFA5_SCK_MARK,
2737 };
2738 static const unsigned int scifa5_ctrl_0_pins[] = {
2739         /* RTS, CTS */
2740         245, 244,
2741 };
2742 static const unsigned int scifa5_ctrl_0_mux[] = {
2743         PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
2744 };
2745 static const unsigned int scifa5_data_1_pins[] = {
2746         /* RXD, TXD */
2747         195, 196,
2748 };
2749 static const unsigned int scifa5_data_1_mux[] = {
2750         PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
2751 };
2752 static const unsigned int scifa5_clk_1_pins[] = {
2753         /* SCK */
2754         197,
2755 };
2756 static const unsigned int scifa5_clk_1_mux[] = {
2757         PORT197_SCIFA5_SCK_MARK,
2758 };
2759 static const unsigned int scifa5_ctrl_1_pins[] = {
2760         /* RTS, CTS */
2761         194, 193,
2762 };
2763 static const unsigned int scifa5_ctrl_1_mux[] = {
2764         PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
2765 };
2766 static const unsigned int scifa5_data_2_pins[] = {
2767         /* RXD, TXD */
2768         162, 160,
2769 };
2770 static const unsigned int scifa5_data_2_mux[] = {
2771         PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
2772 };
2773 static const unsigned int scifa5_clk_2_pins[] = {
2774         /* SCK */
2775         159,
2776 };
2777 static const unsigned int scifa5_clk_2_mux[] = {
2778         PORT159_SCIFA5_SCK_MARK,
2779 };
2780 static const unsigned int scifa5_ctrl_2_pins[] = {
2781         /* RTS, CTS */
2782         163, 161,
2783 };
2784 static const unsigned int scifa5_ctrl_2_mux[] = {
2785         PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
2786 };
2787 /* - SCIFA6 ----------------------------------------------------------------- */
2788 static const unsigned int scifa6_pins[] = {
2789         /* TXD */
2790         240,
2791 };
2792 static const unsigned int scifa6_mux[] = {
2793         SCIFA6_TXD_MARK,
2794 };
2795 /* - SCIFA7 ----------------------------------------------------------------- */
2796 static const unsigned int scifa7_data_pins[] = {
2797         /* RXD, TXD */
2798         12, 18,
2799 };
2800 static const unsigned int scifa7_data_mux[] = {
2801         SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2802 };
2803 static const unsigned int scifa7_ctrl_pins[] = {
2804         /* RTS, CTS */
2805         19, 13,
2806 };
2807 static const unsigned int scifa7_ctrl_mux[] = {
2808         SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
2809 };
2810 /* - SCIFB ------------------------------------------------------------------ */
2811 static const unsigned int scifb_data_0_pins[] = {
2812         /* RXD, TXD */
2813         162, 160,
2814 };
2815 static const unsigned int scifb_data_0_mux[] = {
2816         PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
2817 };
2818 static const unsigned int scifb_clk_0_pins[] = {
2819         /* SCK */
2820         159,
2821 };
2822 static const unsigned int scifb_clk_0_mux[] = {
2823         PORT159_SCIFB_SCK_MARK,
2824 };
2825 static const unsigned int scifb_ctrl_0_pins[] = {
2826         /* RTS, CTS */
2827         163, 161,
2828 };
2829 static const unsigned int scifb_ctrl_0_mux[] = {
2830         PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
2831 };
2832 static const unsigned int scifb_data_1_pins[] = {
2833         /* RXD, TXD */
2834         246, 247,
2835 };
2836 static const unsigned int scifb_data_1_mux[] = {
2837         PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
2838 };
2839 static const unsigned int scifb_clk_1_pins[] = {
2840         /* SCK */
2841         248,
2842 };
2843 static const unsigned int scifb_clk_1_mux[] = {
2844         PORT248_SCIFB_SCK_MARK,
2845 };
2846 static const unsigned int scifb_ctrl_1_pins[] = {
2847         /* RTS, CTS */
2848         245, 244,
2849 };
2850 static const unsigned int scifb_ctrl_1_mux[] = {
2851         PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
2852 };
2853 /* - SDHI0 ------------------------------------------------------------------ */
2854 static const unsigned int sdhi0_data1_pins[] = {
2855         /* D0 */
2856         252,
2857 };
2858 static const unsigned int sdhi0_data1_mux[] = {
2859         SDHID0_0_MARK,
2860 };
2861 static const unsigned int sdhi0_data4_pins[] = {
2862         /* D[0:3] */
2863         252, 253, 254, 255,
2864 };
2865 static const unsigned int sdhi0_data4_mux[] = {
2866         SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
2867 };
2868 static const unsigned int sdhi0_ctrl_pins[] = {
2869         /* CMD, CLK */
2870         256, 250,
2871 };
2872 static const unsigned int sdhi0_ctrl_mux[] = {
2873         SDHICMD0_MARK, SDHICLK0_MARK,
2874 };
2875 static const unsigned int sdhi0_cd_pins[] = {
2876         /* CD */
2877         251,
2878 };
2879 static const unsigned int sdhi0_cd_mux[] = {
2880         SDHICD0_MARK,
2881 };
2882 static const unsigned int sdhi0_wp_pins[] = {
2883         /* WP */
2884         257,
2885 };
2886 static const unsigned int sdhi0_wp_mux[] = {
2887         SDHIWP0_MARK,
2888 };
2889 /* - SDHI1 ------------------------------------------------------------------ */
2890 static const unsigned int sdhi1_data1_pins[] = {
2891         /* D0 */
2892         259,
2893 };
2894 static const unsigned int sdhi1_data1_mux[] = {
2895         SDHID1_0_MARK,
2896 };
2897 static const unsigned int sdhi1_data4_pins[] = {
2898         /* D[0:3] */
2899         259, 260, 261, 262,
2900 };
2901 static const unsigned int sdhi1_data4_mux[] = {
2902         SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
2903 };
2904 static const unsigned int sdhi1_ctrl_pins[] = {
2905         /* CMD, CLK */
2906         263, 258,
2907 };
2908 static const unsigned int sdhi1_ctrl_mux[] = {
2909         SDHICMD1_MARK, SDHICLK1_MARK,
2910 };
2911 /* - SDHI2 ------------------------------------------------------------------ */
2912 static const unsigned int sdhi2_data1_pins[] = {
2913         /* D0 */
2914         265,
2915 };
2916 static const unsigned int sdhi2_data1_mux[] = {
2917         SDHID2_0_MARK,
2918 };
2919 static const unsigned int sdhi2_data4_pins[] = {
2920         /* D[0:3] */
2921         265, 266, 267, 268,
2922 };
2923 static const unsigned int sdhi2_data4_mux[] = {
2924         SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
2925 };
2926 static const unsigned int sdhi2_ctrl_pins[] = {
2927         /* CMD, CLK */
2928         269, 264,
2929 };
2930 static const unsigned int sdhi2_ctrl_mux[] = {
2931         SDHICMD2_MARK, SDHICLK2_MARK,
2932 };
2933 /* - TPU0 ------------------------------------------------------------------- */
2934 static const unsigned int tpu0_to0_pins[] = {
2935         /* TO */
2936         55,
2937 };
2938 static const unsigned int tpu0_to0_mux[] = {
2939         TPU0TO0_MARK,
2940 };
2941 static const unsigned int tpu0_to1_pins[] = {
2942         /* TO */
2943         59,
2944 };
2945 static const unsigned int tpu0_to1_mux[] = {
2946         TPU0TO1_MARK,
2947 };
2948 static const unsigned int tpu0_to2_pins[] = {
2949         /* TO */
2950         140,
2951 };
2952 static const unsigned int tpu0_to2_mux[] = {
2953         TPU0TO2_MARK,
2954 };
2955 static const unsigned int tpu0_to3_pins[] = {
2956         /* TO */
2957         141,
2958 };
2959 static const unsigned int tpu0_to3_mux[] = {
2960         TPU0TO3_MARK,
2961 };
2962 /* - TPU1 ------------------------------------------------------------------- */
2963 static const unsigned int tpu1_to0_pins[] = {
2964         /* TO */
2965         246,
2966 };
2967 static const unsigned int tpu1_to0_mux[] = {
2968         TPU1TO0_MARK,
2969 };
2970 static const unsigned int tpu1_to1_0_pins[] = {
2971         /* TO */
2972         28,
2973 };
2974 static const unsigned int tpu1_to1_0_mux[] = {
2975         PORT28_TPU1TO1_MARK,
2976 };
2977 static const unsigned int tpu1_to1_1_pins[] = {
2978         /* TO */
2979         29,
2980 };
2981 static const unsigned int tpu1_to1_1_mux[] = {
2982         PORT29_TPU1TO1_MARK,
2983 };
2984 static const unsigned int tpu1_to2_pins[] = {
2985         /* TO */
2986         153,
2987 };
2988 static const unsigned int tpu1_to2_mux[] = {
2989         TPU1TO2_MARK,
2990 };
2991 static const unsigned int tpu1_to3_pins[] = {
2992         /* TO */
2993         145,
2994 };
2995 static const unsigned int tpu1_to3_mux[] = {
2996         TPU1TO3_MARK,
2997 };
2998 /* - TPU2 ------------------------------------------------------------------- */
2999 static const unsigned int tpu2_to0_pins[] = {
3000         /* TO */
3001         248,
3002 };
3003 static const unsigned int tpu2_to0_mux[] = {
3004         TPU2TO0_MARK,
3005 };
3006 static const unsigned int tpu2_to1_pins[] = {
3007         /* TO */
3008         197,
3009 };
3010 static const unsigned int tpu2_to1_mux[] = {
3011         TPU2TO1_MARK,
3012 };
3013 static const unsigned int tpu2_to2_pins[] = {
3014         /* TO */
3015         50,
3016 };
3017 static const unsigned int tpu2_to2_mux[] = {
3018         TPU2TO2_MARK,
3019 };
3020 static const unsigned int tpu2_to3_pins[] = {
3021         /* TO */
3022         51,
3023 };
3024 static const unsigned int tpu2_to3_mux[] = {
3025         TPU2TO3_MARK,
3026 };
3027 /* - TPU3 ------------------------------------------------------------------- */
3028 static const unsigned int tpu3_to0_pins[] = {
3029         /* TO */
3030         163,
3031 };
3032 static const unsigned int tpu3_to0_mux[] = {
3033         TPU3TO0_MARK,
3034 };
3035 static const unsigned int tpu3_to1_pins[] = {
3036         /* TO */
3037         247,
3038 };
3039 static const unsigned int tpu3_to1_mux[] = {
3040         TPU3TO1_MARK,
3041 };
3042 static const unsigned int tpu3_to2_pins[] = {
3043         /* TO */
3044         54,
3045 };
3046 static const unsigned int tpu3_to2_mux[] = {
3047         TPU3TO2_MARK,
3048 };
3049 static const unsigned int tpu3_to3_pins[] = {
3050         /* TO */
3051         53,
3052 };
3053 static const unsigned int tpu3_to3_mux[] = {
3054         TPU3TO3_MARK,
3055 };
3056 /* - TPU4 ------------------------------------------------------------------- */
3057 static const unsigned int tpu4_to0_pins[] = {
3058         /* TO */
3059         241,
3060 };
3061 static const unsigned int tpu4_to0_mux[] = {
3062         TPU4TO0_MARK,
3063 };
3064 static const unsigned int tpu4_to1_pins[] = {
3065         /* TO */
3066         199,
3067 };
3068 static const unsigned int tpu4_to1_mux[] = {
3069         TPU4TO1_MARK,
3070 };
3071 static const unsigned int tpu4_to2_pins[] = {
3072         /* TO */
3073         58,
3074 };
3075 static const unsigned int tpu4_to2_mux[] = {
3076         TPU4TO2_MARK,
3077 };
3078 static const unsigned int tpu4_to3_pins[] = {
3079         /* TO */
3080         PIN_A11,
3081 };
3082 static const unsigned int tpu4_to3_mux[] = {
3083         TPU4TO3_MARK,
3084 };
3085 /* - USB -------------------------------------------------------------------- */
3086 static const unsigned int usb_vbus_pins[] = {
3087         /* VBUS */
3088         0,
3089 };
3090 static const unsigned int usb_vbus_mux[] = {
3091         VBUS_0_MARK,
3092 };
3093
3094 static const struct sh_pfc_pin_group pinmux_groups[] = {
3095         SH_PFC_PIN_GROUP(bsc_data_0_7),
3096         SH_PFC_PIN_GROUP(bsc_data_8_15),
3097         SH_PFC_PIN_GROUP(bsc_cs4),
3098         SH_PFC_PIN_GROUP(bsc_cs5_a),
3099         SH_PFC_PIN_GROUP(bsc_cs5_b),
3100         SH_PFC_PIN_GROUP(bsc_cs6_a),
3101         SH_PFC_PIN_GROUP(bsc_cs6_b),
3102         SH_PFC_PIN_GROUP(bsc_rd),
3103         SH_PFC_PIN_GROUP(bsc_rdwr_0),
3104         SH_PFC_PIN_GROUP(bsc_rdwr_1),
3105         SH_PFC_PIN_GROUP(bsc_rdwr_2),
3106         SH_PFC_PIN_GROUP(bsc_we0),
3107         SH_PFC_PIN_GROUP(bsc_we1),
3108         SH_PFC_PIN_GROUP(fsia_mclk_in),
3109         SH_PFC_PIN_GROUP(fsia_mclk_out),
3110         SH_PFC_PIN_GROUP(fsia_sclk_in),
3111         SH_PFC_PIN_GROUP(fsia_sclk_out),
3112         SH_PFC_PIN_GROUP(fsia_data_in),
3113         SH_PFC_PIN_GROUP(fsia_data_out),
3114         SH_PFC_PIN_GROUP(fsia_spdif),
3115         SH_PFC_PIN_GROUP(fsib_mclk_in),
3116         SH_PFC_PIN_GROUP(fsib_mclk_out),
3117         SH_PFC_PIN_GROUP(fsib_sclk_in),
3118         SH_PFC_PIN_GROUP(fsib_sclk_out),
3119         SH_PFC_PIN_GROUP(fsib_data_in),
3120         SH_PFC_PIN_GROUP(fsib_data_out),
3121         SH_PFC_PIN_GROUP(fsib_spdif),
3122         SH_PFC_PIN_GROUP(fsic_mclk_in),
3123         SH_PFC_PIN_GROUP(fsic_mclk_out),
3124         SH_PFC_PIN_GROUP(fsic_sclk_in),
3125         SH_PFC_PIN_GROUP(fsic_sclk_out),
3126         SH_PFC_PIN_GROUP(fsic_data_in),
3127         SH_PFC_PIN_GROUP(fsic_data_out),
3128         SH_PFC_PIN_GROUP(fsic_spdif_0),
3129         SH_PFC_PIN_GROUP(fsic_spdif_1),
3130         SH_PFC_PIN_GROUP(fsid_sclk_in),
3131         SH_PFC_PIN_GROUP(fsid_sclk_out),
3132         SH_PFC_PIN_GROUP(fsid_data_in),
3133         SH_PFC_PIN_GROUP(i2c2_0),
3134         SH_PFC_PIN_GROUP(i2c2_1),
3135         SH_PFC_PIN_GROUP(i2c2_2),
3136         SH_PFC_PIN_GROUP(i2c3_0),
3137         SH_PFC_PIN_GROUP(i2c3_1),
3138         SH_PFC_PIN_GROUP(i2c3_2),
3139         SH_PFC_PIN_GROUP(irda_0),
3140         SH_PFC_PIN_GROUP(irda_1),
3141         SH_PFC_PIN_GROUP(keysc_in5),
3142         SH_PFC_PIN_GROUP(keysc_in6),
3143         SH_PFC_PIN_GROUP(keysc_in7),
3144         SH_PFC_PIN_GROUP(keysc_in8),
3145         SH_PFC_PIN_GROUP(keysc_out04),
3146         SH_PFC_PIN_GROUP(keysc_out5),
3147         SH_PFC_PIN_GROUP(keysc_out6_0),
3148         SH_PFC_PIN_GROUP(keysc_out6_1),
3149         SH_PFC_PIN_GROUP(keysc_out6_2),
3150         SH_PFC_PIN_GROUP(keysc_out7_0),
3151         SH_PFC_PIN_GROUP(keysc_out7_1),
3152         SH_PFC_PIN_GROUP(keysc_out7_2),
3153         SH_PFC_PIN_GROUP(keysc_out8_0),
3154         SH_PFC_PIN_GROUP(keysc_out8_1),
3155         SH_PFC_PIN_GROUP(keysc_out8_2),
3156         SH_PFC_PIN_GROUP(keysc_out9_0),
3157         SH_PFC_PIN_GROUP(keysc_out9_1),
3158         SH_PFC_PIN_GROUP(keysc_out9_2),
3159         SH_PFC_PIN_GROUP(keysc_out10_0),
3160         SH_PFC_PIN_GROUP(keysc_out10_1),
3161         SH_PFC_PIN_GROUP(keysc_out11_0),
3162         SH_PFC_PIN_GROUP(keysc_out11_1),
3163         SH_PFC_PIN_GROUP(lcd_data8),
3164         SH_PFC_PIN_GROUP(lcd_data9),
3165         SH_PFC_PIN_GROUP(lcd_data12),
3166         SH_PFC_PIN_GROUP(lcd_data16),
3167         SH_PFC_PIN_GROUP(lcd_data18),
3168         SH_PFC_PIN_GROUP(lcd_data24),
3169         SH_PFC_PIN_GROUP(lcd_display),
3170         SH_PFC_PIN_GROUP(lcd_lclk),
3171         SH_PFC_PIN_GROUP(lcd_sync),
3172         SH_PFC_PIN_GROUP(lcd_sys),
3173         SH_PFC_PIN_GROUP(lcd2_data8),
3174         SH_PFC_PIN_GROUP(lcd2_data9),
3175         SH_PFC_PIN_GROUP(lcd2_data12),
3176         SH_PFC_PIN_GROUP(lcd2_data16),
3177         SH_PFC_PIN_GROUP(lcd2_data18),
3178         SH_PFC_PIN_GROUP(lcd2_data24),
3179         SH_PFC_PIN_GROUP(lcd2_sync_0),
3180         SH_PFC_PIN_GROUP(lcd2_sync_1),
3181         SH_PFC_PIN_GROUP(lcd2_sys_0),
3182         SH_PFC_PIN_GROUP(lcd2_sys_1),
3183         SH_PFC_PIN_GROUP(mmc0_data1_0),
3184         SH_PFC_PIN_GROUP(mmc0_data4_0),
3185         SH_PFC_PIN_GROUP(mmc0_data8_0),
3186         SH_PFC_PIN_GROUP(mmc0_ctrl_0),
3187         SH_PFC_PIN_GROUP(mmc0_data1_1),
3188         SH_PFC_PIN_GROUP(mmc0_data4_1),
3189         SH_PFC_PIN_GROUP(mmc0_data8_1),
3190         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
3191         SH_PFC_PIN_GROUP(msiof0_rsck),
3192         SH_PFC_PIN_GROUP(msiof0_tsck),
3193         SH_PFC_PIN_GROUP(msiof0_rsync),
3194         SH_PFC_PIN_GROUP(msiof0_tsync),
3195         SH_PFC_PIN_GROUP(msiof0_ss1),
3196         SH_PFC_PIN_GROUP(msiof0_ss2),
3197         SH_PFC_PIN_GROUP(msiof0_rxd),
3198         SH_PFC_PIN_GROUP(msiof0_txd),
3199         SH_PFC_PIN_GROUP(msiof0_mck0),
3200         SH_PFC_PIN_GROUP(msiof0_mck1),
3201         SH_PFC_PIN_GROUP(msiof0l_rsck),
3202         SH_PFC_PIN_GROUP(msiof0l_tsck),
3203         SH_PFC_PIN_GROUP(msiof0l_rsync),
3204         SH_PFC_PIN_GROUP(msiof0l_tsync),
3205         SH_PFC_PIN_GROUP(msiof0l_ss1_a),
3206         SH_PFC_PIN_GROUP(msiof0l_ss1_b),
3207         SH_PFC_PIN_GROUP(msiof0l_ss2_a),
3208         SH_PFC_PIN_GROUP(msiof0l_ss2_b),
3209         SH_PFC_PIN_GROUP(msiof0l_rxd),
3210         SH_PFC_PIN_GROUP(msiof0l_txd),
3211         SH_PFC_PIN_GROUP(msiof0l_mck0),
3212         SH_PFC_PIN_GROUP(msiof0l_mck1),
3213         SH_PFC_PIN_GROUP(msiof1_rsck),
3214         SH_PFC_PIN_GROUP(msiof1_tsck),
3215         SH_PFC_PIN_GROUP(msiof1_rsync),
3216         SH_PFC_PIN_GROUP(msiof1_tsync),
3217         SH_PFC_PIN_GROUP(msiof1_ss1),
3218         SH_PFC_PIN_GROUP(msiof1_ss2),
3219         SH_PFC_PIN_GROUP(msiof1_rxd),
3220         SH_PFC_PIN_GROUP(msiof1_txd),
3221         SH_PFC_PIN_GROUP(msiof1_mck0),
3222         SH_PFC_PIN_GROUP(msiof1_mck1),
3223         SH_PFC_PIN_GROUP(msiof2_rsck),
3224         SH_PFC_PIN_GROUP(msiof2_tsck),
3225         SH_PFC_PIN_GROUP(msiof2_rsync),
3226         SH_PFC_PIN_GROUP(msiof2_tsync),
3227         SH_PFC_PIN_GROUP(msiof2_ss1_a),
3228         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3229         SH_PFC_PIN_GROUP(msiof2_ss2_a),
3230         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3231         SH_PFC_PIN_GROUP(msiof2_rxd_a),
3232         SH_PFC_PIN_GROUP(msiof2_rxd_b),
3233         SH_PFC_PIN_GROUP(msiof2_txd),
3234         SH_PFC_PIN_GROUP(msiof2_mck0),
3235         SH_PFC_PIN_GROUP(msiof2_mck1),
3236         SH_PFC_PIN_GROUP(msiof2r_tsck),
3237         SH_PFC_PIN_GROUP(msiof2r_tsync),
3238         SH_PFC_PIN_GROUP(msiof2r_rxd),
3239         SH_PFC_PIN_GROUP(msiof2r_txd),
3240         SH_PFC_PIN_GROUP(msiof3_rsck),
3241         SH_PFC_PIN_GROUP(msiof3_tsck),
3242         SH_PFC_PIN_GROUP(msiof3_rsync),
3243         SH_PFC_PIN_GROUP(msiof3_tsync),
3244         SH_PFC_PIN_GROUP(msiof3_ss1),
3245         SH_PFC_PIN_GROUP(msiof3_ss2),
3246         SH_PFC_PIN_GROUP(msiof3_rxd),
3247         SH_PFC_PIN_GROUP(msiof3_txd),
3248         SH_PFC_PIN_GROUP(msiof3_flow),
3249         SH_PFC_PIN_GROUP(scifa0_data),
3250         SH_PFC_PIN_GROUP(scifa0_clk),
3251         SH_PFC_PIN_GROUP(scifa0_ctrl),
3252         SH_PFC_PIN_GROUP(scifa1_data),
3253         SH_PFC_PIN_GROUP(scifa1_clk),
3254         SH_PFC_PIN_GROUP(scifa1_ctrl),
3255         SH_PFC_PIN_GROUP(scifa2_data_0),
3256         SH_PFC_PIN_GROUP(scifa2_clk_0),
3257         SH_PFC_PIN_GROUP(scifa2_ctrl_0),
3258         SH_PFC_PIN_GROUP(scifa2_data_1),
3259         SH_PFC_PIN_GROUP(scifa2_clk_1),
3260         SH_PFC_PIN_GROUP(scifa2_ctrl_1),
3261         SH_PFC_PIN_GROUP(scifa3_data),
3262         SH_PFC_PIN_GROUP(scifa3_ctrl),
3263         SH_PFC_PIN_GROUP(scifa4_data),
3264         SH_PFC_PIN_GROUP(scifa4_ctrl),
3265         SH_PFC_PIN_GROUP(scifa5_data_0),
3266         SH_PFC_PIN_GROUP(scifa5_clk_0),
3267         SH_PFC_PIN_GROUP(scifa5_ctrl_0),
3268         SH_PFC_PIN_GROUP(scifa5_data_1),
3269         SH_PFC_PIN_GROUP(scifa5_clk_1),
3270         SH_PFC_PIN_GROUP(scifa5_ctrl_1),
3271         SH_PFC_PIN_GROUP(scifa5_data_2),
3272         SH_PFC_PIN_GROUP(scifa5_clk_2),
3273         SH_PFC_PIN_GROUP(scifa5_ctrl_2),
3274         SH_PFC_PIN_GROUP(scifa6),
3275         SH_PFC_PIN_GROUP(scifa7_data),
3276         SH_PFC_PIN_GROUP(scifa7_ctrl),
3277         SH_PFC_PIN_GROUP(scifb_data_0),
3278         SH_PFC_PIN_GROUP(scifb_clk_0),
3279         SH_PFC_PIN_GROUP(scifb_ctrl_0),
3280         SH_PFC_PIN_GROUP(scifb_data_1),
3281         SH_PFC_PIN_GROUP(scifb_clk_1),
3282         SH_PFC_PIN_GROUP(scifb_ctrl_1),
3283         SH_PFC_PIN_GROUP(sdhi0_data1),
3284         SH_PFC_PIN_GROUP(sdhi0_data4),
3285         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3286         SH_PFC_PIN_GROUP(sdhi0_cd),
3287         SH_PFC_PIN_GROUP(sdhi0_wp),
3288         SH_PFC_PIN_GROUP(sdhi1_data1),
3289         SH_PFC_PIN_GROUP(sdhi1_data4),
3290         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3291         SH_PFC_PIN_GROUP(sdhi2_data1),
3292         SH_PFC_PIN_GROUP(sdhi2_data4),
3293         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3294         SH_PFC_PIN_GROUP(tpu0_to0),
3295         SH_PFC_PIN_GROUP(tpu0_to1),
3296         SH_PFC_PIN_GROUP(tpu0_to2),
3297         SH_PFC_PIN_GROUP(tpu0_to3),
3298         SH_PFC_PIN_GROUP(tpu1_to0),
3299         SH_PFC_PIN_GROUP(tpu1_to1_0),
3300         SH_PFC_PIN_GROUP(tpu1_to1_1),
3301         SH_PFC_PIN_GROUP(tpu1_to2),
3302         SH_PFC_PIN_GROUP(tpu1_to3),
3303         SH_PFC_PIN_GROUP(tpu2_to0),
3304         SH_PFC_PIN_GROUP(tpu2_to1),
3305         SH_PFC_PIN_GROUP(tpu2_to2),
3306         SH_PFC_PIN_GROUP(tpu2_to3),
3307         SH_PFC_PIN_GROUP(tpu3_to0),
3308         SH_PFC_PIN_GROUP(tpu3_to1),
3309         SH_PFC_PIN_GROUP(tpu3_to2),
3310         SH_PFC_PIN_GROUP(tpu3_to3),
3311         SH_PFC_PIN_GROUP(tpu4_to0),
3312         SH_PFC_PIN_GROUP(tpu4_to1),
3313         SH_PFC_PIN_GROUP(tpu4_to2),
3314         SH_PFC_PIN_GROUP(tpu4_to3),
3315         SH_PFC_PIN_GROUP(usb_vbus),
3316 };
3317
3318 static const char * const bsc_groups[] = {
3319         "bsc_data_0_7",
3320         "bsc_data_8_15",
3321         "bsc_cs4",
3322         "bsc_cs5_a",
3323         "bsc_cs5_b",
3324         "bsc_cs6_a",
3325         "bsc_cs6_b",
3326         "bsc_rd",
3327         "bsc_rdwr_0",
3328         "bsc_rdwr_1",
3329         "bsc_rdwr_2",
3330         "bsc_we0",
3331         "bsc_we1",
3332 };
3333
3334 static const char * const fsia_groups[] = {
3335         "fsia_mclk_in",
3336         "fsia_mclk_out",
3337         "fsia_sclk_in",
3338         "fsia_sclk_out",
3339         "fsia_data_in",
3340         "fsia_data_out",
3341         "fsia_spdif",
3342 };
3343
3344 static const char * const fsib_groups[] = {
3345         "fsib_mclk_in",
3346         "fsib_mclk_out",
3347         "fsib_sclk_in",
3348         "fsib_sclk_out",
3349         "fsib_data_in",
3350         "fsib_data_out",
3351         "fsib_spdif",
3352 };
3353
3354 static const char * const fsic_groups[] = {
3355         "fsic_mclk_in",
3356         "fsic_mclk_out",
3357         "fsic_sclk_in",
3358         "fsic_sclk_out",
3359         "fsic_data_in",
3360         "fsic_data_out",
3361         "fsic_spdif_0",
3362         "fsic_spdif_1",
3363 };
3364
3365 static const char * const fsid_groups[] = {
3366         "fsid_sclk_in",
3367         "fsid_sclk_out",
3368         "fsid_data_in",
3369 };
3370
3371 static const char * const i2c2_groups[] = {
3372         "i2c2_0",
3373         "i2c2_1",
3374         "i2c2_2",
3375 };
3376
3377 static const char * const i2c3_groups[] = {
3378         "i2c3_0",
3379         "i2c3_1",
3380         "i2c3_2",
3381 };
3382
3383 static const char * const irda_groups[] = {
3384         "irda_0",
3385         "irda_1",
3386 };
3387
3388 static const char * const keysc_groups[] = {
3389         "keysc_in5",
3390         "keysc_in6",
3391         "keysc_in7",
3392         "keysc_in8",
3393         "keysc_out04",
3394         "keysc_out5",
3395         "keysc_out6_0",
3396         "keysc_out6_1",
3397         "keysc_out6_2",
3398         "keysc_out7_0",
3399         "keysc_out7_1",
3400         "keysc_out7_2",
3401         "keysc_out8_0",
3402         "keysc_out8_1",
3403         "keysc_out8_2",
3404         "keysc_out9_0",
3405         "keysc_out9_1",
3406         "keysc_out9_2",
3407         "keysc_out10_0",
3408         "keysc_out10_1",
3409         "keysc_out11_0",
3410         "keysc_out11_1",
3411 };
3412
3413 static const char * const lcd_groups[] = {
3414         "lcd_data8",
3415         "lcd_data9",
3416         "lcd_data12",
3417         "lcd_data16",
3418         "lcd_data18",
3419         "lcd_data24",
3420         "lcd_display",
3421         "lcd_lclk",
3422         "lcd_sync",
3423         "lcd_sys",
3424 };
3425
3426 static const char * const lcd2_groups[] = {
3427         "lcd2_data8",
3428         "lcd2_data9",
3429         "lcd2_data12",
3430         "lcd2_data16",
3431         "lcd2_data18",
3432         "lcd2_data24",
3433         "lcd2_sync_0",
3434         "lcd2_sync_1",
3435         "lcd2_sys_0",
3436         "lcd2_sys_1",
3437 };
3438
3439 static const char * const mmc0_groups[] = {
3440         "mmc0_data1_0",
3441         "mmc0_data4_0",
3442         "mmc0_data8_0",
3443         "mmc0_ctrl_0",
3444         "mmc0_data1_1",
3445         "mmc0_data4_1",
3446         "mmc0_data8_1",
3447         "mmc0_ctrl_1",
3448 };
3449
3450 static const char * const msiof0_groups[] = {
3451         "msiof0_rsck",
3452         "msiof0_tsck",
3453         "msiof0_rsync",
3454         "msiof0_tsync",
3455         "msiof0_ss1",
3456         "msiof0_ss2",
3457         "msiof0_rxd",
3458         "msiof0_txd",
3459         "msiof0_mck0",
3460         "msiof0_mck1",
3461         "msiof0l_rsck",
3462         "msiof0l_tsck",
3463         "msiof0l_rsync",
3464         "msiof0l_tsync",
3465         "msiof0l_ss1_a",
3466         "msiof0l_ss1_b",
3467         "msiof0l_ss2_a",
3468         "msiof0l_ss2_b",
3469         "msiof0l_rxd",
3470         "msiof0l_txd",
3471         "msiof0l_mck0",
3472         "msiof0l_mck1",
3473 };
3474
3475 static const char * const msiof1_groups[] = {
3476         "msiof1_rsck",
3477         "msiof1_tsck",
3478         "msiof1_rsync",
3479         "msiof1_tsync",
3480         "msiof1_ss1",
3481         "msiof1_ss2",
3482         "msiof1_rxd",
3483         "msiof1_txd",
3484         "msiof1_mck0",
3485         "msiof1_mck1",
3486 };
3487
3488 static const char * const msiof2_groups[] = {
3489         "msiof2_rsck",
3490         "msiof2_tsck",
3491         "msiof2_rsync",
3492         "msiof2_tsync",
3493         "msiof2_ss1_a",
3494         "msiof2_ss1_b",
3495         "msiof2_ss2_a",
3496         "msiof2_ss2_b",
3497         "msiof2_rxd_a",
3498         "msiof2_rxd_b",
3499         "msiof2_txd",
3500         "msiof2_mck0",
3501         "msiof2_mck1",
3502         "msiof2r_tsck",
3503         "msiof2r_tsync",
3504         "msiof2r_rxd",
3505         "msiof2r_txd",
3506 };
3507
3508 static const char * const msiof3_groups[] = {
3509         "msiof3_rsck",
3510         "msiof3_tsck",
3511         "msiof3_rsync",
3512         "msiof3_tsync",
3513         "msiof3_ss1",
3514         "msiof3_ss2",
3515         "msiof3_rxd",
3516         "msiof3_txd",
3517         "msiof3_flow",
3518 };
3519
3520 static const char * const scifa0_groups[] = {
3521         "scifa0_data",
3522         "scifa0_clk",
3523         "scifa0_ctrl",
3524 };
3525
3526 static const char * const scifa1_groups[] = {
3527         "scifa1_data",
3528         "scifa1_clk",
3529         "scifa1_ctrl",
3530 };
3531
3532 static const char * const scifa2_groups[] = {
3533         "scifa2_data_0",
3534         "scifa2_clk_0",
3535         "scifa2_ctrl_0",
3536         "scifa2_data_1",
3537         "scifa2_clk_1",
3538         "scifa2_ctrl_1",
3539 };
3540
3541 static const char * const scifa3_groups[] = {
3542         "scifa3_data",
3543         "scifa3_ctrl",
3544 };
3545
3546 static const char * const scifa4_groups[] = {
3547         "scifa4_data",
3548         "scifa4_ctrl",
3549 };
3550
3551 static const char * const scifa5_groups[] = {
3552         "scifa5_data_0",
3553         "scifa5_clk_0",
3554         "scifa5_ctrl_0",
3555         "scifa5_data_1",
3556         "scifa5_clk_1",
3557         "scifa5_ctrl_1",
3558         "scifa5_data_2",
3559         "scifa5_clk_2",
3560         "scifa5_ctrl_2",
3561 };
3562
3563 static const char * const scifa6_groups[] = {
3564         "scifa6",
3565 };
3566
3567 static const char * const scifa7_groups[] = {
3568         "scifa7_data",
3569         "scifa7_ctrl",
3570 };
3571
3572 static const char * const scifb_groups[] = {
3573         "scifb_data_0",
3574         "scifb_clk_0",
3575         "scifb_ctrl_0",
3576         "scifb_data_1",
3577         "scifb_clk_1",
3578         "scifb_ctrl_1",
3579 };
3580
3581 static const char * const sdhi0_groups[] = {
3582         "sdhi0_data1",
3583         "sdhi0_data4",
3584         "sdhi0_ctrl",
3585         "sdhi0_cd",
3586         "sdhi0_wp",
3587 };
3588
3589 static const char * const sdhi1_groups[] = {
3590         "sdhi1_data1",
3591         "sdhi1_data4",
3592         "sdhi1_ctrl",
3593 };
3594
3595 static const char * const sdhi2_groups[] = {
3596         "sdhi2_data1",
3597         "sdhi2_data4",
3598         "sdhi2_ctrl",
3599 };
3600
3601 static const char * const usb_groups[] = {
3602         "usb_vbus",
3603 };
3604
3605 static const char * const tpu0_groups[] = {
3606         "tpu0_to0",
3607         "tpu0_to1",
3608         "tpu0_to2",
3609         "tpu0_to3",
3610 };
3611
3612 static const char * const tpu1_groups[] = {
3613         "tpu1_to0",
3614         "tpu1_to1_0",
3615         "tpu1_to1_1",
3616         "tpu1_to2",
3617         "tpu1_to3",
3618 };
3619
3620 static const char * const tpu2_groups[] = {
3621         "tpu2_to0",
3622         "tpu2_to1",
3623         "tpu2_to2",
3624         "tpu2_to3",
3625 };
3626
3627 static const char * const tpu3_groups[] = {
3628         "tpu3_to0",
3629         "tpu3_to1",
3630         "tpu3_to2",
3631         "tpu3_to3",
3632 };
3633
3634 static const char * const tpu4_groups[] = {
3635         "tpu4_to0",
3636         "tpu4_to1",
3637         "tpu4_to2",
3638         "tpu4_to3",
3639 };
3640
3641 static const struct sh_pfc_function pinmux_functions[] = {
3642         SH_PFC_FUNCTION(bsc),
3643         SH_PFC_FUNCTION(fsia),
3644         SH_PFC_FUNCTION(fsib),
3645         SH_PFC_FUNCTION(fsic),
3646         SH_PFC_FUNCTION(fsid),
3647         SH_PFC_FUNCTION(i2c2),
3648         SH_PFC_FUNCTION(i2c3),
3649         SH_PFC_FUNCTION(irda),
3650         SH_PFC_FUNCTION(keysc),
3651         SH_PFC_FUNCTION(lcd),
3652         SH_PFC_FUNCTION(lcd2),
3653         SH_PFC_FUNCTION(mmc0),
3654         SH_PFC_FUNCTION(msiof0),
3655         SH_PFC_FUNCTION(msiof1),
3656         SH_PFC_FUNCTION(msiof2),
3657         SH_PFC_FUNCTION(msiof3),
3658         SH_PFC_FUNCTION(scifa0),
3659         SH_PFC_FUNCTION(scifa1),
3660         SH_PFC_FUNCTION(scifa2),
3661         SH_PFC_FUNCTION(scifa3),
3662         SH_PFC_FUNCTION(scifa4),
3663         SH_PFC_FUNCTION(scifa5),
3664         SH_PFC_FUNCTION(scifa6),
3665         SH_PFC_FUNCTION(scifa7),
3666         SH_PFC_FUNCTION(scifb),
3667         SH_PFC_FUNCTION(sdhi0),
3668         SH_PFC_FUNCTION(sdhi1),
3669         SH_PFC_FUNCTION(sdhi2),
3670         SH_PFC_FUNCTION(tpu0),
3671         SH_PFC_FUNCTION(tpu1),
3672         SH_PFC_FUNCTION(tpu2),
3673         SH_PFC_FUNCTION(tpu3),
3674         SH_PFC_FUNCTION(tpu4),
3675         SH_PFC_FUNCTION(usb),
3676 };
3677
3678 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3679         PORTCR(0, 0xe6050000), /* PORT0CR */
3680         PORTCR(1, 0xe6050001), /* PORT1CR */
3681         PORTCR(2, 0xe6050002), /* PORT2CR */
3682         PORTCR(3, 0xe6050003), /* PORT3CR */
3683         PORTCR(4, 0xe6050004), /* PORT4CR */
3684         PORTCR(5, 0xe6050005), /* PORT5CR */
3685         PORTCR(6, 0xe6050006), /* PORT6CR */
3686         PORTCR(7, 0xe6050007), /* PORT7CR */
3687         PORTCR(8, 0xe6050008), /* PORT8CR */
3688         PORTCR(9, 0xe6050009), /* PORT9CR */
3689
3690         PORTCR(10, 0xe605000a), /* PORT10CR */
3691         PORTCR(11, 0xe605000b), /* PORT11CR */
3692         PORTCR(12, 0xe605000c), /* PORT12CR */
3693         PORTCR(13, 0xe605000d), /* PORT13CR */
3694         PORTCR(14, 0xe605000e), /* PORT14CR */
3695         PORTCR(15, 0xe605000f), /* PORT15CR */
3696         PORTCR(16, 0xe6050010), /* PORT16CR */
3697         PORTCR(17, 0xe6050011), /* PORT17CR */
3698         PORTCR(18, 0xe6050012), /* PORT18CR */
3699         PORTCR(19, 0xe6050013), /* PORT19CR */
3700
3701         PORTCR(20, 0xe6050014), /* PORT20CR */
3702         PORTCR(21, 0xe6050015), /* PORT21CR */
3703         PORTCR(22, 0xe6050016), /* PORT22CR */
3704         PORTCR(23, 0xe6050017), /* PORT23CR */
3705         PORTCR(24, 0xe6050018), /* PORT24CR */
3706         PORTCR(25, 0xe6050019), /* PORT25CR */
3707         PORTCR(26, 0xe605001a), /* PORT26CR */
3708         PORTCR(27, 0xe605001b), /* PORT27CR */
3709         PORTCR(28, 0xe605001c), /* PORT28CR */
3710         PORTCR(29, 0xe605001d), /* PORT29CR */
3711
3712         PORTCR(30, 0xe605001e), /* PORT30CR */
3713         PORTCR(31, 0xe605001f), /* PORT31CR */
3714         PORTCR(32, 0xe6051020), /* PORT32CR */
3715         PORTCR(33, 0xe6051021), /* PORT33CR */
3716         PORTCR(34, 0xe6051022), /* PORT34CR */
3717         PORTCR(35, 0xe6051023), /* PORT35CR */
3718         PORTCR(36, 0xe6051024), /* PORT36CR */
3719         PORTCR(37, 0xe6051025), /* PORT37CR */
3720         PORTCR(38, 0xe6051026), /* PORT38CR */
3721         PORTCR(39, 0xe6051027), /* PORT39CR */
3722
3723         PORTCR(40, 0xe6051028), /* PORT40CR */
3724         PORTCR(41, 0xe6051029), /* PORT41CR */
3725         PORTCR(42, 0xe605102a), /* PORT42CR */
3726         PORTCR(43, 0xe605102b), /* PORT43CR */
3727         PORTCR(44, 0xe605102c), /* PORT44CR */
3728         PORTCR(45, 0xe605102d), /* PORT45CR */
3729         PORTCR(46, 0xe605102e), /* PORT46CR */
3730         PORTCR(47, 0xe605102f), /* PORT47CR */
3731         PORTCR(48, 0xe6051030), /* PORT48CR */
3732         PORTCR(49, 0xe6051031), /* PORT49CR */
3733
3734         PORTCR(50, 0xe6051032), /* PORT50CR */
3735         PORTCR(51, 0xe6051033), /* PORT51CR */
3736         PORTCR(52, 0xe6051034), /* PORT52CR */
3737         PORTCR(53, 0xe6051035), /* PORT53CR */
3738         PORTCR(54, 0xe6051036), /* PORT54CR */
3739         PORTCR(55, 0xe6051037), /* PORT55CR */
3740         PORTCR(56, 0xe6051038), /* PORT56CR */
3741         PORTCR(57, 0xe6051039), /* PORT57CR */
3742         PORTCR(58, 0xe605103a), /* PORT58CR */
3743         PORTCR(59, 0xe605103b), /* PORT59CR */
3744
3745         PORTCR(60, 0xe605103c), /* PORT60CR */
3746         PORTCR(61, 0xe605103d), /* PORT61CR */
3747         PORTCR(62, 0xe605103e), /* PORT62CR */
3748         PORTCR(63, 0xe605103f), /* PORT63CR */
3749         PORTCR(64, 0xe6051040), /* PORT64CR */
3750         PORTCR(65, 0xe6051041), /* PORT65CR */
3751         PORTCR(66, 0xe6051042), /* PORT66CR */
3752         PORTCR(67, 0xe6051043), /* PORT67CR */
3753         PORTCR(68, 0xe6051044), /* PORT68CR */
3754         PORTCR(69, 0xe6051045), /* PORT69CR */
3755
3756         PORTCR(70, 0xe6051046), /* PORT70CR */
3757         PORTCR(71, 0xe6051047), /* PORT71CR */
3758         PORTCR(72, 0xe6051048), /* PORT72CR */
3759         PORTCR(73, 0xe6051049), /* PORT73CR */
3760         PORTCR(74, 0xe605104a), /* PORT74CR */
3761         PORTCR(75, 0xe605104b), /* PORT75CR */
3762         PORTCR(76, 0xe605104c), /* PORT76CR */
3763         PORTCR(77, 0xe605104d), /* PORT77CR */
3764         PORTCR(78, 0xe605104e), /* PORT78CR */
3765         PORTCR(79, 0xe605104f), /* PORT79CR */
3766
3767         PORTCR(80, 0xe6051050), /* PORT80CR */
3768         PORTCR(81, 0xe6051051), /* PORT81CR */
3769         PORTCR(82, 0xe6051052), /* PORT82CR */
3770         PORTCR(83, 0xe6051053), /* PORT83CR */
3771         PORTCR(84, 0xe6051054), /* PORT84CR */
3772         PORTCR(85, 0xe6051055), /* PORT85CR */
3773         PORTCR(86, 0xe6051056), /* PORT86CR */
3774         PORTCR(87, 0xe6051057), /* PORT87CR */
3775         PORTCR(88, 0xe6051058), /* PORT88CR */
3776         PORTCR(89, 0xe6051059), /* PORT89CR */
3777
3778         PORTCR(90, 0xe605105a), /* PORT90CR */
3779         PORTCR(91, 0xe605105b), /* PORT91CR */
3780         PORTCR(92, 0xe605105c), /* PORT92CR */
3781         PORTCR(93, 0xe605105d), /* PORT93CR */
3782         PORTCR(94, 0xe605105e), /* PORT94CR */
3783         PORTCR(95, 0xe605105f), /* PORT95CR */
3784         PORTCR(96, 0xe6052060), /* PORT96CR */
3785         PORTCR(97, 0xe6052061), /* PORT97CR */
3786         PORTCR(98, 0xe6052062), /* PORT98CR */
3787         PORTCR(99, 0xe6052063), /* PORT99CR */
3788
3789         PORTCR(100, 0xe6052064), /* PORT100CR */
3790         PORTCR(101, 0xe6052065), /* PORT101CR */
3791         PORTCR(102, 0xe6052066), /* PORT102CR */
3792         PORTCR(103, 0xe6052067), /* PORT103CR */
3793         PORTCR(104, 0xe6052068), /* PORT104CR */
3794         PORTCR(105, 0xe6052069), /* PORT105CR */
3795         PORTCR(106, 0xe605206a), /* PORT106CR */
3796         PORTCR(107, 0xe605206b), /* PORT107CR */
3797         PORTCR(108, 0xe605206c), /* PORT108CR */
3798         PORTCR(109, 0xe605206d), /* PORT109CR */
3799
3800         PORTCR(110, 0xe605206e), /* PORT110CR */
3801         PORTCR(111, 0xe605206f), /* PORT111CR */
3802         PORTCR(112, 0xe6052070), /* PORT112CR */
3803         PORTCR(113, 0xe6052071), /* PORT113CR */
3804         PORTCR(114, 0xe6052072), /* PORT114CR */
3805         PORTCR(115, 0xe6052073), /* PORT115CR */
3806         PORTCR(116, 0xe6052074), /* PORT116CR */
3807         PORTCR(117, 0xe6052075), /* PORT117CR */
3808         PORTCR(118, 0xe6052076), /* PORT118CR */
3809
3810         PORTCR(128, 0xe6052080), /* PORT128CR */
3811         PORTCR(129, 0xe6052081), /* PORT129CR */
3812
3813         PORTCR(130, 0xe6052082), /* PORT130CR */
3814         PORTCR(131, 0xe6052083), /* PORT131CR */
3815         PORTCR(132, 0xe6052084), /* PORT132CR */
3816         PORTCR(133, 0xe6052085), /* PORT133CR */
3817         PORTCR(134, 0xe6052086), /* PORT134CR */
3818         PORTCR(135, 0xe6052087), /* PORT135CR */
3819         PORTCR(136, 0xe6052088), /* PORT136CR */
3820         PORTCR(137, 0xe6052089), /* PORT137CR */
3821         PORTCR(138, 0xe605208a), /* PORT138CR */
3822         PORTCR(139, 0xe605208b), /* PORT139CR */
3823
3824         PORTCR(140, 0xe605208c), /* PORT140CR */
3825         PORTCR(141, 0xe605208d), /* PORT141CR */
3826         PORTCR(142, 0xe605208e), /* PORT142CR */
3827         PORTCR(143, 0xe605208f), /* PORT143CR */
3828         PORTCR(144, 0xe6052090), /* PORT144CR */
3829         PORTCR(145, 0xe6052091), /* PORT145CR */
3830         PORTCR(146, 0xe6052092), /* PORT146CR */
3831         PORTCR(147, 0xe6052093), /* PORT147CR */
3832         PORTCR(148, 0xe6052094), /* PORT148CR */
3833         PORTCR(149, 0xe6052095), /* PORT149CR */
3834
3835         PORTCR(150, 0xe6052096), /* PORT150CR */
3836         PORTCR(151, 0xe6052097), /* PORT151CR */
3837         PORTCR(152, 0xe6052098), /* PORT152CR */
3838         PORTCR(153, 0xe6052099), /* PORT153CR */
3839         PORTCR(154, 0xe605209a), /* PORT154CR */
3840         PORTCR(155, 0xe605209b), /* PORT155CR */
3841         PORTCR(156, 0xe605209c), /* PORT156CR */
3842         PORTCR(157, 0xe605209d), /* PORT157CR */
3843         PORTCR(158, 0xe605209e), /* PORT158CR */
3844         PORTCR(159, 0xe605209f), /* PORT159CR */
3845
3846         PORTCR(160, 0xe60520a0), /* PORT160CR */
3847         PORTCR(161, 0xe60520a1), /* PORT161CR */
3848         PORTCR(162, 0xe60520a2), /* PORT162CR */
3849         PORTCR(163, 0xe60520a3), /* PORT163CR */
3850         PORTCR(164, 0xe60520a4), /* PORT164CR */
3851
3852         PORTCR(192, 0xe60520c0), /* PORT192CR */
3853         PORTCR(193, 0xe60520c1), /* PORT193CR */
3854         PORTCR(194, 0xe60520c2), /* PORT194CR */
3855         PORTCR(195, 0xe60520c3), /* PORT195CR */
3856         PORTCR(196, 0xe60520c4), /* PORT196CR */
3857         PORTCR(197, 0xe60520c5), /* PORT197CR */
3858         PORTCR(198, 0xe60520c6), /* PORT198CR */
3859         PORTCR(199, 0xe60520c7), /* PORT199CR */
3860
3861         PORTCR(200, 0xe60520c8), /* PORT200CR */
3862         PORTCR(201, 0xe60520c9), /* PORT201CR */
3863         PORTCR(202, 0xe60520ca), /* PORT202CR */
3864         PORTCR(203, 0xe60520cb), /* PORT203CR */
3865         PORTCR(204, 0xe60520cc), /* PORT204CR */
3866         PORTCR(205, 0xe60520cd), /* PORT205CR */
3867         PORTCR(206, 0xe60520ce), /* PORT206CR */
3868         PORTCR(207, 0xe60520cf), /* PORT207CR */
3869         PORTCR(208, 0xe60520d0), /* PORT208CR */
3870         PORTCR(209, 0xe60520d1), /* PORT209CR */
3871
3872         PORTCR(210, 0xe60520d2), /* PORT210CR */
3873         PORTCR(211, 0xe60520d3), /* PORT211CR */
3874         PORTCR(212, 0xe60520d4), /* PORT212CR */
3875         PORTCR(213, 0xe60520d5), /* PORT213CR */
3876         PORTCR(214, 0xe60520d6), /* PORT214CR */
3877         PORTCR(215, 0xe60520d7), /* PORT215CR */
3878         PORTCR(216, 0xe60520d8), /* PORT216CR */
3879         PORTCR(217, 0xe60520d9), /* PORT217CR */
3880         PORTCR(218, 0xe60520da), /* PORT218CR */
3881         PORTCR(219, 0xe60520db), /* PORT219CR */
3882
3883         PORTCR(220, 0xe60520dc), /* PORT220CR */
3884         PORTCR(221, 0xe60520dd), /* PORT221CR */
3885         PORTCR(222, 0xe60520de), /* PORT222CR */
3886         PORTCR(223, 0xe60520df), /* PORT223CR */
3887         PORTCR(224, 0xe60530e0), /* PORT224CR */
3888         PORTCR(225, 0xe60530e1), /* PORT225CR */
3889         PORTCR(226, 0xe60530e2), /* PORT226CR */
3890         PORTCR(227, 0xe60530e3), /* PORT227CR */
3891         PORTCR(228, 0xe60530e4), /* PORT228CR */
3892         PORTCR(229, 0xe60530e5), /* PORT229CR */
3893
3894         PORTCR(230, 0xe60530e6), /* PORT230CR */
3895         PORTCR(231, 0xe60530e7), /* PORT231CR */
3896         PORTCR(232, 0xe60530e8), /* PORT232CR */
3897         PORTCR(233, 0xe60530e9), /* PORT233CR */
3898         PORTCR(234, 0xe60530ea), /* PORT234CR */
3899         PORTCR(235, 0xe60530eb), /* PORT235CR */
3900         PORTCR(236, 0xe60530ec), /* PORT236CR */
3901         PORTCR(237, 0xe60530ed), /* PORT237CR */
3902         PORTCR(238, 0xe60530ee), /* PORT238CR */
3903         PORTCR(239, 0xe60530ef), /* PORT239CR */
3904
3905         PORTCR(240, 0xe60530f0), /* PORT240CR */
3906         PORTCR(241, 0xe60530f1), /* PORT241CR */
3907         PORTCR(242, 0xe60530f2), /* PORT242CR */
3908         PORTCR(243, 0xe60530f3), /* PORT243CR */
3909         PORTCR(244, 0xe60530f4), /* PORT244CR */
3910         PORTCR(245, 0xe60530f5), /* PORT245CR */
3911         PORTCR(246, 0xe60530f6), /* PORT246CR */
3912         PORTCR(247, 0xe60530f7), /* PORT247CR */
3913         PORTCR(248, 0xe60530f8), /* PORT248CR */
3914         PORTCR(249, 0xe60530f9), /* PORT249CR */
3915
3916         PORTCR(250, 0xe60530fa), /* PORT250CR */
3917         PORTCR(251, 0xe60530fb), /* PORT251CR */
3918         PORTCR(252, 0xe60530fc), /* PORT252CR */
3919         PORTCR(253, 0xe60530fd), /* PORT253CR */
3920         PORTCR(254, 0xe60530fe), /* PORT254CR */
3921         PORTCR(255, 0xe60530ff), /* PORT255CR */
3922         PORTCR(256, 0xe6053100), /* PORT256CR */
3923         PORTCR(257, 0xe6053101), /* PORT257CR */
3924         PORTCR(258, 0xe6053102), /* PORT258CR */
3925         PORTCR(259, 0xe6053103), /* PORT259CR */
3926
3927         PORTCR(260, 0xe6053104), /* PORT260CR */
3928         PORTCR(261, 0xe6053105), /* PORT261CR */
3929         PORTCR(262, 0xe6053106), /* PORT262CR */
3930         PORTCR(263, 0xe6053107), /* PORT263CR */
3931         PORTCR(264, 0xe6053108), /* PORT264CR */
3932         PORTCR(265, 0xe6053109), /* PORT265CR */
3933         PORTCR(266, 0xe605310a), /* PORT266CR */
3934         PORTCR(267, 0xe605310b), /* PORT267CR */
3935         PORTCR(268, 0xe605310c), /* PORT268CR */
3936         PORTCR(269, 0xe605310d), /* PORT269CR */
3937
3938         PORTCR(270, 0xe605310e), /* PORT270CR */
3939         PORTCR(271, 0xe605310f), /* PORT271CR */
3940         PORTCR(272, 0xe6053110), /* PORT272CR */
3941         PORTCR(273, 0xe6053111), /* PORT273CR */
3942         PORTCR(274, 0xe6053112), /* PORT274CR */
3943         PORTCR(275, 0xe6053113), /* PORT275CR */
3944         PORTCR(276, 0xe6053114), /* PORT276CR */
3945         PORTCR(277, 0xe6053115), /* PORT277CR */
3946         PORTCR(278, 0xe6053116), /* PORT278CR */
3947         PORTCR(279, 0xe6053117), /* PORT279CR */
3948
3949         PORTCR(280, 0xe6053118), /* PORT280CR */
3950         PORTCR(281, 0xe6053119), /* PORT281CR */
3951         PORTCR(282, 0xe605311a), /* PORT282CR */
3952
3953         PORTCR(288, 0xe6052120), /* PORT288CR */
3954         PORTCR(289, 0xe6052121), /* PORT289CR */
3955
3956         PORTCR(290, 0xe6052122), /* PORT290CR */
3957         PORTCR(291, 0xe6052123), /* PORT291CR */
3958         PORTCR(292, 0xe6052124), /* PORT292CR */
3959         PORTCR(293, 0xe6052125), /* PORT293CR */
3960         PORTCR(294, 0xe6052126), /* PORT294CR */
3961         PORTCR(295, 0xe6052127), /* PORT295CR */
3962         PORTCR(296, 0xe6052128), /* PORT296CR */
3963         PORTCR(297, 0xe6052129), /* PORT297CR */
3964         PORTCR(298, 0xe605212a), /* PORT298CR */
3965         PORTCR(299, 0xe605212b), /* PORT299CR */
3966
3967         PORTCR(300, 0xe605212c), /* PORT300CR */
3968         PORTCR(301, 0xe605212d), /* PORT301CR */
3969         PORTCR(302, 0xe605212e), /* PORT302CR */
3970         PORTCR(303, 0xe605212f), /* PORT303CR */
3971         PORTCR(304, 0xe6052130), /* PORT304CR */
3972         PORTCR(305, 0xe6052131), /* PORT305CR */
3973         PORTCR(306, 0xe6052132), /* PORT306CR */
3974         PORTCR(307, 0xe6052133), /* PORT307CR */
3975         PORTCR(308, 0xe6052134), /* PORT308CR */
3976         PORTCR(309, 0xe6052135), /* PORT309CR */
3977
3978         { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1, GROUP(
3979                         0, 0,
3980                         0, 0,
3981                         0, 0,
3982                         0, 0,
3983                         0, 0,
3984                         0, 0,
3985                         0, 0,
3986                         0, 0,
3987                         0, 0,
3988                         0, 0,
3989                         0, 0,
3990                         0, 0,
3991                         MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
3992                         MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
3993                         MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
3994                         MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
3995                         0, 0,
3996                         MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
3997                         MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
3998                         MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
3999                         MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
4000                         MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
4001                         MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
4002                         MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
4003                         MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
4004                         MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
4005                         MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
4006                         MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
4007                         MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
4008                         MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
4009                         MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
4010                         MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
4011                 ))
4012         },
4013         { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
4014                         0, 0,
4015                         0, 0,
4016                         0, 0,
4017                         MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
4018                         0, 0,
4019                         0, 0,
4020                         0, 0,
4021                         0, 0,
4022                         0, 0,
4023                         0, 0,
4024                         0, 0,
4025                         0, 0,
4026                         0, 0,
4027                         0, 0,
4028                         0, 0,
4029                         0, 0,
4030                         MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
4031                         0, 0,
4032                         0, 0,
4033                         0, 0,
4034                         MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
4035                         0, 0,
4036                         MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
4037                         0, 0,
4038                         0, 0,
4039                         MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
4040                         0, 0,
4041                         0, 0,
4042                         0, 0,
4043                         MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
4044                         0, 0,
4045                         0, 0,
4046                 ))
4047         },
4048         { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
4049                         0, 0,
4050                         0, 0,
4051                         MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
4052                         0, 0,
4053                         MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
4054                         MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
4055                         0, 0,
4056                         0, 0,
4057                         0, 0,
4058                         MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
4059                         MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
4060                         MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
4061                         MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
4062                         0, 0,
4063                         0, 0,
4064                         0, 0,
4065                         MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
4066                         0, 0,
4067                         MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
4068                         MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
4069                         MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
4070                         MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
4071                         MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
4072                         MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
4073                         MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
4074                         0, 0,
4075                         0, 0,
4076                         MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
4077                         0, 0,
4078                         0, 0,
4079                         MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
4080                         0, 0,
4081                 ))
4082         },
4083         { },
4084 };
4085
4086 static const struct pinmux_data_reg pinmux_data_regs[] = {
4087         { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
4088                         PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
4089                         PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
4090                         PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
4091                         PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
4092                         PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
4093                         PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
4094                         PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
4095                         PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
4096         },
4097         { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
4098                         PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
4099                         PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
4100                         PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
4101                         PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
4102                         PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
4103                         PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
4104                         PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
4105                         PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
4106         },
4107         { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32, GROUP(
4108                         PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
4109                         PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
4110                         PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
4111                         PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
4112                         PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
4113                         PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
4114                         PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
4115                         PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
4116         },
4117         { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32, GROUP(
4118                         0, 0, 0, 0,
4119                         0, 0, 0, 0,
4120                         0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
4121                         PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
4122                         PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
4123                         PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
4124                         PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
4125                         PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
4126         },
4127         { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32, GROUP(
4128                         PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
4129                         PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
4130                         PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
4131                         PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
4132                         PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
4133                         PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
4134                         PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
4135                         PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
4136         },
4137         { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32, GROUP(
4138                         0, 0, 0, 0,
4139                         0, 0, 0, 0,
4140                         0, 0, 0, 0,
4141                         0, 0, 0, 0,
4142                         0, 0, 0, 0,
4143                         0, 0, 0, 0,
4144                         0, 0, 0, PORT164_DATA,
4145                         PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
4146         },
4147         { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32, GROUP(
4148                         PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
4149                         PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
4150                         PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
4151                         PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
4152                         PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
4153                         PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
4154                         PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
4155                         PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
4156         },
4157         { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32, GROUP(
4158                         PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
4159                         PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
4160                         PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
4161                         PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
4162                         PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
4163                         PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
4164                         PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
4165                         PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA ))
4166         },
4167         { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32, GROUP(
4168                         0, 0, 0, 0,
4169                         0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
4170                         PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
4171                         PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
4172                         PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
4173                         PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
4174                         PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
4175                         PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA ))
4176         },
4177         { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32, GROUP(
4178                         0, 0, 0, 0,
4179                         0, 0, 0, 0,
4180                         0, 0, PORT309_DATA, PORT308_DATA,
4181                         PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
4182                         PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
4183                         PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
4184                         PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
4185                         PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA ))
4186         },
4187         { },
4188 };
4189
4190 static const struct pinmux_irq pinmux_irqs[] = {
4191         PINMUX_IRQ(11),         /* IRQ0 */
4192         PINMUX_IRQ(10),         /* IRQ1 */
4193         PINMUX_IRQ(149),        /* IRQ2 */
4194         PINMUX_IRQ(224),        /* IRQ3 */
4195         PINMUX_IRQ(159),        /* IRQ4 */
4196         PINMUX_IRQ(227),        /* IRQ5 */
4197         PINMUX_IRQ(147),        /* IRQ6 */
4198         PINMUX_IRQ(150),        /* IRQ7 */
4199         PINMUX_IRQ(223),        /* IRQ8 */
4200         PINMUX_IRQ(56, 308),    /* IRQ9 */
4201         PINMUX_IRQ(54),         /* IRQ10 */
4202         PINMUX_IRQ(238),        /* IRQ11 */
4203         PINMUX_IRQ(156),        /* IRQ12 */
4204         PINMUX_IRQ(239),        /* IRQ13 */
4205         PINMUX_IRQ(251),        /* IRQ14 */
4206         PINMUX_IRQ(0),          /* IRQ15 */
4207         PINMUX_IRQ(249),        /* IRQ16 */
4208         PINMUX_IRQ(234),        /* IRQ17 */
4209         PINMUX_IRQ(13),         /* IRQ18 */
4210         PINMUX_IRQ(9),          /* IRQ19 */
4211         PINMUX_IRQ(14),         /* IRQ20 */
4212         PINMUX_IRQ(15),         /* IRQ21 */
4213         PINMUX_IRQ(40),         /* IRQ22 */
4214         PINMUX_IRQ(53),         /* IRQ23 */
4215         PINMUX_IRQ(118),        /* IRQ24 */
4216         PINMUX_IRQ(164),        /* IRQ25 */
4217         PINMUX_IRQ(115),        /* IRQ26 */
4218         PINMUX_IRQ(116),        /* IRQ27 */
4219         PINMUX_IRQ(117),        /* IRQ28 */
4220         PINMUX_IRQ(28),         /* IRQ29 */
4221         PINMUX_IRQ(27),         /* IRQ30 */
4222         PINMUX_IRQ(26),         /* IRQ31 */
4223 };
4224
4225 /* -----------------------------------------------------------------------------
4226  * VCCQ MC0 regulator
4227  */
4228
4229 static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
4230 {
4231         struct sh_pfc *pfc = reg->reg_data;
4232         void __iomem *addr = pfc->windows[1].virt + 4;
4233         unsigned long flags;
4234         u32 value;
4235
4236         spin_lock_irqsave(&pfc->lock, flags);
4237
4238         value = ioread32(addr);
4239
4240         if (enable)
4241                 value |= BIT(28);
4242         else
4243                 value &= ~BIT(28);
4244
4245         iowrite32(value, addr);
4246
4247         spin_unlock_irqrestore(&pfc->lock, flags);
4248 }
4249
4250 static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
4251 {
4252         sh73a0_vccq_mc0_endisable(reg, true);
4253         return 0;
4254 }
4255
4256 static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
4257 {
4258         sh73a0_vccq_mc0_endisable(reg, false);
4259         return 0;
4260 }
4261
4262 static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
4263 {
4264         struct sh_pfc *pfc = reg->reg_data;
4265         void __iomem *addr = pfc->windows[1].virt + 4;
4266         unsigned long flags;
4267         u32 value;
4268
4269         spin_lock_irqsave(&pfc->lock, flags);
4270         value = ioread32(addr);
4271         spin_unlock_irqrestore(&pfc->lock, flags);
4272
4273         return !!(value & BIT(28));
4274 }
4275
4276 static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
4277 {
4278         return 3300000;
4279 }
4280
4281 static const struct regulator_ops sh73a0_vccq_mc0_ops = {
4282         .enable = sh73a0_vccq_mc0_enable,
4283         .disable = sh73a0_vccq_mc0_disable,
4284         .is_enabled = sh73a0_vccq_mc0_is_enabled,
4285         .get_voltage = sh73a0_vccq_mc0_get_voltage,
4286 };
4287
4288 static const struct regulator_desc sh73a0_vccq_mc0_desc = {
4289         .owner = THIS_MODULE,
4290         .name = "vccq_mc0",
4291         .type = REGULATOR_VOLTAGE,
4292         .ops = &sh73a0_vccq_mc0_ops,
4293 };
4294
4295 static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
4296         REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
4297         REGULATOR_SUPPLY("vqmmc", "ee100000.sdhi"),
4298 };
4299
4300 static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
4301         .constraints = {
4302                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
4303         },
4304         .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
4305         .consumer_supplies = sh73a0_vccq_mc0_consumers,
4306 };
4307
4308 /* -----------------------------------------------------------------------------
4309  * Pin bias
4310  */
4311
4312 static const unsigned int sh73a0_portcr_offsets[] = {
4313         0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
4314         0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
4315 };
4316
4317 static void __iomem *sh73a0_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
4318 {
4319         return pfc->windows->virt + sh73a0_portcr_offsets[pin >> 5] + pin;
4320 }
4321
4322 /* -----------------------------------------------------------------------------
4323  * SoC information
4324  */
4325
4326 static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
4327 {
4328         struct regulator_config cfg = { };
4329         struct regulator_dev *vccq;
4330         int ret;
4331
4332         cfg.dev = pfc->dev;
4333         cfg.init_data = &sh73a0_vccq_mc0_init_data;
4334         cfg.driver_data = pfc;
4335
4336         vccq = devm_regulator_register(pfc->dev, &sh73a0_vccq_mc0_desc, &cfg);
4337         if (IS_ERR(vccq)) {
4338                 ret = PTR_ERR(vccq);
4339                 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
4340                         ret);
4341                 return ret;
4342         }
4343
4344         return 0;
4345 }
4346
4347 static const struct sh_pfc_soc_operations sh73a0_pfc_ops = {
4348         .init = sh73a0_pinmux_soc_init,
4349         .get_bias = rmobile_pinmux_get_bias,
4350         .set_bias = rmobile_pinmux_set_bias,
4351         .pin_to_portcr = sh73a0_pin_to_portcr,
4352 };
4353
4354 const struct sh_pfc_soc_info sh73a0_pinmux_info = {
4355         .name = "sh73a0_pfc",
4356         .ops = &sh73a0_pfc_ops,
4357
4358         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
4359         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
4360         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4361
4362         .pins = pinmux_pins,
4363         .nr_pins = ARRAY_SIZE(pinmux_pins),
4364         .groups = pinmux_groups,
4365         .nr_groups = ARRAY_SIZE(pinmux_groups),
4366         .functions = pinmux_functions,
4367         .nr_functions = ARRAY_SIZE(pinmux_functions),
4368
4369         .cfg_regs = pinmux_config_regs,
4370         .data_regs = pinmux_data_regs,
4371
4372         .pinmux_data = pinmux_data,
4373         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4374
4375         .gpio_irq = pinmux_irqs,
4376         .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
4377 };