1 // SPDX-License-Identifier: GPL-2.0
3 * R8A77965 processor support - PFC hardware block.
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Copyright (C) 2016-2019 Renesas Electronics Corp.
8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
10 * R-Car Gen3 processor support - PFC hardware block.
12 * Copyright (C) 2015 Renesas Electronics Corporation
15 #include <linux/errno.h>
16 #include <linux/kernel.h>
20 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
22 #define CPU_ALL_GP(fn, sfx) \
23 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
36 #define CPU_ALL_NOGP(fn) \
37 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
38 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
56 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
71 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
72 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
73 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
75 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
76 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
77 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
78 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
81 * F_() : just information
82 * FM() : macro for FN_xxx / xxx_MARK
86 #define GPSR0_15 F_(D15, IP7_11_8)
87 #define GPSR0_14 F_(D14, IP7_7_4)
88 #define GPSR0_13 F_(D13, IP7_3_0)
89 #define GPSR0_12 F_(D12, IP6_31_28)
90 #define GPSR0_11 F_(D11, IP6_27_24)
91 #define GPSR0_10 F_(D10, IP6_23_20)
92 #define GPSR0_9 F_(D9, IP6_19_16)
93 #define GPSR0_8 F_(D8, IP6_15_12)
94 #define GPSR0_7 F_(D7, IP6_11_8)
95 #define GPSR0_6 F_(D6, IP6_7_4)
96 #define GPSR0_5 F_(D5, IP6_3_0)
97 #define GPSR0_4 F_(D4, IP5_31_28)
98 #define GPSR0_3 F_(D3, IP5_27_24)
99 #define GPSR0_2 F_(D2, IP5_23_20)
100 #define GPSR0_1 F_(D1, IP5_19_16)
101 #define GPSR0_0 F_(D0, IP5_15_12)
104 #define GPSR1_28 FM(CLKOUT)
105 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
106 #define GPSR1_26 F_(WE1_N, IP5_7_4)
107 #define GPSR1_25 F_(WE0_N, IP5_3_0)
108 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
109 #define GPSR1_23 F_(RD_N, IP4_27_24)
110 #define GPSR1_22 F_(BS_N, IP4_23_20)
111 #define GPSR1_21 F_(CS1_N, IP4_19_16)
112 #define GPSR1_20 F_(CS0_N, IP4_15_12)
113 #define GPSR1_19 F_(A19, IP4_11_8)
114 #define GPSR1_18 F_(A18, IP4_7_4)
115 #define GPSR1_17 F_(A17, IP4_3_0)
116 #define GPSR1_16 F_(A16, IP3_31_28)
117 #define GPSR1_15 F_(A15, IP3_27_24)
118 #define GPSR1_14 F_(A14, IP3_23_20)
119 #define GPSR1_13 F_(A13, IP3_19_16)
120 #define GPSR1_12 F_(A12, IP3_15_12)
121 #define GPSR1_11 F_(A11, IP3_11_8)
122 #define GPSR1_10 F_(A10, IP3_7_4)
123 #define GPSR1_9 F_(A9, IP3_3_0)
124 #define GPSR1_8 F_(A8, IP2_31_28)
125 #define GPSR1_7 F_(A7, IP2_27_24)
126 #define GPSR1_6 F_(A6, IP2_23_20)
127 #define GPSR1_5 F_(A5, IP2_19_16)
128 #define GPSR1_4 F_(A4, IP2_15_12)
129 #define GPSR1_3 F_(A3, IP2_11_8)
130 #define GPSR1_2 F_(A2, IP2_7_4)
131 #define GPSR1_1 F_(A1, IP2_3_0)
132 #define GPSR1_0 F_(A0, IP1_31_28)
135 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
136 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
137 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
138 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
139 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
140 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
141 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
142 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
143 #define GPSR2_6 F_(PWM0, IP1_19_16)
144 #define GPSR2_5 F_(IRQ5, IP1_15_12)
145 #define GPSR2_4 F_(IRQ4, IP1_11_8)
146 #define GPSR2_3 F_(IRQ3, IP1_7_4)
147 #define GPSR2_2 F_(IRQ2, IP1_3_0)
148 #define GPSR2_1 F_(IRQ1, IP0_31_28)
149 #define GPSR2_0 F_(IRQ0, IP0_27_24)
152 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
153 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
154 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
155 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
156 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
157 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
158 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
159 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
160 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
161 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
162 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
163 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
164 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
165 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
166 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
167 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
170 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
171 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
172 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
173 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
174 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
175 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
176 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
177 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
178 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
179 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
180 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
181 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
182 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
183 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
184 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
185 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
186 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
187 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
190 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
191 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
192 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
193 #define GPSR5_22 FM(MSIOF0_RXD)
194 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
195 #define GPSR5_20 FM(MSIOF0_TXD)
196 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
197 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
198 #define GPSR5_17 FM(MSIOF0_SCK)
199 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
200 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
201 #define GPSR5_14 F_(HTX0, IP13_19_16)
202 #define GPSR5_13 F_(HRX0, IP13_15_12)
203 #define GPSR5_12 F_(HSCK0, IP13_11_8)
204 #define GPSR5_11 F_(RX2_A, IP13_7_4)
205 #define GPSR5_10 F_(TX2_A, IP13_3_0)
206 #define GPSR5_9 F_(SCK2, IP12_31_28)
207 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
208 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
209 #define GPSR5_6 F_(TX1_A, IP12_19_16)
210 #define GPSR5_5 F_(RX1_A, IP12_15_12)
211 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
212 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
213 #define GPSR5_2 F_(TX0, IP12_3_0)
214 #define GPSR5_1 F_(RX0, IP11_31_28)
215 #define GPSR5_0 F_(SCK0, IP11_27_24)
218 #define GPSR6_31 F_(GP6_31, IP18_7_4)
219 #define GPSR6_30 F_(GP6_30, IP18_3_0)
220 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
221 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
222 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
223 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
224 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
225 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
226 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
227 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
228 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
229 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
230 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
231 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
232 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
233 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
234 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
235 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
236 #define GPSR6_13 FM(SSI_SDATA5)
237 #define GPSR6_12 FM(SSI_WS5)
238 #define GPSR6_11 FM(SSI_SCK5)
239 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
240 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
241 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
242 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
243 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
244 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
245 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
246 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
247 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
248 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
249 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
252 #define GPSR7_3 FM(GP7_03)
253 #define GPSR7_2 FM(GP7_02)
254 #define GPSR7_1 FM(AVS2)
255 #define GPSR7_0 FM(AVS1)
258 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
259 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
288 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
319 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
355 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
376 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
385 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
405 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
406 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
407 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
408 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
409 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
411 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
413 #define PINMUX_GPSR \
421 GPSR1_25 GPSR5_25 GPSR6_25 \
422 GPSR1_24 GPSR5_24 GPSR6_24 \
423 GPSR1_23 GPSR5_23 GPSR6_23 \
424 GPSR1_22 GPSR5_22 GPSR6_22 \
425 GPSR1_21 GPSR5_21 GPSR6_21 \
426 GPSR1_20 GPSR5_20 GPSR6_20 \
427 GPSR1_19 GPSR5_19 GPSR6_19 \
428 GPSR1_18 GPSR5_18 GPSR6_18 \
429 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
430 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
431 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
432 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
433 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
434 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
435 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
436 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
437 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
438 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
439 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
440 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
441 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
442 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
443 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
444 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
445 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
446 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
448 #define PINMUX_IPSR \
450 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
451 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
452 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
453 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
454 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
455 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
456 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
457 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
459 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
460 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
461 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
462 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
463 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
464 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
465 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
466 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
468 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
469 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
470 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
471 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
472 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
473 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
474 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
475 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
477 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
478 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
479 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
480 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
481 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
482 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
483 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
484 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
486 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
487 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
488 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
489 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
490 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
491 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
492 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
493 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
495 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
496 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
497 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
498 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
499 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
500 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
501 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
502 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
503 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
504 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
505 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
506 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
507 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
508 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
509 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
510 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
511 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
512 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
513 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
515 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
516 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
517 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
518 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
519 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
520 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
521 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
522 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
523 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
524 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
525 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
526 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
527 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
528 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
529 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
530 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
531 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
532 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
533 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
534 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
535 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
536 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
537 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
539 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
540 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
541 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
542 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
543 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
544 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
545 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
546 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
547 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
548 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
549 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
550 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
551 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
552 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
554 #define PINMUX_MOD_SELS \
556 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
558 MOD_SEL1_29_28_27 MOD_SEL2_29 \
559 MOD_SEL0_28_27 MOD_SEL2_28_27 \
560 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
561 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
562 MOD_SEL0_23 MOD_SEL1_23_22_21 \
563 MOD_SEL0_22 MOD_SEL2_22 \
564 MOD_SEL0_21 MOD_SEL2_21 \
565 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
566 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
567 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
569 MOD_SEL0_16 MOD_SEL1_16 \
573 MOD_SEL0_12 MOD_SEL1_12 \
574 MOD_SEL0_11 MOD_SEL1_11 \
575 MOD_SEL0_10 MOD_SEL1_10 \
576 MOD_SEL0_9_8 MOD_SEL1_9 \
579 MOD_SEL0_5 MOD_SEL1_5 \
580 MOD_SEL0_4_3 MOD_SEL1_4 \
584 MOD_SEL1_0 MOD_SEL2_0
587 * These pins are not able to be muxed but have other properties
588 * that can be set, such as drive-strength or pull-up/pull-down enable.
590 #define PINMUX_STATIC \
591 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
592 FM(QSPI0_IO2) FM(QSPI0_IO3) \
593 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
594 FM(QSPI1_IO2) FM(QSPI1_IO3) \
595 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
596 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
597 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
598 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
600 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
601 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
603 #define PINMUX_PHYS \
604 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
614 #define FM(x) FN_##x,
615 PINMUX_FUNCTION_BEGIN,
625 #define FM(x) x##_MARK,
637 static const u16 pinmux_data[] = {
638 PINMUX_DATA_GP_ALL(),
642 PINMUX_SINGLE(CLKOUT),
643 PINMUX_SINGLE(GP7_03),
644 PINMUX_SINGLE(GP7_02),
645 PINMUX_SINGLE(MSIOF0_RXD),
646 PINMUX_SINGLE(MSIOF0_SCK),
647 PINMUX_SINGLE(MSIOF0_TXD),
648 PINMUX_SINGLE(SSI_SCK5),
649 PINMUX_SINGLE(SSI_SDATA5),
650 PINMUX_SINGLE(SSI_WS5),
653 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
654 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
656 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
657 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
658 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
660 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
661 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
662 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
664 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
665 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
666 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
667 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
669 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
672 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
674 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
677 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
679 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
680 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
681 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
682 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
683 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
684 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
685 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
687 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
688 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
689 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
690 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
691 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
693 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
696 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
697 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
698 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
699 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
700 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
701 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
703 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
704 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
705 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
706 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
707 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
708 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
710 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
711 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
712 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
713 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
714 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
715 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
717 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
718 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
719 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
720 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
721 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
722 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
723 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
725 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
726 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
727 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
728 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
730 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
733 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
734 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
736 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
737 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
738 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
739 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
741 PINMUX_IPSR_GPSR(IP1_31_28, A0),
742 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
743 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
744 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
745 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
746 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
749 PINMUX_IPSR_GPSR(IP2_3_0, A1),
750 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
751 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
752 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
753 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
754 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
756 PINMUX_IPSR_GPSR(IP2_7_4, A2),
757 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
758 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
759 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
760 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
761 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
763 PINMUX_IPSR_GPSR(IP2_11_8, A3),
764 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
765 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
766 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
767 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
768 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
770 PINMUX_IPSR_GPSR(IP2_15_12, A4),
771 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
772 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
773 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
774 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
775 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
777 PINMUX_IPSR_GPSR(IP2_19_16, A5),
778 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
779 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
780 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
781 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
782 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
783 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
785 PINMUX_IPSR_GPSR(IP2_23_20, A6),
786 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
787 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
788 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
789 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
790 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
791 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
793 PINMUX_IPSR_GPSR(IP2_27_24, A7),
794 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
795 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
796 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
797 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
798 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
799 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
801 PINMUX_IPSR_GPSR(IP2_31_28, A8),
802 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
803 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
804 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
805 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
806 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
807 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
810 PINMUX_IPSR_GPSR(IP3_3_0, A9),
811 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
812 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
813 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
815 PINMUX_IPSR_GPSR(IP3_7_4, A10),
816 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
817 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
818 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
820 PINMUX_IPSR_GPSR(IP3_11_8, A11),
821 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
822 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
823 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
824 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
825 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
826 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
827 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
828 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
830 PINMUX_IPSR_GPSR(IP3_15_12, A12),
831 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
832 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
833 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
834 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
835 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
837 PINMUX_IPSR_GPSR(IP3_19_16, A13),
838 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
839 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
840 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
841 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
842 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
844 PINMUX_IPSR_GPSR(IP3_23_20, A14),
845 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
846 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
847 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
848 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
849 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
851 PINMUX_IPSR_GPSR(IP3_27_24, A15),
852 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
853 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
854 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
855 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
856 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
858 PINMUX_IPSR_GPSR(IP3_31_28, A16),
859 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
860 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
861 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
864 PINMUX_IPSR_GPSR(IP4_3_0, A17),
865 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
866 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
867 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
869 PINMUX_IPSR_GPSR(IP4_7_4, A18),
870 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
871 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
872 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
874 PINMUX_IPSR_GPSR(IP4_11_8, A19),
875 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
876 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
877 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
879 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
880 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
882 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
883 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
884 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
886 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
887 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
888 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
889 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
890 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
891 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
892 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
893 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
895 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
896 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
897 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
898 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
899 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
900 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
902 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
903 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
904 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
905 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
906 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
907 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
910 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
911 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
912 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
913 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
914 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
915 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
916 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
918 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
919 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
920 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
921 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
922 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
923 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
924 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
925 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
927 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
928 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
929 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
930 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
932 PINMUX_IPSR_GPSR(IP5_15_12, D0),
933 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
934 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
935 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
936 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
938 PINMUX_IPSR_GPSR(IP5_19_16, D1),
939 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
940 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
941 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
942 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
944 PINMUX_IPSR_GPSR(IP5_23_20, D2),
945 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
946 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
947 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
949 PINMUX_IPSR_GPSR(IP5_27_24, D3),
950 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
951 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
952 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
954 PINMUX_IPSR_GPSR(IP5_31_28, D4),
955 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
956 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
957 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
960 PINMUX_IPSR_GPSR(IP6_3_0, D5),
961 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
962 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
963 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
965 PINMUX_IPSR_GPSR(IP6_7_4, D6),
966 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
967 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
968 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
970 PINMUX_IPSR_GPSR(IP6_11_8, D7),
971 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
972 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
973 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
975 PINMUX_IPSR_GPSR(IP6_15_12, D8),
976 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
977 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
978 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
979 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
980 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
982 PINMUX_IPSR_GPSR(IP6_19_16, D9),
983 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
984 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
985 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
986 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
988 PINMUX_IPSR_GPSR(IP6_23_20, D10),
989 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
990 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
991 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
992 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
993 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
994 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
996 PINMUX_IPSR_GPSR(IP6_27_24, D11),
997 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
998 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
999 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
1000 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
1001 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
1002 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
1004 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1005 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1006 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1007 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1008 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1009 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1012 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1013 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1014 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1015 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1016 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1017 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1019 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1020 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1021 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1022 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1023 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1024 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1025 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1027 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1028 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1029 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1030 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1031 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1032 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1033 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1035 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1036 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1037 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1039 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1040 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1041 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1043 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1044 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1045 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1046 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1048 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1049 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1050 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1051 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1054 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1055 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1056 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1057 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1059 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1060 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1061 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1062 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1064 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1065 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1066 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1068 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1069 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1070 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1071 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1072 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1074 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1075 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1076 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1077 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1078 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1079 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1081 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1082 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1083 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1084 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1085 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1086 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1088 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1089 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1090 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1091 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1092 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1093 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1095 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1096 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1097 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1098 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1099 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1100 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1103 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1104 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1106 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1107 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1109 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1110 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1112 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1113 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1115 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1116 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1118 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1119 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1121 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1122 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1123 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1125 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1126 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1129 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1130 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1132 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1133 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1135 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1136 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1138 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1139 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1141 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1142 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1144 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1145 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1146 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1148 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1149 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1150 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1152 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1153 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1154 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1157 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1158 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1159 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1161 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1162 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1164 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1165 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
1166 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1167 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1169 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1170 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
1171 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1173 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1174 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1175 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1176 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
1178 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1179 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1180 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1181 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
1183 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1184 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1185 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1186 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
1187 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1188 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1189 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1190 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1191 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1192 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1194 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1195 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1196 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1197 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1198 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1201 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1202 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1203 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1204 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1205 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1207 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1208 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1209 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1210 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1211 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1212 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1213 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1214 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1216 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1217 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1218 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1219 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
1220 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1221 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1222 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1223 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1225 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1226 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1227 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1228 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1229 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1231 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1232 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1233 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1234 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1235 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1237 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1238 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1239 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1240 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1241 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1242 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1243 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1245 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1246 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1247 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1248 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1249 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1250 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1251 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1253 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1254 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1255 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1256 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1257 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1258 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1259 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1262 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1263 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1264 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1265 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1266 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1267 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1269 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1270 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1271 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1272 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1273 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1274 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1276 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1277 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1278 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
1279 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1280 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1281 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1282 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1283 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1285 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1286 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1287 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1288 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1289 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1290 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1292 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1293 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1294 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1295 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1296 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1297 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1299 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1300 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1301 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1302 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1303 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1304 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1305 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1306 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1308 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1309 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1310 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1311 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1312 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1313 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1314 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1316 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1317 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1318 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1319 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1322 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1323 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1324 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1325 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
1326 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1327 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1328 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1329 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1331 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1332 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1333 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1334 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
1335 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1336 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1337 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1338 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1340 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1341 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1342 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1344 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1345 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1346 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1347 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1349 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1350 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1351 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1353 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1354 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1356 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1357 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1359 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1360 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1363 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1365 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1366 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1368 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1369 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1370 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1372 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1373 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1374 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1375 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1377 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1378 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1379 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1380 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1381 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1382 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1383 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1385 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1386 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1387 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1388 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1389 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1390 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1391 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1393 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1394 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1395 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1396 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1397 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1398 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1399 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1401 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1402 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1403 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1404 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1405 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1406 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1407 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1410 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1411 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1413 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1414 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1416 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1417 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1418 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1420 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1421 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1422 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1423 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1424 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1425 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1426 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1428 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1429 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1430 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1431 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1432 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1433 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1434 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1436 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1437 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1438 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1439 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1440 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1441 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1442 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1443 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1445 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1446 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1447 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1448 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1449 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1450 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1451 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1453 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1454 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1455 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1456 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1457 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1458 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1459 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1460 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1463 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
1465 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
1466 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1467 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1468 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1469 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1471 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1472 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1473 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1474 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1475 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1476 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1477 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1479 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1480 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1481 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1482 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1483 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1484 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1486 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1487 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1488 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1489 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1490 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1491 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1492 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1493 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1494 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1496 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1497 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1498 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1499 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1500 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1501 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1502 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1503 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1504 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1506 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1507 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1508 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1509 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1510 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1511 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1512 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1513 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1514 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1515 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1516 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1518 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1519 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1520 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1521 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1522 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1523 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1524 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1525 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1526 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1529 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1530 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1531 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1532 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1533 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1534 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1535 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1536 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1537 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1539 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1540 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1541 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1542 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1543 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1544 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1545 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1546 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1547 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1550 * Static pins can not be muxed between different functions but
1551 * still need mark entries in the pinmux list. Add each static
1552 * pin to the list without an associated function. The sh-pfc
1553 * core will do the right thing and skip trying to mux the pin
1554 * while still applying configuration to it.
1556 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1562 * Pins not associated with a GPIO port.
1569 static const struct sh_pfc_pin pinmux_pins[] = {
1570 PINMUX_GPIO_GP_ALL(),
1574 /* - AUDIO CLOCK ------------------------------------------------------------ */
1575 static const unsigned int audio_clk_a_a_pins[] = {
1579 static const unsigned int audio_clk_a_a_mux[] = {
1582 static const unsigned int audio_clk_a_b_pins[] = {
1586 static const unsigned int audio_clk_a_b_mux[] = {
1589 static const unsigned int audio_clk_a_c_pins[] = {
1593 static const unsigned int audio_clk_a_c_mux[] = {
1596 static const unsigned int audio_clk_b_a_pins[] = {
1600 static const unsigned int audio_clk_b_a_mux[] = {
1603 static const unsigned int audio_clk_b_b_pins[] = {
1607 static const unsigned int audio_clk_b_b_mux[] = {
1610 static const unsigned int audio_clk_c_a_pins[] = {
1614 static const unsigned int audio_clk_c_a_mux[] = {
1617 static const unsigned int audio_clk_c_b_pins[] = {
1621 static const unsigned int audio_clk_c_b_mux[] = {
1624 static const unsigned int audio_clkout_a_pins[] = {
1628 static const unsigned int audio_clkout_a_mux[] = {
1629 AUDIO_CLKOUT_A_MARK,
1631 static const unsigned int audio_clkout_b_pins[] = {
1635 static const unsigned int audio_clkout_b_mux[] = {
1636 AUDIO_CLKOUT_B_MARK,
1638 static const unsigned int audio_clkout_c_pins[] = {
1642 static const unsigned int audio_clkout_c_mux[] = {
1643 AUDIO_CLKOUT_C_MARK,
1645 static const unsigned int audio_clkout_d_pins[] = {
1649 static const unsigned int audio_clkout_d_mux[] = {
1650 AUDIO_CLKOUT_D_MARK,
1652 static const unsigned int audio_clkout1_a_pins[] = {
1656 static const unsigned int audio_clkout1_a_mux[] = {
1657 AUDIO_CLKOUT1_A_MARK,
1659 static const unsigned int audio_clkout1_b_pins[] = {
1663 static const unsigned int audio_clkout1_b_mux[] = {
1664 AUDIO_CLKOUT1_B_MARK,
1666 static const unsigned int audio_clkout2_a_pins[] = {
1670 static const unsigned int audio_clkout2_a_mux[] = {
1671 AUDIO_CLKOUT2_A_MARK,
1673 static const unsigned int audio_clkout2_b_pins[] = {
1677 static const unsigned int audio_clkout2_b_mux[] = {
1678 AUDIO_CLKOUT2_B_MARK,
1681 static const unsigned int audio_clkout3_a_pins[] = {
1685 static const unsigned int audio_clkout3_a_mux[] = {
1686 AUDIO_CLKOUT3_A_MARK,
1688 static const unsigned int audio_clkout3_b_pins[] = {
1692 static const unsigned int audio_clkout3_b_mux[] = {
1693 AUDIO_CLKOUT3_B_MARK,
1696 /* - EtherAVB --------------------------------------------------------------- */
1697 static const unsigned int avb_link_pins[] = {
1701 static const unsigned int avb_link_mux[] = {
1704 static const unsigned int avb_magic_pins[] = {
1708 static const unsigned int avb_magic_mux[] = {
1711 static const unsigned int avb_phy_int_pins[] = {
1715 static const unsigned int avb_phy_int_mux[] = {
1718 static const unsigned int avb_mdio_pins[] = {
1719 /* AVB_MDC, AVB_MDIO */
1720 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1722 static const unsigned int avb_mdio_mux[] = {
1723 AVB_MDC_MARK, AVB_MDIO_MARK,
1725 static const unsigned int avb_mii_pins[] = {
1727 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1728 * AVB_TD1, AVB_TD2, AVB_TD3,
1729 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1730 * AVB_RD1, AVB_RD2, AVB_RD3,
1733 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1734 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1735 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1736 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1739 static const unsigned int avb_mii_mux[] = {
1740 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1741 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1742 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1743 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1746 static const unsigned int avb_avtp_pps_pins[] = {
1750 static const unsigned int avb_avtp_pps_mux[] = {
1753 static const unsigned int avb_avtp_match_a_pins[] = {
1754 /* AVB_AVTP_MATCH_A */
1757 static const unsigned int avb_avtp_match_a_mux[] = {
1758 AVB_AVTP_MATCH_A_MARK,
1760 static const unsigned int avb_avtp_capture_a_pins[] = {
1761 /* AVB_AVTP_CAPTURE_A */
1764 static const unsigned int avb_avtp_capture_a_mux[] = {
1765 AVB_AVTP_CAPTURE_A_MARK,
1767 static const unsigned int avb_avtp_match_b_pins[] = {
1768 /* AVB_AVTP_MATCH_B */
1771 static const unsigned int avb_avtp_match_b_mux[] = {
1772 AVB_AVTP_MATCH_B_MARK,
1774 static const unsigned int avb_avtp_capture_b_pins[] = {
1775 /* AVB_AVTP_CAPTURE_B */
1778 static const unsigned int avb_avtp_capture_b_mux[] = {
1779 AVB_AVTP_CAPTURE_B_MARK,
1782 /* - CAN ------------------------------------------------------------------ */
1783 static const unsigned int can0_data_a_pins[] = {
1785 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1788 static const unsigned int can0_data_a_mux[] = {
1789 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1792 static const unsigned int can0_data_b_pins[] = {
1794 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1797 static const unsigned int can0_data_b_mux[] = {
1798 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1801 static const unsigned int can1_data_pins[] = {
1803 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1806 static const unsigned int can1_data_mux[] = {
1807 CAN1_TX_MARK, CAN1_RX_MARK,
1810 /* - CAN Clock -------------------------------------------------------------- */
1811 static const unsigned int can_clk_pins[] = {
1816 static const unsigned int can_clk_mux[] = {
1820 /* - CAN FD --------------------------------------------------------------- */
1821 static const unsigned int canfd0_data_a_pins[] = {
1823 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1826 static const unsigned int canfd0_data_a_mux[] = {
1827 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1830 static const unsigned int canfd0_data_b_pins[] = {
1832 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1835 static const unsigned int canfd0_data_b_mux[] = {
1836 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1839 static const unsigned int canfd1_data_pins[] = {
1841 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1844 static const unsigned int canfd1_data_mux[] = {
1845 CANFD1_TX_MARK, CANFD1_RX_MARK,
1848 #ifdef CONFIG_PINCTRL_PFC_R8A77965
1849 /* - DRIF0 --------------------------------------------------------------- */
1850 static const unsigned int drif0_ctrl_a_pins[] = {
1852 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1855 static const unsigned int drif0_ctrl_a_mux[] = {
1856 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1859 static const unsigned int drif0_data0_a_pins[] = {
1864 static const unsigned int drif0_data0_a_mux[] = {
1868 static const unsigned int drif0_data1_a_pins[] = {
1873 static const unsigned int drif0_data1_a_mux[] = {
1877 static const unsigned int drif0_ctrl_b_pins[] = {
1879 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1882 static const unsigned int drif0_ctrl_b_mux[] = {
1883 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1886 static const unsigned int drif0_data0_b_pins[] = {
1891 static const unsigned int drif0_data0_b_mux[] = {
1895 static const unsigned int drif0_data1_b_pins[] = {
1900 static const unsigned int drif0_data1_b_mux[] = {
1904 static const unsigned int drif0_ctrl_c_pins[] = {
1906 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1909 static const unsigned int drif0_ctrl_c_mux[] = {
1910 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1913 static const unsigned int drif0_data0_c_pins[] = {
1918 static const unsigned int drif0_data0_c_mux[] = {
1922 static const unsigned int drif0_data1_c_pins[] = {
1927 static const unsigned int drif0_data1_c_mux[] = {
1931 /* - DRIF1 --------------------------------------------------------------- */
1932 static const unsigned int drif1_ctrl_a_pins[] = {
1934 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1937 static const unsigned int drif1_ctrl_a_mux[] = {
1938 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1941 static const unsigned int drif1_data0_a_pins[] = {
1946 static const unsigned int drif1_data0_a_mux[] = {
1950 static const unsigned int drif1_data1_a_pins[] = {
1955 static const unsigned int drif1_data1_a_mux[] = {
1959 static const unsigned int drif1_ctrl_b_pins[] = {
1961 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1964 static const unsigned int drif1_ctrl_b_mux[] = {
1965 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1968 static const unsigned int drif1_data0_b_pins[] = {
1973 static const unsigned int drif1_data0_b_mux[] = {
1977 static const unsigned int drif1_data1_b_pins[] = {
1982 static const unsigned int drif1_data1_b_mux[] = {
1986 static const unsigned int drif1_ctrl_c_pins[] = {
1988 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1991 static const unsigned int drif1_ctrl_c_mux[] = {
1992 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1995 static const unsigned int drif1_data0_c_pins[] = {
2000 static const unsigned int drif1_data0_c_mux[] = {
2004 static const unsigned int drif1_data1_c_pins[] = {
2009 static const unsigned int drif1_data1_c_mux[] = {
2013 /* - DRIF2 --------------------------------------------------------------- */
2014 static const unsigned int drif2_ctrl_a_pins[] = {
2016 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2019 static const unsigned int drif2_ctrl_a_mux[] = {
2020 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
2023 static const unsigned int drif2_data0_a_pins[] = {
2028 static const unsigned int drif2_data0_a_mux[] = {
2032 static const unsigned int drif2_data1_a_pins[] = {
2037 static const unsigned int drif2_data1_a_mux[] = {
2041 static const unsigned int drif2_ctrl_b_pins[] = {
2043 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2046 static const unsigned int drif2_ctrl_b_mux[] = {
2047 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2050 static const unsigned int drif2_data0_b_pins[] = {
2055 static const unsigned int drif2_data0_b_mux[] = {
2059 static const unsigned int drif2_data1_b_pins[] = {
2064 static const unsigned int drif2_data1_b_mux[] = {
2068 /* - DRIF3 --------------------------------------------------------------- */
2069 static const unsigned int drif3_ctrl_a_pins[] = {
2071 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2074 static const unsigned int drif3_ctrl_a_mux[] = {
2075 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2078 static const unsigned int drif3_data0_a_pins[] = {
2083 static const unsigned int drif3_data0_a_mux[] = {
2087 static const unsigned int drif3_data1_a_pins[] = {
2092 static const unsigned int drif3_data1_a_mux[] = {
2096 static const unsigned int drif3_ctrl_b_pins[] = {
2098 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2101 static const unsigned int drif3_ctrl_b_mux[] = {
2102 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2105 static const unsigned int drif3_data0_b_pins[] = {
2110 static const unsigned int drif3_data0_b_mux[] = {
2114 static const unsigned int drif3_data1_b_pins[] = {
2119 static const unsigned int drif3_data1_b_mux[] = {
2122 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */
2124 /* - DU --------------------------------------------------------------------- */
2125 static const unsigned int du_rgb666_pins[] = {
2126 /* R[7:2], G[7:2], B[7:2] */
2127 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2128 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2129 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2130 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2131 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2132 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2135 static const unsigned int du_rgb666_mux[] = {
2136 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2137 DU_DR3_MARK, DU_DR2_MARK,
2138 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2139 DU_DG3_MARK, DU_DG2_MARK,
2140 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2141 DU_DB3_MARK, DU_DB2_MARK,
2144 static const unsigned int du_rgb888_pins[] = {
2145 /* R[7:0], G[7:0], B[7:0] */
2146 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2147 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2148 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2149 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2150 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2151 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2152 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2153 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2154 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2157 static const unsigned int du_rgb888_mux[] = {
2158 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2159 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2160 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2161 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2162 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2163 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2166 static const unsigned int du_clk_out_0_pins[] = {
2171 static const unsigned int du_clk_out_0_mux[] = {
2175 static const unsigned int du_clk_out_1_pins[] = {
2180 static const unsigned int du_clk_out_1_mux[] = {
2184 static const unsigned int du_sync_pins[] = {
2185 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2186 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2189 static const unsigned int du_sync_mux[] = {
2190 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2193 static const unsigned int du_oddf_pins[] = {
2194 /* EXDISP/EXODDF/EXCDE */
2198 static const unsigned int du_oddf_mux[] = {
2199 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2202 static const unsigned int du_cde_pins[] = {
2207 static const unsigned int du_cde_mux[] = {
2211 static const unsigned int du_disp_pins[] = {
2216 static const unsigned int du_disp_mux[] = {
2220 /* - HSCIF0 ----------------------------------------------------------------- */
2221 static const unsigned int hscif0_data_pins[] = {
2223 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2226 static const unsigned int hscif0_data_mux[] = {
2227 HRX0_MARK, HTX0_MARK,
2230 static const unsigned int hscif0_clk_pins[] = {
2235 static const unsigned int hscif0_clk_mux[] = {
2239 static const unsigned int hscif0_ctrl_pins[] = {
2241 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2244 static const unsigned int hscif0_ctrl_mux[] = {
2245 HRTS0_N_MARK, HCTS0_N_MARK,
2248 /* - HSCIF1 ----------------------------------------------------------------- */
2249 static const unsigned int hscif1_data_a_pins[] = {
2251 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2254 static const unsigned int hscif1_data_a_mux[] = {
2255 HRX1_A_MARK, HTX1_A_MARK,
2258 static const unsigned int hscif1_clk_a_pins[] = {
2263 static const unsigned int hscif1_clk_a_mux[] = {
2267 static const unsigned int hscif1_ctrl_a_pins[] = {
2269 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2272 static const unsigned int hscif1_ctrl_a_mux[] = {
2273 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2276 static const unsigned int hscif1_data_b_pins[] = {
2278 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2281 static const unsigned int hscif1_data_b_mux[] = {
2282 HRX1_B_MARK, HTX1_B_MARK,
2285 static const unsigned int hscif1_clk_b_pins[] = {
2290 static const unsigned int hscif1_clk_b_mux[] = {
2294 static const unsigned int hscif1_ctrl_b_pins[] = {
2296 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2299 static const unsigned int hscif1_ctrl_b_mux[] = {
2300 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2303 /* - HSCIF2 ----------------------------------------------------------------- */
2304 static const unsigned int hscif2_data_a_pins[] = {
2306 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2309 static const unsigned int hscif2_data_a_mux[] = {
2310 HRX2_A_MARK, HTX2_A_MARK,
2313 static const unsigned int hscif2_clk_a_pins[] = {
2318 static const unsigned int hscif2_clk_a_mux[] = {
2322 static const unsigned int hscif2_ctrl_a_pins[] = {
2324 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2327 static const unsigned int hscif2_ctrl_a_mux[] = {
2328 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2331 static const unsigned int hscif2_data_b_pins[] = {
2333 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2336 static const unsigned int hscif2_data_b_mux[] = {
2337 HRX2_B_MARK, HTX2_B_MARK,
2340 static const unsigned int hscif2_clk_b_pins[] = {
2345 static const unsigned int hscif2_clk_b_mux[] = {
2349 static const unsigned int hscif2_ctrl_b_pins[] = {
2351 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2354 static const unsigned int hscif2_ctrl_b_mux[] = {
2355 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2358 static const unsigned int hscif2_data_c_pins[] = {
2360 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2363 static const unsigned int hscif2_data_c_mux[] = {
2364 HRX2_C_MARK, HTX2_C_MARK,
2367 static const unsigned int hscif2_clk_c_pins[] = {
2372 static const unsigned int hscif2_clk_c_mux[] = {
2376 static const unsigned int hscif2_ctrl_c_pins[] = {
2378 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2381 static const unsigned int hscif2_ctrl_c_mux[] = {
2382 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2385 /* - HSCIF3 ----------------------------------------------------------------- */
2386 static const unsigned int hscif3_data_a_pins[] = {
2388 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2391 static const unsigned int hscif3_data_a_mux[] = {
2392 HRX3_A_MARK, HTX3_A_MARK,
2395 static const unsigned int hscif3_clk_pins[] = {
2400 static const unsigned int hscif3_clk_mux[] = {
2404 static const unsigned int hscif3_ctrl_pins[] = {
2406 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2409 static const unsigned int hscif3_ctrl_mux[] = {
2410 HRTS3_N_MARK, HCTS3_N_MARK,
2413 static const unsigned int hscif3_data_b_pins[] = {
2415 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2418 static const unsigned int hscif3_data_b_mux[] = {
2419 HRX3_B_MARK, HTX3_B_MARK,
2422 static const unsigned int hscif3_data_c_pins[] = {
2424 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2427 static const unsigned int hscif3_data_c_mux[] = {
2428 HRX3_C_MARK, HTX3_C_MARK,
2431 static const unsigned int hscif3_data_d_pins[] = {
2433 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2436 static const unsigned int hscif3_data_d_mux[] = {
2437 HRX3_D_MARK, HTX3_D_MARK,
2440 /* - HSCIF4 ----------------------------------------------------------------- */
2441 static const unsigned int hscif4_data_a_pins[] = {
2443 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2446 static const unsigned int hscif4_data_a_mux[] = {
2447 HRX4_A_MARK, HTX4_A_MARK,
2450 static const unsigned int hscif4_clk_pins[] = {
2455 static const unsigned int hscif4_clk_mux[] = {
2459 static const unsigned int hscif4_ctrl_pins[] = {
2461 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2464 static const unsigned int hscif4_ctrl_mux[] = {
2465 HRTS4_N_MARK, HCTS4_N_MARK,
2468 static const unsigned int hscif4_data_b_pins[] = {
2470 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2473 static const unsigned int hscif4_data_b_mux[] = {
2474 HRX4_B_MARK, HTX4_B_MARK,
2477 /* - I2C -------------------------------------------------------------------- */
2478 static const unsigned int i2c0_pins[] = {
2480 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2483 static const unsigned int i2c0_mux[] = {
2484 SCL0_MARK, SDA0_MARK,
2487 static const unsigned int i2c1_a_pins[] = {
2489 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2492 static const unsigned int i2c1_a_mux[] = {
2493 SDA1_A_MARK, SCL1_A_MARK,
2496 static const unsigned int i2c1_b_pins[] = {
2498 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2501 static const unsigned int i2c1_b_mux[] = {
2502 SDA1_B_MARK, SCL1_B_MARK,
2505 static const unsigned int i2c2_a_pins[] = {
2507 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2510 static const unsigned int i2c2_a_mux[] = {
2511 SDA2_A_MARK, SCL2_A_MARK,
2514 static const unsigned int i2c2_b_pins[] = {
2516 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2519 static const unsigned int i2c2_b_mux[] = {
2520 SDA2_B_MARK, SCL2_B_MARK,
2523 static const unsigned int i2c3_pins[] = {
2525 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2528 static const unsigned int i2c3_mux[] = {
2529 SCL3_MARK, SDA3_MARK,
2532 static const unsigned int i2c5_pins[] = {
2534 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2537 static const unsigned int i2c5_mux[] = {
2538 SCL5_MARK, SDA5_MARK,
2541 static const unsigned int i2c6_a_pins[] = {
2543 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2546 static const unsigned int i2c6_a_mux[] = {
2547 SDA6_A_MARK, SCL6_A_MARK,
2550 static const unsigned int i2c6_b_pins[] = {
2552 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2555 static const unsigned int i2c6_b_mux[] = {
2556 SDA6_B_MARK, SCL6_B_MARK,
2559 static const unsigned int i2c6_c_pins[] = {
2561 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2564 static const unsigned int i2c6_c_mux[] = {
2565 SDA6_C_MARK, SCL6_C_MARK,
2568 /* - INTC-EX ---------------------------------------------------------------- */
2569 static const unsigned int intc_ex_irq0_pins[] = {
2573 static const unsigned int intc_ex_irq0_mux[] = {
2576 static const unsigned int intc_ex_irq1_pins[] = {
2580 static const unsigned int intc_ex_irq1_mux[] = {
2583 static const unsigned int intc_ex_irq2_pins[] = {
2587 static const unsigned int intc_ex_irq2_mux[] = {
2590 static const unsigned int intc_ex_irq3_pins[] = {
2594 static const unsigned int intc_ex_irq3_mux[] = {
2597 static const unsigned int intc_ex_irq4_pins[] = {
2601 static const unsigned int intc_ex_irq4_mux[] = {
2604 static const unsigned int intc_ex_irq5_pins[] = {
2608 static const unsigned int intc_ex_irq5_mux[] = {
2612 /* - MSIOF0 ----------------------------------------------------------------- */
2613 static const unsigned int msiof0_clk_pins[] = {
2617 static const unsigned int msiof0_clk_mux[] = {
2620 static const unsigned int msiof0_sync_pins[] = {
2624 static const unsigned int msiof0_sync_mux[] = {
2627 static const unsigned int msiof0_ss1_pins[] = {
2631 static const unsigned int msiof0_ss1_mux[] = {
2634 static const unsigned int msiof0_ss2_pins[] = {
2638 static const unsigned int msiof0_ss2_mux[] = {
2641 static const unsigned int msiof0_txd_pins[] = {
2645 static const unsigned int msiof0_txd_mux[] = {
2648 static const unsigned int msiof0_rxd_pins[] = {
2652 static const unsigned int msiof0_rxd_mux[] = {
2655 /* - MSIOF1 ----------------------------------------------------------------- */
2656 static const unsigned int msiof1_clk_a_pins[] = {
2660 static const unsigned int msiof1_clk_a_mux[] = {
2663 static const unsigned int msiof1_sync_a_pins[] = {
2667 static const unsigned int msiof1_sync_a_mux[] = {
2670 static const unsigned int msiof1_ss1_a_pins[] = {
2674 static const unsigned int msiof1_ss1_a_mux[] = {
2677 static const unsigned int msiof1_ss2_a_pins[] = {
2681 static const unsigned int msiof1_ss2_a_mux[] = {
2684 static const unsigned int msiof1_txd_a_pins[] = {
2688 static const unsigned int msiof1_txd_a_mux[] = {
2691 static const unsigned int msiof1_rxd_a_pins[] = {
2695 static const unsigned int msiof1_rxd_a_mux[] = {
2698 static const unsigned int msiof1_clk_b_pins[] = {
2702 static const unsigned int msiof1_clk_b_mux[] = {
2705 static const unsigned int msiof1_sync_b_pins[] = {
2709 static const unsigned int msiof1_sync_b_mux[] = {
2712 static const unsigned int msiof1_ss1_b_pins[] = {
2716 static const unsigned int msiof1_ss1_b_mux[] = {
2719 static const unsigned int msiof1_ss2_b_pins[] = {
2723 static const unsigned int msiof1_ss2_b_mux[] = {
2726 static const unsigned int msiof1_txd_b_pins[] = {
2730 static const unsigned int msiof1_txd_b_mux[] = {
2733 static const unsigned int msiof1_rxd_b_pins[] = {
2737 static const unsigned int msiof1_rxd_b_mux[] = {
2740 static const unsigned int msiof1_clk_c_pins[] = {
2744 static const unsigned int msiof1_clk_c_mux[] = {
2747 static const unsigned int msiof1_sync_c_pins[] = {
2751 static const unsigned int msiof1_sync_c_mux[] = {
2754 static const unsigned int msiof1_ss1_c_pins[] = {
2758 static const unsigned int msiof1_ss1_c_mux[] = {
2761 static const unsigned int msiof1_ss2_c_pins[] = {
2765 static const unsigned int msiof1_ss2_c_mux[] = {
2768 static const unsigned int msiof1_txd_c_pins[] = {
2772 static const unsigned int msiof1_txd_c_mux[] = {
2775 static const unsigned int msiof1_rxd_c_pins[] = {
2779 static const unsigned int msiof1_rxd_c_mux[] = {
2782 static const unsigned int msiof1_clk_d_pins[] = {
2786 static const unsigned int msiof1_clk_d_mux[] = {
2789 static const unsigned int msiof1_sync_d_pins[] = {
2793 static const unsigned int msiof1_sync_d_mux[] = {
2796 static const unsigned int msiof1_ss1_d_pins[] = {
2800 static const unsigned int msiof1_ss1_d_mux[] = {
2803 static const unsigned int msiof1_ss2_d_pins[] = {
2807 static const unsigned int msiof1_ss2_d_mux[] = {
2810 static const unsigned int msiof1_txd_d_pins[] = {
2814 static const unsigned int msiof1_txd_d_mux[] = {
2817 static const unsigned int msiof1_rxd_d_pins[] = {
2821 static const unsigned int msiof1_rxd_d_mux[] = {
2824 static const unsigned int msiof1_clk_e_pins[] = {
2828 static const unsigned int msiof1_clk_e_mux[] = {
2831 static const unsigned int msiof1_sync_e_pins[] = {
2835 static const unsigned int msiof1_sync_e_mux[] = {
2838 static const unsigned int msiof1_ss1_e_pins[] = {
2842 static const unsigned int msiof1_ss1_e_mux[] = {
2845 static const unsigned int msiof1_ss2_e_pins[] = {
2849 static const unsigned int msiof1_ss2_e_mux[] = {
2852 static const unsigned int msiof1_txd_e_pins[] = {
2856 static const unsigned int msiof1_txd_e_mux[] = {
2859 static const unsigned int msiof1_rxd_e_pins[] = {
2863 static const unsigned int msiof1_rxd_e_mux[] = {
2866 static const unsigned int msiof1_clk_f_pins[] = {
2870 static const unsigned int msiof1_clk_f_mux[] = {
2873 static const unsigned int msiof1_sync_f_pins[] = {
2877 static const unsigned int msiof1_sync_f_mux[] = {
2880 static const unsigned int msiof1_ss1_f_pins[] = {
2884 static const unsigned int msiof1_ss1_f_mux[] = {
2887 static const unsigned int msiof1_ss2_f_pins[] = {
2891 static const unsigned int msiof1_ss2_f_mux[] = {
2894 static const unsigned int msiof1_txd_f_pins[] = {
2898 static const unsigned int msiof1_txd_f_mux[] = {
2901 static const unsigned int msiof1_rxd_f_pins[] = {
2905 static const unsigned int msiof1_rxd_f_mux[] = {
2908 static const unsigned int msiof1_clk_g_pins[] = {
2912 static const unsigned int msiof1_clk_g_mux[] = {
2915 static const unsigned int msiof1_sync_g_pins[] = {
2919 static const unsigned int msiof1_sync_g_mux[] = {
2922 static const unsigned int msiof1_ss1_g_pins[] = {
2926 static const unsigned int msiof1_ss1_g_mux[] = {
2929 static const unsigned int msiof1_ss2_g_pins[] = {
2933 static const unsigned int msiof1_ss2_g_mux[] = {
2936 static const unsigned int msiof1_txd_g_pins[] = {
2940 static const unsigned int msiof1_txd_g_mux[] = {
2943 static const unsigned int msiof1_rxd_g_pins[] = {
2947 static const unsigned int msiof1_rxd_g_mux[] = {
2950 /* - MSIOF2 ----------------------------------------------------------------- */
2951 static const unsigned int msiof2_clk_a_pins[] = {
2955 static const unsigned int msiof2_clk_a_mux[] = {
2958 static const unsigned int msiof2_sync_a_pins[] = {
2962 static const unsigned int msiof2_sync_a_mux[] = {
2965 static const unsigned int msiof2_ss1_a_pins[] = {
2969 static const unsigned int msiof2_ss1_a_mux[] = {
2972 static const unsigned int msiof2_ss2_a_pins[] = {
2976 static const unsigned int msiof2_ss2_a_mux[] = {
2979 static const unsigned int msiof2_txd_a_pins[] = {
2983 static const unsigned int msiof2_txd_a_mux[] = {
2986 static const unsigned int msiof2_rxd_a_pins[] = {
2990 static const unsigned int msiof2_rxd_a_mux[] = {
2993 static const unsigned int msiof2_clk_b_pins[] = {
2997 static const unsigned int msiof2_clk_b_mux[] = {
3000 static const unsigned int msiof2_sync_b_pins[] = {
3004 static const unsigned int msiof2_sync_b_mux[] = {
3007 static const unsigned int msiof2_ss1_b_pins[] = {
3011 static const unsigned int msiof2_ss1_b_mux[] = {
3014 static const unsigned int msiof2_ss2_b_pins[] = {
3018 static const unsigned int msiof2_ss2_b_mux[] = {
3021 static const unsigned int msiof2_txd_b_pins[] = {
3025 static const unsigned int msiof2_txd_b_mux[] = {
3028 static const unsigned int msiof2_rxd_b_pins[] = {
3032 static const unsigned int msiof2_rxd_b_mux[] = {
3035 static const unsigned int msiof2_clk_c_pins[] = {
3039 static const unsigned int msiof2_clk_c_mux[] = {
3042 static const unsigned int msiof2_sync_c_pins[] = {
3046 static const unsigned int msiof2_sync_c_mux[] = {
3049 static const unsigned int msiof2_ss1_c_pins[] = {
3053 static const unsigned int msiof2_ss1_c_mux[] = {
3056 static const unsigned int msiof2_ss2_c_pins[] = {
3060 static const unsigned int msiof2_ss2_c_mux[] = {
3063 static const unsigned int msiof2_txd_c_pins[] = {
3067 static const unsigned int msiof2_txd_c_mux[] = {
3070 static const unsigned int msiof2_rxd_c_pins[] = {
3074 static const unsigned int msiof2_rxd_c_mux[] = {
3077 static const unsigned int msiof2_clk_d_pins[] = {
3081 static const unsigned int msiof2_clk_d_mux[] = {
3084 static const unsigned int msiof2_sync_d_pins[] = {
3088 static const unsigned int msiof2_sync_d_mux[] = {
3091 static const unsigned int msiof2_ss1_d_pins[] = {
3095 static const unsigned int msiof2_ss1_d_mux[] = {
3098 static const unsigned int msiof2_ss2_d_pins[] = {
3102 static const unsigned int msiof2_ss2_d_mux[] = {
3105 static const unsigned int msiof2_txd_d_pins[] = {
3109 static const unsigned int msiof2_txd_d_mux[] = {
3112 static const unsigned int msiof2_rxd_d_pins[] = {
3116 static const unsigned int msiof2_rxd_d_mux[] = {
3119 /* - MSIOF3 ----------------------------------------------------------------- */
3120 static const unsigned int msiof3_clk_a_pins[] = {
3124 static const unsigned int msiof3_clk_a_mux[] = {
3127 static const unsigned int msiof3_sync_a_pins[] = {
3131 static const unsigned int msiof3_sync_a_mux[] = {
3134 static const unsigned int msiof3_ss1_a_pins[] = {
3138 static const unsigned int msiof3_ss1_a_mux[] = {
3141 static const unsigned int msiof3_ss2_a_pins[] = {
3145 static const unsigned int msiof3_ss2_a_mux[] = {
3148 static const unsigned int msiof3_txd_a_pins[] = {
3152 static const unsigned int msiof3_txd_a_mux[] = {
3155 static const unsigned int msiof3_rxd_a_pins[] = {
3159 static const unsigned int msiof3_rxd_a_mux[] = {
3162 static const unsigned int msiof3_clk_b_pins[] = {
3166 static const unsigned int msiof3_clk_b_mux[] = {
3169 static const unsigned int msiof3_sync_b_pins[] = {
3173 static const unsigned int msiof3_sync_b_mux[] = {
3176 static const unsigned int msiof3_ss1_b_pins[] = {
3180 static const unsigned int msiof3_ss1_b_mux[] = {
3183 static const unsigned int msiof3_ss2_b_pins[] = {
3187 static const unsigned int msiof3_ss2_b_mux[] = {
3190 static const unsigned int msiof3_txd_b_pins[] = {
3194 static const unsigned int msiof3_txd_b_mux[] = {
3197 static const unsigned int msiof3_rxd_b_pins[] = {
3201 static const unsigned int msiof3_rxd_b_mux[] = {
3204 static const unsigned int msiof3_clk_c_pins[] = {
3208 static const unsigned int msiof3_clk_c_mux[] = {
3211 static const unsigned int msiof3_sync_c_pins[] = {
3215 static const unsigned int msiof3_sync_c_mux[] = {
3218 static const unsigned int msiof3_txd_c_pins[] = {
3222 static const unsigned int msiof3_txd_c_mux[] = {
3225 static const unsigned int msiof3_rxd_c_pins[] = {
3229 static const unsigned int msiof3_rxd_c_mux[] = {
3232 static const unsigned int msiof3_clk_d_pins[] = {
3236 static const unsigned int msiof3_clk_d_mux[] = {
3239 static const unsigned int msiof3_sync_d_pins[] = {
3243 static const unsigned int msiof3_sync_d_mux[] = {
3246 static const unsigned int msiof3_ss1_d_pins[] = {
3250 static const unsigned int msiof3_ss1_d_mux[] = {
3253 static const unsigned int msiof3_txd_d_pins[] = {
3257 static const unsigned int msiof3_txd_d_mux[] = {
3260 static const unsigned int msiof3_rxd_d_pins[] = {
3264 static const unsigned int msiof3_rxd_d_mux[] = {
3267 static const unsigned int msiof3_clk_e_pins[] = {
3271 static const unsigned int msiof3_clk_e_mux[] = {
3274 static const unsigned int msiof3_sync_e_pins[] = {
3278 static const unsigned int msiof3_sync_e_mux[] = {
3281 static const unsigned int msiof3_ss1_e_pins[] = {
3285 static const unsigned int msiof3_ss1_e_mux[] = {
3288 static const unsigned int msiof3_ss2_e_pins[] = {
3292 static const unsigned int msiof3_ss2_e_mux[] = {
3295 static const unsigned int msiof3_txd_e_pins[] = {
3299 static const unsigned int msiof3_txd_e_mux[] = {
3302 static const unsigned int msiof3_rxd_e_pins[] = {
3306 static const unsigned int msiof3_rxd_e_mux[] = {
3310 /* - PWM0 --------------------------------------------------------------------*/
3311 static const unsigned int pwm0_pins[] = {
3315 static const unsigned int pwm0_mux[] = {
3318 /* - PWM1 --------------------------------------------------------------------*/
3319 static const unsigned int pwm1_a_pins[] = {
3323 static const unsigned int pwm1_a_mux[] = {
3326 static const unsigned int pwm1_b_pins[] = {
3330 static const unsigned int pwm1_b_mux[] = {
3333 /* - PWM2 --------------------------------------------------------------------*/
3334 static const unsigned int pwm2_a_pins[] = {
3338 static const unsigned int pwm2_a_mux[] = {
3341 static const unsigned int pwm2_b_pins[] = {
3345 static const unsigned int pwm2_b_mux[] = {
3348 /* - PWM3 --------------------------------------------------------------------*/
3349 static const unsigned int pwm3_a_pins[] = {
3353 static const unsigned int pwm3_a_mux[] = {
3356 static const unsigned int pwm3_b_pins[] = {
3360 static const unsigned int pwm3_b_mux[] = {
3363 /* - PWM4 --------------------------------------------------------------------*/
3364 static const unsigned int pwm4_a_pins[] = {
3368 static const unsigned int pwm4_a_mux[] = {
3371 static const unsigned int pwm4_b_pins[] = {
3375 static const unsigned int pwm4_b_mux[] = {
3378 /* - PWM5 --------------------------------------------------------------------*/
3379 static const unsigned int pwm5_a_pins[] = {
3383 static const unsigned int pwm5_a_mux[] = {
3386 static const unsigned int pwm5_b_pins[] = {
3390 static const unsigned int pwm5_b_mux[] = {
3393 /* - PWM6 --------------------------------------------------------------------*/
3394 static const unsigned int pwm6_a_pins[] = {
3398 static const unsigned int pwm6_a_mux[] = {
3401 static const unsigned int pwm6_b_pins[] = {
3405 static const unsigned int pwm6_b_mux[] = {
3409 /* - QSPI0 ------------------------------------------------------------------ */
3410 static const unsigned int qspi0_ctrl_pins[] = {
3411 /* QSPI0_SPCLK, QSPI0_SSL */
3412 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3414 static const unsigned int qspi0_ctrl_mux[] = {
3415 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3417 static const unsigned int qspi0_data2_pins[] = {
3418 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3419 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3421 static const unsigned int qspi0_data2_mux[] = {
3422 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3424 static const unsigned int qspi0_data4_pins[] = {
3425 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3426 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3427 /* QSPI0_IO2, QSPI0_IO3 */
3428 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3430 static const unsigned int qspi0_data4_mux[] = {
3431 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3432 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3434 /* - QSPI1 ------------------------------------------------------------------ */
3435 static const unsigned int qspi1_ctrl_pins[] = {
3436 /* QSPI1_SPCLK, QSPI1_SSL */
3437 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3439 static const unsigned int qspi1_ctrl_mux[] = {
3440 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3442 static const unsigned int qspi1_data2_pins[] = {
3443 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3444 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3446 static const unsigned int qspi1_data2_mux[] = {
3447 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3449 static const unsigned int qspi1_data4_pins[] = {
3450 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3451 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3452 /* QSPI1_IO2, QSPI1_IO3 */
3453 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3455 static const unsigned int qspi1_data4_mux[] = {
3456 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3457 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3460 /* - SATA --------------------------------------------------------------------*/
3461 static const unsigned int sata0_devslp_a_pins[] = {
3466 static const unsigned int sata0_devslp_a_mux[] = {
3470 static const unsigned int sata0_devslp_b_pins[] = {
3475 static const unsigned int sata0_devslp_b_mux[] = {
3479 /* - SCIF0 ------------------------------------------------------------------ */
3480 static const unsigned int scif0_data_pins[] = {
3482 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3484 static const unsigned int scif0_data_mux[] = {
3487 static const unsigned int scif0_clk_pins[] = {
3491 static const unsigned int scif0_clk_mux[] = {
3494 static const unsigned int scif0_ctrl_pins[] = {
3496 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3498 static const unsigned int scif0_ctrl_mux[] = {
3499 RTS0_N_MARK, CTS0_N_MARK,
3501 /* - SCIF1 ------------------------------------------------------------------ */
3502 static const unsigned int scif1_data_a_pins[] = {
3504 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3506 static const unsigned int scif1_data_a_mux[] = {
3507 RX1_A_MARK, TX1_A_MARK,
3509 static const unsigned int scif1_clk_pins[] = {
3513 static const unsigned int scif1_clk_mux[] = {
3516 static const unsigned int scif1_ctrl_pins[] = {
3518 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3520 static const unsigned int scif1_ctrl_mux[] = {
3521 RTS1_N_MARK, CTS1_N_MARK,
3523 static const unsigned int scif1_data_b_pins[] = {
3525 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3527 static const unsigned int scif1_data_b_mux[] = {
3528 RX1_B_MARK, TX1_B_MARK,
3530 /* - SCIF2 ------------------------------------------------------------------ */
3531 static const unsigned int scif2_data_a_pins[] = {
3533 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3535 static const unsigned int scif2_data_a_mux[] = {
3536 RX2_A_MARK, TX2_A_MARK,
3538 static const unsigned int scif2_clk_pins[] = {
3542 static const unsigned int scif2_clk_mux[] = {
3545 static const unsigned int scif2_data_b_pins[] = {
3547 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3549 static const unsigned int scif2_data_b_mux[] = {
3550 RX2_B_MARK, TX2_B_MARK,
3552 /* - SCIF3 ------------------------------------------------------------------ */
3553 static const unsigned int scif3_data_a_pins[] = {
3555 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3557 static const unsigned int scif3_data_a_mux[] = {
3558 RX3_A_MARK, TX3_A_MARK,
3560 static const unsigned int scif3_clk_pins[] = {
3564 static const unsigned int scif3_clk_mux[] = {
3567 static const unsigned int scif3_ctrl_pins[] = {
3569 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3571 static const unsigned int scif3_ctrl_mux[] = {
3572 RTS3_N_MARK, CTS3_N_MARK,
3574 static const unsigned int scif3_data_b_pins[] = {
3576 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3578 static const unsigned int scif3_data_b_mux[] = {
3579 RX3_B_MARK, TX3_B_MARK,
3581 /* - SCIF4 ------------------------------------------------------------------ */
3582 static const unsigned int scif4_data_a_pins[] = {
3584 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3586 static const unsigned int scif4_data_a_mux[] = {
3587 RX4_A_MARK, TX4_A_MARK,
3589 static const unsigned int scif4_clk_a_pins[] = {
3593 static const unsigned int scif4_clk_a_mux[] = {
3596 static const unsigned int scif4_ctrl_a_pins[] = {
3598 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3600 static const unsigned int scif4_ctrl_a_mux[] = {
3601 RTS4_N_A_MARK, CTS4_N_A_MARK,
3603 static const unsigned int scif4_data_b_pins[] = {
3605 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3607 static const unsigned int scif4_data_b_mux[] = {
3608 RX4_B_MARK, TX4_B_MARK,
3610 static const unsigned int scif4_clk_b_pins[] = {
3614 static const unsigned int scif4_clk_b_mux[] = {
3617 static const unsigned int scif4_ctrl_b_pins[] = {
3619 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3621 static const unsigned int scif4_ctrl_b_mux[] = {
3622 RTS4_N_B_MARK, CTS4_N_B_MARK,
3624 static const unsigned int scif4_data_c_pins[] = {
3626 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3628 static const unsigned int scif4_data_c_mux[] = {
3629 RX4_C_MARK, TX4_C_MARK,
3631 static const unsigned int scif4_clk_c_pins[] = {
3635 static const unsigned int scif4_clk_c_mux[] = {
3638 static const unsigned int scif4_ctrl_c_pins[] = {
3640 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3642 static const unsigned int scif4_ctrl_c_mux[] = {
3643 RTS4_N_C_MARK, CTS4_N_C_MARK,
3645 /* - SCIF5 ------------------------------------------------------------------ */
3646 static const unsigned int scif5_data_a_pins[] = {
3648 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3650 static const unsigned int scif5_data_a_mux[] = {
3651 RX5_A_MARK, TX5_A_MARK,
3653 static const unsigned int scif5_clk_a_pins[] = {
3657 static const unsigned int scif5_clk_a_mux[] = {
3660 static const unsigned int scif5_data_b_pins[] = {
3662 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3664 static const unsigned int scif5_data_b_mux[] = {
3665 RX5_B_MARK, TX5_B_MARK,
3667 static const unsigned int scif5_clk_b_pins[] = {
3671 static const unsigned int scif5_clk_b_mux[] = {
3674 /* - SCIF Clock ------------------------------------------------------------- */
3675 static const unsigned int scif_clk_a_pins[] = {
3679 static const unsigned int scif_clk_a_mux[] = {
3682 static const unsigned int scif_clk_b_pins[] = {
3686 static const unsigned int scif_clk_b_mux[] = {
3690 /* - SDHI0 ------------------------------------------------------------------ */
3691 static const unsigned int sdhi0_data1_pins[] = {
3696 static const unsigned int sdhi0_data1_mux[] = {
3700 static const unsigned int sdhi0_data4_pins[] = {
3702 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3703 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3706 static const unsigned int sdhi0_data4_mux[] = {
3707 SD0_DAT0_MARK, SD0_DAT1_MARK,
3708 SD0_DAT2_MARK, SD0_DAT3_MARK,
3711 static const unsigned int sdhi0_ctrl_pins[] = {
3713 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3716 static const unsigned int sdhi0_ctrl_mux[] = {
3717 SD0_CLK_MARK, SD0_CMD_MARK,
3720 static const unsigned int sdhi0_cd_pins[] = {
3725 static const unsigned int sdhi0_cd_mux[] = {
3729 static const unsigned int sdhi0_wp_pins[] = {
3734 static const unsigned int sdhi0_wp_mux[] = {
3738 /* - SDHI1 ------------------------------------------------------------------ */
3739 static const unsigned int sdhi1_data1_pins[] = {
3744 static const unsigned int sdhi1_data1_mux[] = {
3748 static const unsigned int sdhi1_data4_pins[] = {
3750 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3751 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3754 static const unsigned int sdhi1_data4_mux[] = {
3755 SD1_DAT0_MARK, SD1_DAT1_MARK,
3756 SD1_DAT2_MARK, SD1_DAT3_MARK,
3759 static const unsigned int sdhi1_ctrl_pins[] = {
3761 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3764 static const unsigned int sdhi1_ctrl_mux[] = {
3765 SD1_CLK_MARK, SD1_CMD_MARK,
3768 static const unsigned int sdhi1_cd_pins[] = {
3773 static const unsigned int sdhi1_cd_mux[] = {
3777 static const unsigned int sdhi1_wp_pins[] = {
3782 static const unsigned int sdhi1_wp_mux[] = {
3786 /* - SDHI2 ------------------------------------------------------------------ */
3787 static const unsigned int sdhi2_data1_pins[] = {
3792 static const unsigned int sdhi2_data1_mux[] = {
3796 static const unsigned int sdhi2_data4_pins[] = {
3798 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3799 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3802 static const unsigned int sdhi2_data4_mux[] = {
3803 SD2_DAT0_MARK, SD2_DAT1_MARK,
3804 SD2_DAT2_MARK, SD2_DAT3_MARK,
3807 static const unsigned int sdhi2_data8_pins[] = {
3809 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3810 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3811 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3812 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3815 static const unsigned int sdhi2_data8_mux[] = {
3816 SD2_DAT0_MARK, SD2_DAT1_MARK,
3817 SD2_DAT2_MARK, SD2_DAT3_MARK,
3818 SD2_DAT4_MARK, SD2_DAT5_MARK,
3819 SD2_DAT6_MARK, SD2_DAT7_MARK,
3822 static const unsigned int sdhi2_ctrl_pins[] = {
3824 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3827 static const unsigned int sdhi2_ctrl_mux[] = {
3828 SD2_CLK_MARK, SD2_CMD_MARK,
3831 static const unsigned int sdhi2_cd_a_pins[] = {
3836 static const unsigned int sdhi2_cd_a_mux[] = {
3840 static const unsigned int sdhi2_cd_b_pins[] = {
3845 static const unsigned int sdhi2_cd_b_mux[] = {
3849 static const unsigned int sdhi2_wp_a_pins[] = {
3854 static const unsigned int sdhi2_wp_a_mux[] = {
3858 static const unsigned int sdhi2_wp_b_pins[] = {
3863 static const unsigned int sdhi2_wp_b_mux[] = {
3867 static const unsigned int sdhi2_ds_pins[] = {
3872 static const unsigned int sdhi2_ds_mux[] = {
3876 /* - SDHI3 ------------------------------------------------------------------ */
3877 static const unsigned int sdhi3_data1_pins[] = {
3882 static const unsigned int sdhi3_data1_mux[] = {
3886 static const unsigned int sdhi3_data4_pins[] = {
3888 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3889 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3892 static const unsigned int sdhi3_data4_mux[] = {
3893 SD3_DAT0_MARK, SD3_DAT1_MARK,
3894 SD3_DAT2_MARK, SD3_DAT3_MARK,
3897 static const unsigned int sdhi3_data8_pins[] = {
3899 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3900 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3901 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3902 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3905 static const unsigned int sdhi3_data8_mux[] = {
3906 SD3_DAT0_MARK, SD3_DAT1_MARK,
3907 SD3_DAT2_MARK, SD3_DAT3_MARK,
3908 SD3_DAT4_MARK, SD3_DAT5_MARK,
3909 SD3_DAT6_MARK, SD3_DAT7_MARK,
3912 static const unsigned int sdhi3_ctrl_pins[] = {
3914 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3917 static const unsigned int sdhi3_ctrl_mux[] = {
3918 SD3_CLK_MARK, SD3_CMD_MARK,
3921 static const unsigned int sdhi3_cd_pins[] = {
3926 static const unsigned int sdhi3_cd_mux[] = {
3930 static const unsigned int sdhi3_wp_pins[] = {
3935 static const unsigned int sdhi3_wp_mux[] = {
3939 static const unsigned int sdhi3_ds_pins[] = {
3944 static const unsigned int sdhi3_ds_mux[] = {
3948 /* - SSI -------------------------------------------------------------------- */
3949 static const unsigned int ssi0_data_pins[] = {
3953 static const unsigned int ssi0_data_mux[] = {
3956 static const unsigned int ssi01239_ctrl_pins[] = {
3958 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3960 static const unsigned int ssi01239_ctrl_mux[] = {
3961 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3963 static const unsigned int ssi1_data_a_pins[] = {
3967 static const unsigned int ssi1_data_a_mux[] = {
3970 static const unsigned int ssi1_data_b_pins[] = {
3974 static const unsigned int ssi1_data_b_mux[] = {
3977 static const unsigned int ssi1_ctrl_a_pins[] = {
3979 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3981 static const unsigned int ssi1_ctrl_a_mux[] = {
3982 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3984 static const unsigned int ssi1_ctrl_b_pins[] = {
3986 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3988 static const unsigned int ssi1_ctrl_b_mux[] = {
3989 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3991 static const unsigned int ssi2_data_a_pins[] = {
3995 static const unsigned int ssi2_data_a_mux[] = {
3998 static const unsigned int ssi2_data_b_pins[] = {
4002 static const unsigned int ssi2_data_b_mux[] = {
4005 static const unsigned int ssi2_ctrl_a_pins[] = {
4007 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
4009 static const unsigned int ssi2_ctrl_a_mux[] = {
4010 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
4012 static const unsigned int ssi2_ctrl_b_pins[] = {
4014 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4016 static const unsigned int ssi2_ctrl_b_mux[] = {
4017 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
4019 static const unsigned int ssi3_data_pins[] = {
4023 static const unsigned int ssi3_data_mux[] = {
4026 static const unsigned int ssi349_ctrl_pins[] = {
4028 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
4030 static const unsigned int ssi349_ctrl_mux[] = {
4031 SSI_SCK349_MARK, SSI_WS349_MARK,
4033 static const unsigned int ssi4_data_pins[] = {
4037 static const unsigned int ssi4_data_mux[] = {
4040 static const unsigned int ssi4_ctrl_pins[] = {
4042 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
4044 static const unsigned int ssi4_ctrl_mux[] = {
4045 SSI_SCK4_MARK, SSI_WS4_MARK,
4047 static const unsigned int ssi5_data_pins[] = {
4051 static const unsigned int ssi5_data_mux[] = {
4054 static const unsigned int ssi5_ctrl_pins[] = {
4056 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
4058 static const unsigned int ssi5_ctrl_mux[] = {
4059 SSI_SCK5_MARK, SSI_WS5_MARK,
4061 static const unsigned int ssi6_data_pins[] = {
4065 static const unsigned int ssi6_data_mux[] = {
4068 static const unsigned int ssi6_ctrl_pins[] = {
4070 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
4072 static const unsigned int ssi6_ctrl_mux[] = {
4073 SSI_SCK6_MARK, SSI_WS6_MARK,
4075 static const unsigned int ssi7_data_pins[] = {
4079 static const unsigned int ssi7_data_mux[] = {
4082 static const unsigned int ssi78_ctrl_pins[] = {
4084 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
4086 static const unsigned int ssi78_ctrl_mux[] = {
4087 SSI_SCK78_MARK, SSI_WS78_MARK,
4089 static const unsigned int ssi8_data_pins[] = {
4093 static const unsigned int ssi8_data_mux[] = {
4096 static const unsigned int ssi9_data_a_pins[] = {
4100 static const unsigned int ssi9_data_a_mux[] = {
4103 static const unsigned int ssi9_data_b_pins[] = {
4107 static const unsigned int ssi9_data_b_mux[] = {
4110 static const unsigned int ssi9_ctrl_a_pins[] = {
4112 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
4114 static const unsigned int ssi9_ctrl_a_mux[] = {
4115 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
4117 static const unsigned int ssi9_ctrl_b_pins[] = {
4119 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
4121 static const unsigned int ssi9_ctrl_b_mux[] = {
4122 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4125 /* - TMU -------------------------------------------------------------------- */
4126 static const unsigned int tmu_tclk1_a_pins[] = {
4131 static const unsigned int tmu_tclk1_a_mux[] = {
4135 static const unsigned int tmu_tclk1_b_pins[] = {
4140 static const unsigned int tmu_tclk1_b_mux[] = {
4144 static const unsigned int tmu_tclk2_a_pins[] = {
4149 static const unsigned int tmu_tclk2_a_mux[] = {
4153 static const unsigned int tmu_tclk2_b_pins[] = {
4158 static const unsigned int tmu_tclk2_b_mux[] = {
4162 /* - TPU ------------------------------------------------------------------- */
4163 static const unsigned int tpu_to0_pins[] = {
4167 static const unsigned int tpu_to0_mux[] = {
4170 static const unsigned int tpu_to1_pins[] = {
4174 static const unsigned int tpu_to1_mux[] = {
4177 static const unsigned int tpu_to2_pins[] = {
4181 static const unsigned int tpu_to2_mux[] = {
4184 static const unsigned int tpu_to3_pins[] = {
4188 static const unsigned int tpu_to3_mux[] = {
4192 /* - USB0 ------------------------------------------------------------------- */
4193 static const unsigned int usb0_pins[] = {
4195 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4198 static const unsigned int usb0_mux[] = {
4199 USB0_PWEN_MARK, USB0_OVC_MARK,
4202 /* - USB1 ------------------------------------------------------------------- */
4203 static const unsigned int usb1_pins[] = {
4205 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4208 static const unsigned int usb1_mux[] = {
4209 USB1_PWEN_MARK, USB1_OVC_MARK,
4212 /* - USB30 ------------------------------------------------------------------ */
4213 static const unsigned int usb30_pins[] = {
4215 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4218 static const unsigned int usb30_mux[] = {
4219 USB30_PWEN_MARK, USB30_OVC_MARK,
4222 /* - VIN4 ------------------------------------------------------------------- */
4223 static const unsigned int vin4_data18_a_pins[] = {
4224 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4225 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4226 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4227 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4228 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4229 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4230 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4231 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4232 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4235 static const unsigned int vin4_data18_a_mux[] = {
4236 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4237 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4238 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4239 VI4_DATA10_MARK, VI4_DATA11_MARK,
4240 VI4_DATA12_MARK, VI4_DATA13_MARK,
4241 VI4_DATA14_MARK, VI4_DATA15_MARK,
4242 VI4_DATA18_MARK, VI4_DATA19_MARK,
4243 VI4_DATA20_MARK, VI4_DATA21_MARK,
4244 VI4_DATA22_MARK, VI4_DATA23_MARK,
4247 static const union vin_data vin4_data_a_pins = {
4249 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4250 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4251 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4252 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4253 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4254 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4255 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4256 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4257 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4258 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4259 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4260 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4264 static const union vin_data vin4_data_a_mux = {
4266 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4267 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4268 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4269 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4270 VI4_DATA8_MARK, VI4_DATA9_MARK,
4271 VI4_DATA10_MARK, VI4_DATA11_MARK,
4272 VI4_DATA12_MARK, VI4_DATA13_MARK,
4273 VI4_DATA14_MARK, VI4_DATA15_MARK,
4274 VI4_DATA16_MARK, VI4_DATA17_MARK,
4275 VI4_DATA18_MARK, VI4_DATA19_MARK,
4276 VI4_DATA20_MARK, VI4_DATA21_MARK,
4277 VI4_DATA22_MARK, VI4_DATA23_MARK,
4281 static const unsigned int vin4_data18_b_pins[] = {
4282 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4283 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4284 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4285 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4286 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4287 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4288 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4289 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4290 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4293 static const unsigned int vin4_data18_b_mux[] = {
4294 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4295 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4296 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4297 VI4_DATA10_MARK, VI4_DATA11_MARK,
4298 VI4_DATA12_MARK, VI4_DATA13_MARK,
4299 VI4_DATA14_MARK, VI4_DATA15_MARK,
4300 VI4_DATA18_MARK, VI4_DATA19_MARK,
4301 VI4_DATA20_MARK, VI4_DATA21_MARK,
4302 VI4_DATA22_MARK, VI4_DATA23_MARK,
4305 static const union vin_data vin4_data_b_pins = {
4307 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4308 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4309 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4310 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4311 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4312 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4313 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4314 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4315 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4316 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4317 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4318 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4322 static const union vin_data vin4_data_b_mux = {
4324 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4325 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4326 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4327 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4328 VI4_DATA8_MARK, VI4_DATA9_MARK,
4329 VI4_DATA10_MARK, VI4_DATA11_MARK,
4330 VI4_DATA12_MARK, VI4_DATA13_MARK,
4331 VI4_DATA14_MARK, VI4_DATA15_MARK,
4332 VI4_DATA16_MARK, VI4_DATA17_MARK,
4333 VI4_DATA18_MARK, VI4_DATA19_MARK,
4334 VI4_DATA20_MARK, VI4_DATA21_MARK,
4335 VI4_DATA22_MARK, VI4_DATA23_MARK,
4339 static const unsigned int vin4_g8_pins[] = {
4340 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4341 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4342 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4343 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4346 static const unsigned int vin4_g8_mux[] = {
4347 VI4_DATA8_MARK, VI4_DATA9_MARK,
4348 VI4_DATA10_MARK, VI4_DATA11_MARK,
4349 VI4_DATA12_MARK, VI4_DATA13_MARK,
4350 VI4_DATA14_MARK, VI4_DATA15_MARK,
4353 static const unsigned int vin4_sync_pins[] = {
4354 /* VSYNC_N, HSYNC_N */
4355 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
4358 static const unsigned int vin4_sync_mux[] = {
4359 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4362 static const unsigned int vin4_field_pins[] = {
4366 static const unsigned int vin4_field_mux[] = {
4370 static const unsigned int vin4_clkenb_pins[] = {
4374 static const unsigned int vin4_clkenb_mux[] = {
4378 static const unsigned int vin4_clk_pins[] = {
4382 static const unsigned int vin4_clk_mux[] = {
4386 /* - VIN5 ------------------------------------------------------------------- */
4387 static const union vin_data16 vin5_data_pins = {
4389 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4390 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4391 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4392 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4393 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4394 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4395 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4396 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4400 static const union vin_data16 vin5_data_mux = {
4402 VI5_DATA0_MARK, VI5_DATA1_MARK,
4403 VI5_DATA2_MARK, VI5_DATA3_MARK,
4404 VI5_DATA4_MARK, VI5_DATA5_MARK,
4405 VI5_DATA6_MARK, VI5_DATA7_MARK,
4406 VI5_DATA8_MARK, VI5_DATA9_MARK,
4407 VI5_DATA10_MARK, VI5_DATA11_MARK,
4408 VI5_DATA12_MARK, VI5_DATA13_MARK,
4409 VI5_DATA14_MARK, VI5_DATA15_MARK,
4413 static const unsigned int vin5_high8_pins[] = {
4414 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4415 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4416 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4417 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4420 static const unsigned int vin5_high8_mux[] = {
4421 VI5_DATA8_MARK, VI5_DATA9_MARK,
4422 VI5_DATA10_MARK, VI5_DATA11_MARK,
4423 VI5_DATA12_MARK, VI5_DATA13_MARK,
4424 VI5_DATA14_MARK, VI5_DATA15_MARK,
4427 static const unsigned int vin5_sync_pins[] = {
4428 /* VSYNC_N, HSYNC_N */
4429 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
4432 static const unsigned int vin5_sync_mux[] = {
4433 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4436 static const unsigned int vin5_field_pins[] = {
4440 static const unsigned int vin5_field_mux[] = {
4444 static const unsigned int vin5_clkenb_pins[] = {
4448 static const unsigned int vin5_clkenb_mux[] = {
4452 static const unsigned int vin5_clk_pins[] = {
4456 static const unsigned int vin5_clk_mux[] = {
4460 static const struct {
4461 struct sh_pfc_pin_group common[326];
4462 #ifdef CONFIG_PINCTRL_PFC_R8A77965
4463 struct sh_pfc_pin_group automotive[30];
4467 SH_PFC_PIN_GROUP(audio_clk_a_a),
4468 SH_PFC_PIN_GROUP(audio_clk_a_b),
4469 SH_PFC_PIN_GROUP(audio_clk_a_c),
4470 SH_PFC_PIN_GROUP(audio_clk_b_a),
4471 SH_PFC_PIN_GROUP(audio_clk_b_b),
4472 SH_PFC_PIN_GROUP(audio_clk_c_a),
4473 SH_PFC_PIN_GROUP(audio_clk_c_b),
4474 SH_PFC_PIN_GROUP(audio_clkout_a),
4475 SH_PFC_PIN_GROUP(audio_clkout_b),
4476 SH_PFC_PIN_GROUP(audio_clkout_c),
4477 SH_PFC_PIN_GROUP(audio_clkout_d),
4478 SH_PFC_PIN_GROUP(audio_clkout1_a),
4479 SH_PFC_PIN_GROUP(audio_clkout1_b),
4480 SH_PFC_PIN_GROUP(audio_clkout2_a),
4481 SH_PFC_PIN_GROUP(audio_clkout2_b),
4482 SH_PFC_PIN_GROUP(audio_clkout3_a),
4483 SH_PFC_PIN_GROUP(audio_clkout3_b),
4484 SH_PFC_PIN_GROUP(avb_link),
4485 SH_PFC_PIN_GROUP(avb_magic),
4486 SH_PFC_PIN_GROUP(avb_phy_int),
4487 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4488 SH_PFC_PIN_GROUP(avb_mdio),
4489 SH_PFC_PIN_GROUP(avb_mii),
4490 SH_PFC_PIN_GROUP(avb_avtp_pps),
4491 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4492 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4493 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4494 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4495 SH_PFC_PIN_GROUP(can0_data_a),
4496 SH_PFC_PIN_GROUP(can0_data_b),
4497 SH_PFC_PIN_GROUP(can1_data),
4498 SH_PFC_PIN_GROUP(can_clk),
4499 SH_PFC_PIN_GROUP(canfd0_data_a),
4500 SH_PFC_PIN_GROUP(canfd0_data_b),
4501 SH_PFC_PIN_GROUP(canfd1_data),
4502 SH_PFC_PIN_GROUP(du_rgb666),
4503 SH_PFC_PIN_GROUP(du_rgb888),
4504 SH_PFC_PIN_GROUP(du_clk_out_0),
4505 SH_PFC_PIN_GROUP(du_clk_out_1),
4506 SH_PFC_PIN_GROUP(du_sync),
4507 SH_PFC_PIN_GROUP(du_oddf),
4508 SH_PFC_PIN_GROUP(du_cde),
4509 SH_PFC_PIN_GROUP(du_disp),
4510 SH_PFC_PIN_GROUP(hscif0_data),
4511 SH_PFC_PIN_GROUP(hscif0_clk),
4512 SH_PFC_PIN_GROUP(hscif0_ctrl),
4513 SH_PFC_PIN_GROUP(hscif1_data_a),
4514 SH_PFC_PIN_GROUP(hscif1_clk_a),
4515 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4516 SH_PFC_PIN_GROUP(hscif1_data_b),
4517 SH_PFC_PIN_GROUP(hscif1_clk_b),
4518 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4519 SH_PFC_PIN_GROUP(hscif2_data_a),
4520 SH_PFC_PIN_GROUP(hscif2_clk_a),
4521 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4522 SH_PFC_PIN_GROUP(hscif2_data_b),
4523 SH_PFC_PIN_GROUP(hscif2_clk_b),
4524 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4525 SH_PFC_PIN_GROUP(hscif2_data_c),
4526 SH_PFC_PIN_GROUP(hscif2_clk_c),
4527 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4528 SH_PFC_PIN_GROUP(hscif3_data_a),
4529 SH_PFC_PIN_GROUP(hscif3_clk),
4530 SH_PFC_PIN_GROUP(hscif3_ctrl),
4531 SH_PFC_PIN_GROUP(hscif3_data_b),
4532 SH_PFC_PIN_GROUP(hscif3_data_c),
4533 SH_PFC_PIN_GROUP(hscif3_data_d),
4534 SH_PFC_PIN_GROUP(hscif4_data_a),
4535 SH_PFC_PIN_GROUP(hscif4_clk),
4536 SH_PFC_PIN_GROUP(hscif4_ctrl),
4537 SH_PFC_PIN_GROUP(hscif4_data_b),
4538 SH_PFC_PIN_GROUP(i2c0),
4539 SH_PFC_PIN_GROUP(i2c1_a),
4540 SH_PFC_PIN_GROUP(i2c1_b),
4541 SH_PFC_PIN_GROUP(i2c2_a),
4542 SH_PFC_PIN_GROUP(i2c2_b),
4543 SH_PFC_PIN_GROUP(i2c3),
4544 SH_PFC_PIN_GROUP(i2c5),
4545 SH_PFC_PIN_GROUP(i2c6_a),
4546 SH_PFC_PIN_GROUP(i2c6_b),
4547 SH_PFC_PIN_GROUP(i2c6_c),
4548 SH_PFC_PIN_GROUP(intc_ex_irq0),
4549 SH_PFC_PIN_GROUP(intc_ex_irq1),
4550 SH_PFC_PIN_GROUP(intc_ex_irq2),
4551 SH_PFC_PIN_GROUP(intc_ex_irq3),
4552 SH_PFC_PIN_GROUP(intc_ex_irq4),
4553 SH_PFC_PIN_GROUP(intc_ex_irq5),
4554 SH_PFC_PIN_GROUP(msiof0_clk),
4555 SH_PFC_PIN_GROUP(msiof0_sync),
4556 SH_PFC_PIN_GROUP(msiof0_ss1),
4557 SH_PFC_PIN_GROUP(msiof0_ss2),
4558 SH_PFC_PIN_GROUP(msiof0_txd),
4559 SH_PFC_PIN_GROUP(msiof0_rxd),
4560 SH_PFC_PIN_GROUP(msiof1_clk_a),
4561 SH_PFC_PIN_GROUP(msiof1_sync_a),
4562 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4563 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4564 SH_PFC_PIN_GROUP(msiof1_txd_a),
4565 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4566 SH_PFC_PIN_GROUP(msiof1_clk_b),
4567 SH_PFC_PIN_GROUP(msiof1_sync_b),
4568 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4569 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4570 SH_PFC_PIN_GROUP(msiof1_txd_b),
4571 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4572 SH_PFC_PIN_GROUP(msiof1_clk_c),
4573 SH_PFC_PIN_GROUP(msiof1_sync_c),
4574 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4575 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4576 SH_PFC_PIN_GROUP(msiof1_txd_c),
4577 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4578 SH_PFC_PIN_GROUP(msiof1_clk_d),
4579 SH_PFC_PIN_GROUP(msiof1_sync_d),
4580 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4581 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4582 SH_PFC_PIN_GROUP(msiof1_txd_d),
4583 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4584 SH_PFC_PIN_GROUP(msiof1_clk_e),
4585 SH_PFC_PIN_GROUP(msiof1_sync_e),
4586 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4587 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4588 SH_PFC_PIN_GROUP(msiof1_txd_e),
4589 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4590 SH_PFC_PIN_GROUP(msiof1_clk_f),
4591 SH_PFC_PIN_GROUP(msiof1_sync_f),
4592 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4593 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4594 SH_PFC_PIN_GROUP(msiof1_txd_f),
4595 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4596 SH_PFC_PIN_GROUP(msiof1_clk_g),
4597 SH_PFC_PIN_GROUP(msiof1_sync_g),
4598 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4599 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4600 SH_PFC_PIN_GROUP(msiof1_txd_g),
4601 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4602 SH_PFC_PIN_GROUP(msiof2_clk_a),
4603 SH_PFC_PIN_GROUP(msiof2_sync_a),
4604 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4605 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4606 SH_PFC_PIN_GROUP(msiof2_txd_a),
4607 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4608 SH_PFC_PIN_GROUP(msiof2_clk_b),
4609 SH_PFC_PIN_GROUP(msiof2_sync_b),
4610 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4611 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4612 SH_PFC_PIN_GROUP(msiof2_txd_b),
4613 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4614 SH_PFC_PIN_GROUP(msiof2_clk_c),
4615 SH_PFC_PIN_GROUP(msiof2_sync_c),
4616 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4617 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4618 SH_PFC_PIN_GROUP(msiof2_txd_c),
4619 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4620 SH_PFC_PIN_GROUP(msiof2_clk_d),
4621 SH_PFC_PIN_GROUP(msiof2_sync_d),
4622 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4623 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4624 SH_PFC_PIN_GROUP(msiof2_txd_d),
4625 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4626 SH_PFC_PIN_GROUP(msiof3_clk_a),
4627 SH_PFC_PIN_GROUP(msiof3_sync_a),
4628 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4629 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4630 SH_PFC_PIN_GROUP(msiof3_txd_a),
4631 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4632 SH_PFC_PIN_GROUP(msiof3_clk_b),
4633 SH_PFC_PIN_GROUP(msiof3_sync_b),
4634 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4635 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4636 SH_PFC_PIN_GROUP(msiof3_txd_b),
4637 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4638 SH_PFC_PIN_GROUP(msiof3_clk_c),
4639 SH_PFC_PIN_GROUP(msiof3_sync_c),
4640 SH_PFC_PIN_GROUP(msiof3_txd_c),
4641 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4642 SH_PFC_PIN_GROUP(msiof3_clk_d),
4643 SH_PFC_PIN_GROUP(msiof3_sync_d),
4644 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4645 SH_PFC_PIN_GROUP(msiof3_txd_d),
4646 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4647 SH_PFC_PIN_GROUP(msiof3_clk_e),
4648 SH_PFC_PIN_GROUP(msiof3_sync_e),
4649 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4650 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4651 SH_PFC_PIN_GROUP(msiof3_txd_e),
4652 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4653 SH_PFC_PIN_GROUP(pwm0),
4654 SH_PFC_PIN_GROUP(pwm1_a),
4655 SH_PFC_PIN_GROUP(pwm1_b),
4656 SH_PFC_PIN_GROUP(pwm2_a),
4657 SH_PFC_PIN_GROUP(pwm2_b),
4658 SH_PFC_PIN_GROUP(pwm3_a),
4659 SH_PFC_PIN_GROUP(pwm3_b),
4660 SH_PFC_PIN_GROUP(pwm4_a),
4661 SH_PFC_PIN_GROUP(pwm4_b),
4662 SH_PFC_PIN_GROUP(pwm5_a),
4663 SH_PFC_PIN_GROUP(pwm5_b),
4664 SH_PFC_PIN_GROUP(pwm6_a),
4665 SH_PFC_PIN_GROUP(pwm6_b),
4666 SH_PFC_PIN_GROUP(qspi0_ctrl),
4667 SH_PFC_PIN_GROUP(qspi0_data2),
4668 SH_PFC_PIN_GROUP(qspi0_data4),
4669 SH_PFC_PIN_GROUP(qspi1_ctrl),
4670 SH_PFC_PIN_GROUP(qspi1_data2),
4671 SH_PFC_PIN_GROUP(qspi1_data4),
4672 SH_PFC_PIN_GROUP(sata0_devslp_a),
4673 SH_PFC_PIN_GROUP(sata0_devslp_b),
4674 SH_PFC_PIN_GROUP(scif0_data),
4675 SH_PFC_PIN_GROUP(scif0_clk),
4676 SH_PFC_PIN_GROUP(scif0_ctrl),
4677 SH_PFC_PIN_GROUP(scif1_data_a),
4678 SH_PFC_PIN_GROUP(scif1_clk),
4679 SH_PFC_PIN_GROUP(scif1_ctrl),
4680 SH_PFC_PIN_GROUP(scif1_data_b),
4681 SH_PFC_PIN_GROUP(scif2_data_a),
4682 SH_PFC_PIN_GROUP(scif2_clk),
4683 SH_PFC_PIN_GROUP(scif2_data_b),
4684 SH_PFC_PIN_GROUP(scif3_data_a),
4685 SH_PFC_PIN_GROUP(scif3_clk),
4686 SH_PFC_PIN_GROUP(scif3_ctrl),
4687 SH_PFC_PIN_GROUP(scif3_data_b),
4688 SH_PFC_PIN_GROUP(scif4_data_a),
4689 SH_PFC_PIN_GROUP(scif4_clk_a),
4690 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4691 SH_PFC_PIN_GROUP(scif4_data_b),
4692 SH_PFC_PIN_GROUP(scif4_clk_b),
4693 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4694 SH_PFC_PIN_GROUP(scif4_data_c),
4695 SH_PFC_PIN_GROUP(scif4_clk_c),
4696 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4697 SH_PFC_PIN_GROUP(scif5_data_a),
4698 SH_PFC_PIN_GROUP(scif5_clk_a),
4699 SH_PFC_PIN_GROUP(scif5_data_b),
4700 SH_PFC_PIN_GROUP(scif5_clk_b),
4701 SH_PFC_PIN_GROUP(scif_clk_a),
4702 SH_PFC_PIN_GROUP(scif_clk_b),
4703 SH_PFC_PIN_GROUP(sdhi0_data1),
4704 SH_PFC_PIN_GROUP(sdhi0_data4),
4705 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4706 SH_PFC_PIN_GROUP(sdhi0_cd),
4707 SH_PFC_PIN_GROUP(sdhi0_wp),
4708 SH_PFC_PIN_GROUP(sdhi1_data1),
4709 SH_PFC_PIN_GROUP(sdhi1_data4),
4710 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4711 SH_PFC_PIN_GROUP(sdhi1_cd),
4712 SH_PFC_PIN_GROUP(sdhi1_wp),
4713 SH_PFC_PIN_GROUP(sdhi2_data1),
4714 SH_PFC_PIN_GROUP(sdhi2_data4),
4715 SH_PFC_PIN_GROUP(sdhi2_data8),
4716 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4717 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4718 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4719 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4720 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4721 SH_PFC_PIN_GROUP(sdhi2_ds),
4722 SH_PFC_PIN_GROUP(sdhi3_data1),
4723 SH_PFC_PIN_GROUP(sdhi3_data4),
4724 SH_PFC_PIN_GROUP(sdhi3_data8),
4725 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4726 SH_PFC_PIN_GROUP(sdhi3_cd),
4727 SH_PFC_PIN_GROUP(sdhi3_wp),
4728 SH_PFC_PIN_GROUP(sdhi3_ds),
4729 SH_PFC_PIN_GROUP(ssi0_data),
4730 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4731 SH_PFC_PIN_GROUP(ssi1_data_a),
4732 SH_PFC_PIN_GROUP(ssi1_data_b),
4733 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4734 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4735 SH_PFC_PIN_GROUP(ssi2_data_a),
4736 SH_PFC_PIN_GROUP(ssi2_data_b),
4737 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4738 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4739 SH_PFC_PIN_GROUP(ssi3_data),
4740 SH_PFC_PIN_GROUP(ssi349_ctrl),
4741 SH_PFC_PIN_GROUP(ssi4_data),
4742 SH_PFC_PIN_GROUP(ssi4_ctrl),
4743 SH_PFC_PIN_GROUP(ssi5_data),
4744 SH_PFC_PIN_GROUP(ssi5_ctrl),
4745 SH_PFC_PIN_GROUP(ssi6_data),
4746 SH_PFC_PIN_GROUP(ssi6_ctrl),
4747 SH_PFC_PIN_GROUP(ssi7_data),
4748 SH_PFC_PIN_GROUP(ssi78_ctrl),
4749 SH_PFC_PIN_GROUP(ssi8_data),
4750 SH_PFC_PIN_GROUP(ssi9_data_a),
4751 SH_PFC_PIN_GROUP(ssi9_data_b),
4752 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4753 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4754 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4755 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4756 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4757 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4758 SH_PFC_PIN_GROUP(tpu_to0),
4759 SH_PFC_PIN_GROUP(tpu_to1),
4760 SH_PFC_PIN_GROUP(tpu_to2),
4761 SH_PFC_PIN_GROUP(tpu_to3),
4762 SH_PFC_PIN_GROUP(usb0),
4763 SH_PFC_PIN_GROUP(usb1),
4764 SH_PFC_PIN_GROUP(usb30),
4765 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4766 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4767 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4768 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4769 SH_PFC_PIN_GROUP(vin4_data18_a),
4770 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4771 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4772 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4773 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4774 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4775 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4776 SH_PFC_PIN_GROUP(vin4_data18_b),
4777 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4778 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4779 SH_PFC_PIN_GROUP(vin4_g8),
4780 SH_PFC_PIN_GROUP(vin4_sync),
4781 SH_PFC_PIN_GROUP(vin4_field),
4782 SH_PFC_PIN_GROUP(vin4_clkenb),
4783 SH_PFC_PIN_GROUP(vin4_clk),
4784 VIN_DATA_PIN_GROUP(vin5_data, 8),
4785 VIN_DATA_PIN_GROUP(vin5_data, 10),
4786 VIN_DATA_PIN_GROUP(vin5_data, 12),
4787 VIN_DATA_PIN_GROUP(vin5_data, 16),
4788 SH_PFC_PIN_GROUP(vin5_high8),
4789 SH_PFC_PIN_GROUP(vin5_sync),
4790 SH_PFC_PIN_GROUP(vin5_field),
4791 SH_PFC_PIN_GROUP(vin5_clkenb),
4792 SH_PFC_PIN_GROUP(vin5_clk),
4794 #ifdef CONFIG_PINCTRL_PFC_R8A77965
4796 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4797 SH_PFC_PIN_GROUP(drif0_data0_a),
4798 SH_PFC_PIN_GROUP(drif0_data1_a),
4799 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4800 SH_PFC_PIN_GROUP(drif0_data0_b),
4801 SH_PFC_PIN_GROUP(drif0_data1_b),
4802 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4803 SH_PFC_PIN_GROUP(drif0_data0_c),
4804 SH_PFC_PIN_GROUP(drif0_data1_c),
4805 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4806 SH_PFC_PIN_GROUP(drif1_data0_a),
4807 SH_PFC_PIN_GROUP(drif1_data1_a),
4808 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4809 SH_PFC_PIN_GROUP(drif1_data0_b),
4810 SH_PFC_PIN_GROUP(drif1_data1_b),
4811 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4812 SH_PFC_PIN_GROUP(drif1_data0_c),
4813 SH_PFC_PIN_GROUP(drif1_data1_c),
4814 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4815 SH_PFC_PIN_GROUP(drif2_data0_a),
4816 SH_PFC_PIN_GROUP(drif2_data1_a),
4817 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4818 SH_PFC_PIN_GROUP(drif2_data0_b),
4819 SH_PFC_PIN_GROUP(drif2_data1_b),
4820 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4821 SH_PFC_PIN_GROUP(drif3_data0_a),
4822 SH_PFC_PIN_GROUP(drif3_data1_a),
4823 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4824 SH_PFC_PIN_GROUP(drif3_data0_b),
4825 SH_PFC_PIN_GROUP(drif3_data1_b),
4827 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */
4830 static const char * const audio_clk_groups[] = {
4850 static const char * const avb_groups[] = {
4854 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4859 "avb_avtp_capture_a",
4861 "avb_avtp_capture_b",
4864 static const char * const can0_groups[] = {
4869 static const char * const can1_groups[] = {
4873 static const char * const can_clk_groups[] = {
4877 static const char * const canfd0_groups[] = {
4882 static const char * const canfd1_groups[] = {
4886 #ifdef CONFIG_PINCTRL_PFC_R8A77965
4887 static const char * const drif0_groups[] = {
4899 static const char * const drif1_groups[] = {
4911 static const char * const drif2_groups[] = {
4920 static const char * const drif3_groups[] = {
4928 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */
4930 static const char * const du_groups[] = {
4941 static const char * const hscif0_groups[] = {
4947 static const char * const hscif1_groups[] = {
4956 static const char * const hscif2_groups[] = {
4968 static const char * const hscif3_groups[] = {
4977 static const char * const hscif4_groups[] = {
4984 static const char * const i2c0_groups[] = {
4988 static const char * const i2c1_groups[] = {
4993 static const char * const i2c2_groups[] = {
4998 static const char * const i2c3_groups[] = {
5002 static const char * const i2c5_groups[] = {
5006 static const char * const i2c6_groups[] = {
5012 static const char * const intc_ex_groups[] = {
5021 static const char * const msiof0_groups[] = {
5030 static const char * const msiof1_groups[] = {
5075 static const char * const msiof2_groups[] = {
5102 static const char * const msiof3_groups[] = {
5132 static const char * const pwm0_groups[] = {
5136 static const char * const pwm1_groups[] = {
5141 static const char * const pwm2_groups[] = {
5146 static const char * const pwm3_groups[] = {
5151 static const char * const pwm4_groups[] = {
5156 static const char * const pwm5_groups[] = {
5161 static const char * const pwm6_groups[] = {
5166 static const char * const qspi0_groups[] = {
5172 static const char * const qspi1_groups[] = {
5178 static const char * const sata0_groups[] = {
5183 static const char * const scif0_groups[] = {
5189 static const char * const scif1_groups[] = {
5195 static const char * const scif2_groups[] = {
5201 static const char * const scif3_groups[] = {
5208 static const char * const scif4_groups[] = {
5220 static const char * const scif5_groups[] = {
5227 static const char * const scif_clk_groups[] = {
5232 static const char * const sdhi0_groups[] = {
5240 static const char * const sdhi1_groups[] = {
5248 static const char * const sdhi2_groups[] = {
5260 static const char * const sdhi3_groups[] = {
5270 static const char * const ssi_groups[] = {
5298 static const char * const tmu_groups[] = {
5305 static const char * const tpu_groups[] = {
5312 static const char * const usb0_groups[] = {
5316 static const char * const usb1_groups[] = {
5320 static const char * const usb30_groups[] = {
5324 static const char * const vin4_groups[] = {
5346 static const char * const vin5_groups[] = {
5358 static const struct {
5359 struct sh_pfc_function common[53];
5360 #ifdef CONFIG_PINCTRL_PFC_R8A77965
5361 struct sh_pfc_function automotive[4];
5363 } pinmux_functions = {
5365 SH_PFC_FUNCTION(audio_clk),
5366 SH_PFC_FUNCTION(avb),
5367 SH_PFC_FUNCTION(can0),
5368 SH_PFC_FUNCTION(can1),
5369 SH_PFC_FUNCTION(can_clk),
5370 SH_PFC_FUNCTION(canfd0),
5371 SH_PFC_FUNCTION(canfd1),
5372 SH_PFC_FUNCTION(du),
5373 SH_PFC_FUNCTION(hscif0),
5374 SH_PFC_FUNCTION(hscif1),
5375 SH_PFC_FUNCTION(hscif2),
5376 SH_PFC_FUNCTION(hscif3),
5377 SH_PFC_FUNCTION(hscif4),
5378 SH_PFC_FUNCTION(i2c0),
5379 SH_PFC_FUNCTION(i2c1),
5380 SH_PFC_FUNCTION(i2c2),
5381 SH_PFC_FUNCTION(i2c3),
5382 SH_PFC_FUNCTION(i2c5),
5383 SH_PFC_FUNCTION(i2c6),
5384 SH_PFC_FUNCTION(intc_ex),
5385 SH_PFC_FUNCTION(msiof0),
5386 SH_PFC_FUNCTION(msiof1),
5387 SH_PFC_FUNCTION(msiof2),
5388 SH_PFC_FUNCTION(msiof3),
5389 SH_PFC_FUNCTION(pwm0),
5390 SH_PFC_FUNCTION(pwm1),
5391 SH_PFC_FUNCTION(pwm2),
5392 SH_PFC_FUNCTION(pwm3),
5393 SH_PFC_FUNCTION(pwm4),
5394 SH_PFC_FUNCTION(pwm5),
5395 SH_PFC_FUNCTION(pwm6),
5396 SH_PFC_FUNCTION(qspi0),
5397 SH_PFC_FUNCTION(qspi1),
5398 SH_PFC_FUNCTION(sata0),
5399 SH_PFC_FUNCTION(scif0),
5400 SH_PFC_FUNCTION(scif1),
5401 SH_PFC_FUNCTION(scif2),
5402 SH_PFC_FUNCTION(scif3),
5403 SH_PFC_FUNCTION(scif4),
5404 SH_PFC_FUNCTION(scif5),
5405 SH_PFC_FUNCTION(scif_clk),
5406 SH_PFC_FUNCTION(sdhi0),
5407 SH_PFC_FUNCTION(sdhi1),
5408 SH_PFC_FUNCTION(sdhi2),
5409 SH_PFC_FUNCTION(sdhi3),
5410 SH_PFC_FUNCTION(ssi),
5411 SH_PFC_FUNCTION(tmu),
5412 SH_PFC_FUNCTION(tpu),
5413 SH_PFC_FUNCTION(usb0),
5414 SH_PFC_FUNCTION(usb1),
5415 SH_PFC_FUNCTION(usb30),
5416 SH_PFC_FUNCTION(vin4),
5417 SH_PFC_FUNCTION(vin5),
5419 #ifdef CONFIG_PINCTRL_PFC_R8A77965
5421 SH_PFC_FUNCTION(drif0),
5422 SH_PFC_FUNCTION(drif1),
5423 SH_PFC_FUNCTION(drif2),
5424 SH_PFC_FUNCTION(drif3),
5426 #endif /* CONFIG_PINCTRL_PFC_R8A77965 */
5429 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5430 #define F_(x, y) FN_##y
5431 #define FM(x) FN_##x
5432 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5449 GP_0_15_FN, GPSR0_15,
5450 GP_0_14_FN, GPSR0_14,
5451 GP_0_13_FN, GPSR0_13,
5452 GP_0_12_FN, GPSR0_12,
5453 GP_0_11_FN, GPSR0_11,
5454 GP_0_10_FN, GPSR0_10,
5464 GP_0_0_FN, GPSR0_0, ))
5466 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5470 GP_1_28_FN, GPSR1_28,
5471 GP_1_27_FN, GPSR1_27,
5472 GP_1_26_FN, GPSR1_26,
5473 GP_1_25_FN, GPSR1_25,
5474 GP_1_24_FN, GPSR1_24,
5475 GP_1_23_FN, GPSR1_23,
5476 GP_1_22_FN, GPSR1_22,
5477 GP_1_21_FN, GPSR1_21,
5478 GP_1_20_FN, GPSR1_20,
5479 GP_1_19_FN, GPSR1_19,
5480 GP_1_18_FN, GPSR1_18,
5481 GP_1_17_FN, GPSR1_17,
5482 GP_1_16_FN, GPSR1_16,
5483 GP_1_15_FN, GPSR1_15,
5484 GP_1_14_FN, GPSR1_14,
5485 GP_1_13_FN, GPSR1_13,
5486 GP_1_12_FN, GPSR1_12,
5487 GP_1_11_FN, GPSR1_11,
5488 GP_1_10_FN, GPSR1_10,
5498 GP_1_0_FN, GPSR1_0, ))
5500 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5518 GP_2_14_FN, GPSR2_14,
5519 GP_2_13_FN, GPSR2_13,
5520 GP_2_12_FN, GPSR2_12,
5521 GP_2_11_FN, GPSR2_11,
5522 GP_2_10_FN, GPSR2_10,
5532 GP_2_0_FN, GPSR2_0, ))
5534 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5551 GP_3_15_FN, GPSR3_15,
5552 GP_3_14_FN, GPSR3_14,
5553 GP_3_13_FN, GPSR3_13,
5554 GP_3_12_FN, GPSR3_12,
5555 GP_3_11_FN, GPSR3_11,
5556 GP_3_10_FN, GPSR3_10,
5566 GP_3_0_FN, GPSR3_0, ))
5568 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5583 GP_4_17_FN, GPSR4_17,
5584 GP_4_16_FN, GPSR4_16,
5585 GP_4_15_FN, GPSR4_15,
5586 GP_4_14_FN, GPSR4_14,
5587 GP_4_13_FN, GPSR4_13,
5588 GP_4_12_FN, GPSR4_12,
5589 GP_4_11_FN, GPSR4_11,
5590 GP_4_10_FN, GPSR4_10,
5600 GP_4_0_FN, GPSR4_0, ))
5602 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5609 GP_5_25_FN, GPSR5_25,
5610 GP_5_24_FN, GPSR5_24,
5611 GP_5_23_FN, GPSR5_23,
5612 GP_5_22_FN, GPSR5_22,
5613 GP_5_21_FN, GPSR5_21,
5614 GP_5_20_FN, GPSR5_20,
5615 GP_5_19_FN, GPSR5_19,
5616 GP_5_18_FN, GPSR5_18,
5617 GP_5_17_FN, GPSR5_17,
5618 GP_5_16_FN, GPSR5_16,
5619 GP_5_15_FN, GPSR5_15,
5620 GP_5_14_FN, GPSR5_14,
5621 GP_5_13_FN, GPSR5_13,
5622 GP_5_12_FN, GPSR5_12,
5623 GP_5_11_FN, GPSR5_11,
5624 GP_5_10_FN, GPSR5_10,
5634 GP_5_0_FN, GPSR5_0, ))
5636 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5637 GP_6_31_FN, GPSR6_31,
5638 GP_6_30_FN, GPSR6_30,
5639 GP_6_29_FN, GPSR6_29,
5640 GP_6_28_FN, GPSR6_28,
5641 GP_6_27_FN, GPSR6_27,
5642 GP_6_26_FN, GPSR6_26,
5643 GP_6_25_FN, GPSR6_25,
5644 GP_6_24_FN, GPSR6_24,
5645 GP_6_23_FN, GPSR6_23,
5646 GP_6_22_FN, GPSR6_22,
5647 GP_6_21_FN, GPSR6_21,
5648 GP_6_20_FN, GPSR6_20,
5649 GP_6_19_FN, GPSR6_19,
5650 GP_6_18_FN, GPSR6_18,
5651 GP_6_17_FN, GPSR6_17,
5652 GP_6_16_FN, GPSR6_16,
5653 GP_6_15_FN, GPSR6_15,
5654 GP_6_14_FN, GPSR6_14,
5655 GP_6_13_FN, GPSR6_13,
5656 GP_6_12_FN, GPSR6_12,
5657 GP_6_11_FN, GPSR6_11,
5658 GP_6_10_FN, GPSR6_10,
5668 GP_6_0_FN, GPSR6_0, ))
5670 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5702 GP_7_0_FN, GPSR7_0, ))
5708 #define FM(x) FN_##x,
5709 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5719 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5729 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5739 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5749 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5759 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5769 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5779 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5784 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5789 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5799 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5809 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5819 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5829 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5839 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5849 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5859 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5869 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5879 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5889 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5890 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5891 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5892 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5893 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5894 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5895 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5903 #define FM(x) FN_##x,
5904 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5905 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5906 1, 1, 1, 2, 2, 1, 2, 3),
5918 0, 0, /* RESERVED 15 */
5927 /* RESERVED 2, 1, 0 */
5928 0, 0, 0, 0, 0, 0, 0, 0 ))
5930 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5931 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5932 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5949 0, 0, 0, 0, /* RESERVED 8, 7 */
5958 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5959 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5976 /* RESERVED 15, 14, 13, 12 */
5977 0, 0, 0, 0, 0, 0, 0, 0,
5978 0, 0, 0, 0, 0, 0, 0, 0,
5979 /* RESERVED 11, 10, 9, 8 */
5980 0, 0, 0, 0, 0, 0, 0, 0,
5981 0, 0, 0, 0, 0, 0, 0, 0,
5982 /* RESERVED 7, 6, 5, 4 */
5983 0, 0, 0, 0, 0, 0, 0, 0,
5984 0, 0, 0, 0, 0, 0, 0, 0,
5985 /* RESERVED 3, 2, 1 */
5986 0, 0, 0, 0, 0, 0, 0, 0,
5992 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5993 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5994 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5995 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5996 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5997 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5998 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5999 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
6000 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
6001 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
6003 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
6004 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
6005 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
6006 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
6007 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
6008 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
6009 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
6010 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
6011 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
6013 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
6014 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
6015 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
6016 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
6017 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
6018 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
6019 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
6020 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
6021 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
6023 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
6024 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
6025 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
6026 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
6027 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
6028 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
6029 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
6030 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
6031 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
6033 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
6034 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
6035 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
6036 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
6037 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
6038 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
6039 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
6040 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
6041 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
6043 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
6044 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
6045 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
6046 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
6047 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
6048 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
6049 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
6050 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
6051 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
6053 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
6054 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
6055 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
6056 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
6057 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
6058 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
6059 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
6060 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
6061 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
6063 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
6064 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
6065 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
6066 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
6067 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
6068 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
6069 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
6070 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
6071 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
6073 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
6074 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
6075 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
6076 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
6077 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
6078 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
6079 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
6080 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
6081 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
6083 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
6084 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
6085 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
6086 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
6087 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
6088 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
6089 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
6090 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
6091 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
6093 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
6094 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
6095 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
6096 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
6097 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
6098 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
6099 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
6100 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
6101 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
6103 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
6104 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
6105 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
6106 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
6107 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
6108 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
6109 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
6110 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
6111 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
6113 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
6114 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
6115 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
6116 { PIN_TMS, 4, 2 }, /* TMS */
6118 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
6119 { PIN_TDO, 28, 2 }, /* TDO */
6120 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
6121 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
6122 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
6123 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
6124 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
6125 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
6126 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
6128 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
6129 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
6130 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
6131 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
6132 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
6133 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
6134 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
6135 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
6136 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
6138 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
6139 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
6140 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
6141 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
6142 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
6143 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
6144 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
6145 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
6146 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
6148 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
6149 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
6150 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
6151 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
6152 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
6153 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
6154 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
6155 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
6156 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
6158 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
6159 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
6160 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
6161 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
6162 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
6163 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
6164 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
6165 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
6166 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
6168 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
6169 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
6170 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
6171 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
6172 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
6173 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
6174 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
6175 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
6176 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
6178 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
6179 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
6180 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
6181 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
6182 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
6183 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
6184 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
6185 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
6186 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
6188 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
6189 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
6190 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
6191 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
6192 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
6193 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
6194 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
6195 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
6196 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
6198 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
6199 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
6200 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
6201 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
6202 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
6203 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
6204 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
6205 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
6206 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
6208 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
6209 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
6210 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
6211 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
6212 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
6213 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
6214 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
6215 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
6216 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
6218 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
6219 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
6220 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
6221 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
6222 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
6223 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
6224 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
6225 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
6226 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
6228 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
6229 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
6230 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
6231 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
6232 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
6233 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
6234 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
6235 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
6245 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
6246 [POCCTRL] = { 0xe6060380, },
6247 [TDSELCTRL] = { 0xe60603c0, },
6251 static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc,
6252 unsigned int pin, u32 *pocctrl)
6256 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
6258 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
6261 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
6262 bit = (pin & 0x1f) + 12;
6267 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6268 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
6269 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
6270 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
6271 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
6272 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
6273 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
6274 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
6275 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
6276 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
6277 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
6278 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
6279 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
6280 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
6281 [12] = PIN_RPC_INT_N, /* RPC_INT# */
6282 [13] = PIN_RPC_WP_N, /* RPC_WP# */
6283 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
6284 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
6285 [16] = PIN_AVB_RXC, /* AVB_RXC */
6286 [17] = PIN_AVB_RD0, /* AVB_RD0 */
6287 [18] = PIN_AVB_RD1, /* AVB_RD1 */
6288 [19] = PIN_AVB_RD2, /* AVB_RD2 */
6289 [20] = PIN_AVB_RD3, /* AVB_RD3 */
6290 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
6291 [22] = PIN_AVB_TXC, /* AVB_TXC */
6292 [23] = PIN_AVB_TD0, /* AVB_TD0 */
6293 [24] = PIN_AVB_TD1, /* AVB_TD1 */
6294 [25] = PIN_AVB_TD2, /* AVB_TD2 */
6295 [26] = PIN_AVB_TD3, /* AVB_TD3 */
6296 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
6297 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
6298 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
6299 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
6300 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
6302 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6303 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
6304 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
6305 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
6306 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
6307 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
6308 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
6309 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
6310 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
6311 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
6312 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
6313 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
6314 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
6315 [12] = RCAR_GP_PIN(1, 0), /* A0 */
6316 [13] = RCAR_GP_PIN(1, 1), /* A1 */
6317 [14] = RCAR_GP_PIN(1, 2), /* A2 */
6318 [15] = RCAR_GP_PIN(1, 3), /* A3 */
6319 [16] = RCAR_GP_PIN(1, 4), /* A4 */
6320 [17] = RCAR_GP_PIN(1, 5), /* A5 */
6321 [18] = RCAR_GP_PIN(1, 6), /* A6 */
6322 [19] = RCAR_GP_PIN(1, 7), /* A7 */
6323 [20] = RCAR_GP_PIN(1, 8), /* A8 */
6324 [21] = RCAR_GP_PIN(1, 9), /* A9 */
6325 [22] = RCAR_GP_PIN(1, 10), /* A10 */
6326 [23] = RCAR_GP_PIN(1, 11), /* A11 */
6327 [24] = RCAR_GP_PIN(1, 12), /* A12 */
6328 [25] = RCAR_GP_PIN(1, 13), /* A13 */
6329 [26] = RCAR_GP_PIN(1, 14), /* A14 */
6330 [27] = RCAR_GP_PIN(1, 15), /* A15 */
6331 [28] = RCAR_GP_PIN(1, 16), /* A16 */
6332 [29] = RCAR_GP_PIN(1, 17), /* A17 */
6333 [30] = RCAR_GP_PIN(1, 18), /* A18 */
6334 [31] = RCAR_GP_PIN(1, 19), /* A19 */
6336 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6337 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6338 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
6339 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
6340 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
6341 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
6342 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
6343 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
6344 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
6345 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
6346 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
6347 [10] = RCAR_GP_PIN(0, 0), /* D0 */
6348 [11] = RCAR_GP_PIN(0, 1), /* D1 */
6349 [12] = RCAR_GP_PIN(0, 2), /* D2 */
6350 [13] = RCAR_GP_PIN(0, 3), /* D3 */
6351 [14] = RCAR_GP_PIN(0, 4), /* D4 */
6352 [15] = RCAR_GP_PIN(0, 5), /* D5 */
6353 [16] = RCAR_GP_PIN(0, 6), /* D6 */
6354 [17] = RCAR_GP_PIN(0, 7), /* D7 */
6355 [18] = RCAR_GP_PIN(0, 8), /* D8 */
6356 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6357 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6358 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6359 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6360 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6361 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6362 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6363 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6364 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
6365 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
6366 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
6367 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
6368 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
6370 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6371 [ 0] = SH_PFC_PIN_NONE,
6372 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
6373 [ 2] = PIN_FSCLKST, /* FSCLKST */
6374 [ 3] = PIN_EXTALR, /* EXTALR*/
6375 [ 4] = PIN_TRST_N, /* TRST# */
6376 [ 5] = PIN_TCK, /* TCK */
6377 [ 6] = PIN_TMS, /* TMS */
6378 [ 7] = PIN_TDI, /* TDI */
6379 [ 8] = SH_PFC_PIN_NONE,
6380 [ 9] = PIN_ASEBRK, /* ASEBRK */
6381 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6382 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6383 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6384 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6385 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6386 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6387 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6388 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6389 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6390 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6391 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6392 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6393 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6394 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6395 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6396 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6397 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6398 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6399 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6400 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6401 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6402 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6404 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6405 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6406 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6407 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6408 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6409 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6410 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6411 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6412 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6413 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6414 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6415 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6416 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6417 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6418 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6419 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6420 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6421 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6422 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6423 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6424 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6425 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6426 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6427 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6428 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6429 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6430 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6431 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6432 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6433 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6434 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6435 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6436 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6438 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6439 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6440 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6441 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6442 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6443 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6444 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6445 [ 6] = PIN_MLB_REF, /* MLB_REF */
6446 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6447 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6448 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6449 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6450 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6451 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6452 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6453 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6454 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6455 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6456 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6457 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6458 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6459 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6460 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6461 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6462 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6463 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6464 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6465 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6466 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6467 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6468 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6469 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6470 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6472 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6473 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6474 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6475 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6476 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6477 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6478 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6479 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
6480 [ 7] = SH_PFC_PIN_NONE,
6481 [ 8] = SH_PFC_PIN_NONE,
6482 [ 9] = SH_PFC_PIN_NONE,
6483 [10] = SH_PFC_PIN_NONE,
6484 [11] = SH_PFC_PIN_NONE,
6485 [12] = SH_PFC_PIN_NONE,
6486 [13] = SH_PFC_PIN_NONE,
6487 [14] = SH_PFC_PIN_NONE,
6488 [15] = SH_PFC_PIN_NONE,
6489 [16] = SH_PFC_PIN_NONE,
6490 [17] = SH_PFC_PIN_NONE,
6491 [18] = SH_PFC_PIN_NONE,
6492 [19] = SH_PFC_PIN_NONE,
6493 [20] = SH_PFC_PIN_NONE,
6494 [21] = SH_PFC_PIN_NONE,
6495 [22] = SH_PFC_PIN_NONE,
6496 [23] = SH_PFC_PIN_NONE,
6497 [24] = SH_PFC_PIN_NONE,
6498 [25] = SH_PFC_PIN_NONE,
6499 [26] = SH_PFC_PIN_NONE,
6500 [27] = SH_PFC_PIN_NONE,
6501 [28] = SH_PFC_PIN_NONE,
6502 [29] = SH_PFC_PIN_NONE,
6503 [30] = SH_PFC_PIN_NONE,
6504 [31] = SH_PFC_PIN_NONE,
6509 static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
6510 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
6511 .get_bias = rcar_pinmux_get_bias,
6512 .set_bias = rcar_pinmux_set_bias,
6515 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
6516 const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
6517 .name = "r8a774b1_pfc",
6518 .ops = &r8a77965_pinmux_ops,
6519 .unlock_reg = 0xe6060000, /* PMMR */
6521 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6523 .pins = pinmux_pins,
6524 .nr_pins = ARRAY_SIZE(pinmux_pins),
6525 .groups = pinmux_groups.common,
6526 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6527 .functions = pinmux_functions.common,
6528 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6530 .cfg_regs = pinmux_config_regs,
6531 .drive_regs = pinmux_drive_regs,
6532 .bias_regs = pinmux_bias_regs,
6533 .ioctrl_regs = pinmux_ioctrl_regs,
6535 .pinmux_data = pinmux_data,
6536 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6540 #ifdef CONFIG_PINCTRL_PFC_R8A77965
6541 const struct sh_pfc_soc_info r8a77965_pinmux_info = {
6542 .name = "r8a77965_pfc",
6543 .ops = &r8a77965_pinmux_ops,
6544 .unlock_reg = 0xe6060000, /* PMMR */
6546 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6548 .pins = pinmux_pins,
6549 .nr_pins = ARRAY_SIZE(pinmux_pins),
6550 .groups = pinmux_groups.common,
6551 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6552 ARRAY_SIZE(pinmux_groups.automotive),
6553 .functions = pinmux_functions.common,
6554 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6555 ARRAY_SIZE(pinmux_functions.automotive),
6557 .cfg_regs = pinmux_config_regs,
6558 .drive_regs = pinmux_drive_regs,
6559 .bias_regs = pinmux_bias_regs,
6560 .ioctrl_regs = pinmux_ioctrl_regs,
6562 .pinmux_data = pinmux_data,
6563 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
projects / linux-2.6-microblaze.git / blob