1 // SPDX-License-Identifier: GPL-2.0
3 * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
5 * Copyright (C) 2016-2019 Renesas Electronics Corp.
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
9 * R-Car Gen3 processor support - PFC hardware block.
11 * Copyright (C) 2015 Renesas Electronics Corporation
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
20 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
22 #define CPU_ALL_GP(fn, sfx) \
23 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
36 #define CPU_ALL_NOGP(fn) \
37 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
38 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
56 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
71 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
72 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
73 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
75 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
76 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
77 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
78 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
81 * F_() : just information
82 * FM() : macro for FN_xxx / xxx_MARK
86 #define GPSR0_15 F_(D15, IP7_11_8)
87 #define GPSR0_14 F_(D14, IP7_7_4)
88 #define GPSR0_13 F_(D13, IP7_3_0)
89 #define GPSR0_12 F_(D12, IP6_31_28)
90 #define GPSR0_11 F_(D11, IP6_27_24)
91 #define GPSR0_10 F_(D10, IP6_23_20)
92 #define GPSR0_9 F_(D9, IP6_19_16)
93 #define GPSR0_8 F_(D8, IP6_15_12)
94 #define GPSR0_7 F_(D7, IP6_11_8)
95 #define GPSR0_6 F_(D6, IP6_7_4)
96 #define GPSR0_5 F_(D5, IP6_3_0)
97 #define GPSR0_4 F_(D4, IP5_31_28)
98 #define GPSR0_3 F_(D3, IP5_27_24)
99 #define GPSR0_2 F_(D2, IP5_23_20)
100 #define GPSR0_1 F_(D1, IP5_19_16)
101 #define GPSR0_0 F_(D0, IP5_15_12)
104 #define GPSR1_28 FM(CLKOUT)
105 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
106 #define GPSR1_26 F_(WE1_N, IP5_7_4)
107 #define GPSR1_25 F_(WE0_N, IP5_3_0)
108 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
109 #define GPSR1_23 F_(RD_N, IP4_27_24)
110 #define GPSR1_22 F_(BS_N, IP4_23_20)
111 #define GPSR1_21 F_(CS1_N, IP4_19_16)
112 #define GPSR1_20 F_(CS0_N, IP4_15_12)
113 #define GPSR1_19 F_(A19, IP4_11_8)
114 #define GPSR1_18 F_(A18, IP4_7_4)
115 #define GPSR1_17 F_(A17, IP4_3_0)
116 #define GPSR1_16 F_(A16, IP3_31_28)
117 #define GPSR1_15 F_(A15, IP3_27_24)
118 #define GPSR1_14 F_(A14, IP3_23_20)
119 #define GPSR1_13 F_(A13, IP3_19_16)
120 #define GPSR1_12 F_(A12, IP3_15_12)
121 #define GPSR1_11 F_(A11, IP3_11_8)
122 #define GPSR1_10 F_(A10, IP3_7_4)
123 #define GPSR1_9 F_(A9, IP3_3_0)
124 #define GPSR1_8 F_(A8, IP2_31_28)
125 #define GPSR1_7 F_(A7, IP2_27_24)
126 #define GPSR1_6 F_(A6, IP2_23_20)
127 #define GPSR1_5 F_(A5, IP2_19_16)
128 #define GPSR1_4 F_(A4, IP2_15_12)
129 #define GPSR1_3 F_(A3, IP2_11_8)
130 #define GPSR1_2 F_(A2, IP2_7_4)
131 #define GPSR1_1 F_(A1, IP2_3_0)
132 #define GPSR1_0 F_(A0, IP1_31_28)
135 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
136 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
137 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
138 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
139 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
140 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
141 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
142 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
143 #define GPSR2_6 F_(PWM0, IP1_19_16)
144 #define GPSR2_5 F_(IRQ5, IP1_15_12)
145 #define GPSR2_4 F_(IRQ4, IP1_11_8)
146 #define GPSR2_3 F_(IRQ3, IP1_7_4)
147 #define GPSR2_2 F_(IRQ2, IP1_3_0)
148 #define GPSR2_1 F_(IRQ1, IP0_31_28)
149 #define GPSR2_0 F_(IRQ0, IP0_27_24)
152 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
153 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
154 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
155 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
156 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
157 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
158 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
159 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
160 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
161 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
162 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
163 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
164 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
165 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
166 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
167 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
170 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
171 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
172 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
173 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
174 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
175 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
176 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
177 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
178 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
179 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
180 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
181 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
182 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
183 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
184 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
185 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
186 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
187 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
190 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
191 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
192 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
193 #define GPSR5_22 FM(MSIOF0_RXD)
194 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
195 #define GPSR5_20 FM(MSIOF0_TXD)
196 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
197 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
198 #define GPSR5_17 FM(MSIOF0_SCK)
199 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
200 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
201 #define GPSR5_14 F_(HTX0, IP13_19_16)
202 #define GPSR5_13 F_(HRX0, IP13_15_12)
203 #define GPSR5_12 F_(HSCK0, IP13_11_8)
204 #define GPSR5_11 F_(RX2_A, IP13_7_4)
205 #define GPSR5_10 F_(TX2_A, IP13_3_0)
206 #define GPSR5_9 F_(SCK2, IP12_31_28)
207 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
208 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
209 #define GPSR5_6 F_(TX1_A, IP12_19_16)
210 #define GPSR5_5 F_(RX1_A, IP12_15_12)
211 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
212 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
213 #define GPSR5_2 F_(TX0, IP12_3_0)
214 #define GPSR5_1 F_(RX0, IP11_31_28)
215 #define GPSR5_0 F_(SCK0, IP11_27_24)
218 #define GPSR6_31 F_(GP6_31, IP18_7_4)
219 #define GPSR6_30 F_(GP6_30, IP18_3_0)
220 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
221 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
222 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
223 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
224 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
225 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
226 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
227 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
228 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
229 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
230 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
231 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
232 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
233 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
234 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
235 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
236 #define GPSR6_13 FM(SSI_SDATA5)
237 #define GPSR6_12 FM(SSI_WS5)
238 #define GPSR6_11 FM(SSI_SCK5)
239 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
240 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
241 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
242 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
243 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
244 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
245 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
246 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
247 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
248 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
249 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
252 #define GPSR7_3 FM(GP7_03)
253 #define GPSR7_2 FM(GP7_02)
254 #define GPSR7_1 FM(AVS2)
255 #define GPSR7_0 FM(AVS1)
258 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
259 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
288 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
319 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
355 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
376 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
385 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
405 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
406 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
407 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
408 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
409 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
411 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
413 #define PINMUX_GPSR \
421 GPSR1_25 GPSR5_25 GPSR6_25 \
422 GPSR1_24 GPSR5_24 GPSR6_24 \
423 GPSR1_23 GPSR5_23 GPSR6_23 \
424 GPSR1_22 GPSR5_22 GPSR6_22 \
425 GPSR1_21 GPSR5_21 GPSR6_21 \
426 GPSR1_20 GPSR5_20 GPSR6_20 \
427 GPSR1_19 GPSR5_19 GPSR6_19 \
428 GPSR1_18 GPSR5_18 GPSR6_18 \
429 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
430 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
431 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
432 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
433 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
434 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
435 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
436 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
437 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
438 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
439 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
440 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
441 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
442 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
443 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
444 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
445 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
446 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
448 #define PINMUX_IPSR \
450 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
451 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
452 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
453 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
454 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
455 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
456 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
457 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
459 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
460 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
461 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
462 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
463 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
464 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
465 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
466 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
468 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
469 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
470 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
471 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
472 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
473 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
474 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
475 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
477 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
478 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
479 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
480 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
481 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
482 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
483 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
484 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
486 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
487 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
488 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
489 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
490 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
491 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
492 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
493 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
495 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
496 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
497 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
498 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
499 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
500 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
501 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
502 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
503 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
504 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
505 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
506 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
507 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
508 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
509 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
510 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
511 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
512 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
513 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
515 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
516 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
517 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
518 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
519 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
520 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
521 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
522 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
523 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
524 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
525 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
526 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
527 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
528 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
529 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
530 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
531 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
532 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
533 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
534 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
535 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
536 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
537 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
539 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
540 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
541 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
542 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
543 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
544 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
545 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
546 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
547 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
548 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
549 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
550 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
551 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
552 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
554 #define PINMUX_MOD_SELS \
556 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
558 MOD_SEL1_29_28_27 MOD_SEL2_29 \
559 MOD_SEL0_28_27 MOD_SEL2_28_27 \
560 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
561 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
562 MOD_SEL0_23 MOD_SEL1_23_22_21 \
563 MOD_SEL0_22 MOD_SEL2_22 \
564 MOD_SEL0_21 MOD_SEL2_21 \
565 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
566 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
567 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
569 MOD_SEL0_16 MOD_SEL1_16 \
573 MOD_SEL0_12 MOD_SEL1_12 \
574 MOD_SEL0_11 MOD_SEL1_11 \
575 MOD_SEL0_10 MOD_SEL1_10 \
576 MOD_SEL0_9_8 MOD_SEL1_9 \
579 MOD_SEL0_5 MOD_SEL1_5 \
580 MOD_SEL0_4_3 MOD_SEL1_4 \
584 MOD_SEL1_0 MOD_SEL2_0
587 * These pins are not able to be muxed but have other properties
588 * that can be set, such as drive-strength or pull-up/pull-down enable.
590 #define PINMUX_STATIC \
591 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
592 FM(QSPI0_IO2) FM(QSPI0_IO3) \
593 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
594 FM(QSPI1_IO2) FM(QSPI1_IO3) \
595 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
596 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
597 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
598 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
600 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
601 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
603 #define PINMUX_PHYS \
604 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
614 #define FM(x) FN_##x,
615 PINMUX_FUNCTION_BEGIN,
625 #define FM(x) x##_MARK,
637 static const u16 pinmux_data[] = {
638 PINMUX_DATA_GP_ALL(),
642 PINMUX_SINGLE(CLKOUT),
643 PINMUX_SINGLE(GP7_03),
644 PINMUX_SINGLE(GP7_02),
645 PINMUX_SINGLE(MSIOF0_RXD),
646 PINMUX_SINGLE(MSIOF0_SCK),
647 PINMUX_SINGLE(MSIOF0_TXD),
648 PINMUX_SINGLE(SSI_SCK5),
649 PINMUX_SINGLE(SSI_SDATA5),
650 PINMUX_SINGLE(SSI_WS5),
653 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
654 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
656 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
657 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
658 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
660 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
661 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
662 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
664 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
665 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
666 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
668 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
669 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
671 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
673 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
674 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
676 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
678 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
679 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
680 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
681 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
682 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
683 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
684 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
686 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
687 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
688 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
689 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
690 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
691 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
695 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
696 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
697 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
698 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
699 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
700 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
702 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
703 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
704 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
705 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
706 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
707 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
709 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
710 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
711 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
712 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
713 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
714 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
716 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
717 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
718 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
719 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
720 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
721 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
723 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
724 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
725 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
726 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
728 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
729 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
730 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
732 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
734 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
735 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
736 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
737 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
739 PINMUX_IPSR_GPSR(IP1_31_28, A0),
740 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
741 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
742 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
743 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
744 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
747 PINMUX_IPSR_GPSR(IP2_3_0, A1),
748 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
749 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
750 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
751 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
752 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
754 PINMUX_IPSR_GPSR(IP2_7_4, A2),
755 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
756 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
757 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
758 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
759 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
761 PINMUX_IPSR_GPSR(IP2_11_8, A3),
762 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
763 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
764 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
765 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
766 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
768 PINMUX_IPSR_GPSR(IP2_15_12, A4),
769 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
770 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
771 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
772 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
773 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
775 PINMUX_IPSR_GPSR(IP2_19_16, A5),
776 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
777 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
778 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
779 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
780 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
781 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
783 PINMUX_IPSR_GPSR(IP2_23_20, A6),
784 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
785 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
786 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
787 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
788 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
789 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
791 PINMUX_IPSR_GPSR(IP2_27_24, A7),
792 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
793 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
794 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
795 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
796 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
797 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
799 PINMUX_IPSR_GPSR(IP2_31_28, A8),
800 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
801 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
802 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
803 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
804 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
805 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
808 PINMUX_IPSR_GPSR(IP3_3_0, A9),
809 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
810 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
811 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
813 PINMUX_IPSR_GPSR(IP3_7_4, A10),
814 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
815 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
816 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
818 PINMUX_IPSR_GPSR(IP3_11_8, A11),
819 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
820 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
821 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
822 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
823 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
824 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
825 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
826 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
828 PINMUX_IPSR_GPSR(IP3_15_12, A12),
829 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
830 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
831 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
832 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
833 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
835 PINMUX_IPSR_GPSR(IP3_19_16, A13),
836 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
837 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
838 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
839 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
840 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
842 PINMUX_IPSR_GPSR(IP3_23_20, A14),
843 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
844 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
845 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
846 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
847 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
849 PINMUX_IPSR_GPSR(IP3_27_24, A15),
850 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
851 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
852 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
853 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
854 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
856 PINMUX_IPSR_GPSR(IP3_31_28, A16),
857 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
858 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
859 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
862 PINMUX_IPSR_GPSR(IP4_3_0, A17),
863 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
864 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
865 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
867 PINMUX_IPSR_GPSR(IP4_7_4, A18),
868 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
869 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
870 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
872 PINMUX_IPSR_GPSR(IP4_11_8, A19),
873 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
874 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
875 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
877 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
878 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
880 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
881 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
882 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
884 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
885 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
886 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
887 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
888 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
889 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
890 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
891 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
893 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
894 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
895 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
896 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
897 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
898 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
900 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
901 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
902 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
903 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
904 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
905 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
908 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
909 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
910 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
911 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
912 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
913 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
914 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
916 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
917 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
918 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
919 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
920 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
921 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
922 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
923 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
925 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
926 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
927 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
928 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
930 PINMUX_IPSR_GPSR(IP5_15_12, D0),
931 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
932 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
933 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
934 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
936 PINMUX_IPSR_GPSR(IP5_19_16, D1),
937 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
938 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
939 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
940 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
942 PINMUX_IPSR_GPSR(IP5_23_20, D2),
943 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
944 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
945 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
947 PINMUX_IPSR_GPSR(IP5_27_24, D3),
948 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
949 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
950 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
952 PINMUX_IPSR_GPSR(IP5_31_28, D4),
953 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
954 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
955 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
958 PINMUX_IPSR_GPSR(IP6_3_0, D5),
959 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
960 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
961 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
963 PINMUX_IPSR_GPSR(IP6_7_4, D6),
964 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
965 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
966 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
968 PINMUX_IPSR_GPSR(IP6_11_8, D7),
969 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
970 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
971 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
973 PINMUX_IPSR_GPSR(IP6_15_12, D8),
974 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
975 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
976 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
977 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
978 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
980 PINMUX_IPSR_GPSR(IP6_19_16, D9),
981 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
982 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
983 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
984 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
986 PINMUX_IPSR_GPSR(IP6_23_20, D10),
987 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
988 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
989 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
990 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
991 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
992 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
994 PINMUX_IPSR_GPSR(IP6_27_24, D11),
995 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
996 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
997 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
998 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
999 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
1000 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
1002 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1003 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1004 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1005 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1006 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1007 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1010 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1011 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1012 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1013 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1014 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1015 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1017 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1018 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1019 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1020 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1021 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1022 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1023 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1025 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1026 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1027 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1028 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1029 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1030 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1031 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1033 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1034 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1035 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1037 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1038 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1039 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1041 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1042 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1043 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1044 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1046 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1047 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1048 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1049 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1052 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1053 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1054 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1055 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1057 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1058 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1059 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1060 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1062 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1063 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1064 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1066 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1067 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1068 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1069 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1070 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1072 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1073 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1074 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1075 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1076 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1077 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1079 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1080 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1081 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1082 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1083 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1084 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1086 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1087 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1088 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1089 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1090 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1091 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1093 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1094 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1095 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1096 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1097 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1098 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1101 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1102 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1104 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1105 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1107 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1108 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1110 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1111 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1113 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1114 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1116 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1117 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1119 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1120 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1122 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1123 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1126 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1127 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1129 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1130 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1132 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1133 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1135 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1136 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1138 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1139 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1141 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1142 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1143 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1145 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1146 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1147 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1149 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1150 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1151 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1154 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1155 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1156 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1158 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1159 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1161 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1162 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
1163 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1164 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1166 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1167 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
1168 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1170 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1171 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1172 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1173 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
1175 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1176 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1177 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1178 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
1180 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1181 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1182 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1183 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
1184 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1185 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1186 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1187 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1188 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1189 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1191 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1192 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1193 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1194 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1195 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1198 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1199 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1200 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1201 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1202 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1204 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1205 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1206 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1207 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1208 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1209 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1210 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1211 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1213 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1214 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1215 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1216 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
1217 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1218 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1219 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1220 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1222 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1223 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1224 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1225 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1226 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1228 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1229 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1230 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1231 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1232 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1234 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1235 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1236 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1237 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1238 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1239 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1240 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1242 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1243 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1244 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1245 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1246 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1247 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1248 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1250 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1251 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1252 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1253 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1254 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1255 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1256 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1259 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1260 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1261 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1262 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1263 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1264 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1266 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1267 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1268 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1269 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1270 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1271 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1273 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1274 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1275 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
1276 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1277 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1278 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1279 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1280 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1282 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1283 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1284 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1285 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1286 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1287 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1289 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1290 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1291 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1292 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1293 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1294 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1296 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1297 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1298 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1299 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1300 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1301 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1302 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1303 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1305 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1306 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1307 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1308 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1309 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1310 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1311 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1313 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1314 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1315 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1316 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1319 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1320 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1321 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1322 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
1323 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1324 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1325 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1326 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1328 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1329 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1330 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1331 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
1332 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1333 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1334 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1335 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1337 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1338 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1339 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1341 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1342 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1343 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1344 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1346 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1347 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1348 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1350 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1351 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1353 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1354 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1356 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1357 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1360 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1362 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1363 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1365 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1366 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1367 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1369 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1370 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1371 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1372 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1374 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1375 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1376 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1377 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1378 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1379 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1380 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1382 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1383 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1384 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1385 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1386 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1387 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1388 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1390 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1391 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1392 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1393 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1394 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1395 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1396 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1398 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1399 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1400 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1401 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1402 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1403 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1404 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1407 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1408 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1410 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1411 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1413 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1414 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1416 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1417 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1418 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1419 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1420 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1421 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1422 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1424 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1425 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1426 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1427 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1428 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1429 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1430 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1432 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1433 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1434 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1435 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1436 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1437 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1438 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1439 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1441 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1442 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1443 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1444 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1445 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1446 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1447 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1449 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1450 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1451 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1452 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1453 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1454 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1455 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1456 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1459 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
1461 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
1462 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1463 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1464 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1465 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1467 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1468 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1469 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1470 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1471 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1472 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1473 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1475 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1476 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1477 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1478 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1479 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1480 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1482 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1483 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1484 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1485 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1486 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1487 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1488 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1489 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1490 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1492 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1493 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1494 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1495 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1496 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1497 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1498 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1499 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1500 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1502 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1503 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1504 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1505 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1506 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1507 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1508 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1509 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1510 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1511 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1512 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1514 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1515 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1516 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1517 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1518 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1519 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1520 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1521 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1522 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1525 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1526 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1527 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1528 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1529 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1530 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1531 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1532 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1533 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1535 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1536 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1537 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1538 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1539 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1540 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1541 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1542 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1543 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1546 * Static pins can not be muxed between different functions but
1547 * still need mark entries in the pinmux list. Add each static
1548 * pin to the list without an associated function. The sh-pfc
1549 * core will do the right thing and skip trying to mux the pin
1550 * while still applying configuration to it.
1552 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1558 * Pins not associated with a GPIO port.
1565 static const struct sh_pfc_pin pinmux_pins[] = {
1566 PINMUX_GPIO_GP_ALL(),
1570 /* - AUDIO CLOCK ------------------------------------------------------------ */
1571 static const unsigned int audio_clk_a_a_pins[] = {
1575 static const unsigned int audio_clk_a_a_mux[] = {
1578 static const unsigned int audio_clk_a_b_pins[] = {
1582 static const unsigned int audio_clk_a_b_mux[] = {
1585 static const unsigned int audio_clk_a_c_pins[] = {
1589 static const unsigned int audio_clk_a_c_mux[] = {
1592 static const unsigned int audio_clk_b_a_pins[] = {
1596 static const unsigned int audio_clk_b_a_mux[] = {
1599 static const unsigned int audio_clk_b_b_pins[] = {
1603 static const unsigned int audio_clk_b_b_mux[] = {
1606 static const unsigned int audio_clk_c_a_pins[] = {
1610 static const unsigned int audio_clk_c_a_mux[] = {
1613 static const unsigned int audio_clk_c_b_pins[] = {
1617 static const unsigned int audio_clk_c_b_mux[] = {
1620 static const unsigned int audio_clkout_a_pins[] = {
1624 static const unsigned int audio_clkout_a_mux[] = {
1625 AUDIO_CLKOUT_A_MARK,
1627 static const unsigned int audio_clkout_b_pins[] = {
1631 static const unsigned int audio_clkout_b_mux[] = {
1632 AUDIO_CLKOUT_B_MARK,
1634 static const unsigned int audio_clkout_c_pins[] = {
1638 static const unsigned int audio_clkout_c_mux[] = {
1639 AUDIO_CLKOUT_C_MARK,
1641 static const unsigned int audio_clkout_d_pins[] = {
1645 static const unsigned int audio_clkout_d_mux[] = {
1646 AUDIO_CLKOUT_D_MARK,
1648 static const unsigned int audio_clkout1_a_pins[] = {
1652 static const unsigned int audio_clkout1_a_mux[] = {
1653 AUDIO_CLKOUT1_A_MARK,
1655 static const unsigned int audio_clkout1_b_pins[] = {
1659 static const unsigned int audio_clkout1_b_mux[] = {
1660 AUDIO_CLKOUT1_B_MARK,
1662 static const unsigned int audio_clkout2_a_pins[] = {
1666 static const unsigned int audio_clkout2_a_mux[] = {
1667 AUDIO_CLKOUT2_A_MARK,
1669 static const unsigned int audio_clkout2_b_pins[] = {
1673 static const unsigned int audio_clkout2_b_mux[] = {
1674 AUDIO_CLKOUT2_B_MARK,
1677 static const unsigned int audio_clkout3_a_pins[] = {
1681 static const unsigned int audio_clkout3_a_mux[] = {
1682 AUDIO_CLKOUT3_A_MARK,
1684 static const unsigned int audio_clkout3_b_pins[] = {
1688 static const unsigned int audio_clkout3_b_mux[] = {
1689 AUDIO_CLKOUT3_B_MARK,
1692 /* - EtherAVB --------------------------------------------------------------- */
1693 static const unsigned int avb_link_pins[] = {
1697 static const unsigned int avb_link_mux[] = {
1700 static const unsigned int avb_magic_pins[] = {
1704 static const unsigned int avb_magic_mux[] = {
1707 static const unsigned int avb_phy_int_pins[] = {
1711 static const unsigned int avb_phy_int_mux[] = {
1714 static const unsigned int avb_mdio_pins[] = {
1715 /* AVB_MDC, AVB_MDIO */
1716 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1718 static const unsigned int avb_mdio_mux[] = {
1719 AVB_MDC_MARK, AVB_MDIO_MARK,
1721 static const unsigned int avb_mii_pins[] = {
1723 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1724 * AVB_TD1, AVB_TD2, AVB_TD3,
1725 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1726 * AVB_RD1, AVB_RD2, AVB_RD3,
1729 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1730 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1731 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1732 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1736 static const unsigned int avb_mii_mux[] = {
1737 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1738 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1739 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1740 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1743 static const unsigned int avb_avtp_pps_pins[] = {
1747 static const unsigned int avb_avtp_pps_mux[] = {
1750 static const unsigned int avb_avtp_match_a_pins[] = {
1751 /* AVB_AVTP_MATCH_A */
1754 static const unsigned int avb_avtp_match_a_mux[] = {
1755 AVB_AVTP_MATCH_A_MARK,
1757 static const unsigned int avb_avtp_capture_a_pins[] = {
1758 /* AVB_AVTP_CAPTURE_A */
1761 static const unsigned int avb_avtp_capture_a_mux[] = {
1762 AVB_AVTP_CAPTURE_A_MARK,
1764 static const unsigned int avb_avtp_match_b_pins[] = {
1765 /* AVB_AVTP_MATCH_B */
1768 static const unsigned int avb_avtp_match_b_mux[] = {
1769 AVB_AVTP_MATCH_B_MARK,
1771 static const unsigned int avb_avtp_capture_b_pins[] = {
1772 /* AVB_AVTP_CAPTURE_B */
1775 static const unsigned int avb_avtp_capture_b_mux[] = {
1776 AVB_AVTP_CAPTURE_B_MARK,
1779 /* - CAN ------------------------------------------------------------------ */
1780 static const unsigned int can0_data_a_pins[] = {
1782 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1784 static const unsigned int can0_data_a_mux[] = {
1785 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1787 static const unsigned int can0_data_b_pins[] = {
1789 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1791 static const unsigned int can0_data_b_mux[] = {
1792 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1794 static const unsigned int can1_data_pins[] = {
1796 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1798 static const unsigned int can1_data_mux[] = {
1799 CAN1_TX_MARK, CAN1_RX_MARK,
1802 /* - CAN Clock -------------------------------------------------------------- */
1803 static const unsigned int can_clk_pins[] = {
1807 static const unsigned int can_clk_mux[] = {
1811 /* - CAN FD --------------------------------------------------------------- */
1812 static const unsigned int canfd0_data_a_pins[] = {
1814 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1816 static const unsigned int canfd0_data_a_mux[] = {
1817 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1819 static const unsigned int canfd0_data_b_pins[] = {
1821 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1823 static const unsigned int canfd0_data_b_mux[] = {
1824 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1826 static const unsigned int canfd1_data_pins[] = {
1828 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1830 static const unsigned int canfd1_data_mux[] = {
1831 CANFD1_TX_MARK, CANFD1_RX_MARK,
1834 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
1835 /* - DRIF0 --------------------------------------------------------------- */
1836 static const unsigned int drif0_ctrl_a_pins[] = {
1838 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1840 static const unsigned int drif0_ctrl_a_mux[] = {
1841 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1843 static const unsigned int drif0_data0_a_pins[] = {
1847 static const unsigned int drif0_data0_a_mux[] = {
1850 static const unsigned int drif0_data1_a_pins[] = {
1854 static const unsigned int drif0_data1_a_mux[] = {
1857 static const unsigned int drif0_ctrl_b_pins[] = {
1859 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1861 static const unsigned int drif0_ctrl_b_mux[] = {
1862 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1864 static const unsigned int drif0_data0_b_pins[] = {
1868 static const unsigned int drif0_data0_b_mux[] = {
1871 static const unsigned int drif0_data1_b_pins[] = {
1875 static const unsigned int drif0_data1_b_mux[] = {
1878 static const unsigned int drif0_ctrl_c_pins[] = {
1880 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1882 static const unsigned int drif0_ctrl_c_mux[] = {
1883 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1885 static const unsigned int drif0_data0_c_pins[] = {
1889 static const unsigned int drif0_data0_c_mux[] = {
1892 static const unsigned int drif0_data1_c_pins[] = {
1896 static const unsigned int drif0_data1_c_mux[] = {
1899 /* - DRIF1 --------------------------------------------------------------- */
1900 static const unsigned int drif1_ctrl_a_pins[] = {
1902 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1904 static const unsigned int drif1_ctrl_a_mux[] = {
1905 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1907 static const unsigned int drif1_data0_a_pins[] = {
1911 static const unsigned int drif1_data0_a_mux[] = {
1914 static const unsigned int drif1_data1_a_pins[] = {
1918 static const unsigned int drif1_data1_a_mux[] = {
1921 static const unsigned int drif1_ctrl_b_pins[] = {
1923 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1925 static const unsigned int drif1_ctrl_b_mux[] = {
1926 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1928 static const unsigned int drif1_data0_b_pins[] = {
1932 static const unsigned int drif1_data0_b_mux[] = {
1935 static const unsigned int drif1_data1_b_pins[] = {
1939 static const unsigned int drif1_data1_b_mux[] = {
1942 static const unsigned int drif1_ctrl_c_pins[] = {
1944 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1946 static const unsigned int drif1_ctrl_c_mux[] = {
1947 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1949 static const unsigned int drif1_data0_c_pins[] = {
1953 static const unsigned int drif1_data0_c_mux[] = {
1956 static const unsigned int drif1_data1_c_pins[] = {
1960 static const unsigned int drif1_data1_c_mux[] = {
1963 /* - DRIF2 --------------------------------------------------------------- */
1964 static const unsigned int drif2_ctrl_a_pins[] = {
1966 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1968 static const unsigned int drif2_ctrl_a_mux[] = {
1969 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1971 static const unsigned int drif2_data0_a_pins[] = {
1975 static const unsigned int drif2_data0_a_mux[] = {
1978 static const unsigned int drif2_data1_a_pins[] = {
1982 static const unsigned int drif2_data1_a_mux[] = {
1985 static const unsigned int drif2_ctrl_b_pins[] = {
1987 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1989 static const unsigned int drif2_ctrl_b_mux[] = {
1990 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1992 static const unsigned int drif2_data0_b_pins[] = {
1996 static const unsigned int drif2_data0_b_mux[] = {
1999 static const unsigned int drif2_data1_b_pins[] = {
2003 static const unsigned int drif2_data1_b_mux[] = {
2006 /* - DRIF3 --------------------------------------------------------------- */
2007 static const unsigned int drif3_ctrl_a_pins[] = {
2009 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2011 static const unsigned int drif3_ctrl_a_mux[] = {
2012 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2014 static const unsigned int drif3_data0_a_pins[] = {
2018 static const unsigned int drif3_data0_a_mux[] = {
2021 static const unsigned int drif3_data1_a_pins[] = {
2025 static const unsigned int drif3_data1_a_mux[] = {
2028 static const unsigned int drif3_ctrl_b_pins[] = {
2030 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2032 static const unsigned int drif3_ctrl_b_mux[] = {
2033 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2035 static const unsigned int drif3_data0_b_pins[] = {
2039 static const unsigned int drif3_data0_b_mux[] = {
2042 static const unsigned int drif3_data1_b_pins[] = {
2046 static const unsigned int drif3_data1_b_mux[] = {
2049 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
2051 /* - DU --------------------------------------------------------------------- */
2052 static const unsigned int du_rgb666_pins[] = {
2053 /* R[7:2], G[7:2], B[7:2] */
2054 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2055 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2056 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2057 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2058 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2059 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2061 static const unsigned int du_rgb666_mux[] = {
2062 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2063 DU_DR3_MARK, DU_DR2_MARK,
2064 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2065 DU_DG3_MARK, DU_DG2_MARK,
2066 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2067 DU_DB3_MARK, DU_DB2_MARK,
2069 static const unsigned int du_rgb888_pins[] = {
2070 /* R[7:0], G[7:0], B[7:0] */
2071 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2072 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2073 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2074 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2075 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2076 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2077 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2078 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2079 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2081 static const unsigned int du_rgb888_mux[] = {
2082 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2083 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2084 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2085 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2086 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2087 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2089 static const unsigned int du_clk_out_0_pins[] = {
2093 static const unsigned int du_clk_out_0_mux[] = {
2096 static const unsigned int du_clk_out_1_pins[] = {
2100 static const unsigned int du_clk_out_1_mux[] = {
2103 static const unsigned int du_sync_pins[] = {
2104 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2105 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2107 static const unsigned int du_sync_mux[] = {
2108 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2110 static const unsigned int du_oddf_pins[] = {
2111 /* EXDISP/EXODDF/EXCDE */
2114 static const unsigned int du_oddf_mux[] = {
2115 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2117 static const unsigned int du_cde_pins[] = {
2121 static const unsigned int du_cde_mux[] = {
2124 static const unsigned int du_disp_pins[] = {
2128 static const unsigned int du_disp_mux[] = {
2132 /* - HSCIF0 ----------------------------------------------------------------- */
2133 static const unsigned int hscif0_data_pins[] = {
2135 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2137 static const unsigned int hscif0_data_mux[] = {
2138 HRX0_MARK, HTX0_MARK,
2140 static const unsigned int hscif0_clk_pins[] = {
2144 static const unsigned int hscif0_clk_mux[] = {
2147 static const unsigned int hscif0_ctrl_pins[] = {
2149 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2151 static const unsigned int hscif0_ctrl_mux[] = {
2152 HRTS0_N_MARK, HCTS0_N_MARK,
2154 /* - HSCIF1 ----------------------------------------------------------------- */
2155 static const unsigned int hscif1_data_a_pins[] = {
2157 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2159 static const unsigned int hscif1_data_a_mux[] = {
2160 HRX1_A_MARK, HTX1_A_MARK,
2162 static const unsigned int hscif1_clk_a_pins[] = {
2166 static const unsigned int hscif1_clk_a_mux[] = {
2169 static const unsigned int hscif1_ctrl_a_pins[] = {
2171 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2173 static const unsigned int hscif1_ctrl_a_mux[] = {
2174 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2177 static const unsigned int hscif1_data_b_pins[] = {
2179 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2181 static const unsigned int hscif1_data_b_mux[] = {
2182 HRX1_B_MARK, HTX1_B_MARK,
2184 static const unsigned int hscif1_clk_b_pins[] = {
2188 static const unsigned int hscif1_clk_b_mux[] = {
2191 static const unsigned int hscif1_ctrl_b_pins[] = {
2193 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2195 static const unsigned int hscif1_ctrl_b_mux[] = {
2196 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2198 /* - HSCIF2 ----------------------------------------------------------------- */
2199 static const unsigned int hscif2_data_a_pins[] = {
2201 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2203 static const unsigned int hscif2_data_a_mux[] = {
2204 HRX2_A_MARK, HTX2_A_MARK,
2206 static const unsigned int hscif2_clk_a_pins[] = {
2210 static const unsigned int hscif2_clk_a_mux[] = {
2213 static const unsigned int hscif2_ctrl_a_pins[] = {
2215 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2217 static const unsigned int hscif2_ctrl_a_mux[] = {
2218 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2221 static const unsigned int hscif2_data_b_pins[] = {
2223 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2225 static const unsigned int hscif2_data_b_mux[] = {
2226 HRX2_B_MARK, HTX2_B_MARK,
2228 static const unsigned int hscif2_clk_b_pins[] = {
2232 static const unsigned int hscif2_clk_b_mux[] = {
2235 static const unsigned int hscif2_ctrl_b_pins[] = {
2237 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2239 static const unsigned int hscif2_ctrl_b_mux[] = {
2240 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2243 static const unsigned int hscif2_data_c_pins[] = {
2245 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2247 static const unsigned int hscif2_data_c_mux[] = {
2248 HRX2_C_MARK, HTX2_C_MARK,
2250 static const unsigned int hscif2_clk_c_pins[] = {
2254 static const unsigned int hscif2_clk_c_mux[] = {
2257 static const unsigned int hscif2_ctrl_c_pins[] = {
2259 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2261 static const unsigned int hscif2_ctrl_c_mux[] = {
2262 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2264 /* - HSCIF3 ----------------------------------------------------------------- */
2265 static const unsigned int hscif3_data_a_pins[] = {
2267 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2269 static const unsigned int hscif3_data_a_mux[] = {
2270 HRX3_A_MARK, HTX3_A_MARK,
2272 static const unsigned int hscif3_clk_pins[] = {
2276 static const unsigned int hscif3_clk_mux[] = {
2279 static const unsigned int hscif3_ctrl_pins[] = {
2281 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2283 static const unsigned int hscif3_ctrl_mux[] = {
2284 HRTS3_N_MARK, HCTS3_N_MARK,
2287 static const unsigned int hscif3_data_b_pins[] = {
2289 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2291 static const unsigned int hscif3_data_b_mux[] = {
2292 HRX3_B_MARK, HTX3_B_MARK,
2294 static const unsigned int hscif3_data_c_pins[] = {
2296 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2298 static const unsigned int hscif3_data_c_mux[] = {
2299 HRX3_C_MARK, HTX3_C_MARK,
2301 static const unsigned int hscif3_data_d_pins[] = {
2303 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2305 static const unsigned int hscif3_data_d_mux[] = {
2306 HRX3_D_MARK, HTX3_D_MARK,
2308 /* - HSCIF4 ----------------------------------------------------------------- */
2309 static const unsigned int hscif4_data_a_pins[] = {
2311 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2313 static const unsigned int hscif4_data_a_mux[] = {
2314 HRX4_A_MARK, HTX4_A_MARK,
2316 static const unsigned int hscif4_clk_pins[] = {
2320 static const unsigned int hscif4_clk_mux[] = {
2323 static const unsigned int hscif4_ctrl_pins[] = {
2325 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2327 static const unsigned int hscif4_ctrl_mux[] = {
2328 HRTS4_N_MARK, HCTS4_N_MARK,
2331 static const unsigned int hscif4_data_b_pins[] = {
2333 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2335 static const unsigned int hscif4_data_b_mux[] = {
2336 HRX4_B_MARK, HTX4_B_MARK,
2339 /* - I2C -------------------------------------------------------------------- */
2340 static const unsigned int i2c0_pins[] = {
2342 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2345 static const unsigned int i2c0_mux[] = {
2346 SCL0_MARK, SDA0_MARK,
2349 static const unsigned int i2c1_a_pins[] = {
2351 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2353 static const unsigned int i2c1_a_mux[] = {
2354 SDA1_A_MARK, SCL1_A_MARK,
2356 static const unsigned int i2c1_b_pins[] = {
2358 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2360 static const unsigned int i2c1_b_mux[] = {
2361 SDA1_B_MARK, SCL1_B_MARK,
2363 static const unsigned int i2c2_a_pins[] = {
2365 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2367 static const unsigned int i2c2_a_mux[] = {
2368 SDA2_A_MARK, SCL2_A_MARK,
2370 static const unsigned int i2c2_b_pins[] = {
2372 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2374 static const unsigned int i2c2_b_mux[] = {
2375 SDA2_B_MARK, SCL2_B_MARK,
2378 static const unsigned int i2c3_pins[] = {
2380 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2383 static const unsigned int i2c3_mux[] = {
2384 SCL3_MARK, SDA3_MARK,
2387 static const unsigned int i2c5_pins[] = {
2389 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2392 static const unsigned int i2c5_mux[] = {
2393 SCL5_MARK, SDA5_MARK,
2396 static const unsigned int i2c6_a_pins[] = {
2398 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2400 static const unsigned int i2c6_a_mux[] = {
2401 SDA6_A_MARK, SCL6_A_MARK,
2403 static const unsigned int i2c6_b_pins[] = {
2405 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2407 static const unsigned int i2c6_b_mux[] = {
2408 SDA6_B_MARK, SCL6_B_MARK,
2410 static const unsigned int i2c6_c_pins[] = {
2412 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2414 static const unsigned int i2c6_c_mux[] = {
2415 SDA6_C_MARK, SCL6_C_MARK,
2418 /* - INTC-EX ---------------------------------------------------------------- */
2419 static const unsigned int intc_ex_irq0_pins[] = {
2423 static const unsigned int intc_ex_irq0_mux[] = {
2426 static const unsigned int intc_ex_irq1_pins[] = {
2430 static const unsigned int intc_ex_irq1_mux[] = {
2433 static const unsigned int intc_ex_irq2_pins[] = {
2437 static const unsigned int intc_ex_irq2_mux[] = {
2440 static const unsigned int intc_ex_irq3_pins[] = {
2444 static const unsigned int intc_ex_irq3_mux[] = {
2447 static const unsigned int intc_ex_irq4_pins[] = {
2451 static const unsigned int intc_ex_irq4_mux[] = {
2454 static const unsigned int intc_ex_irq5_pins[] = {
2458 static const unsigned int intc_ex_irq5_mux[] = {
2462 /* - MSIOF0 ----------------------------------------------------------------- */
2463 static const unsigned int msiof0_clk_pins[] = {
2467 static const unsigned int msiof0_clk_mux[] = {
2470 static const unsigned int msiof0_sync_pins[] = {
2474 static const unsigned int msiof0_sync_mux[] = {
2477 static const unsigned int msiof0_ss1_pins[] = {
2481 static const unsigned int msiof0_ss1_mux[] = {
2484 static const unsigned int msiof0_ss2_pins[] = {
2488 static const unsigned int msiof0_ss2_mux[] = {
2491 static const unsigned int msiof0_txd_pins[] = {
2495 static const unsigned int msiof0_txd_mux[] = {
2498 static const unsigned int msiof0_rxd_pins[] = {
2502 static const unsigned int msiof0_rxd_mux[] = {
2505 /* - MSIOF1 ----------------------------------------------------------------- */
2506 static const unsigned int msiof1_clk_a_pins[] = {
2510 static const unsigned int msiof1_clk_a_mux[] = {
2513 static const unsigned int msiof1_sync_a_pins[] = {
2517 static const unsigned int msiof1_sync_a_mux[] = {
2520 static const unsigned int msiof1_ss1_a_pins[] = {
2524 static const unsigned int msiof1_ss1_a_mux[] = {
2527 static const unsigned int msiof1_ss2_a_pins[] = {
2531 static const unsigned int msiof1_ss2_a_mux[] = {
2534 static const unsigned int msiof1_txd_a_pins[] = {
2538 static const unsigned int msiof1_txd_a_mux[] = {
2541 static const unsigned int msiof1_rxd_a_pins[] = {
2545 static const unsigned int msiof1_rxd_a_mux[] = {
2548 static const unsigned int msiof1_clk_b_pins[] = {
2552 static const unsigned int msiof1_clk_b_mux[] = {
2555 static const unsigned int msiof1_sync_b_pins[] = {
2559 static const unsigned int msiof1_sync_b_mux[] = {
2562 static const unsigned int msiof1_ss1_b_pins[] = {
2566 static const unsigned int msiof1_ss1_b_mux[] = {
2569 static const unsigned int msiof1_ss2_b_pins[] = {
2573 static const unsigned int msiof1_ss2_b_mux[] = {
2576 static const unsigned int msiof1_txd_b_pins[] = {
2580 static const unsigned int msiof1_txd_b_mux[] = {
2583 static const unsigned int msiof1_rxd_b_pins[] = {
2587 static const unsigned int msiof1_rxd_b_mux[] = {
2590 static const unsigned int msiof1_clk_c_pins[] = {
2594 static const unsigned int msiof1_clk_c_mux[] = {
2597 static const unsigned int msiof1_sync_c_pins[] = {
2601 static const unsigned int msiof1_sync_c_mux[] = {
2604 static const unsigned int msiof1_ss1_c_pins[] = {
2608 static const unsigned int msiof1_ss1_c_mux[] = {
2611 static const unsigned int msiof1_ss2_c_pins[] = {
2615 static const unsigned int msiof1_ss2_c_mux[] = {
2618 static const unsigned int msiof1_txd_c_pins[] = {
2622 static const unsigned int msiof1_txd_c_mux[] = {
2625 static const unsigned int msiof1_rxd_c_pins[] = {
2629 static const unsigned int msiof1_rxd_c_mux[] = {
2632 static const unsigned int msiof1_clk_d_pins[] = {
2636 static const unsigned int msiof1_clk_d_mux[] = {
2639 static const unsigned int msiof1_sync_d_pins[] = {
2643 static const unsigned int msiof1_sync_d_mux[] = {
2646 static const unsigned int msiof1_ss1_d_pins[] = {
2650 static const unsigned int msiof1_ss1_d_mux[] = {
2653 static const unsigned int msiof1_ss2_d_pins[] = {
2657 static const unsigned int msiof1_ss2_d_mux[] = {
2660 static const unsigned int msiof1_txd_d_pins[] = {
2664 static const unsigned int msiof1_txd_d_mux[] = {
2667 static const unsigned int msiof1_rxd_d_pins[] = {
2671 static const unsigned int msiof1_rxd_d_mux[] = {
2674 static const unsigned int msiof1_clk_e_pins[] = {
2678 static const unsigned int msiof1_clk_e_mux[] = {
2681 static const unsigned int msiof1_sync_e_pins[] = {
2685 static const unsigned int msiof1_sync_e_mux[] = {
2688 static const unsigned int msiof1_ss1_e_pins[] = {
2692 static const unsigned int msiof1_ss1_e_mux[] = {
2695 static const unsigned int msiof1_ss2_e_pins[] = {
2699 static const unsigned int msiof1_ss2_e_mux[] = {
2702 static const unsigned int msiof1_txd_e_pins[] = {
2706 static const unsigned int msiof1_txd_e_mux[] = {
2709 static const unsigned int msiof1_rxd_e_pins[] = {
2713 static const unsigned int msiof1_rxd_e_mux[] = {
2716 static const unsigned int msiof1_clk_f_pins[] = {
2720 static const unsigned int msiof1_clk_f_mux[] = {
2723 static const unsigned int msiof1_sync_f_pins[] = {
2727 static const unsigned int msiof1_sync_f_mux[] = {
2730 static const unsigned int msiof1_ss1_f_pins[] = {
2734 static const unsigned int msiof1_ss1_f_mux[] = {
2737 static const unsigned int msiof1_ss2_f_pins[] = {
2741 static const unsigned int msiof1_ss2_f_mux[] = {
2744 static const unsigned int msiof1_txd_f_pins[] = {
2748 static const unsigned int msiof1_txd_f_mux[] = {
2751 static const unsigned int msiof1_rxd_f_pins[] = {
2755 static const unsigned int msiof1_rxd_f_mux[] = {
2758 static const unsigned int msiof1_clk_g_pins[] = {
2762 static const unsigned int msiof1_clk_g_mux[] = {
2765 static const unsigned int msiof1_sync_g_pins[] = {
2769 static const unsigned int msiof1_sync_g_mux[] = {
2772 static const unsigned int msiof1_ss1_g_pins[] = {
2776 static const unsigned int msiof1_ss1_g_mux[] = {
2779 static const unsigned int msiof1_ss2_g_pins[] = {
2783 static const unsigned int msiof1_ss2_g_mux[] = {
2786 static const unsigned int msiof1_txd_g_pins[] = {
2790 static const unsigned int msiof1_txd_g_mux[] = {
2793 static const unsigned int msiof1_rxd_g_pins[] = {
2797 static const unsigned int msiof1_rxd_g_mux[] = {
2800 /* - MSIOF2 ----------------------------------------------------------------- */
2801 static const unsigned int msiof2_clk_a_pins[] = {
2805 static const unsigned int msiof2_clk_a_mux[] = {
2808 static const unsigned int msiof2_sync_a_pins[] = {
2812 static const unsigned int msiof2_sync_a_mux[] = {
2815 static const unsigned int msiof2_ss1_a_pins[] = {
2819 static const unsigned int msiof2_ss1_a_mux[] = {
2822 static const unsigned int msiof2_ss2_a_pins[] = {
2826 static const unsigned int msiof2_ss2_a_mux[] = {
2829 static const unsigned int msiof2_txd_a_pins[] = {
2833 static const unsigned int msiof2_txd_a_mux[] = {
2836 static const unsigned int msiof2_rxd_a_pins[] = {
2840 static const unsigned int msiof2_rxd_a_mux[] = {
2843 static const unsigned int msiof2_clk_b_pins[] = {
2847 static const unsigned int msiof2_clk_b_mux[] = {
2850 static const unsigned int msiof2_sync_b_pins[] = {
2854 static const unsigned int msiof2_sync_b_mux[] = {
2857 static const unsigned int msiof2_ss1_b_pins[] = {
2861 static const unsigned int msiof2_ss1_b_mux[] = {
2864 static const unsigned int msiof2_ss2_b_pins[] = {
2868 static const unsigned int msiof2_ss2_b_mux[] = {
2871 static const unsigned int msiof2_txd_b_pins[] = {
2875 static const unsigned int msiof2_txd_b_mux[] = {
2878 static const unsigned int msiof2_rxd_b_pins[] = {
2882 static const unsigned int msiof2_rxd_b_mux[] = {
2885 static const unsigned int msiof2_clk_c_pins[] = {
2889 static const unsigned int msiof2_clk_c_mux[] = {
2892 static const unsigned int msiof2_sync_c_pins[] = {
2896 static const unsigned int msiof2_sync_c_mux[] = {
2899 static const unsigned int msiof2_ss1_c_pins[] = {
2903 static const unsigned int msiof2_ss1_c_mux[] = {
2906 static const unsigned int msiof2_ss2_c_pins[] = {
2910 static const unsigned int msiof2_ss2_c_mux[] = {
2913 static const unsigned int msiof2_txd_c_pins[] = {
2917 static const unsigned int msiof2_txd_c_mux[] = {
2920 static const unsigned int msiof2_rxd_c_pins[] = {
2924 static const unsigned int msiof2_rxd_c_mux[] = {
2927 static const unsigned int msiof2_clk_d_pins[] = {
2931 static const unsigned int msiof2_clk_d_mux[] = {
2934 static const unsigned int msiof2_sync_d_pins[] = {
2938 static const unsigned int msiof2_sync_d_mux[] = {
2941 static const unsigned int msiof2_ss1_d_pins[] = {
2945 static const unsigned int msiof2_ss1_d_mux[] = {
2948 static const unsigned int msiof2_ss2_d_pins[] = {
2952 static const unsigned int msiof2_ss2_d_mux[] = {
2955 static const unsigned int msiof2_txd_d_pins[] = {
2959 static const unsigned int msiof2_txd_d_mux[] = {
2962 static const unsigned int msiof2_rxd_d_pins[] = {
2966 static const unsigned int msiof2_rxd_d_mux[] = {
2969 /* - MSIOF3 ----------------------------------------------------------------- */
2970 static const unsigned int msiof3_clk_a_pins[] = {
2974 static const unsigned int msiof3_clk_a_mux[] = {
2977 static const unsigned int msiof3_sync_a_pins[] = {
2981 static const unsigned int msiof3_sync_a_mux[] = {
2984 static const unsigned int msiof3_ss1_a_pins[] = {
2988 static const unsigned int msiof3_ss1_a_mux[] = {
2991 static const unsigned int msiof3_ss2_a_pins[] = {
2995 static const unsigned int msiof3_ss2_a_mux[] = {
2998 static const unsigned int msiof3_txd_a_pins[] = {
3002 static const unsigned int msiof3_txd_a_mux[] = {
3005 static const unsigned int msiof3_rxd_a_pins[] = {
3009 static const unsigned int msiof3_rxd_a_mux[] = {
3012 static const unsigned int msiof3_clk_b_pins[] = {
3016 static const unsigned int msiof3_clk_b_mux[] = {
3019 static const unsigned int msiof3_sync_b_pins[] = {
3023 static const unsigned int msiof3_sync_b_mux[] = {
3026 static const unsigned int msiof3_ss1_b_pins[] = {
3030 static const unsigned int msiof3_ss1_b_mux[] = {
3033 static const unsigned int msiof3_ss2_b_pins[] = {
3037 static const unsigned int msiof3_ss2_b_mux[] = {
3040 static const unsigned int msiof3_txd_b_pins[] = {
3044 static const unsigned int msiof3_txd_b_mux[] = {
3047 static const unsigned int msiof3_rxd_b_pins[] = {
3051 static const unsigned int msiof3_rxd_b_mux[] = {
3054 static const unsigned int msiof3_clk_c_pins[] = {
3058 static const unsigned int msiof3_clk_c_mux[] = {
3061 static const unsigned int msiof3_sync_c_pins[] = {
3065 static const unsigned int msiof3_sync_c_mux[] = {
3068 static const unsigned int msiof3_txd_c_pins[] = {
3072 static const unsigned int msiof3_txd_c_mux[] = {
3075 static const unsigned int msiof3_rxd_c_pins[] = {
3079 static const unsigned int msiof3_rxd_c_mux[] = {
3082 static const unsigned int msiof3_clk_d_pins[] = {
3086 static const unsigned int msiof3_clk_d_mux[] = {
3089 static const unsigned int msiof3_sync_d_pins[] = {
3093 static const unsigned int msiof3_sync_d_mux[] = {
3096 static const unsigned int msiof3_ss1_d_pins[] = {
3100 static const unsigned int msiof3_ss1_d_mux[] = {
3103 static const unsigned int msiof3_txd_d_pins[] = {
3107 static const unsigned int msiof3_txd_d_mux[] = {
3110 static const unsigned int msiof3_rxd_d_pins[] = {
3114 static const unsigned int msiof3_rxd_d_mux[] = {
3118 static const unsigned int msiof3_clk_e_pins[] = {
3122 static const unsigned int msiof3_clk_e_mux[] = {
3125 static const unsigned int msiof3_sync_e_pins[] = {
3129 static const unsigned int msiof3_sync_e_mux[] = {
3132 static const unsigned int msiof3_ss1_e_pins[] = {
3136 static const unsigned int msiof3_ss1_e_mux[] = {
3139 static const unsigned int msiof3_ss2_e_pins[] = {
3143 static const unsigned int msiof3_ss2_e_mux[] = {
3146 static const unsigned int msiof3_txd_e_pins[] = {
3150 static const unsigned int msiof3_txd_e_mux[] = {
3153 static const unsigned int msiof3_rxd_e_pins[] = {
3157 static const unsigned int msiof3_rxd_e_mux[] = {
3161 /* - PWM0 --------------------------------------------------------------------*/
3162 static const unsigned int pwm0_pins[] = {
3166 static const unsigned int pwm0_mux[] = {
3169 /* - PWM1 --------------------------------------------------------------------*/
3170 static const unsigned int pwm1_a_pins[] = {
3174 static const unsigned int pwm1_a_mux[] = {
3177 static const unsigned int pwm1_b_pins[] = {
3181 static const unsigned int pwm1_b_mux[] = {
3184 /* - PWM2 --------------------------------------------------------------------*/
3185 static const unsigned int pwm2_a_pins[] = {
3189 static const unsigned int pwm2_a_mux[] = {
3192 static const unsigned int pwm2_b_pins[] = {
3196 static const unsigned int pwm2_b_mux[] = {
3199 /* - PWM3 --------------------------------------------------------------------*/
3200 static const unsigned int pwm3_a_pins[] = {
3204 static const unsigned int pwm3_a_mux[] = {
3207 static const unsigned int pwm3_b_pins[] = {
3211 static const unsigned int pwm3_b_mux[] = {
3214 /* - PWM4 --------------------------------------------------------------------*/
3215 static const unsigned int pwm4_a_pins[] = {
3219 static const unsigned int pwm4_a_mux[] = {
3222 static const unsigned int pwm4_b_pins[] = {
3226 static const unsigned int pwm4_b_mux[] = {
3229 /* - PWM5 --------------------------------------------------------------------*/
3230 static const unsigned int pwm5_a_pins[] = {
3234 static const unsigned int pwm5_a_mux[] = {
3237 static const unsigned int pwm5_b_pins[] = {
3241 static const unsigned int pwm5_b_mux[] = {
3244 /* - PWM6 --------------------------------------------------------------------*/
3245 static const unsigned int pwm6_a_pins[] = {
3249 static const unsigned int pwm6_a_mux[] = {
3252 static const unsigned int pwm6_b_pins[] = {
3256 static const unsigned int pwm6_b_mux[] = {
3260 /* - QSPI0 ------------------------------------------------------------------ */
3261 static const unsigned int qspi0_ctrl_pins[] = {
3262 /* QSPI0_SPCLK, QSPI0_SSL */
3263 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3265 static const unsigned int qspi0_ctrl_mux[] = {
3266 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3268 static const unsigned int qspi0_data2_pins[] = {
3269 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3270 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3272 static const unsigned int qspi0_data2_mux[] = {
3273 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3275 static const unsigned int qspi0_data4_pins[] = {
3276 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3277 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3278 /* QSPI0_IO2, QSPI0_IO3 */
3279 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3281 static const unsigned int qspi0_data4_mux[] = {
3282 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3283 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3285 /* - QSPI1 ------------------------------------------------------------------ */
3286 static const unsigned int qspi1_ctrl_pins[] = {
3287 /* QSPI1_SPCLK, QSPI1_SSL */
3288 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3290 static const unsigned int qspi1_ctrl_mux[] = {
3291 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3293 static const unsigned int qspi1_data2_pins[] = {
3294 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3295 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3297 static const unsigned int qspi1_data2_mux[] = {
3298 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3300 static const unsigned int qspi1_data4_pins[] = {
3301 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3302 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3303 /* QSPI1_IO2, QSPI1_IO3 */
3304 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3306 static const unsigned int qspi1_data4_mux[] = {
3307 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3308 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3311 /* - SCIF0 ------------------------------------------------------------------ */
3312 static const unsigned int scif0_data_pins[] = {
3314 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3316 static const unsigned int scif0_data_mux[] = {
3319 static const unsigned int scif0_clk_pins[] = {
3323 static const unsigned int scif0_clk_mux[] = {
3326 static const unsigned int scif0_ctrl_pins[] = {
3328 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3330 static const unsigned int scif0_ctrl_mux[] = {
3331 RTS0_N_MARK, CTS0_N_MARK,
3333 /* - SCIF1 ------------------------------------------------------------------ */
3334 static const unsigned int scif1_data_a_pins[] = {
3336 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3338 static const unsigned int scif1_data_a_mux[] = {
3339 RX1_A_MARK, TX1_A_MARK,
3341 static const unsigned int scif1_clk_pins[] = {
3345 static const unsigned int scif1_clk_mux[] = {
3348 static const unsigned int scif1_ctrl_pins[] = {
3350 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3352 static const unsigned int scif1_ctrl_mux[] = {
3353 RTS1_N_MARK, CTS1_N_MARK,
3356 static const unsigned int scif1_data_b_pins[] = {
3358 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3360 static const unsigned int scif1_data_b_mux[] = {
3361 RX1_B_MARK, TX1_B_MARK,
3363 /* - SCIF2 ------------------------------------------------------------------ */
3364 static const unsigned int scif2_data_a_pins[] = {
3366 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3368 static const unsigned int scif2_data_a_mux[] = {
3369 RX2_A_MARK, TX2_A_MARK,
3371 static const unsigned int scif2_clk_pins[] = {
3375 static const unsigned int scif2_clk_mux[] = {
3378 static const unsigned int scif2_data_b_pins[] = {
3380 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3382 static const unsigned int scif2_data_b_mux[] = {
3383 RX2_B_MARK, TX2_B_MARK,
3385 /* - SCIF3 ------------------------------------------------------------------ */
3386 static const unsigned int scif3_data_a_pins[] = {
3388 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3390 static const unsigned int scif3_data_a_mux[] = {
3391 RX3_A_MARK, TX3_A_MARK,
3393 static const unsigned int scif3_clk_pins[] = {
3397 static const unsigned int scif3_clk_mux[] = {
3400 static const unsigned int scif3_ctrl_pins[] = {
3402 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3404 static const unsigned int scif3_ctrl_mux[] = {
3405 RTS3_N_MARK, CTS3_N_MARK,
3407 static const unsigned int scif3_data_b_pins[] = {
3409 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3411 static const unsigned int scif3_data_b_mux[] = {
3412 RX3_B_MARK, TX3_B_MARK,
3414 /* - SCIF4 ------------------------------------------------------------------ */
3415 static const unsigned int scif4_data_a_pins[] = {
3417 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3419 static const unsigned int scif4_data_a_mux[] = {
3420 RX4_A_MARK, TX4_A_MARK,
3422 static const unsigned int scif4_clk_a_pins[] = {
3426 static const unsigned int scif4_clk_a_mux[] = {
3429 static const unsigned int scif4_ctrl_a_pins[] = {
3431 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3433 static const unsigned int scif4_ctrl_a_mux[] = {
3434 RTS4_N_A_MARK, CTS4_N_A_MARK,
3436 static const unsigned int scif4_data_b_pins[] = {
3438 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3440 static const unsigned int scif4_data_b_mux[] = {
3441 RX4_B_MARK, TX4_B_MARK,
3443 static const unsigned int scif4_clk_b_pins[] = {
3447 static const unsigned int scif4_clk_b_mux[] = {
3450 static const unsigned int scif4_ctrl_b_pins[] = {
3452 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3454 static const unsigned int scif4_ctrl_b_mux[] = {
3455 RTS4_N_B_MARK, CTS4_N_B_MARK,
3457 static const unsigned int scif4_data_c_pins[] = {
3459 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3461 static const unsigned int scif4_data_c_mux[] = {
3462 RX4_C_MARK, TX4_C_MARK,
3464 static const unsigned int scif4_clk_c_pins[] = {
3468 static const unsigned int scif4_clk_c_mux[] = {
3471 static const unsigned int scif4_ctrl_c_pins[] = {
3473 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3475 static const unsigned int scif4_ctrl_c_mux[] = {
3476 RTS4_N_C_MARK, CTS4_N_C_MARK,
3478 /* - SCIF5 ------------------------------------------------------------------ */
3479 static const unsigned int scif5_data_a_pins[] = {
3481 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3483 static const unsigned int scif5_data_a_mux[] = {
3484 RX5_A_MARK, TX5_A_MARK,
3486 static const unsigned int scif5_clk_a_pins[] = {
3490 static const unsigned int scif5_clk_a_mux[] = {
3494 static const unsigned int scif5_data_b_pins[] = {
3496 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3498 static const unsigned int scif5_data_b_mux[] = {
3499 RX5_B_MARK, TX5_B_MARK,
3501 static const unsigned int scif5_clk_b_pins[] = {
3505 static const unsigned int scif5_clk_b_mux[] = {
3509 /* - SCIF Clock ------------------------------------------------------------- */
3510 static const unsigned int scif_clk_a_pins[] = {
3514 static const unsigned int scif_clk_a_mux[] = {
3517 static const unsigned int scif_clk_b_pins[] = {
3521 static const unsigned int scif_clk_b_mux[] = {
3525 /* - SDHI0 ------------------------------------------------------------------ */
3526 static const unsigned int sdhi0_data1_pins[] = {
3530 static const unsigned int sdhi0_data1_mux[] = {
3533 static const unsigned int sdhi0_data4_pins[] = {
3535 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3536 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3538 static const unsigned int sdhi0_data4_mux[] = {
3539 SD0_DAT0_MARK, SD0_DAT1_MARK,
3540 SD0_DAT2_MARK, SD0_DAT3_MARK,
3542 static const unsigned int sdhi0_ctrl_pins[] = {
3544 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3546 static const unsigned int sdhi0_ctrl_mux[] = {
3547 SD0_CLK_MARK, SD0_CMD_MARK,
3549 static const unsigned int sdhi0_cd_pins[] = {
3553 static const unsigned int sdhi0_cd_mux[] = {
3556 static const unsigned int sdhi0_wp_pins[] = {
3560 static const unsigned int sdhi0_wp_mux[] = {
3563 /* - SDHI1 ------------------------------------------------------------------ */
3564 static const unsigned int sdhi1_data1_pins[] = {
3568 static const unsigned int sdhi1_data1_mux[] = {
3571 static const unsigned int sdhi1_data4_pins[] = {
3573 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3574 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3576 static const unsigned int sdhi1_data4_mux[] = {
3577 SD1_DAT0_MARK, SD1_DAT1_MARK,
3578 SD1_DAT2_MARK, SD1_DAT3_MARK,
3580 static const unsigned int sdhi1_ctrl_pins[] = {
3582 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3584 static const unsigned int sdhi1_ctrl_mux[] = {
3585 SD1_CLK_MARK, SD1_CMD_MARK,
3587 static const unsigned int sdhi1_cd_pins[] = {
3591 static const unsigned int sdhi1_cd_mux[] = {
3594 static const unsigned int sdhi1_wp_pins[] = {
3598 static const unsigned int sdhi1_wp_mux[] = {
3601 /* - SDHI2 ------------------------------------------------------------------ */
3602 static const unsigned int sdhi2_data1_pins[] = {
3606 static const unsigned int sdhi2_data1_mux[] = {
3609 static const unsigned int sdhi2_data4_pins[] = {
3611 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3612 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3614 static const unsigned int sdhi2_data4_mux[] = {
3615 SD2_DAT0_MARK, SD2_DAT1_MARK,
3616 SD2_DAT2_MARK, SD2_DAT3_MARK,
3618 static const unsigned int sdhi2_data8_pins[] = {
3620 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3621 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3622 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3623 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3625 static const unsigned int sdhi2_data8_mux[] = {
3626 SD2_DAT0_MARK, SD2_DAT1_MARK,
3627 SD2_DAT2_MARK, SD2_DAT3_MARK,
3628 SD2_DAT4_MARK, SD2_DAT5_MARK,
3629 SD2_DAT6_MARK, SD2_DAT7_MARK,
3631 static const unsigned int sdhi2_ctrl_pins[] = {
3633 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3635 static const unsigned int sdhi2_ctrl_mux[] = {
3636 SD2_CLK_MARK, SD2_CMD_MARK,
3638 static const unsigned int sdhi2_cd_a_pins[] = {
3642 static const unsigned int sdhi2_cd_a_mux[] = {
3645 static const unsigned int sdhi2_cd_b_pins[] = {
3649 static const unsigned int sdhi2_cd_b_mux[] = {
3652 static const unsigned int sdhi2_wp_a_pins[] = {
3656 static const unsigned int sdhi2_wp_a_mux[] = {
3659 static const unsigned int sdhi2_wp_b_pins[] = {
3663 static const unsigned int sdhi2_wp_b_mux[] = {
3666 static const unsigned int sdhi2_ds_pins[] = {
3670 static const unsigned int sdhi2_ds_mux[] = {
3673 /* - SDHI3 ------------------------------------------------------------------ */
3674 static const unsigned int sdhi3_data1_pins[] = {
3678 static const unsigned int sdhi3_data1_mux[] = {
3681 static const unsigned int sdhi3_data4_pins[] = {
3683 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3684 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3686 static const unsigned int sdhi3_data4_mux[] = {
3687 SD3_DAT0_MARK, SD3_DAT1_MARK,
3688 SD3_DAT2_MARK, SD3_DAT3_MARK,
3690 static const unsigned int sdhi3_data8_pins[] = {
3692 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3693 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3694 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3695 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3697 static const unsigned int sdhi3_data8_mux[] = {
3698 SD3_DAT0_MARK, SD3_DAT1_MARK,
3699 SD3_DAT2_MARK, SD3_DAT3_MARK,
3700 SD3_DAT4_MARK, SD3_DAT5_MARK,
3701 SD3_DAT6_MARK, SD3_DAT7_MARK,
3703 static const unsigned int sdhi3_ctrl_pins[] = {
3705 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3707 static const unsigned int sdhi3_ctrl_mux[] = {
3708 SD3_CLK_MARK, SD3_CMD_MARK,
3710 static const unsigned int sdhi3_cd_pins[] = {
3714 static const unsigned int sdhi3_cd_mux[] = {
3717 static const unsigned int sdhi3_wp_pins[] = {
3721 static const unsigned int sdhi3_wp_mux[] = {
3724 static const unsigned int sdhi3_ds_pins[] = {
3728 static const unsigned int sdhi3_ds_mux[] = {
3732 /* - SSI -------------------------------------------------------------------- */
3733 static const unsigned int ssi0_data_pins[] = {
3737 static const unsigned int ssi0_data_mux[] = {
3740 static const unsigned int ssi01239_ctrl_pins[] = {
3742 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3744 static const unsigned int ssi01239_ctrl_mux[] = {
3745 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3747 static const unsigned int ssi1_data_a_pins[] = {
3751 static const unsigned int ssi1_data_a_mux[] = {
3754 static const unsigned int ssi1_data_b_pins[] = {
3758 static const unsigned int ssi1_data_b_mux[] = {
3761 static const unsigned int ssi1_ctrl_a_pins[] = {
3763 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3765 static const unsigned int ssi1_ctrl_a_mux[] = {
3766 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3768 static const unsigned int ssi1_ctrl_b_pins[] = {
3770 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3772 static const unsigned int ssi1_ctrl_b_mux[] = {
3773 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3775 static const unsigned int ssi2_data_a_pins[] = {
3779 static const unsigned int ssi2_data_a_mux[] = {
3782 static const unsigned int ssi2_data_b_pins[] = {
3786 static const unsigned int ssi2_data_b_mux[] = {
3789 static const unsigned int ssi2_ctrl_a_pins[] = {
3791 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3793 static const unsigned int ssi2_ctrl_a_mux[] = {
3794 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3796 static const unsigned int ssi2_ctrl_b_pins[] = {
3798 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3800 static const unsigned int ssi2_ctrl_b_mux[] = {
3801 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3803 static const unsigned int ssi3_data_pins[] = {
3807 static const unsigned int ssi3_data_mux[] = {
3810 static const unsigned int ssi349_ctrl_pins[] = {
3812 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3814 static const unsigned int ssi349_ctrl_mux[] = {
3815 SSI_SCK349_MARK, SSI_WS349_MARK,
3817 static const unsigned int ssi4_data_pins[] = {
3821 static const unsigned int ssi4_data_mux[] = {
3824 static const unsigned int ssi4_ctrl_pins[] = {
3826 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3828 static const unsigned int ssi4_ctrl_mux[] = {
3829 SSI_SCK4_MARK, SSI_WS4_MARK,
3831 static const unsigned int ssi5_data_pins[] = {
3835 static const unsigned int ssi5_data_mux[] = {
3838 static const unsigned int ssi5_ctrl_pins[] = {
3840 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3842 static const unsigned int ssi5_ctrl_mux[] = {
3843 SSI_SCK5_MARK, SSI_WS5_MARK,
3845 static const unsigned int ssi6_data_pins[] = {
3849 static const unsigned int ssi6_data_mux[] = {
3852 static const unsigned int ssi6_ctrl_pins[] = {
3854 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3856 static const unsigned int ssi6_ctrl_mux[] = {
3857 SSI_SCK6_MARK, SSI_WS6_MARK,
3859 static const unsigned int ssi7_data_pins[] = {
3863 static const unsigned int ssi7_data_mux[] = {
3866 static const unsigned int ssi78_ctrl_pins[] = {
3868 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3870 static const unsigned int ssi78_ctrl_mux[] = {
3871 SSI_SCK78_MARK, SSI_WS78_MARK,
3873 static const unsigned int ssi8_data_pins[] = {
3877 static const unsigned int ssi8_data_mux[] = {
3880 static const unsigned int ssi9_data_a_pins[] = {
3884 static const unsigned int ssi9_data_a_mux[] = {
3887 static const unsigned int ssi9_data_b_pins[] = {
3891 static const unsigned int ssi9_data_b_mux[] = {
3894 static const unsigned int ssi9_ctrl_a_pins[] = {
3896 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3898 static const unsigned int ssi9_ctrl_a_mux[] = {
3899 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3901 static const unsigned int ssi9_ctrl_b_pins[] = {
3903 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3905 static const unsigned int ssi9_ctrl_b_mux[] = {
3906 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3909 /* - TMU -------------------------------------------------------------------- */
3910 static const unsigned int tmu_tclk1_a_pins[] = {
3914 static const unsigned int tmu_tclk1_a_mux[] = {
3917 static const unsigned int tmu_tclk1_b_pins[] = {
3921 static const unsigned int tmu_tclk1_b_mux[] = {
3924 static const unsigned int tmu_tclk2_a_pins[] = {
3928 static const unsigned int tmu_tclk2_a_mux[] = {
3931 static const unsigned int tmu_tclk2_b_pins[] = {
3935 static const unsigned int tmu_tclk2_b_mux[] = {
3939 /* - TPU ------------------------------------------------------------------- */
3940 static const unsigned int tpu_to0_pins[] = {
3944 static const unsigned int tpu_to0_mux[] = {
3947 static const unsigned int tpu_to1_pins[] = {
3951 static const unsigned int tpu_to1_mux[] = {
3954 static const unsigned int tpu_to2_pins[] = {
3958 static const unsigned int tpu_to2_mux[] = {
3961 static const unsigned int tpu_to3_pins[] = {
3965 static const unsigned int tpu_to3_mux[] = {
3969 /* - USB0 ------------------------------------------------------------------- */
3970 static const unsigned int usb0_pins[] = {
3972 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3974 static const unsigned int usb0_mux[] = {
3975 USB0_PWEN_MARK, USB0_OVC_MARK,
3977 /* - USB1 ------------------------------------------------------------------- */
3978 static const unsigned int usb1_pins[] = {
3980 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3982 static const unsigned int usb1_mux[] = {
3983 USB1_PWEN_MARK, USB1_OVC_MARK,
3986 /* - USB30 ------------------------------------------------------------------ */
3987 static const unsigned int usb30_pins[] = {
3989 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3991 static const unsigned int usb30_mux[] = {
3992 USB30_PWEN_MARK, USB30_OVC_MARK,
3995 /* - VIN4 ------------------------------------------------------------------- */
3996 static const unsigned int vin4_data18_a_pins[] = {
3997 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3998 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3999 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4000 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4001 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4002 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4003 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4004 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4005 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4007 static const unsigned int vin4_data18_a_mux[] = {
4008 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4009 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4010 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4011 VI4_DATA10_MARK, VI4_DATA11_MARK,
4012 VI4_DATA12_MARK, VI4_DATA13_MARK,
4013 VI4_DATA14_MARK, VI4_DATA15_MARK,
4014 VI4_DATA18_MARK, VI4_DATA19_MARK,
4015 VI4_DATA20_MARK, VI4_DATA21_MARK,
4016 VI4_DATA22_MARK, VI4_DATA23_MARK,
4018 static const unsigned int vin4_data18_b_pins[] = {
4019 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4020 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4021 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4022 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4023 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4024 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4025 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4026 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4027 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4029 static const unsigned int vin4_data18_b_mux[] = {
4030 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4031 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4032 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4033 VI4_DATA10_MARK, VI4_DATA11_MARK,
4034 VI4_DATA12_MARK, VI4_DATA13_MARK,
4035 VI4_DATA14_MARK, VI4_DATA15_MARK,
4036 VI4_DATA18_MARK, VI4_DATA19_MARK,
4037 VI4_DATA20_MARK, VI4_DATA21_MARK,
4038 VI4_DATA22_MARK, VI4_DATA23_MARK,
4040 static const union vin_data vin4_data_a_pins = {
4042 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4043 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4044 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4045 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4046 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4047 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4048 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4049 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4050 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4051 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4052 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4053 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4056 static const union vin_data vin4_data_a_mux = {
4058 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4059 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4060 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4061 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4062 VI4_DATA8_MARK, VI4_DATA9_MARK,
4063 VI4_DATA10_MARK, VI4_DATA11_MARK,
4064 VI4_DATA12_MARK, VI4_DATA13_MARK,
4065 VI4_DATA14_MARK, VI4_DATA15_MARK,
4066 VI4_DATA16_MARK, VI4_DATA17_MARK,
4067 VI4_DATA18_MARK, VI4_DATA19_MARK,
4068 VI4_DATA20_MARK, VI4_DATA21_MARK,
4069 VI4_DATA22_MARK, VI4_DATA23_MARK,
4072 static const union vin_data vin4_data_b_pins = {
4074 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4075 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4076 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4077 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4078 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4079 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4080 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4081 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4082 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4083 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4084 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4085 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4088 static const union vin_data vin4_data_b_mux = {
4090 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4091 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4092 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4093 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4094 VI4_DATA8_MARK, VI4_DATA9_MARK,
4095 VI4_DATA10_MARK, VI4_DATA11_MARK,
4096 VI4_DATA12_MARK, VI4_DATA13_MARK,
4097 VI4_DATA14_MARK, VI4_DATA15_MARK,
4098 VI4_DATA16_MARK, VI4_DATA17_MARK,
4099 VI4_DATA18_MARK, VI4_DATA19_MARK,
4100 VI4_DATA20_MARK, VI4_DATA21_MARK,
4101 VI4_DATA22_MARK, VI4_DATA23_MARK,
4104 static const unsigned int vin4_sync_pins[] = {
4105 /* HSYNC#, VSYNC# */
4106 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4108 static const unsigned int vin4_sync_mux[] = {
4109 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4111 static const unsigned int vin4_field_pins[] = {
4115 static const unsigned int vin4_field_mux[] = {
4118 static const unsigned int vin4_clkenb_pins[] = {
4122 static const unsigned int vin4_clkenb_mux[] = {
4125 static const unsigned int vin4_clk_pins[] = {
4129 static const unsigned int vin4_clk_mux[] = {
4133 /* - VIN5 ------------------------------------------------------------------- */
4134 static const union vin_data16 vin5_data_pins = {
4136 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4137 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4138 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4139 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4140 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4141 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4142 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4143 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4146 static const union vin_data16 vin5_data_mux = {
4148 VI5_DATA0_MARK, VI5_DATA1_MARK,
4149 VI5_DATA2_MARK, VI5_DATA3_MARK,
4150 VI5_DATA4_MARK, VI5_DATA5_MARK,
4151 VI5_DATA6_MARK, VI5_DATA7_MARK,
4152 VI5_DATA8_MARK, VI5_DATA9_MARK,
4153 VI5_DATA10_MARK, VI5_DATA11_MARK,
4154 VI5_DATA12_MARK, VI5_DATA13_MARK,
4155 VI5_DATA14_MARK, VI5_DATA15_MARK,
4158 static const unsigned int vin5_sync_pins[] = {
4159 /* HSYNC#, VSYNC# */
4160 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4162 static const unsigned int vin5_sync_mux[] = {
4163 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4165 static const unsigned int vin5_field_pins[] = {
4168 static const unsigned int vin5_field_mux[] = {
4172 static const unsigned int vin5_clkenb_pins[] = {
4175 static const unsigned int vin5_clkenb_mux[] = {
4179 static const unsigned int vin5_clk_pins[] = {
4182 static const unsigned int vin5_clk_mux[] = {
4187 static const struct {
4188 struct sh_pfc_pin_group common[322];
4189 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4190 struct sh_pfc_pin_group automotive[30];
4194 SH_PFC_PIN_GROUP(audio_clk_a_a),
4195 SH_PFC_PIN_GROUP(audio_clk_a_b),
4196 SH_PFC_PIN_GROUP(audio_clk_a_c),
4197 SH_PFC_PIN_GROUP(audio_clk_b_a),
4198 SH_PFC_PIN_GROUP(audio_clk_b_b),
4199 SH_PFC_PIN_GROUP(audio_clk_c_a),
4200 SH_PFC_PIN_GROUP(audio_clk_c_b),
4201 SH_PFC_PIN_GROUP(audio_clkout_a),
4202 SH_PFC_PIN_GROUP(audio_clkout_b),
4203 SH_PFC_PIN_GROUP(audio_clkout_c),
4204 SH_PFC_PIN_GROUP(audio_clkout_d),
4205 SH_PFC_PIN_GROUP(audio_clkout1_a),
4206 SH_PFC_PIN_GROUP(audio_clkout1_b),
4207 SH_PFC_PIN_GROUP(audio_clkout2_a),
4208 SH_PFC_PIN_GROUP(audio_clkout2_b),
4209 SH_PFC_PIN_GROUP(audio_clkout3_a),
4210 SH_PFC_PIN_GROUP(audio_clkout3_b),
4211 SH_PFC_PIN_GROUP(avb_link),
4212 SH_PFC_PIN_GROUP(avb_magic),
4213 SH_PFC_PIN_GROUP(avb_phy_int),
4214 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4215 SH_PFC_PIN_GROUP(avb_mdio),
4216 SH_PFC_PIN_GROUP(avb_mii),
4217 SH_PFC_PIN_GROUP(avb_avtp_pps),
4218 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4219 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4220 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4221 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4222 SH_PFC_PIN_GROUP(can0_data_a),
4223 SH_PFC_PIN_GROUP(can0_data_b),
4224 SH_PFC_PIN_GROUP(can1_data),
4225 SH_PFC_PIN_GROUP(can_clk),
4226 SH_PFC_PIN_GROUP(canfd0_data_a),
4227 SH_PFC_PIN_GROUP(canfd0_data_b),
4228 SH_PFC_PIN_GROUP(canfd1_data),
4229 SH_PFC_PIN_GROUP(du_rgb666),
4230 SH_PFC_PIN_GROUP(du_rgb888),
4231 SH_PFC_PIN_GROUP(du_clk_out_0),
4232 SH_PFC_PIN_GROUP(du_clk_out_1),
4233 SH_PFC_PIN_GROUP(du_sync),
4234 SH_PFC_PIN_GROUP(du_oddf),
4235 SH_PFC_PIN_GROUP(du_cde),
4236 SH_PFC_PIN_GROUP(du_disp),
4237 SH_PFC_PIN_GROUP(hscif0_data),
4238 SH_PFC_PIN_GROUP(hscif0_clk),
4239 SH_PFC_PIN_GROUP(hscif0_ctrl),
4240 SH_PFC_PIN_GROUP(hscif1_data_a),
4241 SH_PFC_PIN_GROUP(hscif1_clk_a),
4242 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4243 SH_PFC_PIN_GROUP(hscif1_data_b),
4244 SH_PFC_PIN_GROUP(hscif1_clk_b),
4245 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4246 SH_PFC_PIN_GROUP(hscif2_data_a),
4247 SH_PFC_PIN_GROUP(hscif2_clk_a),
4248 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4249 SH_PFC_PIN_GROUP(hscif2_data_b),
4250 SH_PFC_PIN_GROUP(hscif2_clk_b),
4251 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4252 SH_PFC_PIN_GROUP(hscif2_data_c),
4253 SH_PFC_PIN_GROUP(hscif2_clk_c),
4254 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4255 SH_PFC_PIN_GROUP(hscif3_data_a),
4256 SH_PFC_PIN_GROUP(hscif3_clk),
4257 SH_PFC_PIN_GROUP(hscif3_ctrl),
4258 SH_PFC_PIN_GROUP(hscif3_data_b),
4259 SH_PFC_PIN_GROUP(hscif3_data_c),
4260 SH_PFC_PIN_GROUP(hscif3_data_d),
4261 SH_PFC_PIN_GROUP(hscif4_data_a),
4262 SH_PFC_PIN_GROUP(hscif4_clk),
4263 SH_PFC_PIN_GROUP(hscif4_ctrl),
4264 SH_PFC_PIN_GROUP(hscif4_data_b),
4265 SH_PFC_PIN_GROUP(i2c0),
4266 SH_PFC_PIN_GROUP(i2c1_a),
4267 SH_PFC_PIN_GROUP(i2c1_b),
4268 SH_PFC_PIN_GROUP(i2c2_a),
4269 SH_PFC_PIN_GROUP(i2c2_b),
4270 SH_PFC_PIN_GROUP(i2c3),
4271 SH_PFC_PIN_GROUP(i2c5),
4272 SH_PFC_PIN_GROUP(i2c6_a),
4273 SH_PFC_PIN_GROUP(i2c6_b),
4274 SH_PFC_PIN_GROUP(i2c6_c),
4275 SH_PFC_PIN_GROUP(intc_ex_irq0),
4276 SH_PFC_PIN_GROUP(intc_ex_irq1),
4277 SH_PFC_PIN_GROUP(intc_ex_irq2),
4278 SH_PFC_PIN_GROUP(intc_ex_irq3),
4279 SH_PFC_PIN_GROUP(intc_ex_irq4),
4280 SH_PFC_PIN_GROUP(intc_ex_irq5),
4281 SH_PFC_PIN_GROUP(msiof0_clk),
4282 SH_PFC_PIN_GROUP(msiof0_sync),
4283 SH_PFC_PIN_GROUP(msiof0_ss1),
4284 SH_PFC_PIN_GROUP(msiof0_ss2),
4285 SH_PFC_PIN_GROUP(msiof0_txd),
4286 SH_PFC_PIN_GROUP(msiof0_rxd),
4287 SH_PFC_PIN_GROUP(msiof1_clk_a),
4288 SH_PFC_PIN_GROUP(msiof1_sync_a),
4289 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4290 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4291 SH_PFC_PIN_GROUP(msiof1_txd_a),
4292 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4293 SH_PFC_PIN_GROUP(msiof1_clk_b),
4294 SH_PFC_PIN_GROUP(msiof1_sync_b),
4295 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4296 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4297 SH_PFC_PIN_GROUP(msiof1_txd_b),
4298 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4299 SH_PFC_PIN_GROUP(msiof1_clk_c),
4300 SH_PFC_PIN_GROUP(msiof1_sync_c),
4301 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4302 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4303 SH_PFC_PIN_GROUP(msiof1_txd_c),
4304 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4305 SH_PFC_PIN_GROUP(msiof1_clk_d),
4306 SH_PFC_PIN_GROUP(msiof1_sync_d),
4307 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4308 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4309 SH_PFC_PIN_GROUP(msiof1_txd_d),
4310 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4311 SH_PFC_PIN_GROUP(msiof1_clk_e),
4312 SH_PFC_PIN_GROUP(msiof1_sync_e),
4313 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4314 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4315 SH_PFC_PIN_GROUP(msiof1_txd_e),
4316 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4317 SH_PFC_PIN_GROUP(msiof1_clk_f),
4318 SH_PFC_PIN_GROUP(msiof1_sync_f),
4319 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4320 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4321 SH_PFC_PIN_GROUP(msiof1_txd_f),
4322 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4323 SH_PFC_PIN_GROUP(msiof1_clk_g),
4324 SH_PFC_PIN_GROUP(msiof1_sync_g),
4325 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4326 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4327 SH_PFC_PIN_GROUP(msiof1_txd_g),
4328 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4329 SH_PFC_PIN_GROUP(msiof2_clk_a),
4330 SH_PFC_PIN_GROUP(msiof2_sync_a),
4331 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4332 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4333 SH_PFC_PIN_GROUP(msiof2_txd_a),
4334 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4335 SH_PFC_PIN_GROUP(msiof2_clk_b),
4336 SH_PFC_PIN_GROUP(msiof2_sync_b),
4337 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4338 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4339 SH_PFC_PIN_GROUP(msiof2_txd_b),
4340 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4341 SH_PFC_PIN_GROUP(msiof2_clk_c),
4342 SH_PFC_PIN_GROUP(msiof2_sync_c),
4343 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4344 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4345 SH_PFC_PIN_GROUP(msiof2_txd_c),
4346 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4347 SH_PFC_PIN_GROUP(msiof2_clk_d),
4348 SH_PFC_PIN_GROUP(msiof2_sync_d),
4349 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4350 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4351 SH_PFC_PIN_GROUP(msiof2_txd_d),
4352 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4353 SH_PFC_PIN_GROUP(msiof3_clk_a),
4354 SH_PFC_PIN_GROUP(msiof3_sync_a),
4355 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4356 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4357 SH_PFC_PIN_GROUP(msiof3_txd_a),
4358 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4359 SH_PFC_PIN_GROUP(msiof3_clk_b),
4360 SH_PFC_PIN_GROUP(msiof3_sync_b),
4361 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4362 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4363 SH_PFC_PIN_GROUP(msiof3_txd_b),
4364 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4365 SH_PFC_PIN_GROUP(msiof3_clk_c),
4366 SH_PFC_PIN_GROUP(msiof3_sync_c),
4367 SH_PFC_PIN_GROUP(msiof3_txd_c),
4368 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4369 SH_PFC_PIN_GROUP(msiof3_clk_d),
4370 SH_PFC_PIN_GROUP(msiof3_sync_d),
4371 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4372 SH_PFC_PIN_GROUP(msiof3_txd_d),
4373 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4374 SH_PFC_PIN_GROUP(msiof3_clk_e),
4375 SH_PFC_PIN_GROUP(msiof3_sync_e),
4376 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4377 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4378 SH_PFC_PIN_GROUP(msiof3_txd_e),
4379 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4380 SH_PFC_PIN_GROUP(pwm0),
4381 SH_PFC_PIN_GROUP(pwm1_a),
4382 SH_PFC_PIN_GROUP(pwm1_b),
4383 SH_PFC_PIN_GROUP(pwm2_a),
4384 SH_PFC_PIN_GROUP(pwm2_b),
4385 SH_PFC_PIN_GROUP(pwm3_a),
4386 SH_PFC_PIN_GROUP(pwm3_b),
4387 SH_PFC_PIN_GROUP(pwm4_a),
4388 SH_PFC_PIN_GROUP(pwm4_b),
4389 SH_PFC_PIN_GROUP(pwm5_a),
4390 SH_PFC_PIN_GROUP(pwm5_b),
4391 SH_PFC_PIN_GROUP(pwm6_a),
4392 SH_PFC_PIN_GROUP(pwm6_b),
4393 SH_PFC_PIN_GROUP(qspi0_ctrl),
4394 SH_PFC_PIN_GROUP(qspi0_data2),
4395 SH_PFC_PIN_GROUP(qspi0_data4),
4396 SH_PFC_PIN_GROUP(qspi1_ctrl),
4397 SH_PFC_PIN_GROUP(qspi1_data2),
4398 SH_PFC_PIN_GROUP(qspi1_data4),
4399 SH_PFC_PIN_GROUP(scif0_data),
4400 SH_PFC_PIN_GROUP(scif0_clk),
4401 SH_PFC_PIN_GROUP(scif0_ctrl),
4402 SH_PFC_PIN_GROUP(scif1_data_a),
4403 SH_PFC_PIN_GROUP(scif1_clk),
4404 SH_PFC_PIN_GROUP(scif1_ctrl),
4405 SH_PFC_PIN_GROUP(scif1_data_b),
4406 SH_PFC_PIN_GROUP(scif2_data_a),
4407 SH_PFC_PIN_GROUP(scif2_clk),
4408 SH_PFC_PIN_GROUP(scif2_data_b),
4409 SH_PFC_PIN_GROUP(scif3_data_a),
4410 SH_PFC_PIN_GROUP(scif3_clk),
4411 SH_PFC_PIN_GROUP(scif3_ctrl),
4412 SH_PFC_PIN_GROUP(scif3_data_b),
4413 SH_PFC_PIN_GROUP(scif4_data_a),
4414 SH_PFC_PIN_GROUP(scif4_clk_a),
4415 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4416 SH_PFC_PIN_GROUP(scif4_data_b),
4417 SH_PFC_PIN_GROUP(scif4_clk_b),
4418 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4419 SH_PFC_PIN_GROUP(scif4_data_c),
4420 SH_PFC_PIN_GROUP(scif4_clk_c),
4421 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4422 SH_PFC_PIN_GROUP(scif5_data_a),
4423 SH_PFC_PIN_GROUP(scif5_clk_a),
4424 SH_PFC_PIN_GROUP(scif5_data_b),
4425 SH_PFC_PIN_GROUP(scif5_clk_b),
4426 SH_PFC_PIN_GROUP(scif_clk_a),
4427 SH_PFC_PIN_GROUP(scif_clk_b),
4428 SH_PFC_PIN_GROUP(sdhi0_data1),
4429 SH_PFC_PIN_GROUP(sdhi0_data4),
4430 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4431 SH_PFC_PIN_GROUP(sdhi0_cd),
4432 SH_PFC_PIN_GROUP(sdhi0_wp),
4433 SH_PFC_PIN_GROUP(sdhi1_data1),
4434 SH_PFC_PIN_GROUP(sdhi1_data4),
4435 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4436 SH_PFC_PIN_GROUP(sdhi1_cd),
4437 SH_PFC_PIN_GROUP(sdhi1_wp),
4438 SH_PFC_PIN_GROUP(sdhi2_data1),
4439 SH_PFC_PIN_GROUP(sdhi2_data4),
4440 SH_PFC_PIN_GROUP(sdhi2_data8),
4441 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4442 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4443 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4444 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4445 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4446 SH_PFC_PIN_GROUP(sdhi2_ds),
4447 SH_PFC_PIN_GROUP(sdhi3_data1),
4448 SH_PFC_PIN_GROUP(sdhi3_data4),
4449 SH_PFC_PIN_GROUP(sdhi3_data8),
4450 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4451 SH_PFC_PIN_GROUP(sdhi3_cd),
4452 SH_PFC_PIN_GROUP(sdhi3_wp),
4453 SH_PFC_PIN_GROUP(sdhi3_ds),
4454 SH_PFC_PIN_GROUP(ssi0_data),
4455 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4456 SH_PFC_PIN_GROUP(ssi1_data_a),
4457 SH_PFC_PIN_GROUP(ssi1_data_b),
4458 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4459 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4460 SH_PFC_PIN_GROUP(ssi2_data_a),
4461 SH_PFC_PIN_GROUP(ssi2_data_b),
4462 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4463 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4464 SH_PFC_PIN_GROUP(ssi3_data),
4465 SH_PFC_PIN_GROUP(ssi349_ctrl),
4466 SH_PFC_PIN_GROUP(ssi4_data),
4467 SH_PFC_PIN_GROUP(ssi4_ctrl),
4468 SH_PFC_PIN_GROUP(ssi5_data),
4469 SH_PFC_PIN_GROUP(ssi5_ctrl),
4470 SH_PFC_PIN_GROUP(ssi6_data),
4471 SH_PFC_PIN_GROUP(ssi6_ctrl),
4472 SH_PFC_PIN_GROUP(ssi7_data),
4473 SH_PFC_PIN_GROUP(ssi78_ctrl),
4474 SH_PFC_PIN_GROUP(ssi8_data),
4475 SH_PFC_PIN_GROUP(ssi9_data_a),
4476 SH_PFC_PIN_GROUP(ssi9_data_b),
4477 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4478 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4479 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4480 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4481 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4482 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4483 SH_PFC_PIN_GROUP(tpu_to0),
4484 SH_PFC_PIN_GROUP(tpu_to1),
4485 SH_PFC_PIN_GROUP(tpu_to2),
4486 SH_PFC_PIN_GROUP(tpu_to3),
4487 SH_PFC_PIN_GROUP(usb0),
4488 SH_PFC_PIN_GROUP(usb1),
4489 SH_PFC_PIN_GROUP(usb30),
4490 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4491 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4492 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4493 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4494 SH_PFC_PIN_GROUP(vin4_data18_a),
4495 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4496 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4497 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4498 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4499 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4500 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4501 SH_PFC_PIN_GROUP(vin4_data18_b),
4502 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4503 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4504 SH_PFC_PIN_GROUP(vin4_sync),
4505 SH_PFC_PIN_GROUP(vin4_field),
4506 SH_PFC_PIN_GROUP(vin4_clkenb),
4507 SH_PFC_PIN_GROUP(vin4_clk),
4508 VIN_DATA_PIN_GROUP(vin5_data, 8),
4509 VIN_DATA_PIN_GROUP(vin5_data, 10),
4510 VIN_DATA_PIN_GROUP(vin5_data, 12),
4511 VIN_DATA_PIN_GROUP(vin5_data, 16),
4512 SH_PFC_PIN_GROUP(vin5_sync),
4513 SH_PFC_PIN_GROUP(vin5_field),
4514 SH_PFC_PIN_GROUP(vin5_clkenb),
4515 SH_PFC_PIN_GROUP(vin5_clk),
4517 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4519 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4520 SH_PFC_PIN_GROUP(drif0_data0_a),
4521 SH_PFC_PIN_GROUP(drif0_data1_a),
4522 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4523 SH_PFC_PIN_GROUP(drif0_data0_b),
4524 SH_PFC_PIN_GROUP(drif0_data1_b),
4525 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4526 SH_PFC_PIN_GROUP(drif0_data0_c),
4527 SH_PFC_PIN_GROUP(drif0_data1_c),
4528 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4529 SH_PFC_PIN_GROUP(drif1_data0_a),
4530 SH_PFC_PIN_GROUP(drif1_data1_a),
4531 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4532 SH_PFC_PIN_GROUP(drif1_data0_b),
4533 SH_PFC_PIN_GROUP(drif1_data1_b),
4534 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4535 SH_PFC_PIN_GROUP(drif1_data0_c),
4536 SH_PFC_PIN_GROUP(drif1_data1_c),
4537 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4538 SH_PFC_PIN_GROUP(drif2_data0_a),
4539 SH_PFC_PIN_GROUP(drif2_data1_a),
4540 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4541 SH_PFC_PIN_GROUP(drif2_data0_b),
4542 SH_PFC_PIN_GROUP(drif2_data1_b),
4543 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4544 SH_PFC_PIN_GROUP(drif3_data0_a),
4545 SH_PFC_PIN_GROUP(drif3_data1_a),
4546 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4547 SH_PFC_PIN_GROUP(drif3_data0_b),
4548 SH_PFC_PIN_GROUP(drif3_data1_b),
4550 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4553 static const char * const audio_clk_groups[] = {
4573 static const char * const avb_groups[] = {
4577 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4582 "avb_avtp_capture_a",
4584 "avb_avtp_capture_b",
4587 static const char * const can0_groups[] = {
4592 static const char * const can1_groups[] = {
4596 static const char * const can_clk_groups[] = {
4600 static const char * const canfd0_groups[] = {
4605 static const char * const canfd1_groups[] = {
4609 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4610 static const char * const drif0_groups[] = {
4622 static const char * const drif1_groups[] = {
4634 static const char * const drif2_groups[] = {
4643 static const char * const drif3_groups[] = {
4651 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4653 static const char * const du_groups[] = {
4664 static const char * const hscif0_groups[] = {
4670 static const char * const hscif1_groups[] = {
4679 static const char * const hscif2_groups[] = {
4691 static const char * const hscif3_groups[] = {
4700 static const char * const hscif4_groups[] = {
4707 static const char * const i2c0_groups[] = {
4711 static const char * const i2c1_groups[] = {
4716 static const char * const i2c2_groups[] = {
4721 static const char * const i2c3_groups[] = {
4725 static const char * const i2c5_groups[] = {
4729 static const char * const i2c6_groups[] = {
4735 static const char * const intc_ex_groups[] = {
4744 static const char * const msiof0_groups[] = {
4753 static const char * const msiof1_groups[] = {
4798 static const char * const msiof2_groups[] = {
4825 static const char * const msiof3_groups[] = {
4855 static const char * const pwm0_groups[] = {
4859 static const char * const pwm1_groups[] = {
4864 static const char * const pwm2_groups[] = {
4869 static const char * const pwm3_groups[] = {
4874 static const char * const pwm4_groups[] = {
4879 static const char * const pwm5_groups[] = {
4884 static const char * const pwm6_groups[] = {
4889 static const char * const qspi0_groups[] = {
4895 static const char * const qspi1_groups[] = {
4901 static const char * const scif0_groups[] = {
4907 static const char * const scif1_groups[] = {
4914 static const char * const scif2_groups[] = {
4920 static const char * const scif3_groups[] = {
4927 static const char * const scif4_groups[] = {
4939 static const char * const scif5_groups[] = {
4946 static const char * const scif_clk_groups[] = {
4951 static const char * const sdhi0_groups[] = {
4959 static const char * const sdhi1_groups[] = {
4967 static const char * const sdhi2_groups[] = {
4979 static const char * const sdhi3_groups[] = {
4989 static const char * const ssi_groups[] = {
5017 static const char * const tmu_groups[] = {
5024 static const char * const tpu_groups[] = {
5031 static const char * const usb0_groups[] = {
5035 static const char * const usb1_groups[] = {
5039 static const char * const usb30_groups[] = {
5043 static const char * const vin4_groups[] = {
5064 static const char * const vin5_groups[] = {
5075 static const struct {
5076 struct sh_pfc_function common[52];
5077 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5078 struct sh_pfc_function automotive[4];
5080 } pinmux_functions = {
5082 SH_PFC_FUNCTION(audio_clk),
5083 SH_PFC_FUNCTION(avb),
5084 SH_PFC_FUNCTION(can0),
5085 SH_PFC_FUNCTION(can1),
5086 SH_PFC_FUNCTION(can_clk),
5087 SH_PFC_FUNCTION(canfd0),
5088 SH_PFC_FUNCTION(canfd1),
5089 SH_PFC_FUNCTION(du),
5090 SH_PFC_FUNCTION(hscif0),
5091 SH_PFC_FUNCTION(hscif1),
5092 SH_PFC_FUNCTION(hscif2),
5093 SH_PFC_FUNCTION(hscif3),
5094 SH_PFC_FUNCTION(hscif4),
5095 SH_PFC_FUNCTION(i2c0),
5096 SH_PFC_FUNCTION(i2c1),
5097 SH_PFC_FUNCTION(i2c2),
5098 SH_PFC_FUNCTION(i2c3),
5099 SH_PFC_FUNCTION(i2c5),
5100 SH_PFC_FUNCTION(i2c6),
5101 SH_PFC_FUNCTION(intc_ex),
5102 SH_PFC_FUNCTION(msiof0),
5103 SH_PFC_FUNCTION(msiof1),
5104 SH_PFC_FUNCTION(msiof2),
5105 SH_PFC_FUNCTION(msiof3),
5106 SH_PFC_FUNCTION(pwm0),
5107 SH_PFC_FUNCTION(pwm1),
5108 SH_PFC_FUNCTION(pwm2),
5109 SH_PFC_FUNCTION(pwm3),
5110 SH_PFC_FUNCTION(pwm4),
5111 SH_PFC_FUNCTION(pwm5),
5112 SH_PFC_FUNCTION(pwm6),
5113 SH_PFC_FUNCTION(qspi0),
5114 SH_PFC_FUNCTION(qspi1),
5115 SH_PFC_FUNCTION(scif0),
5116 SH_PFC_FUNCTION(scif1),
5117 SH_PFC_FUNCTION(scif2),
5118 SH_PFC_FUNCTION(scif3),
5119 SH_PFC_FUNCTION(scif4),
5120 SH_PFC_FUNCTION(scif5),
5121 SH_PFC_FUNCTION(scif_clk),
5122 SH_PFC_FUNCTION(sdhi0),
5123 SH_PFC_FUNCTION(sdhi1),
5124 SH_PFC_FUNCTION(sdhi2),
5125 SH_PFC_FUNCTION(sdhi3),
5126 SH_PFC_FUNCTION(ssi),
5127 SH_PFC_FUNCTION(tmu),
5128 SH_PFC_FUNCTION(tpu),
5129 SH_PFC_FUNCTION(usb0),
5130 SH_PFC_FUNCTION(usb1),
5131 SH_PFC_FUNCTION(usb30),
5132 SH_PFC_FUNCTION(vin4),
5133 SH_PFC_FUNCTION(vin5),
5135 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5137 SH_PFC_FUNCTION(drif0),
5138 SH_PFC_FUNCTION(drif1),
5139 SH_PFC_FUNCTION(drif2),
5140 SH_PFC_FUNCTION(drif3),
5142 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
5145 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5146 #define F_(x, y) FN_##y
5147 #define FM(x) FN_##x
5148 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
5165 GP_0_15_FN, GPSR0_15,
5166 GP_0_14_FN, GPSR0_14,
5167 GP_0_13_FN, GPSR0_13,
5168 GP_0_12_FN, GPSR0_12,
5169 GP_0_11_FN, GPSR0_11,
5170 GP_0_10_FN, GPSR0_10,
5180 GP_0_0_FN, GPSR0_0, ))
5182 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5186 GP_1_28_FN, GPSR1_28,
5187 GP_1_27_FN, GPSR1_27,
5188 GP_1_26_FN, GPSR1_26,
5189 GP_1_25_FN, GPSR1_25,
5190 GP_1_24_FN, GPSR1_24,
5191 GP_1_23_FN, GPSR1_23,
5192 GP_1_22_FN, GPSR1_22,
5193 GP_1_21_FN, GPSR1_21,
5194 GP_1_20_FN, GPSR1_20,
5195 GP_1_19_FN, GPSR1_19,
5196 GP_1_18_FN, GPSR1_18,
5197 GP_1_17_FN, GPSR1_17,
5198 GP_1_16_FN, GPSR1_16,
5199 GP_1_15_FN, GPSR1_15,
5200 GP_1_14_FN, GPSR1_14,
5201 GP_1_13_FN, GPSR1_13,
5202 GP_1_12_FN, GPSR1_12,
5203 GP_1_11_FN, GPSR1_11,
5204 GP_1_10_FN, GPSR1_10,
5214 GP_1_0_FN, GPSR1_0, ))
5216 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
5234 GP_2_14_FN, GPSR2_14,
5235 GP_2_13_FN, GPSR2_13,
5236 GP_2_12_FN, GPSR2_12,
5237 GP_2_11_FN, GPSR2_11,
5238 GP_2_10_FN, GPSR2_10,
5248 GP_2_0_FN, GPSR2_0, ))
5250 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
5267 GP_3_15_FN, GPSR3_15,
5268 GP_3_14_FN, GPSR3_14,
5269 GP_3_13_FN, GPSR3_13,
5270 GP_3_12_FN, GPSR3_12,
5271 GP_3_11_FN, GPSR3_11,
5272 GP_3_10_FN, GPSR3_10,
5282 GP_3_0_FN, GPSR3_0, ))
5284 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
5299 GP_4_17_FN, GPSR4_17,
5300 GP_4_16_FN, GPSR4_16,
5301 GP_4_15_FN, GPSR4_15,
5302 GP_4_14_FN, GPSR4_14,
5303 GP_4_13_FN, GPSR4_13,
5304 GP_4_12_FN, GPSR4_12,
5305 GP_4_11_FN, GPSR4_11,
5306 GP_4_10_FN, GPSR4_10,
5316 GP_4_0_FN, GPSR4_0, ))
5318 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5325 GP_5_25_FN, GPSR5_25,
5326 GP_5_24_FN, GPSR5_24,
5327 GP_5_23_FN, GPSR5_23,
5328 GP_5_22_FN, GPSR5_22,
5329 GP_5_21_FN, GPSR5_21,
5330 GP_5_20_FN, GPSR5_20,
5331 GP_5_19_FN, GPSR5_19,
5332 GP_5_18_FN, GPSR5_18,
5333 GP_5_17_FN, GPSR5_17,
5334 GP_5_16_FN, GPSR5_16,
5335 GP_5_15_FN, GPSR5_15,
5336 GP_5_14_FN, GPSR5_14,
5337 GP_5_13_FN, GPSR5_13,
5338 GP_5_12_FN, GPSR5_12,
5339 GP_5_11_FN, GPSR5_11,
5340 GP_5_10_FN, GPSR5_10,
5350 GP_5_0_FN, GPSR5_0, ))
5352 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5353 GP_6_31_FN, GPSR6_31,
5354 GP_6_30_FN, GPSR6_30,
5355 GP_6_29_FN, GPSR6_29,
5356 GP_6_28_FN, GPSR6_28,
5357 GP_6_27_FN, GPSR6_27,
5358 GP_6_26_FN, GPSR6_26,
5359 GP_6_25_FN, GPSR6_25,
5360 GP_6_24_FN, GPSR6_24,
5361 GP_6_23_FN, GPSR6_23,
5362 GP_6_22_FN, GPSR6_22,
5363 GP_6_21_FN, GPSR6_21,
5364 GP_6_20_FN, GPSR6_20,
5365 GP_6_19_FN, GPSR6_19,
5366 GP_6_18_FN, GPSR6_18,
5367 GP_6_17_FN, GPSR6_17,
5368 GP_6_16_FN, GPSR6_16,
5369 GP_6_15_FN, GPSR6_15,
5370 GP_6_14_FN, GPSR6_14,
5371 GP_6_13_FN, GPSR6_13,
5372 GP_6_12_FN, GPSR6_12,
5373 GP_6_11_FN, GPSR6_11,
5374 GP_6_10_FN, GPSR6_10,
5384 GP_6_0_FN, GPSR6_0, ))
5386 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5418 GP_7_0_FN, GPSR7_0, ))
5424 #define FM(x) FN_##x,
5425 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5435 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5445 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5455 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5465 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5475 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5485 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5495 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5500 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5505 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5515 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5525 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5535 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5545 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5555 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5565 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5575 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5585 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5595 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5605 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
5606 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5607 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5608 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5609 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5610 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5611 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5619 #define FM(x) FN_##x,
5620 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5621 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5622 1, 1, 1, 2, 2, 1, 2, 3),
5634 0, 0, /* RESERVED 15 */
5643 /* RESERVED 2, 1, 0 */
5644 0, 0, 0, 0, 0, 0, 0, 0 ))
5646 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5647 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5648 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5665 0, 0, 0, 0, /* RESERVED 8, 7 */
5674 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5675 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5692 /* RESERVED 15, 14, 13, 12 */
5693 0, 0, 0, 0, 0, 0, 0, 0,
5694 0, 0, 0, 0, 0, 0, 0, 0,
5695 /* RESERVED 11, 10, 9, 8 */
5696 0, 0, 0, 0, 0, 0, 0, 0,
5697 0, 0, 0, 0, 0, 0, 0, 0,
5698 /* RESERVED 7, 6, 5, 4 */
5699 0, 0, 0, 0, 0, 0, 0, 0,
5700 0, 0, 0, 0, 0, 0, 0, 0,
5701 /* RESERVED 3, 2, 1 */
5702 0, 0, 0, 0, 0, 0, 0, 0,
5708 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5709 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5710 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5711 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5712 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5713 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5714 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5715 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5716 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5717 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
5719 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5720 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5721 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5722 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5723 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5724 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5725 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5726 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5727 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
5729 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5730 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5731 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5732 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5733 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5734 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5735 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5736 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5737 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
5739 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5740 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5741 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5742 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5743 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5744 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5745 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5746 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5747 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5749 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5750 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5751 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5752 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5753 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5754 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5755 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5756 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5757 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5759 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5760 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5761 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5762 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5763 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5764 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5765 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5766 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5767 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5769 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5770 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5771 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5772 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5773 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5774 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5775 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5776 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5777 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5779 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5780 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5781 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5782 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5783 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5784 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5785 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5786 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5787 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5789 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5790 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5791 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5792 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5793 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5794 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5795 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5796 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5797 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5799 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5800 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5801 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
5802 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5803 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5804 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5805 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5806 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5807 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5809 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5810 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5811 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5812 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5813 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5814 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5815 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5816 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5817 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5819 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5820 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5821 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5822 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5823 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5824 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5825 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5826 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5827 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
5829 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5830 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5831 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
5832 { PIN_TMS, 4, 2 }, /* TMS */
5834 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5835 { PIN_TDO, 28, 2 }, /* TDO */
5836 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5837 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5838 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5839 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5840 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5841 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5842 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5844 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5845 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5846 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5847 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5848 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5849 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5850 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5851 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5852 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5854 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5855 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5856 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5857 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5858 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5859 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5860 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5861 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5862 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5864 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5865 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5866 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5867 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5868 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5869 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5870 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5871 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5872 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5874 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5875 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5876 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5877 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5878 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5879 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5880 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5881 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5882 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5884 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5885 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5886 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5887 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5888 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5889 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5890 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5891 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5892 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5894 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5895 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5896 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5897 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5898 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5899 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5900 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5901 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5902 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5904 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5905 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5906 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5907 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5908 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5909 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5910 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5911 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
5912 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5914 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5915 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5916 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5917 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5918 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5919 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5920 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5921 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5922 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5924 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5925 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5926 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5927 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5928 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5929 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5930 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5931 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5932 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5934 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5935 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5936 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5937 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5938 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5939 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5940 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5941 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5942 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5944 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5945 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5946 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5947 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5948 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5949 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5950 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
5951 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
5961 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5962 [POCCTRL] = { 0xe6060380, },
5963 [TDSELCTRL] = { 0xe60603c0, },
5967 static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5971 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5973 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5976 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5977 bit = (pin & 0x1f) + 12;
5982 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5983 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5984 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5985 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5986 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5987 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5988 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5989 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5990 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5991 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5992 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5993 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5994 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5995 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5996 [12] = PIN_RPC_INT_N, /* RPC_INT# */
5997 [13] = PIN_RPC_WP_N, /* RPC_WP# */
5998 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
5999 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
6000 [16] = PIN_AVB_RXC, /* AVB_RXC */
6001 [17] = PIN_AVB_RD0, /* AVB_RD0 */
6002 [18] = PIN_AVB_RD1, /* AVB_RD1 */
6003 [19] = PIN_AVB_RD2, /* AVB_RD2 */
6004 [20] = PIN_AVB_RD3, /* AVB_RD3 */
6005 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
6006 [22] = PIN_AVB_TXC, /* AVB_TXC */
6007 [23] = PIN_AVB_TD0, /* AVB_TD0 */
6008 [24] = PIN_AVB_TD1, /* AVB_TD1 */
6009 [25] = PIN_AVB_TD2, /* AVB_TD2 */
6010 [26] = PIN_AVB_TD3, /* AVB_TD3 */
6011 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
6012 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
6013 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
6014 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
6015 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
6017 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6018 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
6019 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
6020 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
6021 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
6022 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
6023 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
6024 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
6025 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
6026 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
6027 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
6028 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
6029 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
6030 [12] = RCAR_GP_PIN(1, 0), /* A0 */
6031 [13] = RCAR_GP_PIN(1, 1), /* A1 */
6032 [14] = RCAR_GP_PIN(1, 2), /* A2 */
6033 [15] = RCAR_GP_PIN(1, 3), /* A3 */
6034 [16] = RCAR_GP_PIN(1, 4), /* A4 */
6035 [17] = RCAR_GP_PIN(1, 5), /* A5 */
6036 [18] = RCAR_GP_PIN(1, 6), /* A6 */
6037 [19] = RCAR_GP_PIN(1, 7), /* A7 */
6038 [20] = RCAR_GP_PIN(1, 8), /* A8 */
6039 [21] = RCAR_GP_PIN(1, 9), /* A9 */
6040 [22] = RCAR_GP_PIN(1, 10), /* A10 */
6041 [23] = RCAR_GP_PIN(1, 11), /* A11 */
6042 [24] = RCAR_GP_PIN(1, 12), /* A12 */
6043 [25] = RCAR_GP_PIN(1, 13), /* A13 */
6044 [26] = RCAR_GP_PIN(1, 14), /* A14 */
6045 [27] = RCAR_GP_PIN(1, 15), /* A15 */
6046 [28] = RCAR_GP_PIN(1, 16), /* A16 */
6047 [29] = RCAR_GP_PIN(1, 17), /* A17 */
6048 [30] = RCAR_GP_PIN(1, 18), /* A18 */
6049 [31] = RCAR_GP_PIN(1, 19), /* A19 */
6051 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6052 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6053 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
6054 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
6055 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
6056 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
6057 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
6058 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
6059 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
6060 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
6061 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
6062 [10] = RCAR_GP_PIN(0, 0), /* D0 */
6063 [11] = RCAR_GP_PIN(0, 1), /* D1 */
6064 [12] = RCAR_GP_PIN(0, 2), /* D2 */
6065 [13] = RCAR_GP_PIN(0, 3), /* D3 */
6066 [14] = RCAR_GP_PIN(0, 4), /* D4 */
6067 [15] = RCAR_GP_PIN(0, 5), /* D5 */
6068 [16] = RCAR_GP_PIN(0, 6), /* D6 */
6069 [17] = RCAR_GP_PIN(0, 7), /* D7 */
6070 [18] = RCAR_GP_PIN(0, 8), /* D8 */
6071 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6072 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6073 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6074 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6075 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6076 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6077 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6078 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6079 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
6080 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
6081 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
6082 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
6083 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
6085 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6086 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
6087 [ 1] = SH_PFC_PIN_NONE,
6088 [ 2] = PIN_FSCLKST, /* FSCLKST */
6089 [ 3] = PIN_EXTALR, /* EXTALR*/
6090 [ 4] = PIN_TRST_N, /* TRST# */
6091 [ 5] = PIN_TCK, /* TCK */
6092 [ 6] = PIN_TMS, /* TMS */
6093 [ 7] = PIN_TDI, /* TDI */
6094 [ 8] = SH_PFC_PIN_NONE,
6095 [ 9] = PIN_ASEBRK, /* ASEBRK */
6096 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6097 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6098 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6099 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6100 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6101 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6102 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6103 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6104 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6105 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6106 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6107 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6108 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6109 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6110 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6111 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6112 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6113 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6114 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6115 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6116 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6117 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6119 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6120 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6121 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6122 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6123 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6124 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6125 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6126 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6127 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6128 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6129 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6130 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6131 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6132 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6133 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6134 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6135 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6136 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6137 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6138 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6139 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6140 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6141 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6142 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6143 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6144 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6145 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6146 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6147 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6148 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6149 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6150 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6151 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6153 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6154 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6155 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6156 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6157 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6158 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6159 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6160 [ 6] = PIN_MLB_REF, /* MLB_REF */
6161 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6162 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6163 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6164 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6165 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6166 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6167 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6168 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6169 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6170 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6171 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6172 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6173 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6174 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6175 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6176 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6177 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6178 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6179 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6180 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6181 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6182 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6183 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6184 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6185 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6187 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6188 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6189 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6190 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6191 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6192 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6193 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6194 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
6195 [ 7] = SH_PFC_PIN_NONE,
6196 [ 8] = SH_PFC_PIN_NONE,
6197 [ 9] = SH_PFC_PIN_NONE,
6198 [10] = SH_PFC_PIN_NONE,
6199 [11] = SH_PFC_PIN_NONE,
6200 [12] = SH_PFC_PIN_NONE,
6201 [13] = SH_PFC_PIN_NONE,
6202 [14] = SH_PFC_PIN_NONE,
6203 [15] = SH_PFC_PIN_NONE,
6204 [16] = SH_PFC_PIN_NONE,
6205 [17] = SH_PFC_PIN_NONE,
6206 [18] = SH_PFC_PIN_NONE,
6207 [19] = SH_PFC_PIN_NONE,
6208 [20] = SH_PFC_PIN_NONE,
6209 [21] = SH_PFC_PIN_NONE,
6210 [22] = SH_PFC_PIN_NONE,
6211 [23] = SH_PFC_PIN_NONE,
6212 [24] = SH_PFC_PIN_NONE,
6213 [25] = SH_PFC_PIN_NONE,
6214 [26] = SH_PFC_PIN_NONE,
6215 [27] = SH_PFC_PIN_NONE,
6216 [28] = SH_PFC_PIN_NONE,
6217 [29] = SH_PFC_PIN_NONE,
6218 [30] = SH_PFC_PIN_NONE,
6219 [31] = SH_PFC_PIN_NONE,
6224 static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
6225 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
6226 .get_bias = rcar_pinmux_get_bias,
6227 .set_bias = rcar_pinmux_set_bias,
6230 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
6231 const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6232 .name = "r8a774a1_pfc",
6233 .ops = &r8a7796_pinmux_ops,
6234 .unlock_reg = 0xe6060000, /* PMMR */
6236 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6238 .pins = pinmux_pins,
6239 .nr_pins = ARRAY_SIZE(pinmux_pins),
6240 .groups = pinmux_groups.common,
6241 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6242 .functions = pinmux_functions.common,
6243 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6245 .cfg_regs = pinmux_config_regs,
6246 .drive_regs = pinmux_drive_regs,
6247 .bias_regs = pinmux_bias_regs,
6248 .ioctrl_regs = pinmux_ioctrl_regs,
6250 .pinmux_data = pinmux_data,
6251 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6255 #ifdef CONFIG_PINCTRL_PFC_R8A77960
6256 const struct sh_pfc_soc_info r8a77960_pinmux_info = {
6257 .name = "r8a77960_pfc",
6258 .ops = &r8a7796_pinmux_ops,
6259 .unlock_reg = 0xe6060000, /* PMMR */
6261 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6263 .pins = pinmux_pins,
6264 .nr_pins = ARRAY_SIZE(pinmux_pins),
6265 .groups = pinmux_groups.common,
6266 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6267 ARRAY_SIZE(pinmux_groups.automotive),
6268 .functions = pinmux_functions.common,
6269 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6270 ARRAY_SIZE(pinmux_functions.automotive),
6272 .cfg_regs = pinmux_config_regs,
6273 .drive_regs = pinmux_drive_regs,
6274 .bias_regs = pinmux_bias_regs,
6275 .ioctrl_regs = pinmux_ioctrl_regs,
6277 .pinmux_data = pinmux_data,
6278 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6282 #ifdef CONFIG_PINCTRL_PFC_R8A77961
6283 const struct sh_pfc_soc_info r8a77961_pinmux_info = {
6284 .name = "r8a77961_pfc",
6285 .ops = &r8a7796_pinmux_ops,
6286 .unlock_reg = 0xe6060000, /* PMMR */
6288 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6290 .pins = pinmux_pins,
6291 .nr_pins = ARRAY_SIZE(pinmux_pins),
6292 .groups = pinmux_groups.common,
6293 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6294 ARRAY_SIZE(pinmux_groups.automotive),
6295 .functions = pinmux_functions.common,
6296 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6297 ARRAY_SIZE(pinmux_functions.automotive),
6299 .cfg_regs = pinmux_config_regs,
6300 .drive_regs = pinmux_drive_regs,
6301 .bias_regs = pinmux_bias_regs,
6302 .ioctrl_regs = pinmux_ioctrl_regs,
6304 .pinmux_data = pinmux_data,
6305 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
projects / linux-2.6-microblaze.git / blob