1 // SPDX-License-Identifier: GPL-2.0
3 * R8A77950 processor support - PFC hardware block.
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
13 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
15 #define CPU_ALL_GP(fn, sfx) \
16 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
17 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
18 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
19 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
20 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
21 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
29 #define CPU_ALL_NOGP(fn) \
30 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
31 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
32 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
33 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
34 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
35 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
36 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
37 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
38 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(CLKOUT, "CLKOUT", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
51 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
70 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
71 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
72 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
73 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
76 * F_() : just information
77 * FM() : macro for FN_xxx / xxx_MARK
81 #define GPSR0_15 F_(D15, IP7_11_8)
82 #define GPSR0_14 F_(D14, IP7_7_4)
83 #define GPSR0_13 F_(D13, IP7_3_0)
84 #define GPSR0_12 F_(D12, IP6_31_28)
85 #define GPSR0_11 F_(D11, IP6_27_24)
86 #define GPSR0_10 F_(D10, IP6_23_20)
87 #define GPSR0_9 F_(D9, IP6_19_16)
88 #define GPSR0_8 F_(D8, IP6_15_12)
89 #define GPSR0_7 F_(D7, IP6_11_8)
90 #define GPSR0_6 F_(D6, IP6_7_4)
91 #define GPSR0_5 F_(D5, IP6_3_0)
92 #define GPSR0_4 F_(D4, IP5_31_28)
93 #define GPSR0_3 F_(D3, IP5_27_24)
94 #define GPSR0_2 F_(D2, IP5_23_20)
95 #define GPSR0_1 F_(D1, IP5_19_16)
96 #define GPSR0_0 F_(D0, IP5_15_12)
99 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
100 #define GPSR1_26 F_(WE1_N, IP5_7_4)
101 #define GPSR1_25 F_(WE0_N, IP5_3_0)
102 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
103 #define GPSR1_23 F_(RD_N, IP4_27_24)
104 #define GPSR1_22 F_(BS_N, IP4_23_20)
105 #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
106 #define GPSR1_20 F_(CS0_N, IP4_15_12)
107 #define GPSR1_19 F_(A19, IP4_11_8)
108 #define GPSR1_18 F_(A18, IP4_7_4)
109 #define GPSR1_17 F_(A17, IP4_3_0)
110 #define GPSR1_16 F_(A16, IP3_31_28)
111 #define GPSR1_15 F_(A15, IP3_27_24)
112 #define GPSR1_14 F_(A14, IP3_23_20)
113 #define GPSR1_13 F_(A13, IP3_19_16)
114 #define GPSR1_12 F_(A12, IP3_15_12)
115 #define GPSR1_11 F_(A11, IP3_11_8)
116 #define GPSR1_10 F_(A10, IP3_7_4)
117 #define GPSR1_9 F_(A9, IP3_3_0)
118 #define GPSR1_8 F_(A8, IP2_31_28)
119 #define GPSR1_7 F_(A7, IP2_27_24)
120 #define GPSR1_6 F_(A6, IP2_23_20)
121 #define GPSR1_5 F_(A5, IP2_19_16)
122 #define GPSR1_4 F_(A4, IP2_15_12)
123 #define GPSR1_3 F_(A3, IP2_11_8)
124 #define GPSR1_2 F_(A2, IP2_7_4)
125 #define GPSR1_1 F_(A1, IP2_3_0)
126 #define GPSR1_0 F_(A0, IP1_31_28)
129 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
130 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
131 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
132 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
133 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
134 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
135 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
136 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
137 #define GPSR2_6 F_(PWM0, IP1_19_16)
138 #define GPSR2_5 F_(IRQ5, IP1_15_12)
139 #define GPSR2_4 F_(IRQ4, IP1_11_8)
140 #define GPSR2_3 F_(IRQ3, IP1_7_4)
141 #define GPSR2_2 F_(IRQ2, IP1_3_0)
142 #define GPSR2_1 F_(IRQ1, IP0_31_28)
143 #define GPSR2_0 F_(IRQ0, IP0_27_24)
146 #define GPSR3_15 F_(SD1_WP, IP10_23_20)
147 #define GPSR3_14 F_(SD1_CD, IP10_19_16)
148 #define GPSR3_13 F_(SD0_WP, IP10_15_12)
149 #define GPSR3_12 F_(SD0_CD, IP10_11_8)
150 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
151 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
152 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
153 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
154 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
155 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
156 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
157 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
158 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
159 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
160 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
161 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
164 #define GPSR4_17 FM(SD3_DS)
165 #define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
166 #define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
167 #define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
168 #define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
169 #define GPSR4_12 FM(SD3_DAT3)
170 #define GPSR4_11 FM(SD3_DAT2)
171 #define GPSR4_10 FM(SD3_DAT1)
172 #define GPSR4_9 FM(SD3_DAT0)
173 #define GPSR4_8 FM(SD3_CMD)
174 #define GPSR4_7 FM(SD3_CLK)
175 #define GPSR4_6 F_(SD2_DS, IP9_23_20)
176 #define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
177 #define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
178 #define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
179 #define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
180 #define GPSR4_1 FM(SD2_CMD)
181 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
184 #define GPSR5_25 F_(MLB_DAT, IP13_19_16)
185 #define GPSR5_24 F_(MLB_SIG, IP13_15_12)
186 #define GPSR5_23 F_(MLB_CLK, IP13_11_8)
187 #define GPSR5_22 FM(MSIOF0_RXD)
188 #define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
189 #define GPSR5_20 FM(MSIOF0_TXD)
190 #define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
191 #define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
192 #define GPSR5_17 FM(MSIOF0_SCK)
193 #define GPSR5_16 F_(HRTS0_N, IP12_27_24)
194 #define GPSR5_15 F_(HCTS0_N, IP12_23_20)
195 #define GPSR5_14 F_(HTX0, IP12_19_16)
196 #define GPSR5_13 F_(HRX0, IP12_15_12)
197 #define GPSR5_12 F_(HSCK0, IP12_11_8)
198 #define GPSR5_11 F_(RX2_A, IP12_7_4)
199 #define GPSR5_10 F_(TX2_A, IP12_3_0)
200 #define GPSR5_9 F_(SCK2, IP11_31_28)
201 #define GPSR5_8 F_(RTS1_N, IP11_27_24)
202 #define GPSR5_7 F_(CTS1_N, IP11_23_20)
203 #define GPSR5_6 F_(TX1_A, IP11_19_16)
204 #define GPSR5_5 F_(RX1_A, IP11_15_12)
205 #define GPSR5_4 F_(RTS0_N, IP11_11_8)
206 #define GPSR5_3 F_(CTS0_N, IP11_7_4)
207 #define GPSR5_2 F_(TX0, IP11_3_0)
208 #define GPSR5_1 F_(RX0, IP10_31_28)
209 #define GPSR5_0 F_(SCK0, IP10_27_24)
212 #define GPSR6_31 F_(USB31_OVC, IP17_7_4)
213 #define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
214 #define GPSR6_29 F_(USB30_OVC, IP16_31_28)
215 #define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
216 #define GPSR6_27 F_(USB1_OVC, IP16_23_20)
217 #define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
218 #define GPSR6_25 F_(USB0_OVC, IP16_15_12)
219 #define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
220 #define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
221 #define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
222 #define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
223 #define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
224 #define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
225 #define GPSR6_18 F_(SSI_WS78, IP15_19_16)
226 #define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
227 #define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
228 #define GPSR6_15 F_(SSI_WS6, IP15_7_4)
229 #define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
230 #define GPSR6_13 FM(SSI_SDATA5)
231 #define GPSR6_12 FM(SSI_WS5)
232 #define GPSR6_11 FM(SSI_SCK5)
233 #define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
234 #define GPSR6_9 F_(SSI_WS4, IP14_27_24)
235 #define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
236 #define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
237 #define GPSR6_6 F_(SSI_WS349, IP14_15_12)
238 #define GPSR6_5 F_(SSI_SCK349, IP14_11_8)
239 #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
240 #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
241 #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
242 #define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
243 #define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
246 #define GPSR7_3 FM(GP7_03)
247 #define GPSR7_2 FM(GP7_02)
248 #define GPSR7_1 FM(AVS2)
249 #define GPSR7_0 FM(AVS1)
252 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
253 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
274 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
318 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP11_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP11_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
362 #define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP14_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP14_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383 #define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 #define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385 #define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define PINMUX_GPSR \
406 GPSR1_25 GPSR5_25 GPSR6_25 \
407 GPSR1_24 GPSR5_24 GPSR6_24 \
408 GPSR1_23 GPSR5_23 GPSR6_23 \
409 GPSR1_22 GPSR5_22 GPSR6_22 \
410 GPSR1_21 GPSR5_21 GPSR6_21 \
411 GPSR1_20 GPSR5_20 GPSR6_20 \
412 GPSR1_19 GPSR5_19 GPSR6_19 \
413 GPSR1_18 GPSR5_18 GPSR6_18 \
414 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
415 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
416 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
417 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
418 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
419 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
420 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
421 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
422 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
423 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
424 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
425 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
426 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
427 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
428 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
429 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
430 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
431 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
433 #define PINMUX_IPSR \
435 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
436 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
437 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
438 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
439 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
440 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
441 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
442 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
444 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
445 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
446 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
447 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
448 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
449 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
450 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
451 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
453 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
454 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
455 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
456 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
457 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
458 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
459 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
460 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
462 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
463 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
464 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
465 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
466 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
467 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
468 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
469 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
471 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
472 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
473 FM(IP16_11_8) IP16_11_8 \
474 FM(IP16_15_12) IP16_15_12 \
475 FM(IP16_19_16) IP16_19_16 \
476 FM(IP16_23_20) IP16_23_20 \
477 FM(IP16_27_24) IP16_27_24 \
478 FM(IP16_31_28) IP16_31_28
480 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
481 #define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
482 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
483 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
484 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
485 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
486 #define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
487 #define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
488 #define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
489 #define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
490 #define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
491 #define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
492 #define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
493 #define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
494 #define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
495 #define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
496 #define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
497 #define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
498 #define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
499 #define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
500 #define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
501 #define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
503 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
504 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
505 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
506 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
507 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
508 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
509 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
510 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
511 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
512 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
513 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
514 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
515 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
516 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
517 #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
518 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
519 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
520 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
521 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
522 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
523 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
524 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
525 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
527 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
528 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
529 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
530 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
531 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
533 #define PINMUX_MOD_SELS\
535 MOD_SEL1_31_30 MOD_SEL2_31 \
536 MOD_SEL0_30_29 MOD_SEL2_30 \
537 MOD_SEL1_29_28_27 MOD_SEL2_29 \
540 MOD_SEL0_26_25_24 MOD_SEL1_26 \
543 MOD_SEL0_23 MOD_SEL1_23_22_21 \
547 MOD_SEL0_19 MOD_SEL1_19 \
548 MOD_SEL0_18 MOD_SEL1_18_17 \
550 MOD_SEL0_16_15 MOD_SEL1_16 \
553 MOD_SEL0_13 MOD_SEL1_13 \
554 MOD_SEL0_12 MOD_SEL1_12 \
555 MOD_SEL0_11 MOD_SEL1_11 \
556 MOD_SEL0_10 MOD_SEL1_10 \
557 MOD_SEL0_9 MOD_SEL1_9 \
561 MOD_SEL0_5_4 MOD_SEL1_5 \
563 MOD_SEL0_3 MOD_SEL1_3 \
564 MOD_SEL0_2_1 MOD_SEL1_2 \
566 MOD_SEL1_0 MOD_SEL2_0
569 * These pins are not able to be muxed but have other properties
570 * that can be set, such as drive-strength or pull-up/pull-down enable.
572 #define PINMUX_STATIC \
573 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
574 FM(QSPI0_IO2) FM(QSPI0_IO3) \
575 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
576 FM(QSPI1_IO2) FM(QSPI1_IO3) \
577 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
578 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
579 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
580 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
581 FM(CLKOUT) FM(PRESETOUT) \
582 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
583 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
585 #define PINMUX_PHYS \
586 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
596 #define FM(x) FN_##x,
597 PINMUX_FUNCTION_BEGIN,
607 #define FM(x) x##_MARK,
619 static const u16 pinmux_data[] = {
620 PINMUX_DATA_GP_ALL(),
624 PINMUX_SINGLE(GP7_02),
625 PINMUX_SINGLE(GP7_03),
626 PINMUX_SINGLE(MSIOF0_RXD),
627 PINMUX_SINGLE(MSIOF0_SCK),
628 PINMUX_SINGLE(MSIOF0_TXD),
629 PINMUX_SINGLE(SD2_CMD),
630 PINMUX_SINGLE(SD3_CLK),
631 PINMUX_SINGLE(SD3_CMD),
632 PINMUX_SINGLE(SD3_DAT0),
633 PINMUX_SINGLE(SD3_DAT1),
634 PINMUX_SINGLE(SD3_DAT2),
635 PINMUX_SINGLE(SD3_DAT3),
636 PINMUX_SINGLE(SD3_DS),
637 PINMUX_SINGLE(SSI_SCK5),
638 PINMUX_SINGLE(SSI_SDATA5),
639 PINMUX_SINGLE(SSI_WS5),
642 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
643 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
645 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
646 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
647 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
649 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
650 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
651 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
653 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
654 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
655 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
657 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
658 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
659 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
660 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
662 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
663 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
664 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
665 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
667 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
668 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
669 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
670 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
671 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
672 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
674 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
675 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
676 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
677 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
678 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
679 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
682 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
683 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
684 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
685 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
686 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
688 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
689 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
690 PINMUX_IPSR_GPSR(IP1_7_4, A25),
691 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
692 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
693 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
695 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
696 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
697 PINMUX_IPSR_GPSR(IP1_11_8, A24),
698 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
699 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
700 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
702 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
703 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
704 PINMUX_IPSR_GPSR(IP1_15_12, A23),
705 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
706 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
707 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
709 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
710 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
711 PINMUX_IPSR_GPSR(IP1_19_16, A22),
712 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
713 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
715 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
716 PINMUX_IPSR_MSEL(IP1_23_20, A21, I2C_SEL_3_0),
717 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
718 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
719 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
720 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
722 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
723 PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0),
724 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
725 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
726 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
728 PINMUX_IPSR_GPSR(IP1_31_28, A0),
729 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
730 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
731 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
732 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
733 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
736 PINMUX_IPSR_GPSR(IP2_3_0, A1),
737 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
738 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
739 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
740 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
741 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
743 PINMUX_IPSR_GPSR(IP2_7_4, A2),
744 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
745 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
746 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
747 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
748 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
750 PINMUX_IPSR_GPSR(IP2_11_8, A3),
751 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
752 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
753 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
754 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
755 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
757 PINMUX_IPSR_GPSR(IP2_15_12, A4),
758 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
759 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
760 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
761 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
762 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
764 PINMUX_IPSR_GPSR(IP2_19_16, A5),
765 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
766 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
767 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
768 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
769 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
770 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
772 PINMUX_IPSR_GPSR(IP2_23_20, A6),
773 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
774 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
775 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
776 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
777 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
778 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
780 PINMUX_IPSR_GPSR(IP2_27_24, A7),
781 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
782 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
783 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
784 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
785 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
786 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
788 PINMUX_IPSR_GPSR(IP2_31_28, A8),
789 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
790 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
791 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
792 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
793 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
794 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
797 PINMUX_IPSR_GPSR(IP3_3_0, A9),
798 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
799 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
800 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
802 PINMUX_IPSR_GPSR(IP3_7_4, A10),
803 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
804 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
805 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
807 PINMUX_IPSR_GPSR(IP3_11_8, A11),
808 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
809 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
810 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
811 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
812 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
813 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
814 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
815 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
817 PINMUX_IPSR_GPSR(IP3_15_12, A12),
818 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
819 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
820 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
821 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
822 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
824 PINMUX_IPSR_GPSR(IP3_19_16, A13),
825 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
826 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
827 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
828 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
829 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
831 PINMUX_IPSR_GPSR(IP3_23_20, A14),
832 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
833 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
834 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
835 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
836 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
838 PINMUX_IPSR_GPSR(IP3_27_24, A15),
839 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
840 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
841 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
842 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
843 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
845 PINMUX_IPSR_GPSR(IP3_31_28, A16),
846 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
847 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
848 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
851 PINMUX_IPSR_GPSR(IP4_3_0, A17),
852 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
853 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
854 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
856 PINMUX_IPSR_GPSR(IP4_7_4, A18),
857 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
858 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
859 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
861 PINMUX_IPSR_GPSR(IP4_11_8, A19),
862 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
863 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
864 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
866 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
867 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
869 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
870 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
871 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
873 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
874 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
875 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
876 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
877 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
878 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
879 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
880 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
882 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
883 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
884 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
885 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
886 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
887 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
889 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
890 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
891 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
892 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
893 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
894 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
897 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
898 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
899 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
900 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
901 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
902 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
903 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
905 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
906 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
907 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
908 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
909 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
910 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
911 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
912 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
914 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
915 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
916 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
917 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
919 PINMUX_IPSR_GPSR(IP5_15_12, D0),
920 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
921 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
922 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
923 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
925 PINMUX_IPSR_GPSR(IP5_19_16, D1),
926 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
927 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
928 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
929 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
931 PINMUX_IPSR_GPSR(IP5_23_20, D2),
932 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
933 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
934 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
936 PINMUX_IPSR_GPSR(IP5_27_24, D3),
937 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
938 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
939 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
941 PINMUX_IPSR_GPSR(IP5_31_28, D4),
942 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
943 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
944 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
947 PINMUX_IPSR_GPSR(IP6_3_0, D5),
948 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
949 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
950 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
952 PINMUX_IPSR_GPSR(IP6_7_4, D6),
953 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
954 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
955 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
957 PINMUX_IPSR_GPSR(IP6_11_8, D7),
958 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
959 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
960 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
962 PINMUX_IPSR_GPSR(IP6_15_12, D8),
963 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
964 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
965 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
966 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
967 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
969 PINMUX_IPSR_GPSR(IP6_19_16, D9),
970 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
971 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
972 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
973 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
975 PINMUX_IPSR_GPSR(IP6_23_20, D10),
976 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
977 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
978 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
979 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
980 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
981 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
983 PINMUX_IPSR_GPSR(IP6_27_24, D11),
984 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
985 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
986 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
987 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
988 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
989 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
991 PINMUX_IPSR_GPSR(IP6_31_28, D12),
992 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
993 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
994 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
995 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
996 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
999 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1000 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1001 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1002 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1003 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1004 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1006 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1007 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1008 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1009 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1010 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1011 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1012 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1014 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1015 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1016 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1017 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1018 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1019 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1020 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1022 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
1024 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1025 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1026 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1028 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1029 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1030 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1032 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1033 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1034 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1035 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1037 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1038 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1039 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1040 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1043 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1044 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1045 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1046 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1048 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1049 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1050 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1051 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1053 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1054 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1055 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1057 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1058 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1059 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1060 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1062 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1063 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1064 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1065 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1066 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1068 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1069 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1070 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1071 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1072 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1074 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1075 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1076 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1077 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1078 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1080 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1081 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1082 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1083 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1084 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1087 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1089 PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
1091 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
1093 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
1095 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
1097 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
1098 PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
1100 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
1101 PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
1103 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
1104 PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
1107 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
1108 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
1110 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
1111 PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
1113 PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
1114 PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
1115 PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1117 PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
1118 PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
1120 PINMUX_IPSR_MSEL(IP10_19_16, SD1_CD, I2C_SEL_0_0),
1121 PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1122 PINMUX_IPSR_PHYS(IP10_19_16, SCL0, I2C_SEL_0_1),
1124 PINMUX_IPSR_MSEL(IP10_23_20, SD1_WP, I2C_SEL_0_0),
1125 PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1126 PINMUX_IPSR_PHYS(IP10_23_20, SDA0, I2C_SEL_0_1),
1128 PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
1129 PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
1130 PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1131 PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
1132 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
1133 PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1134 PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1135 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1136 PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
1138 PINMUX_IPSR_GPSR(IP10_31_28, RX0),
1139 PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
1140 PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
1141 PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1142 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1145 PINMUX_IPSR_GPSR(IP11_3_0, TX0),
1146 PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
1147 PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1148 PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1149 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1151 PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
1152 PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1153 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1154 PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1155 PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1156 PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1157 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
1158 PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
1160 PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N),
1161 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1162 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1163 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
1164 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
1165 PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1166 PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1167 PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
1169 PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
1170 PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
1171 PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1172 PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1173 PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1175 PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
1176 PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
1177 PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1178 PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1179 PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
1181 PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
1182 PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1183 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1184 PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1185 PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1186 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
1187 PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
1189 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
1190 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1191 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1192 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1193 PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1194 PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
1195 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
1197 PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
1198 PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1199 PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1200 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
1201 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1202 PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1203 PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
1206 PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
1207 PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
1208 PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
1209 PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
1210 PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
1211 PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
1213 PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
1214 PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
1215 PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
1216 PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
1217 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1218 PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
1220 PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
1221 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1222 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
1223 PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
1224 PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
1225 PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1226 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1228 PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
1229 PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1230 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
1231 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1232 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1233 PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
1235 PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
1236 PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1237 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
1238 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1239 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1240 PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
1242 PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
1243 PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
1244 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1245 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
1246 PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1247 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1248 PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1249 PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
1251 PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
1252 PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
1253 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1254 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
1255 PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1256 PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
1257 PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
1259 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1260 PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
1263 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1264 PINMUX_IPSR_GPSR(IP13_3_0, RX5),
1265 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
1266 PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
1267 PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1268 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
1269 PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1271 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1272 PINMUX_IPSR_GPSR(IP13_7_4, TX5),
1273 PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1274 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
1275 PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
1276 PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1277 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
1278 PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1280 PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
1281 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1282 PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
1284 PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
1285 PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
1286 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1287 PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
1289 PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
1290 PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
1291 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1293 PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
1294 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1296 PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
1297 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1299 PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
1300 PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1303 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
1305 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
1306 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
1308 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK349),
1309 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1310 PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1312 PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS349),
1313 PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1314 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1315 PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1317 PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
1318 PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1319 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1320 PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
1321 PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1322 PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
1323 PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
1325 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
1326 PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
1327 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1328 PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1329 PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1330 PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1331 PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1333 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
1334 PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
1335 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1336 PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1337 PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1338 PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1339 PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1341 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
1342 PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
1343 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1344 PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1345 PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1346 PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
1347 PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
1350 PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
1351 PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
1352 PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1354 PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
1355 PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
1356 PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
1358 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
1359 PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1360 PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
1362 PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
1363 PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
1364 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1365 PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
1366 PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1367 PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1368 PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1370 PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
1371 PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
1372 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1373 PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1374 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1375 PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1376 PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1378 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
1379 PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1380 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1381 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1382 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1383 PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
1384 PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
1385 PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1387 PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
1388 PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1389 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1390 PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1391 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1392 PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
1393 PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
1395 PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
1396 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
1397 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1398 PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
1399 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
1400 PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
1401 PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1402 PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
1405 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
1407 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
1408 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1409 PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1410 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
1411 PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1413 PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
1414 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1415 PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
1416 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1417 PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
1418 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1420 PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
1421 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
1422 PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
1423 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
1424 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
1426 PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
1427 PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1428 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
1429 PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
1430 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1431 PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
1432 PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1433 PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1435 PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
1436 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1437 PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
1438 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1439 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1440 PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
1441 PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1442 PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
1444 PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
1445 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
1446 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
1447 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1448 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1449 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1450 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
1451 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1452 PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
1454 PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
1455 PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
1456 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
1457 PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1458 PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1459 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1460 PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
1461 PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
1462 PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
1465 PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
1466 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
1467 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
1468 PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1469 PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1470 PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
1471 PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
1473 PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
1474 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
1475 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
1476 PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1477 PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1478 PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
1479 PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
1482 * Static pins can not be muxed between different functions but
1483 * still need mark entries in the pinmux list. Add each static
1484 * pin to the list without an associated function. The sh-pfc
1485 * core will do the right thing and skip trying to mux the pin
1486 * while still applying configuration to it.
1488 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1494 * Pins not associated with a GPIO port.
1501 static const struct sh_pfc_pin pinmux_pins[] = {
1502 PINMUX_GPIO_GP_ALL(),
1506 /* - AUDIO CLOCK ------------------------------------------------------------ */
1507 static const unsigned int audio_clk_a_a_pins[] = {
1511 static const unsigned int audio_clk_a_a_mux[] = {
1514 static const unsigned int audio_clk_a_b_pins[] = {
1518 static const unsigned int audio_clk_a_b_mux[] = {
1521 static const unsigned int audio_clk_a_c_pins[] = {
1525 static const unsigned int audio_clk_a_c_mux[] = {
1528 static const unsigned int audio_clk_b_a_pins[] = {
1532 static const unsigned int audio_clk_b_a_mux[] = {
1535 static const unsigned int audio_clk_b_b_pins[] = {
1539 static const unsigned int audio_clk_b_b_mux[] = {
1542 static const unsigned int audio_clk_c_a_pins[] = {
1546 static const unsigned int audio_clk_c_a_mux[] = {
1549 static const unsigned int audio_clk_c_b_pins[] = {
1553 static const unsigned int audio_clk_c_b_mux[] = {
1556 static const unsigned int audio_clkout_a_pins[] = {
1560 static const unsigned int audio_clkout_a_mux[] = {
1561 AUDIO_CLKOUT_A_MARK,
1563 static const unsigned int audio_clkout_b_pins[] = {
1567 static const unsigned int audio_clkout_b_mux[] = {
1568 AUDIO_CLKOUT_B_MARK,
1570 static const unsigned int audio_clkout_c_pins[] = {
1574 static const unsigned int audio_clkout_c_mux[] = {
1575 AUDIO_CLKOUT_C_MARK,
1577 static const unsigned int audio_clkout_d_pins[] = {
1581 static const unsigned int audio_clkout_d_mux[] = {
1582 AUDIO_CLKOUT_D_MARK,
1584 static const unsigned int audio_clkout1_a_pins[] = {
1588 static const unsigned int audio_clkout1_a_mux[] = {
1589 AUDIO_CLKOUT1_A_MARK,
1591 static const unsigned int audio_clkout1_b_pins[] = {
1595 static const unsigned int audio_clkout1_b_mux[] = {
1596 AUDIO_CLKOUT1_B_MARK,
1598 static const unsigned int audio_clkout2_a_pins[] = {
1602 static const unsigned int audio_clkout2_a_mux[] = {
1603 AUDIO_CLKOUT2_A_MARK,
1605 static const unsigned int audio_clkout2_b_pins[] = {
1609 static const unsigned int audio_clkout2_b_mux[] = {
1610 AUDIO_CLKOUT2_B_MARK,
1613 static const unsigned int audio_clkout3_a_pins[] = {
1617 static const unsigned int audio_clkout3_a_mux[] = {
1618 AUDIO_CLKOUT3_A_MARK,
1620 static const unsigned int audio_clkout3_b_pins[] = {
1624 static const unsigned int audio_clkout3_b_mux[] = {
1625 AUDIO_CLKOUT3_B_MARK,
1628 /* - EtherAVB --------------------------------------------------------------- */
1629 static const unsigned int avb_link_pins[] = {
1633 static const unsigned int avb_link_mux[] = {
1636 static const unsigned int avb_magic_pins[] = {
1640 static const unsigned int avb_magic_mux[] = {
1643 static const unsigned int avb_phy_int_pins[] = {
1647 static const unsigned int avb_phy_int_mux[] = {
1650 static const unsigned int avb_mdio_pins[] = {
1651 /* AVB_MDC, AVB_MDIO */
1652 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1654 static const unsigned int avb_mdio_mux[] = {
1655 AVB_MDC_MARK, AVB_MDIO_MARK,
1657 static const unsigned int avb_mii_pins[] = {
1659 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1660 * AVB_TD1, AVB_TD2, AVB_TD3,
1661 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1662 * AVB_RD1, AVB_RD2, AVB_RD3,
1665 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1666 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1667 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1668 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1671 static const unsigned int avb_mii_mux[] = {
1672 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1673 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1674 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1675 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1678 static const unsigned int avb_avtp_pps_pins[] = {
1682 static const unsigned int avb_avtp_pps_mux[] = {
1685 static const unsigned int avb_avtp_match_a_pins[] = {
1686 /* AVB_AVTP_MATCH_A */
1689 static const unsigned int avb_avtp_match_a_mux[] = {
1690 AVB_AVTP_MATCH_A_MARK,
1692 static const unsigned int avb_avtp_capture_a_pins[] = {
1693 /* AVB_AVTP_CAPTURE_A */
1696 static const unsigned int avb_avtp_capture_a_mux[] = {
1697 AVB_AVTP_CAPTURE_A_MARK,
1699 static const unsigned int avb_avtp_match_b_pins[] = {
1700 /* AVB_AVTP_MATCH_B */
1703 static const unsigned int avb_avtp_match_b_mux[] = {
1704 AVB_AVTP_MATCH_B_MARK,
1706 static const unsigned int avb_avtp_capture_b_pins[] = {
1707 /* AVB_AVTP_CAPTURE_B */
1710 static const unsigned int avb_avtp_capture_b_mux[] = {
1711 AVB_AVTP_CAPTURE_B_MARK,
1714 /* - CAN ------------------------------------------------------------------ */
1715 static const unsigned int can0_data_a_pins[] = {
1717 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1719 static const unsigned int can0_data_a_mux[] = {
1720 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1722 static const unsigned int can0_data_b_pins[] = {
1724 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1726 static const unsigned int can0_data_b_mux[] = {
1727 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1729 static const unsigned int can1_data_pins[] = {
1731 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1733 static const unsigned int can1_data_mux[] = {
1734 CAN1_TX_MARK, CAN1_RX_MARK,
1737 /* - CAN Clock -------------------------------------------------------------- */
1738 static const unsigned int can_clk_pins[] = {
1742 static const unsigned int can_clk_mux[] = {
1746 /* - CAN FD --------------------------------------------------------------- */
1747 static const unsigned int canfd0_data_a_pins[] = {
1749 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1751 static const unsigned int canfd0_data_a_mux[] = {
1752 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1754 static const unsigned int canfd0_data_b_pins[] = {
1756 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1758 static const unsigned int canfd0_data_b_mux[] = {
1759 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1761 static const unsigned int canfd1_data_pins[] = {
1763 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1765 static const unsigned int canfd1_data_mux[] = {
1766 CANFD1_TX_MARK, CANFD1_RX_MARK,
1769 /* - DRIF0 --------------------------------------------------------------- */
1770 static const unsigned int drif0_ctrl_a_pins[] = {
1772 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1774 static const unsigned int drif0_ctrl_a_mux[] = {
1775 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1777 static const unsigned int drif0_data0_a_pins[] = {
1781 static const unsigned int drif0_data0_a_mux[] = {
1784 static const unsigned int drif0_data1_a_pins[] = {
1788 static const unsigned int drif0_data1_a_mux[] = {
1791 static const unsigned int drif0_ctrl_b_pins[] = {
1793 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1795 static const unsigned int drif0_ctrl_b_mux[] = {
1796 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1798 static const unsigned int drif0_data0_b_pins[] = {
1802 static const unsigned int drif0_data0_b_mux[] = {
1805 static const unsigned int drif0_data1_b_pins[] = {
1809 static const unsigned int drif0_data1_b_mux[] = {
1812 static const unsigned int drif0_ctrl_c_pins[] = {
1814 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1816 static const unsigned int drif0_ctrl_c_mux[] = {
1817 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1819 static const unsigned int drif0_data0_c_pins[] = {
1823 static const unsigned int drif0_data0_c_mux[] = {
1826 static const unsigned int drif0_data1_c_pins[] = {
1830 static const unsigned int drif0_data1_c_mux[] = {
1833 /* - DRIF1 --------------------------------------------------------------- */
1834 static const unsigned int drif1_ctrl_a_pins[] = {
1836 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1838 static const unsigned int drif1_ctrl_a_mux[] = {
1839 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1841 static const unsigned int drif1_data0_a_pins[] = {
1845 static const unsigned int drif1_data0_a_mux[] = {
1848 static const unsigned int drif1_data1_a_pins[] = {
1852 static const unsigned int drif1_data1_a_mux[] = {
1855 static const unsigned int drif1_ctrl_b_pins[] = {
1857 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1859 static const unsigned int drif1_ctrl_b_mux[] = {
1860 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1862 static const unsigned int drif1_data0_b_pins[] = {
1866 static const unsigned int drif1_data0_b_mux[] = {
1869 static const unsigned int drif1_data1_b_pins[] = {
1873 static const unsigned int drif1_data1_b_mux[] = {
1876 static const unsigned int drif1_ctrl_c_pins[] = {
1878 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1880 static const unsigned int drif1_ctrl_c_mux[] = {
1881 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1883 static const unsigned int drif1_data0_c_pins[] = {
1887 static const unsigned int drif1_data0_c_mux[] = {
1890 static const unsigned int drif1_data1_c_pins[] = {
1894 static const unsigned int drif1_data1_c_mux[] = {
1897 /* - DRIF2 --------------------------------------------------------------- */
1898 static const unsigned int drif2_ctrl_a_pins[] = {
1900 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1902 static const unsigned int drif2_ctrl_a_mux[] = {
1903 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1905 static const unsigned int drif2_data0_a_pins[] = {
1909 static const unsigned int drif2_data0_a_mux[] = {
1912 static const unsigned int drif2_data1_a_pins[] = {
1916 static const unsigned int drif2_data1_a_mux[] = {
1919 static const unsigned int drif2_ctrl_b_pins[] = {
1921 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1923 static const unsigned int drif2_ctrl_b_mux[] = {
1924 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1926 static const unsigned int drif2_data0_b_pins[] = {
1930 static const unsigned int drif2_data0_b_mux[] = {
1933 static const unsigned int drif2_data1_b_pins[] = {
1937 static const unsigned int drif2_data1_b_mux[] = {
1940 /* - DRIF3 --------------------------------------------------------------- */
1941 static const unsigned int drif3_ctrl_a_pins[] = {
1943 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1945 static const unsigned int drif3_ctrl_a_mux[] = {
1946 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1948 static const unsigned int drif3_data0_a_pins[] = {
1952 static const unsigned int drif3_data0_a_mux[] = {
1955 static const unsigned int drif3_data1_a_pins[] = {
1959 static const unsigned int drif3_data1_a_mux[] = {
1962 static const unsigned int drif3_ctrl_b_pins[] = {
1964 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1966 static const unsigned int drif3_ctrl_b_mux[] = {
1967 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1969 static const unsigned int drif3_data0_b_pins[] = {
1973 static const unsigned int drif3_data0_b_mux[] = {
1976 static const unsigned int drif3_data1_b_pins[] = {
1980 static const unsigned int drif3_data1_b_mux[] = {
1984 /* - DU --------------------------------------------------------------------- */
1985 static const unsigned int du_rgb666_pins[] = {
1986 /* R[7:2], G[7:2], B[7:2] */
1987 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1988 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1989 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1990 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1991 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1992 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1994 static const unsigned int du_rgb666_mux[] = {
1995 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1996 DU_DR3_MARK, DU_DR2_MARK,
1997 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1998 DU_DG3_MARK, DU_DG2_MARK,
1999 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2000 DU_DB3_MARK, DU_DB2_MARK,
2002 static const unsigned int du_rgb888_pins[] = {
2003 /* R[7:0], G[7:0], B[7:0] */
2004 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2005 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2006 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2007 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2008 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2009 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2010 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2011 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2012 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2014 static const unsigned int du_rgb888_mux[] = {
2015 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2016 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2017 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2018 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2019 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2020 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2022 static const unsigned int du_clk_out_0_pins[] = {
2026 static const unsigned int du_clk_out_0_mux[] = {
2029 static const unsigned int du_clk_out_1_pins[] = {
2033 static const unsigned int du_clk_out_1_mux[] = {
2036 static const unsigned int du_sync_pins[] = {
2037 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2038 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2040 static const unsigned int du_sync_mux[] = {
2041 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2043 static const unsigned int du_oddf_pins[] = {
2044 /* EXDISP/EXODDF/EXCDE */
2047 static const unsigned int du_oddf_mux[] = {
2048 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2050 static const unsigned int du_cde_pins[] = {
2054 static const unsigned int du_cde_mux[] = {
2057 static const unsigned int du_disp_pins[] = {
2061 static const unsigned int du_disp_mux[] = {
2064 /* - HSCIF0 ----------------------------------------------------------------- */
2065 static const unsigned int hscif0_data_pins[] = {
2067 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2069 static const unsigned int hscif0_data_mux[] = {
2070 HRX0_MARK, HTX0_MARK,
2072 static const unsigned int hscif0_clk_pins[] = {
2076 static const unsigned int hscif0_clk_mux[] = {
2079 static const unsigned int hscif0_ctrl_pins[] = {
2081 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2083 static const unsigned int hscif0_ctrl_mux[] = {
2084 HRTS0_N_MARK, HCTS0_N_MARK,
2086 /* - HSCIF1 ----------------------------------------------------------------- */
2087 static const unsigned int hscif1_data_a_pins[] = {
2089 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2091 static const unsigned int hscif1_data_a_mux[] = {
2092 HRX1_A_MARK, HTX1_A_MARK,
2094 static const unsigned int hscif1_clk_a_pins[] = {
2098 static const unsigned int hscif1_clk_a_mux[] = {
2101 static const unsigned int hscif1_ctrl_a_pins[] = {
2103 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2105 static const unsigned int hscif1_ctrl_a_mux[] = {
2106 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2109 static const unsigned int hscif1_data_b_pins[] = {
2111 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2113 static const unsigned int hscif1_data_b_mux[] = {
2114 HRX1_B_MARK, HTX1_B_MARK,
2116 static const unsigned int hscif1_clk_b_pins[] = {
2120 static const unsigned int hscif1_clk_b_mux[] = {
2123 static const unsigned int hscif1_ctrl_b_pins[] = {
2125 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2127 static const unsigned int hscif1_ctrl_b_mux[] = {
2128 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2130 /* - HSCIF2 ----------------------------------------------------------------- */
2131 static const unsigned int hscif2_data_a_pins[] = {
2133 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2135 static const unsigned int hscif2_data_a_mux[] = {
2136 HRX2_A_MARK, HTX2_A_MARK,
2138 static const unsigned int hscif2_clk_a_pins[] = {
2142 static const unsigned int hscif2_clk_a_mux[] = {
2145 static const unsigned int hscif2_ctrl_a_pins[] = {
2147 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2149 static const unsigned int hscif2_ctrl_a_mux[] = {
2150 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2153 static const unsigned int hscif2_data_b_pins[] = {
2155 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2157 static const unsigned int hscif2_data_b_mux[] = {
2158 HRX2_B_MARK, HTX2_B_MARK,
2160 static const unsigned int hscif2_clk_b_pins[] = {
2164 static const unsigned int hscif2_clk_b_mux[] = {
2167 static const unsigned int hscif2_ctrl_b_pins[] = {
2169 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2171 static const unsigned int hscif2_ctrl_b_mux[] = {
2172 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2174 /* - HSCIF3 ----------------------------------------------------------------- */
2175 static const unsigned int hscif3_data_a_pins[] = {
2177 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2179 static const unsigned int hscif3_data_a_mux[] = {
2180 HRX3_A_MARK, HTX3_A_MARK,
2182 static const unsigned int hscif3_clk_pins[] = {
2186 static const unsigned int hscif3_clk_mux[] = {
2189 static const unsigned int hscif3_ctrl_pins[] = {
2191 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2193 static const unsigned int hscif3_ctrl_mux[] = {
2194 HRTS3_N_MARK, HCTS3_N_MARK,
2197 static const unsigned int hscif3_data_b_pins[] = {
2199 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2201 static const unsigned int hscif3_data_b_mux[] = {
2202 HRX3_B_MARK, HTX3_B_MARK,
2204 static const unsigned int hscif3_data_c_pins[] = {
2206 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2208 static const unsigned int hscif3_data_c_mux[] = {
2209 HRX3_C_MARK, HTX3_C_MARK,
2211 static const unsigned int hscif3_data_d_pins[] = {
2213 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2215 static const unsigned int hscif3_data_d_mux[] = {
2216 HRX3_D_MARK, HTX3_D_MARK,
2218 /* - HSCIF4 ----------------------------------------------------------------- */
2219 static const unsigned int hscif4_data_a_pins[] = {
2221 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2223 static const unsigned int hscif4_data_a_mux[] = {
2224 HRX4_A_MARK, HTX4_A_MARK,
2226 static const unsigned int hscif4_clk_pins[] = {
2230 static const unsigned int hscif4_clk_mux[] = {
2233 static const unsigned int hscif4_ctrl_pins[] = {
2235 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2237 static const unsigned int hscif4_ctrl_mux[] = {
2238 HRTS4_N_MARK, HCTS4_N_MARK,
2241 static const unsigned int hscif4_data_b_pins[] = {
2243 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2245 static const unsigned int hscif4_data_b_mux[] = {
2246 HRX4_B_MARK, HTX4_B_MARK,
2249 /* - I2C -------------------------------------------------------------------- */
2250 static const unsigned int i2c0_pins[] = {
2252 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2255 static const unsigned int i2c0_mux[] = {
2256 SCL0_MARK, SDA0_MARK,
2259 static const unsigned int i2c1_a_pins[] = {
2261 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2263 static const unsigned int i2c1_a_mux[] = {
2264 SDA1_A_MARK, SCL1_A_MARK,
2266 static const unsigned int i2c1_b_pins[] = {
2268 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2270 static const unsigned int i2c1_b_mux[] = {
2271 SDA1_B_MARK, SCL1_B_MARK,
2273 static const unsigned int i2c2_a_pins[] = {
2275 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2277 static const unsigned int i2c2_a_mux[] = {
2278 SDA2_A_MARK, SCL2_A_MARK,
2280 static const unsigned int i2c2_b_pins[] = {
2282 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2284 static const unsigned int i2c2_b_mux[] = {
2285 SDA2_B_MARK, SCL2_B_MARK,
2288 static const unsigned int i2c3_pins[] = {
2290 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2293 static const unsigned int i2c3_mux[] = {
2294 SCL3_MARK, SDA3_MARK,
2297 static const unsigned int i2c5_pins[] = {
2299 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2302 static const unsigned int i2c5_mux[] = {
2303 SCL5_MARK, SDA5_MARK,
2306 static const unsigned int i2c6_a_pins[] = {
2308 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2310 static const unsigned int i2c6_a_mux[] = {
2311 SDA6_A_MARK, SCL6_A_MARK,
2313 static const unsigned int i2c6_b_pins[] = {
2315 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2317 static const unsigned int i2c6_b_mux[] = {
2318 SDA6_B_MARK, SCL6_B_MARK,
2320 static const unsigned int i2c6_c_pins[] = {
2322 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2324 static const unsigned int i2c6_c_mux[] = {
2325 SDA6_C_MARK, SCL6_C_MARK,
2328 /* - INTC-EX ---------------------------------------------------------------- */
2329 static const unsigned int intc_ex_irq0_pins[] = {
2333 static const unsigned int intc_ex_irq0_mux[] = {
2336 static const unsigned int intc_ex_irq1_pins[] = {
2340 static const unsigned int intc_ex_irq1_mux[] = {
2343 static const unsigned int intc_ex_irq2_pins[] = {
2347 static const unsigned int intc_ex_irq2_mux[] = {
2350 static const unsigned int intc_ex_irq3_pins[] = {
2354 static const unsigned int intc_ex_irq3_mux[] = {
2357 static const unsigned int intc_ex_irq4_pins[] = {
2361 static const unsigned int intc_ex_irq4_mux[] = {
2364 static const unsigned int intc_ex_irq5_pins[] = {
2368 static const unsigned int intc_ex_irq5_mux[] = {
2372 /* - MSIOF0 ----------------------------------------------------------------- */
2373 static const unsigned int msiof0_clk_pins[] = {
2377 static const unsigned int msiof0_clk_mux[] = {
2380 static const unsigned int msiof0_sync_pins[] = {
2384 static const unsigned int msiof0_sync_mux[] = {
2387 static const unsigned int msiof0_ss1_pins[] = {
2391 static const unsigned int msiof0_ss1_mux[] = {
2394 static const unsigned int msiof0_ss2_pins[] = {
2398 static const unsigned int msiof0_ss2_mux[] = {
2401 static const unsigned int msiof0_txd_pins[] = {
2405 static const unsigned int msiof0_txd_mux[] = {
2408 static const unsigned int msiof0_rxd_pins[] = {
2412 static const unsigned int msiof0_rxd_mux[] = {
2415 /* - MSIOF1 ----------------------------------------------------------------- */
2416 static const unsigned int msiof1_clk_a_pins[] = {
2420 static const unsigned int msiof1_clk_a_mux[] = {
2423 static const unsigned int msiof1_sync_a_pins[] = {
2427 static const unsigned int msiof1_sync_a_mux[] = {
2430 static const unsigned int msiof1_ss1_a_pins[] = {
2434 static const unsigned int msiof1_ss1_a_mux[] = {
2437 static const unsigned int msiof1_ss2_a_pins[] = {
2441 static const unsigned int msiof1_ss2_a_mux[] = {
2444 static const unsigned int msiof1_txd_a_pins[] = {
2448 static const unsigned int msiof1_txd_a_mux[] = {
2451 static const unsigned int msiof1_rxd_a_pins[] = {
2455 static const unsigned int msiof1_rxd_a_mux[] = {
2458 static const unsigned int msiof1_clk_b_pins[] = {
2462 static const unsigned int msiof1_clk_b_mux[] = {
2465 static const unsigned int msiof1_sync_b_pins[] = {
2469 static const unsigned int msiof1_sync_b_mux[] = {
2472 static const unsigned int msiof1_ss1_b_pins[] = {
2476 static const unsigned int msiof1_ss1_b_mux[] = {
2479 static const unsigned int msiof1_ss2_b_pins[] = {
2483 static const unsigned int msiof1_ss2_b_mux[] = {
2486 static const unsigned int msiof1_txd_b_pins[] = {
2490 static const unsigned int msiof1_txd_b_mux[] = {
2493 static const unsigned int msiof1_rxd_b_pins[] = {
2497 static const unsigned int msiof1_rxd_b_mux[] = {
2500 static const unsigned int msiof1_clk_c_pins[] = {
2504 static const unsigned int msiof1_clk_c_mux[] = {
2507 static const unsigned int msiof1_sync_c_pins[] = {
2511 static const unsigned int msiof1_sync_c_mux[] = {
2514 static const unsigned int msiof1_ss1_c_pins[] = {
2518 static const unsigned int msiof1_ss1_c_mux[] = {
2521 static const unsigned int msiof1_ss2_c_pins[] = {
2525 static const unsigned int msiof1_ss2_c_mux[] = {
2528 static const unsigned int msiof1_txd_c_pins[] = {
2532 static const unsigned int msiof1_txd_c_mux[] = {
2535 static const unsigned int msiof1_rxd_c_pins[] = {
2539 static const unsigned int msiof1_rxd_c_mux[] = {
2542 static const unsigned int msiof1_clk_d_pins[] = {
2546 static const unsigned int msiof1_clk_d_mux[] = {
2549 static const unsigned int msiof1_sync_d_pins[] = {
2553 static const unsigned int msiof1_sync_d_mux[] = {
2556 static const unsigned int msiof1_ss1_d_pins[] = {
2560 static const unsigned int msiof1_ss1_d_mux[] = {
2563 static const unsigned int msiof1_ss2_d_pins[] = {
2567 static const unsigned int msiof1_ss2_d_mux[] = {
2570 static const unsigned int msiof1_txd_d_pins[] = {
2574 static const unsigned int msiof1_txd_d_mux[] = {
2577 static const unsigned int msiof1_rxd_d_pins[] = {
2581 static const unsigned int msiof1_rxd_d_mux[] = {
2584 static const unsigned int msiof1_clk_e_pins[] = {
2588 static const unsigned int msiof1_clk_e_mux[] = {
2591 static const unsigned int msiof1_sync_e_pins[] = {
2595 static const unsigned int msiof1_sync_e_mux[] = {
2598 static const unsigned int msiof1_ss1_e_pins[] = {
2602 static const unsigned int msiof1_ss1_e_mux[] = {
2605 static const unsigned int msiof1_ss2_e_pins[] = {
2609 static const unsigned int msiof1_ss2_e_mux[] = {
2612 static const unsigned int msiof1_txd_e_pins[] = {
2616 static const unsigned int msiof1_txd_e_mux[] = {
2619 static const unsigned int msiof1_rxd_e_pins[] = {
2623 static const unsigned int msiof1_rxd_e_mux[] = {
2626 static const unsigned int msiof1_clk_f_pins[] = {
2630 static const unsigned int msiof1_clk_f_mux[] = {
2633 static const unsigned int msiof1_sync_f_pins[] = {
2637 static const unsigned int msiof1_sync_f_mux[] = {
2640 static const unsigned int msiof1_ss1_f_pins[] = {
2644 static const unsigned int msiof1_ss1_f_mux[] = {
2647 static const unsigned int msiof1_ss2_f_pins[] = {
2651 static const unsigned int msiof1_ss2_f_mux[] = {
2654 static const unsigned int msiof1_txd_f_pins[] = {
2658 static const unsigned int msiof1_txd_f_mux[] = {
2661 static const unsigned int msiof1_rxd_f_pins[] = {
2665 static const unsigned int msiof1_rxd_f_mux[] = {
2668 static const unsigned int msiof1_clk_g_pins[] = {
2672 static const unsigned int msiof1_clk_g_mux[] = {
2675 static const unsigned int msiof1_sync_g_pins[] = {
2679 static const unsigned int msiof1_sync_g_mux[] = {
2682 static const unsigned int msiof1_ss1_g_pins[] = {
2686 static const unsigned int msiof1_ss1_g_mux[] = {
2689 static const unsigned int msiof1_ss2_g_pins[] = {
2693 static const unsigned int msiof1_ss2_g_mux[] = {
2696 static const unsigned int msiof1_txd_g_pins[] = {
2700 static const unsigned int msiof1_txd_g_mux[] = {
2703 static const unsigned int msiof1_rxd_g_pins[] = {
2707 static const unsigned int msiof1_rxd_g_mux[] = {
2710 /* - MSIOF2 ----------------------------------------------------------------- */
2711 static const unsigned int msiof2_clk_a_pins[] = {
2715 static const unsigned int msiof2_clk_a_mux[] = {
2718 static const unsigned int msiof2_sync_a_pins[] = {
2722 static const unsigned int msiof2_sync_a_mux[] = {
2725 static const unsigned int msiof2_ss1_a_pins[] = {
2729 static const unsigned int msiof2_ss1_a_mux[] = {
2732 static const unsigned int msiof2_ss2_a_pins[] = {
2736 static const unsigned int msiof2_ss2_a_mux[] = {
2739 static const unsigned int msiof2_txd_a_pins[] = {
2743 static const unsigned int msiof2_txd_a_mux[] = {
2746 static const unsigned int msiof2_rxd_a_pins[] = {
2750 static const unsigned int msiof2_rxd_a_mux[] = {
2753 static const unsigned int msiof2_clk_b_pins[] = {
2757 static const unsigned int msiof2_clk_b_mux[] = {
2760 static const unsigned int msiof2_sync_b_pins[] = {
2764 static const unsigned int msiof2_sync_b_mux[] = {
2767 static const unsigned int msiof2_ss1_b_pins[] = {
2771 static const unsigned int msiof2_ss1_b_mux[] = {
2774 static const unsigned int msiof2_ss2_b_pins[] = {
2778 static const unsigned int msiof2_ss2_b_mux[] = {
2781 static const unsigned int msiof2_txd_b_pins[] = {
2785 static const unsigned int msiof2_txd_b_mux[] = {
2788 static const unsigned int msiof2_rxd_b_pins[] = {
2792 static const unsigned int msiof2_rxd_b_mux[] = {
2795 static const unsigned int msiof2_clk_c_pins[] = {
2799 static const unsigned int msiof2_clk_c_mux[] = {
2802 static const unsigned int msiof2_sync_c_pins[] = {
2806 static const unsigned int msiof2_sync_c_mux[] = {
2809 static const unsigned int msiof2_ss1_c_pins[] = {
2813 static const unsigned int msiof2_ss1_c_mux[] = {
2816 static const unsigned int msiof2_ss2_c_pins[] = {
2820 static const unsigned int msiof2_ss2_c_mux[] = {
2823 static const unsigned int msiof2_txd_c_pins[] = {
2827 static const unsigned int msiof2_txd_c_mux[] = {
2830 static const unsigned int msiof2_rxd_c_pins[] = {
2834 static const unsigned int msiof2_rxd_c_mux[] = {
2837 static const unsigned int msiof2_clk_d_pins[] = {
2841 static const unsigned int msiof2_clk_d_mux[] = {
2844 static const unsigned int msiof2_sync_d_pins[] = {
2848 static const unsigned int msiof2_sync_d_mux[] = {
2851 static const unsigned int msiof2_ss1_d_pins[] = {
2855 static const unsigned int msiof2_ss1_d_mux[] = {
2858 static const unsigned int msiof2_ss2_d_pins[] = {
2862 static const unsigned int msiof2_ss2_d_mux[] = {
2865 static const unsigned int msiof2_txd_d_pins[] = {
2869 static const unsigned int msiof2_txd_d_mux[] = {
2872 static const unsigned int msiof2_rxd_d_pins[] = {
2876 static const unsigned int msiof2_rxd_d_mux[] = {
2879 /* - MSIOF3 ----------------------------------------------------------------- */
2880 static const unsigned int msiof3_clk_a_pins[] = {
2884 static const unsigned int msiof3_clk_a_mux[] = {
2887 static const unsigned int msiof3_sync_a_pins[] = {
2891 static const unsigned int msiof3_sync_a_mux[] = {
2894 static const unsigned int msiof3_ss1_a_pins[] = {
2898 static const unsigned int msiof3_ss1_a_mux[] = {
2901 static const unsigned int msiof3_ss2_a_pins[] = {
2905 static const unsigned int msiof3_ss2_a_mux[] = {
2908 static const unsigned int msiof3_txd_a_pins[] = {
2912 static const unsigned int msiof3_txd_a_mux[] = {
2915 static const unsigned int msiof3_rxd_a_pins[] = {
2919 static const unsigned int msiof3_rxd_a_mux[] = {
2922 static const unsigned int msiof3_clk_b_pins[] = {
2926 static const unsigned int msiof3_clk_b_mux[] = {
2929 static const unsigned int msiof3_sync_b_pins[] = {
2933 static const unsigned int msiof3_sync_b_mux[] = {
2936 static const unsigned int msiof3_ss1_b_pins[] = {
2940 static const unsigned int msiof3_ss1_b_mux[] = {
2943 static const unsigned int msiof3_ss2_b_pins[] = {
2947 static const unsigned int msiof3_ss2_b_mux[] = {
2950 static const unsigned int msiof3_txd_b_pins[] = {
2954 static const unsigned int msiof3_txd_b_mux[] = {
2957 static const unsigned int msiof3_rxd_b_pins[] = {
2961 static const unsigned int msiof3_rxd_b_mux[] = {
2964 static const unsigned int msiof3_clk_c_pins[] = {
2968 static const unsigned int msiof3_clk_c_mux[] = {
2971 static const unsigned int msiof3_sync_c_pins[] = {
2975 static const unsigned int msiof3_sync_c_mux[] = {
2978 static const unsigned int msiof3_txd_c_pins[] = {
2982 static const unsigned int msiof3_txd_c_mux[] = {
2985 static const unsigned int msiof3_rxd_c_pins[] = {
2989 static const unsigned int msiof3_rxd_c_mux[] = {
2992 static const unsigned int msiof3_clk_d_pins[] = {
2996 static const unsigned int msiof3_clk_d_mux[] = {
2999 static const unsigned int msiof3_sync_d_pins[] = {
3003 static const unsigned int msiof3_sync_d_mux[] = {
3006 static const unsigned int msiof3_ss1_d_pins[] = {
3010 static const unsigned int msiof3_ss1_d_mux[] = {
3013 static const unsigned int msiof3_txd_d_pins[] = {
3017 static const unsigned int msiof3_txd_d_mux[] = {
3020 static const unsigned int msiof3_rxd_d_pins[] = {
3024 static const unsigned int msiof3_rxd_d_mux[] = {
3028 /* - PWM0 --------------------------------------------------------------------*/
3029 static const unsigned int pwm0_pins[] = {
3033 static const unsigned int pwm0_mux[] = {
3036 /* - PWM1 --------------------------------------------------------------------*/
3037 static const unsigned int pwm1_a_pins[] = {
3041 static const unsigned int pwm1_a_mux[] = {
3044 static const unsigned int pwm1_b_pins[] = {
3048 static const unsigned int pwm1_b_mux[] = {
3051 /* - PWM2 --------------------------------------------------------------------*/
3052 static const unsigned int pwm2_a_pins[] = {
3056 static const unsigned int pwm2_a_mux[] = {
3059 static const unsigned int pwm2_b_pins[] = {
3063 static const unsigned int pwm2_b_mux[] = {
3066 /* - PWM3 --------------------------------------------------------------------*/
3067 static const unsigned int pwm3_a_pins[] = {
3071 static const unsigned int pwm3_a_mux[] = {
3074 static const unsigned int pwm3_b_pins[] = {
3078 static const unsigned int pwm3_b_mux[] = {
3081 /* - PWM4 --------------------------------------------------------------------*/
3082 static const unsigned int pwm4_a_pins[] = {
3086 static const unsigned int pwm4_a_mux[] = {
3089 static const unsigned int pwm4_b_pins[] = {
3093 static const unsigned int pwm4_b_mux[] = {
3096 /* - PWM5 --------------------------------------------------------------------*/
3097 static const unsigned int pwm5_a_pins[] = {
3101 static const unsigned int pwm5_a_mux[] = {
3104 static const unsigned int pwm5_b_pins[] = {
3108 static const unsigned int pwm5_b_mux[] = {
3111 /* - PWM6 --------------------------------------------------------------------*/
3112 static const unsigned int pwm6_a_pins[] = {
3116 static const unsigned int pwm6_a_mux[] = {
3119 static const unsigned int pwm6_b_pins[] = {
3123 static const unsigned int pwm6_b_mux[] = {
3127 /* - QSPI0 ------------------------------------------------------------------ */
3128 static const unsigned int qspi0_ctrl_pins[] = {
3129 /* QSPI0_SPCLK, QSPI0_SSL */
3130 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3132 static const unsigned int qspi0_ctrl_mux[] = {
3133 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3135 static const unsigned int qspi0_data2_pins[] = {
3136 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3137 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3139 static const unsigned int qspi0_data2_mux[] = {
3140 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3142 static const unsigned int qspi0_data4_pins[] = {
3143 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
3144 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3146 static const unsigned int qspi0_data4_mux[] = {
3147 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3148 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3150 /* - QSPI1 ------------------------------------------------------------------ */
3151 static const unsigned int qspi1_ctrl_pins[] = {
3152 /* QSPI1_SPCLK, QSPI1_SSL */
3153 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3155 static const unsigned int qspi1_ctrl_mux[] = {
3156 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3158 static const unsigned int qspi1_data2_pins[] = {
3159 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3160 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3162 static const unsigned int qspi1_data2_mux[] = {
3163 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3165 static const unsigned int qspi1_data4_pins[] = {
3166 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
3167 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3169 static const unsigned int qspi1_data4_mux[] = {
3170 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3171 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3174 /* - SATA --------------------------------------------------------------------*/
3175 static const unsigned int sata0_devslp_a_pins[] = {
3179 static const unsigned int sata0_devslp_a_mux[] = {
3182 static const unsigned int sata0_devslp_b_pins[] = {
3186 static const unsigned int sata0_devslp_b_mux[] = {
3190 /* - SCIF0 ------------------------------------------------------------------ */
3191 static const unsigned int scif0_data_pins[] = {
3193 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3195 static const unsigned int scif0_data_mux[] = {
3198 static const unsigned int scif0_clk_pins[] = {
3202 static const unsigned int scif0_clk_mux[] = {
3205 static const unsigned int scif0_ctrl_pins[] = {
3207 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3209 static const unsigned int scif0_ctrl_mux[] = {
3210 RTS0_N_MARK, CTS0_N_MARK,
3212 /* - SCIF1 ------------------------------------------------------------------ */
3213 static const unsigned int scif1_data_a_pins[] = {
3215 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3217 static const unsigned int scif1_data_a_mux[] = {
3218 RX1_A_MARK, TX1_A_MARK,
3220 static const unsigned int scif1_clk_pins[] = {
3224 static const unsigned int scif1_clk_mux[] = {
3227 static const unsigned int scif1_ctrl_pins[] = {
3229 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3231 static const unsigned int scif1_ctrl_mux[] = {
3232 RTS1_N_MARK, CTS1_N_MARK,
3235 static const unsigned int scif1_data_b_pins[] = {
3237 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3239 static const unsigned int scif1_data_b_mux[] = {
3240 RX1_B_MARK, TX1_B_MARK,
3242 /* - SCIF2 ------------------------------------------------------------------ */
3243 static const unsigned int scif2_data_a_pins[] = {
3245 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3247 static const unsigned int scif2_data_a_mux[] = {
3248 RX2_A_MARK, TX2_A_MARK,
3250 static const unsigned int scif2_clk_pins[] = {
3254 static const unsigned int scif2_clk_mux[] = {
3257 static const unsigned int scif2_data_b_pins[] = {
3259 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3261 static const unsigned int scif2_data_b_mux[] = {
3262 RX2_B_MARK, TX2_B_MARK,
3264 /* - SCIF3 ------------------------------------------------------------------ */
3265 static const unsigned int scif3_data_a_pins[] = {
3267 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3269 static const unsigned int scif3_data_a_mux[] = {
3270 RX3_A_MARK, TX3_A_MARK,
3272 static const unsigned int scif3_clk_pins[] = {
3276 static const unsigned int scif3_clk_mux[] = {
3279 static const unsigned int scif3_ctrl_pins[] = {
3281 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3283 static const unsigned int scif3_ctrl_mux[] = {
3284 RTS3_N_MARK, CTS3_N_MARK,
3286 static const unsigned int scif3_data_b_pins[] = {
3288 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3290 static const unsigned int scif3_data_b_mux[] = {
3291 RX3_B_MARK, TX3_B_MARK,
3293 /* - SCIF4 ------------------------------------------------------------------ */
3294 static const unsigned int scif4_data_a_pins[] = {
3296 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3298 static const unsigned int scif4_data_a_mux[] = {
3299 RX4_A_MARK, TX4_A_MARK,
3301 static const unsigned int scif4_clk_a_pins[] = {
3305 static const unsigned int scif4_clk_a_mux[] = {
3308 static const unsigned int scif4_ctrl_a_pins[] = {
3310 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3312 static const unsigned int scif4_ctrl_a_mux[] = {
3313 RTS4_N_A_MARK, CTS4_N_A_MARK,
3315 static const unsigned int scif4_data_b_pins[] = {
3317 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3319 static const unsigned int scif4_data_b_mux[] = {
3320 RX4_B_MARK, TX4_B_MARK,
3322 static const unsigned int scif4_clk_b_pins[] = {
3326 static const unsigned int scif4_clk_b_mux[] = {
3329 static const unsigned int scif4_ctrl_b_pins[] = {
3331 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3333 static const unsigned int scif4_ctrl_b_mux[] = {
3334 RTS4_N_B_MARK, CTS4_N_B_MARK,
3336 static const unsigned int scif4_data_c_pins[] = {
3338 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3340 static const unsigned int scif4_data_c_mux[] = {
3341 RX4_C_MARK, TX4_C_MARK,
3343 static const unsigned int scif4_clk_c_pins[] = {
3347 static const unsigned int scif4_clk_c_mux[] = {
3350 static const unsigned int scif4_ctrl_c_pins[] = {
3352 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3354 static const unsigned int scif4_ctrl_c_mux[] = {
3355 RTS4_N_C_MARK, CTS4_N_C_MARK,
3357 /* - SCIF5 ------------------------------------------------------------------ */
3358 static const unsigned int scif5_data_pins[] = {
3360 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3362 static const unsigned int scif5_data_mux[] = {
3365 static const unsigned int scif5_clk_pins[] = {
3369 static const unsigned int scif5_clk_mux[] = {
3373 /* - SCIF Clock ------------------------------------------------------------- */
3374 static const unsigned int scif_clk_a_pins[] = {
3378 static const unsigned int scif_clk_a_mux[] = {
3381 static const unsigned int scif_clk_b_pins[] = {
3385 static const unsigned int scif_clk_b_mux[] = {
3389 /* - SDHI0 ------------------------------------------------------------------ */
3390 static const unsigned int sdhi0_data1_pins[] = {
3394 static const unsigned int sdhi0_data1_mux[] = {
3397 static const unsigned int sdhi0_data4_pins[] = {
3399 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3400 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3402 static const unsigned int sdhi0_data4_mux[] = {
3403 SD0_DAT0_MARK, SD0_DAT1_MARK,
3404 SD0_DAT2_MARK, SD0_DAT3_MARK,
3406 static const unsigned int sdhi0_ctrl_pins[] = {
3408 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3410 static const unsigned int sdhi0_ctrl_mux[] = {
3411 SD0_CLK_MARK, SD0_CMD_MARK,
3413 static const unsigned int sdhi0_cd_pins[] = {
3417 static const unsigned int sdhi0_cd_mux[] = {
3420 static const unsigned int sdhi0_wp_pins[] = {
3424 static const unsigned int sdhi0_wp_mux[] = {
3427 /* - SDHI1 ------------------------------------------------------------------ */
3428 static const unsigned int sdhi1_data1_pins[] = {
3432 static const unsigned int sdhi1_data1_mux[] = {
3435 static const unsigned int sdhi1_data4_pins[] = {
3437 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3438 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3440 static const unsigned int sdhi1_data4_mux[] = {
3441 SD1_DAT0_MARK, SD1_DAT1_MARK,
3442 SD1_DAT2_MARK, SD1_DAT3_MARK,
3444 static const unsigned int sdhi1_ctrl_pins[] = {
3446 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3448 static const unsigned int sdhi1_ctrl_mux[] = {
3449 SD1_CLK_MARK, SD1_CMD_MARK,
3451 static const unsigned int sdhi1_cd_pins[] = {
3455 static const unsigned int sdhi1_cd_mux[] = {
3458 static const unsigned int sdhi1_wp_pins[] = {
3462 static const unsigned int sdhi1_wp_mux[] = {
3465 /* - SDHI2 ------------------------------------------------------------------ */
3466 static const unsigned int sdhi2_data1_pins[] = {
3470 static const unsigned int sdhi2_data1_mux[] = {
3473 static const unsigned int sdhi2_data4_pins[] = {
3475 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3476 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3478 static const unsigned int sdhi2_data4_mux[] = {
3479 SD2_DAT0_MARK, SD2_DAT1_MARK,
3480 SD2_DAT2_MARK, SD2_DAT3_MARK,
3482 static const unsigned int sdhi2_data8_pins[] = {
3484 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3485 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3486 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3487 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3489 static const unsigned int sdhi2_data8_mux[] = {
3490 SD2_DAT0_MARK, SD2_DAT1_MARK,
3491 SD2_DAT2_MARK, SD2_DAT3_MARK,
3492 SD2_DAT4_MARK, SD2_DAT5_MARK,
3493 SD2_DAT6_MARK, SD2_DAT7_MARK,
3495 static const unsigned int sdhi2_ctrl_pins[] = {
3497 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3499 static const unsigned int sdhi2_ctrl_mux[] = {
3500 SD2_CLK_MARK, SD2_CMD_MARK,
3502 static const unsigned int sdhi2_cd_a_pins[] = {
3506 static const unsigned int sdhi2_cd_a_mux[] = {
3509 static const unsigned int sdhi2_cd_b_pins[] = {
3513 static const unsigned int sdhi2_cd_b_mux[] = {
3516 static const unsigned int sdhi2_wp_a_pins[] = {
3520 static const unsigned int sdhi2_wp_a_mux[] = {
3523 static const unsigned int sdhi2_wp_b_pins[] = {
3527 static const unsigned int sdhi2_wp_b_mux[] = {
3530 static const unsigned int sdhi2_ds_pins[] = {
3534 static const unsigned int sdhi2_ds_mux[] = {
3537 /* - SDHI3 ------------------------------------------------------------------ */
3538 static const unsigned int sdhi3_data1_pins[] = {
3542 static const unsigned int sdhi3_data1_mux[] = {
3545 static const unsigned int sdhi3_data4_pins[] = {
3547 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3548 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3550 static const unsigned int sdhi3_data4_mux[] = {
3551 SD3_DAT0_MARK, SD3_DAT1_MARK,
3552 SD3_DAT2_MARK, SD3_DAT3_MARK,
3554 static const unsigned int sdhi3_data8_pins[] = {
3556 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3557 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3558 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3559 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3561 static const unsigned int sdhi3_data8_mux[] = {
3562 SD3_DAT0_MARK, SD3_DAT1_MARK,
3563 SD3_DAT2_MARK, SD3_DAT3_MARK,
3564 SD3_DAT4_MARK, SD3_DAT5_MARK,
3565 SD3_DAT6_MARK, SD3_DAT7_MARK,
3567 static const unsigned int sdhi3_ctrl_pins[] = {
3569 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3571 static const unsigned int sdhi3_ctrl_mux[] = {
3572 SD3_CLK_MARK, SD3_CMD_MARK,
3574 static const unsigned int sdhi3_cd_pins[] = {
3578 static const unsigned int sdhi3_cd_mux[] = {
3581 static const unsigned int sdhi3_wp_pins[] = {
3585 static const unsigned int sdhi3_wp_mux[] = {
3588 static const unsigned int sdhi3_ds_pins[] = {
3592 static const unsigned int sdhi3_ds_mux[] = {
3596 /* - SSI -------------------------------------------------------------------- */
3597 static const unsigned int ssi0_data_pins[] = {
3601 static const unsigned int ssi0_data_mux[] = {
3604 static const unsigned int ssi01239_ctrl_pins[] = {
3606 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3608 static const unsigned int ssi01239_ctrl_mux[] = {
3609 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3611 static const unsigned int ssi1_data_a_pins[] = {
3615 static const unsigned int ssi1_data_a_mux[] = {
3618 static const unsigned int ssi1_data_b_pins[] = {
3622 static const unsigned int ssi1_data_b_mux[] = {
3625 static const unsigned int ssi1_ctrl_a_pins[] = {
3627 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3629 static const unsigned int ssi1_ctrl_a_mux[] = {
3630 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3632 static const unsigned int ssi1_ctrl_b_pins[] = {
3634 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3636 static const unsigned int ssi1_ctrl_b_mux[] = {
3637 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3639 static const unsigned int ssi2_data_a_pins[] = {
3643 static const unsigned int ssi2_data_a_mux[] = {
3646 static const unsigned int ssi2_data_b_pins[] = {
3650 static const unsigned int ssi2_data_b_mux[] = {
3653 static const unsigned int ssi2_ctrl_a_pins[] = {
3655 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3657 static const unsigned int ssi2_ctrl_a_mux[] = {
3658 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3660 static const unsigned int ssi2_ctrl_b_pins[] = {
3662 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3664 static const unsigned int ssi2_ctrl_b_mux[] = {
3665 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3667 static const unsigned int ssi3_data_pins[] = {
3671 static const unsigned int ssi3_data_mux[] = {
3674 static const unsigned int ssi349_ctrl_pins[] = {
3676 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3678 static const unsigned int ssi349_ctrl_mux[] = {
3679 SSI_SCK349_MARK, SSI_WS349_MARK,
3681 static const unsigned int ssi4_data_pins[] = {
3685 static const unsigned int ssi4_data_mux[] = {
3688 static const unsigned int ssi4_ctrl_pins[] = {
3690 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3692 static const unsigned int ssi4_ctrl_mux[] = {
3693 SSI_SCK4_MARK, SSI_WS4_MARK,
3695 static const unsigned int ssi5_data_pins[] = {
3699 static const unsigned int ssi5_data_mux[] = {
3702 static const unsigned int ssi5_ctrl_pins[] = {
3704 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3706 static const unsigned int ssi5_ctrl_mux[] = {
3707 SSI_SCK5_MARK, SSI_WS5_MARK,
3709 static const unsigned int ssi6_data_pins[] = {
3713 static const unsigned int ssi6_data_mux[] = {
3716 static const unsigned int ssi6_ctrl_pins[] = {
3718 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3720 static const unsigned int ssi6_ctrl_mux[] = {
3721 SSI_SCK6_MARK, SSI_WS6_MARK,
3723 static const unsigned int ssi7_data_pins[] = {
3727 static const unsigned int ssi7_data_mux[] = {
3730 static const unsigned int ssi78_ctrl_pins[] = {
3732 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3734 static const unsigned int ssi78_ctrl_mux[] = {
3735 SSI_SCK78_MARK, SSI_WS78_MARK,
3737 static const unsigned int ssi8_data_pins[] = {
3741 static const unsigned int ssi8_data_mux[] = {
3744 static const unsigned int ssi9_data_a_pins[] = {
3748 static const unsigned int ssi9_data_a_mux[] = {
3751 static const unsigned int ssi9_data_b_pins[] = {
3755 static const unsigned int ssi9_data_b_mux[] = {
3758 static const unsigned int ssi9_ctrl_a_pins[] = {
3760 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3762 static const unsigned int ssi9_ctrl_a_mux[] = {
3763 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3765 static const unsigned int ssi9_ctrl_b_pins[] = {
3767 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3769 static const unsigned int ssi9_ctrl_b_mux[] = {
3770 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3773 /* - TMU -------------------------------------------------------------------- */
3774 static const unsigned int tmu_tclk1_a_pins[] = {
3778 static const unsigned int tmu_tclk1_a_mux[] = {
3781 static const unsigned int tmu_tclk1_b_pins[] = {
3785 static const unsigned int tmu_tclk1_b_mux[] = {
3788 static const unsigned int tmu_tclk2_a_pins[] = {
3792 static const unsigned int tmu_tclk2_a_mux[] = {
3795 static const unsigned int tmu_tclk2_b_pins[] = {
3799 static const unsigned int tmu_tclk2_b_mux[] = {
3803 /* - TPU ------------------------------------------------------------------- */
3804 static const unsigned int tpu_to0_pins[] = {
3808 static const unsigned int tpu_to0_mux[] = {
3811 static const unsigned int tpu_to1_pins[] = {
3815 static const unsigned int tpu_to1_mux[] = {
3818 static const unsigned int tpu_to2_pins[] = {
3822 static const unsigned int tpu_to2_mux[] = {
3825 static const unsigned int tpu_to3_pins[] = {
3829 static const unsigned int tpu_to3_mux[] = {
3833 /* - USB0 ------------------------------------------------------------------- */
3834 static const unsigned int usb0_pins[] = {
3836 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3838 static const unsigned int usb0_mux[] = {
3839 USB0_PWEN_MARK, USB0_OVC_MARK,
3841 /* - USB1 ------------------------------------------------------------------- */
3842 static const unsigned int usb1_pins[] = {
3844 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3846 static const unsigned int usb1_mux[] = {
3847 USB1_PWEN_MARK, USB1_OVC_MARK,
3849 /* - USB2 ------------------------------------------------------------------- */
3850 static const unsigned int usb2_pins[] = {
3852 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3854 static const unsigned int usb2_mux[] = {
3855 USB2_PWEN_MARK, USB2_OVC_MARK,
3858 /* - USB30 ------------------------------------------------------------------ */
3859 static const unsigned int usb30_pins[] = {
3861 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3863 static const unsigned int usb30_mux[] = {
3864 USB30_PWEN_MARK, USB30_OVC_MARK,
3866 /* - USB31 ------------------------------------------------------------------ */
3867 static const unsigned int usb31_pins[] = {
3869 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3871 static const unsigned int usb31_mux[] = {
3872 USB31_PWEN_MARK, USB31_OVC_MARK,
3875 static const struct sh_pfc_pin_group pinmux_groups[] = {
3876 SH_PFC_PIN_GROUP(audio_clk_a_a),
3877 SH_PFC_PIN_GROUP(audio_clk_a_b),
3878 SH_PFC_PIN_GROUP(audio_clk_a_c),
3879 SH_PFC_PIN_GROUP(audio_clk_b_a),
3880 SH_PFC_PIN_GROUP(audio_clk_b_b),
3881 SH_PFC_PIN_GROUP(audio_clk_c_a),
3882 SH_PFC_PIN_GROUP(audio_clk_c_b),
3883 SH_PFC_PIN_GROUP(audio_clkout_a),
3884 SH_PFC_PIN_GROUP(audio_clkout_b),
3885 SH_PFC_PIN_GROUP(audio_clkout_c),
3886 SH_PFC_PIN_GROUP(audio_clkout_d),
3887 SH_PFC_PIN_GROUP(audio_clkout1_a),
3888 SH_PFC_PIN_GROUP(audio_clkout1_b),
3889 SH_PFC_PIN_GROUP(audio_clkout2_a),
3890 SH_PFC_PIN_GROUP(audio_clkout2_b),
3891 SH_PFC_PIN_GROUP(audio_clkout3_a),
3892 SH_PFC_PIN_GROUP(audio_clkout3_b),
3893 SH_PFC_PIN_GROUP(avb_link),
3894 SH_PFC_PIN_GROUP(avb_magic),
3895 SH_PFC_PIN_GROUP(avb_phy_int),
3896 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
3897 SH_PFC_PIN_GROUP(avb_mdio),
3898 SH_PFC_PIN_GROUP(avb_mii),
3899 SH_PFC_PIN_GROUP(avb_avtp_pps),
3900 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3901 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3902 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3903 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3904 SH_PFC_PIN_GROUP(can0_data_a),
3905 SH_PFC_PIN_GROUP(can0_data_b),
3906 SH_PFC_PIN_GROUP(can1_data),
3907 SH_PFC_PIN_GROUP(can_clk),
3908 SH_PFC_PIN_GROUP(canfd0_data_a),
3909 SH_PFC_PIN_GROUP(canfd0_data_b),
3910 SH_PFC_PIN_GROUP(canfd1_data),
3911 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3912 SH_PFC_PIN_GROUP(drif0_data0_a),
3913 SH_PFC_PIN_GROUP(drif0_data1_a),
3914 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3915 SH_PFC_PIN_GROUP(drif0_data0_b),
3916 SH_PFC_PIN_GROUP(drif0_data1_b),
3917 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3918 SH_PFC_PIN_GROUP(drif0_data0_c),
3919 SH_PFC_PIN_GROUP(drif0_data1_c),
3920 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3921 SH_PFC_PIN_GROUP(drif1_data0_a),
3922 SH_PFC_PIN_GROUP(drif1_data1_a),
3923 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3924 SH_PFC_PIN_GROUP(drif1_data0_b),
3925 SH_PFC_PIN_GROUP(drif1_data1_b),
3926 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3927 SH_PFC_PIN_GROUP(drif1_data0_c),
3928 SH_PFC_PIN_GROUP(drif1_data1_c),
3929 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3930 SH_PFC_PIN_GROUP(drif2_data0_a),
3931 SH_PFC_PIN_GROUP(drif2_data1_a),
3932 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3933 SH_PFC_PIN_GROUP(drif2_data0_b),
3934 SH_PFC_PIN_GROUP(drif2_data1_b),
3935 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3936 SH_PFC_PIN_GROUP(drif3_data0_a),
3937 SH_PFC_PIN_GROUP(drif3_data1_a),
3938 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3939 SH_PFC_PIN_GROUP(drif3_data0_b),
3940 SH_PFC_PIN_GROUP(drif3_data1_b),
3941 SH_PFC_PIN_GROUP(du_rgb666),
3942 SH_PFC_PIN_GROUP(du_rgb888),
3943 SH_PFC_PIN_GROUP(du_clk_out_0),
3944 SH_PFC_PIN_GROUP(du_clk_out_1),
3945 SH_PFC_PIN_GROUP(du_sync),
3946 SH_PFC_PIN_GROUP(du_oddf),
3947 SH_PFC_PIN_GROUP(du_cde),
3948 SH_PFC_PIN_GROUP(du_disp),
3949 SH_PFC_PIN_GROUP(hscif0_data),
3950 SH_PFC_PIN_GROUP(hscif0_clk),
3951 SH_PFC_PIN_GROUP(hscif0_ctrl),
3952 SH_PFC_PIN_GROUP(hscif1_data_a),
3953 SH_PFC_PIN_GROUP(hscif1_clk_a),
3954 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3955 SH_PFC_PIN_GROUP(hscif1_data_b),
3956 SH_PFC_PIN_GROUP(hscif1_clk_b),
3957 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3958 SH_PFC_PIN_GROUP(hscif2_data_a),
3959 SH_PFC_PIN_GROUP(hscif2_clk_a),
3960 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3961 SH_PFC_PIN_GROUP(hscif2_data_b),
3962 SH_PFC_PIN_GROUP(hscif2_clk_b),
3963 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3964 SH_PFC_PIN_GROUP(hscif3_data_a),
3965 SH_PFC_PIN_GROUP(hscif3_clk),
3966 SH_PFC_PIN_GROUP(hscif3_ctrl),
3967 SH_PFC_PIN_GROUP(hscif3_data_b),
3968 SH_PFC_PIN_GROUP(hscif3_data_c),
3969 SH_PFC_PIN_GROUP(hscif3_data_d),
3970 SH_PFC_PIN_GROUP(hscif4_data_a),
3971 SH_PFC_PIN_GROUP(hscif4_clk),
3972 SH_PFC_PIN_GROUP(hscif4_ctrl),
3973 SH_PFC_PIN_GROUP(hscif4_data_b),
3974 SH_PFC_PIN_GROUP(i2c0),
3975 SH_PFC_PIN_GROUP(i2c1_a),
3976 SH_PFC_PIN_GROUP(i2c1_b),
3977 SH_PFC_PIN_GROUP(i2c2_a),
3978 SH_PFC_PIN_GROUP(i2c2_b),
3979 SH_PFC_PIN_GROUP(i2c3),
3980 SH_PFC_PIN_GROUP(i2c5),
3981 SH_PFC_PIN_GROUP(i2c6_a),
3982 SH_PFC_PIN_GROUP(i2c6_b),
3983 SH_PFC_PIN_GROUP(i2c6_c),
3984 SH_PFC_PIN_GROUP(intc_ex_irq0),
3985 SH_PFC_PIN_GROUP(intc_ex_irq1),
3986 SH_PFC_PIN_GROUP(intc_ex_irq2),
3987 SH_PFC_PIN_GROUP(intc_ex_irq3),
3988 SH_PFC_PIN_GROUP(intc_ex_irq4),
3989 SH_PFC_PIN_GROUP(intc_ex_irq5),
3990 SH_PFC_PIN_GROUP(msiof0_clk),
3991 SH_PFC_PIN_GROUP(msiof0_sync),
3992 SH_PFC_PIN_GROUP(msiof0_ss1),
3993 SH_PFC_PIN_GROUP(msiof0_ss2),
3994 SH_PFC_PIN_GROUP(msiof0_txd),
3995 SH_PFC_PIN_GROUP(msiof0_rxd),
3996 SH_PFC_PIN_GROUP(msiof1_clk_a),
3997 SH_PFC_PIN_GROUP(msiof1_sync_a),
3998 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3999 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4000 SH_PFC_PIN_GROUP(msiof1_txd_a),
4001 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4002 SH_PFC_PIN_GROUP(msiof1_clk_b),
4003 SH_PFC_PIN_GROUP(msiof1_sync_b),
4004 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4005 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4006 SH_PFC_PIN_GROUP(msiof1_txd_b),
4007 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4008 SH_PFC_PIN_GROUP(msiof1_clk_c),
4009 SH_PFC_PIN_GROUP(msiof1_sync_c),
4010 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4011 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4012 SH_PFC_PIN_GROUP(msiof1_txd_c),
4013 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4014 SH_PFC_PIN_GROUP(msiof1_clk_d),
4015 SH_PFC_PIN_GROUP(msiof1_sync_d),
4016 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4017 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4018 SH_PFC_PIN_GROUP(msiof1_txd_d),
4019 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4020 SH_PFC_PIN_GROUP(msiof1_clk_e),
4021 SH_PFC_PIN_GROUP(msiof1_sync_e),
4022 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4023 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4024 SH_PFC_PIN_GROUP(msiof1_txd_e),
4025 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4026 SH_PFC_PIN_GROUP(msiof1_clk_f),
4027 SH_PFC_PIN_GROUP(msiof1_sync_f),
4028 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4029 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4030 SH_PFC_PIN_GROUP(msiof1_txd_f),
4031 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4032 SH_PFC_PIN_GROUP(msiof1_clk_g),
4033 SH_PFC_PIN_GROUP(msiof1_sync_g),
4034 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4035 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4036 SH_PFC_PIN_GROUP(msiof1_txd_g),
4037 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4038 SH_PFC_PIN_GROUP(msiof2_clk_a),
4039 SH_PFC_PIN_GROUP(msiof2_sync_a),
4040 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4041 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4042 SH_PFC_PIN_GROUP(msiof2_txd_a),
4043 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4044 SH_PFC_PIN_GROUP(msiof2_clk_b),
4045 SH_PFC_PIN_GROUP(msiof2_sync_b),
4046 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4047 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4048 SH_PFC_PIN_GROUP(msiof2_txd_b),
4049 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4050 SH_PFC_PIN_GROUP(msiof2_clk_c),
4051 SH_PFC_PIN_GROUP(msiof2_sync_c),
4052 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4053 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4054 SH_PFC_PIN_GROUP(msiof2_txd_c),
4055 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4056 SH_PFC_PIN_GROUP(msiof2_clk_d),
4057 SH_PFC_PIN_GROUP(msiof2_sync_d),
4058 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4059 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4060 SH_PFC_PIN_GROUP(msiof2_txd_d),
4061 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4062 SH_PFC_PIN_GROUP(msiof3_clk_a),
4063 SH_PFC_PIN_GROUP(msiof3_sync_a),
4064 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4065 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4066 SH_PFC_PIN_GROUP(msiof3_txd_a),
4067 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4068 SH_PFC_PIN_GROUP(msiof3_clk_b),
4069 SH_PFC_PIN_GROUP(msiof3_sync_b),
4070 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4071 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4072 SH_PFC_PIN_GROUP(msiof3_txd_b),
4073 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4074 SH_PFC_PIN_GROUP(msiof3_clk_c),
4075 SH_PFC_PIN_GROUP(msiof3_sync_c),
4076 SH_PFC_PIN_GROUP(msiof3_txd_c),
4077 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4078 SH_PFC_PIN_GROUP(msiof3_clk_d),
4079 SH_PFC_PIN_GROUP(msiof3_sync_d),
4080 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4081 SH_PFC_PIN_GROUP(msiof3_txd_d),
4082 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4083 SH_PFC_PIN_GROUP(pwm0),
4084 SH_PFC_PIN_GROUP(pwm1_a),
4085 SH_PFC_PIN_GROUP(pwm1_b),
4086 SH_PFC_PIN_GROUP(pwm2_a),
4087 SH_PFC_PIN_GROUP(pwm2_b),
4088 SH_PFC_PIN_GROUP(pwm3_a),
4089 SH_PFC_PIN_GROUP(pwm3_b),
4090 SH_PFC_PIN_GROUP(pwm4_a),
4091 SH_PFC_PIN_GROUP(pwm4_b),
4092 SH_PFC_PIN_GROUP(pwm5_a),
4093 SH_PFC_PIN_GROUP(pwm5_b),
4094 SH_PFC_PIN_GROUP(pwm6_a),
4095 SH_PFC_PIN_GROUP(pwm6_b),
4096 SH_PFC_PIN_GROUP(qspi0_ctrl),
4097 SH_PFC_PIN_GROUP(qspi0_data2),
4098 SH_PFC_PIN_GROUP(qspi0_data4),
4099 SH_PFC_PIN_GROUP(qspi1_ctrl),
4100 SH_PFC_PIN_GROUP(qspi1_data2),
4101 SH_PFC_PIN_GROUP(qspi1_data4),
4102 SH_PFC_PIN_GROUP(sata0_devslp_a),
4103 SH_PFC_PIN_GROUP(sata0_devslp_b),
4104 SH_PFC_PIN_GROUP(scif0_data),
4105 SH_PFC_PIN_GROUP(scif0_clk),
4106 SH_PFC_PIN_GROUP(scif0_ctrl),
4107 SH_PFC_PIN_GROUP(scif1_data_a),
4108 SH_PFC_PIN_GROUP(scif1_clk),
4109 SH_PFC_PIN_GROUP(scif1_ctrl),
4110 SH_PFC_PIN_GROUP(scif1_data_b),
4111 SH_PFC_PIN_GROUP(scif2_data_a),
4112 SH_PFC_PIN_GROUP(scif2_clk),
4113 SH_PFC_PIN_GROUP(scif2_data_b),
4114 SH_PFC_PIN_GROUP(scif3_data_a),
4115 SH_PFC_PIN_GROUP(scif3_clk),
4116 SH_PFC_PIN_GROUP(scif3_ctrl),
4117 SH_PFC_PIN_GROUP(scif3_data_b),
4118 SH_PFC_PIN_GROUP(scif4_data_a),
4119 SH_PFC_PIN_GROUP(scif4_clk_a),
4120 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4121 SH_PFC_PIN_GROUP(scif4_data_b),
4122 SH_PFC_PIN_GROUP(scif4_clk_b),
4123 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4124 SH_PFC_PIN_GROUP(scif4_data_c),
4125 SH_PFC_PIN_GROUP(scif4_clk_c),
4126 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4127 SH_PFC_PIN_GROUP(scif5_data),
4128 SH_PFC_PIN_GROUP(scif5_clk),
4129 SH_PFC_PIN_GROUP(scif_clk_a),
4130 SH_PFC_PIN_GROUP(scif_clk_b),
4131 SH_PFC_PIN_GROUP(sdhi0_data1),
4132 SH_PFC_PIN_GROUP(sdhi0_data4),
4133 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4134 SH_PFC_PIN_GROUP(sdhi0_cd),
4135 SH_PFC_PIN_GROUP(sdhi0_wp),
4136 SH_PFC_PIN_GROUP(sdhi1_data1),
4137 SH_PFC_PIN_GROUP(sdhi1_data4),
4138 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4139 SH_PFC_PIN_GROUP(sdhi1_cd),
4140 SH_PFC_PIN_GROUP(sdhi1_wp),
4141 SH_PFC_PIN_GROUP(sdhi2_data1),
4142 SH_PFC_PIN_GROUP(sdhi2_data4),
4143 SH_PFC_PIN_GROUP(sdhi2_data8),
4144 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4145 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4146 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4147 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4148 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4149 SH_PFC_PIN_GROUP(sdhi2_ds),
4150 SH_PFC_PIN_GROUP(sdhi3_data1),
4151 SH_PFC_PIN_GROUP(sdhi3_data4),
4152 SH_PFC_PIN_GROUP(sdhi3_data8),
4153 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4154 SH_PFC_PIN_GROUP(sdhi3_cd),
4155 SH_PFC_PIN_GROUP(sdhi3_wp),
4156 SH_PFC_PIN_GROUP(sdhi3_ds),
4157 SH_PFC_PIN_GROUP(ssi0_data),
4158 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4159 SH_PFC_PIN_GROUP(ssi1_data_a),
4160 SH_PFC_PIN_GROUP(ssi1_data_b),
4161 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4162 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4163 SH_PFC_PIN_GROUP(ssi2_data_a),
4164 SH_PFC_PIN_GROUP(ssi2_data_b),
4165 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4166 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4167 SH_PFC_PIN_GROUP(ssi3_data),
4168 SH_PFC_PIN_GROUP(ssi349_ctrl),
4169 SH_PFC_PIN_GROUP(ssi4_data),
4170 SH_PFC_PIN_GROUP(ssi4_ctrl),
4171 SH_PFC_PIN_GROUP(ssi5_data),
4172 SH_PFC_PIN_GROUP(ssi5_ctrl),
4173 SH_PFC_PIN_GROUP(ssi6_data),
4174 SH_PFC_PIN_GROUP(ssi6_ctrl),
4175 SH_PFC_PIN_GROUP(ssi7_data),
4176 SH_PFC_PIN_GROUP(ssi78_ctrl),
4177 SH_PFC_PIN_GROUP(ssi8_data),
4178 SH_PFC_PIN_GROUP(ssi9_data_a),
4179 SH_PFC_PIN_GROUP(ssi9_data_b),
4180 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4181 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4182 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4183 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4184 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4185 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4186 SH_PFC_PIN_GROUP(tpu_to0),
4187 SH_PFC_PIN_GROUP(tpu_to1),
4188 SH_PFC_PIN_GROUP(tpu_to2),
4189 SH_PFC_PIN_GROUP(tpu_to3),
4190 SH_PFC_PIN_GROUP(usb0),
4191 SH_PFC_PIN_GROUP(usb1),
4192 SH_PFC_PIN_GROUP(usb2),
4193 SH_PFC_PIN_GROUP(usb30),
4194 SH_PFC_PIN_GROUP(usb31),
4197 static const char * const audio_clk_groups[] = {
4217 static const char * const avb_groups[] = {
4221 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4226 "avb_avtp_capture_a",
4228 "avb_avtp_capture_b",
4231 static const char * const can0_groups[] = {
4236 static const char * const can1_groups[] = {
4240 static const char * const can_clk_groups[] = {
4244 static const char * const canfd0_groups[] = {
4249 static const char * const canfd1_groups[] = {
4253 static const char * const drif0_groups[] = {
4265 static const char * const drif1_groups[] = {
4277 static const char * const drif2_groups[] = {
4286 static const char * const drif3_groups[] = {
4295 static const char * const du_groups[] = {
4306 static const char * const hscif0_groups[] = {
4312 static const char * const hscif1_groups[] = {
4321 static const char * const hscif2_groups[] = {
4330 static const char * const hscif3_groups[] = {
4339 static const char * const hscif4_groups[] = {
4346 static const char * const i2c0_groups[] = {
4350 static const char * const i2c1_groups[] = {
4355 static const char * const i2c2_groups[] = {
4360 static const char * const i2c3_groups[] = {
4364 static const char * const i2c5_groups[] = {
4368 static const char * const i2c6_groups[] = {
4374 static const char * const intc_ex_groups[] = {
4383 static const char * const msiof0_groups[] = {
4392 static const char * const msiof1_groups[] = {
4437 static const char * const msiof2_groups[] = {
4464 static const char * const msiof3_groups[] = {
4488 static const char * const pwm0_groups[] = {
4492 static const char * const pwm1_groups[] = {
4497 static const char * const pwm2_groups[] = {
4502 static const char * const pwm3_groups[] = {
4507 static const char * const pwm4_groups[] = {
4512 static const char * const pwm5_groups[] = {
4517 static const char * const pwm6_groups[] = {
4522 static const char * const qspi0_groups[] = {
4528 static const char * const qspi1_groups[] = {
4534 static const char * const sata0_groups[] = {
4539 static const char * const scif0_groups[] = {
4545 static const char * const scif1_groups[] = {
4552 static const char * const scif2_groups[] = {
4558 static const char * const scif3_groups[] = {
4565 static const char * const scif4_groups[] = {
4577 static const char * const scif5_groups[] = {
4582 static const char * const scif_clk_groups[] = {
4587 static const char * const sdhi0_groups[] = {
4595 static const char * const sdhi1_groups[] = {
4603 static const char * const sdhi2_groups[] = {
4615 static const char * const sdhi3_groups[] = {
4625 static const char * const ssi_groups[] = {
4653 static const char * const tmu_groups[] = {
4660 static const char * const tpu_groups[] = {
4667 static const char * const usb0_groups[] = {
4671 static const char * const usb1_groups[] = {
4675 static const char * const usb2_groups[] = {
4679 static const char * const usb30_groups[] = {
4683 static const char * const usb31_groups[] = {
4687 static const struct sh_pfc_function pinmux_functions[] = {
4688 SH_PFC_FUNCTION(audio_clk),
4689 SH_PFC_FUNCTION(avb),
4690 SH_PFC_FUNCTION(can0),
4691 SH_PFC_FUNCTION(can1),
4692 SH_PFC_FUNCTION(can_clk),
4693 SH_PFC_FUNCTION(canfd0),
4694 SH_PFC_FUNCTION(canfd1),
4695 SH_PFC_FUNCTION(drif0),
4696 SH_PFC_FUNCTION(drif1),
4697 SH_PFC_FUNCTION(drif2),
4698 SH_PFC_FUNCTION(drif3),
4699 SH_PFC_FUNCTION(du),
4700 SH_PFC_FUNCTION(hscif0),
4701 SH_PFC_FUNCTION(hscif1),
4702 SH_PFC_FUNCTION(hscif2),
4703 SH_PFC_FUNCTION(hscif3),
4704 SH_PFC_FUNCTION(hscif4),
4705 SH_PFC_FUNCTION(i2c0),
4706 SH_PFC_FUNCTION(i2c1),
4707 SH_PFC_FUNCTION(i2c2),
4708 SH_PFC_FUNCTION(i2c3),
4709 SH_PFC_FUNCTION(i2c5),
4710 SH_PFC_FUNCTION(i2c6),
4711 SH_PFC_FUNCTION(intc_ex),
4712 SH_PFC_FUNCTION(msiof0),
4713 SH_PFC_FUNCTION(msiof1),
4714 SH_PFC_FUNCTION(msiof2),
4715 SH_PFC_FUNCTION(msiof3),
4716 SH_PFC_FUNCTION(pwm0),
4717 SH_PFC_FUNCTION(pwm1),
4718 SH_PFC_FUNCTION(pwm2),
4719 SH_PFC_FUNCTION(pwm3),
4720 SH_PFC_FUNCTION(pwm4),
4721 SH_PFC_FUNCTION(pwm5),
4722 SH_PFC_FUNCTION(pwm6),
4723 SH_PFC_FUNCTION(qspi0),
4724 SH_PFC_FUNCTION(qspi1),
4725 SH_PFC_FUNCTION(sata0),
4726 SH_PFC_FUNCTION(scif0),
4727 SH_PFC_FUNCTION(scif1),
4728 SH_PFC_FUNCTION(scif2),
4729 SH_PFC_FUNCTION(scif3),
4730 SH_PFC_FUNCTION(scif4),
4731 SH_PFC_FUNCTION(scif5),
4732 SH_PFC_FUNCTION(scif_clk),
4733 SH_PFC_FUNCTION(sdhi0),
4734 SH_PFC_FUNCTION(sdhi1),
4735 SH_PFC_FUNCTION(sdhi2),
4736 SH_PFC_FUNCTION(sdhi3),
4737 SH_PFC_FUNCTION(ssi),
4738 SH_PFC_FUNCTION(tmu),
4739 SH_PFC_FUNCTION(tpu),
4740 SH_PFC_FUNCTION(usb0),
4741 SH_PFC_FUNCTION(usb1),
4742 SH_PFC_FUNCTION(usb2),
4743 SH_PFC_FUNCTION(usb30),
4744 SH_PFC_FUNCTION(usb31),
4747 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4748 #define F_(x, y) FN_##y
4749 #define FM(x) FN_##x
4750 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
4767 GP_0_15_FN, GPSR0_15,
4768 GP_0_14_FN, GPSR0_14,
4769 GP_0_13_FN, GPSR0_13,
4770 GP_0_12_FN, GPSR0_12,
4771 GP_0_11_FN, GPSR0_11,
4772 GP_0_10_FN, GPSR0_10,
4782 GP_0_0_FN, GPSR0_0, ))
4784 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
4789 GP_1_27_FN, GPSR1_27,
4790 GP_1_26_FN, GPSR1_26,
4791 GP_1_25_FN, GPSR1_25,
4792 GP_1_24_FN, GPSR1_24,
4793 GP_1_23_FN, GPSR1_23,
4794 GP_1_22_FN, GPSR1_22,
4795 GP_1_21_FN, GPSR1_21,
4796 GP_1_20_FN, GPSR1_20,
4797 GP_1_19_FN, GPSR1_19,
4798 GP_1_18_FN, GPSR1_18,
4799 GP_1_17_FN, GPSR1_17,
4800 GP_1_16_FN, GPSR1_16,
4801 GP_1_15_FN, GPSR1_15,
4802 GP_1_14_FN, GPSR1_14,
4803 GP_1_13_FN, GPSR1_13,
4804 GP_1_12_FN, GPSR1_12,
4805 GP_1_11_FN, GPSR1_11,
4806 GP_1_10_FN, GPSR1_10,
4816 GP_1_0_FN, GPSR1_0, ))
4818 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
4836 GP_2_14_FN, GPSR2_14,
4837 GP_2_13_FN, GPSR2_13,
4838 GP_2_12_FN, GPSR2_12,
4839 GP_2_11_FN, GPSR2_11,
4840 GP_2_10_FN, GPSR2_10,
4850 GP_2_0_FN, GPSR2_0, ))
4852 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
4869 GP_3_15_FN, GPSR3_15,
4870 GP_3_14_FN, GPSR3_14,
4871 GP_3_13_FN, GPSR3_13,
4872 GP_3_12_FN, GPSR3_12,
4873 GP_3_11_FN, GPSR3_11,
4874 GP_3_10_FN, GPSR3_10,
4884 GP_3_0_FN, GPSR3_0, ))
4886 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
4901 GP_4_17_FN, GPSR4_17,
4902 GP_4_16_FN, GPSR4_16,
4903 GP_4_15_FN, GPSR4_15,
4904 GP_4_14_FN, GPSR4_14,
4905 GP_4_13_FN, GPSR4_13,
4906 GP_4_12_FN, GPSR4_12,
4907 GP_4_11_FN, GPSR4_11,
4908 GP_4_10_FN, GPSR4_10,
4918 GP_4_0_FN, GPSR4_0, ))
4920 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
4927 GP_5_25_FN, GPSR5_25,
4928 GP_5_24_FN, GPSR5_24,
4929 GP_5_23_FN, GPSR5_23,
4930 GP_5_22_FN, GPSR5_22,
4931 GP_5_21_FN, GPSR5_21,
4932 GP_5_20_FN, GPSR5_20,
4933 GP_5_19_FN, GPSR5_19,
4934 GP_5_18_FN, GPSR5_18,
4935 GP_5_17_FN, GPSR5_17,
4936 GP_5_16_FN, GPSR5_16,
4937 GP_5_15_FN, GPSR5_15,
4938 GP_5_14_FN, GPSR5_14,
4939 GP_5_13_FN, GPSR5_13,
4940 GP_5_12_FN, GPSR5_12,
4941 GP_5_11_FN, GPSR5_11,
4942 GP_5_10_FN, GPSR5_10,
4952 GP_5_0_FN, GPSR5_0, ))
4954 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
4955 GP_6_31_FN, GPSR6_31,
4956 GP_6_30_FN, GPSR6_30,
4957 GP_6_29_FN, GPSR6_29,
4958 GP_6_28_FN, GPSR6_28,
4959 GP_6_27_FN, GPSR6_27,
4960 GP_6_26_FN, GPSR6_26,
4961 GP_6_25_FN, GPSR6_25,
4962 GP_6_24_FN, GPSR6_24,
4963 GP_6_23_FN, GPSR6_23,
4964 GP_6_22_FN, GPSR6_22,
4965 GP_6_21_FN, GPSR6_21,
4966 GP_6_20_FN, GPSR6_20,
4967 GP_6_19_FN, GPSR6_19,
4968 GP_6_18_FN, GPSR6_18,
4969 GP_6_17_FN, GPSR6_17,
4970 GP_6_16_FN, GPSR6_16,
4971 GP_6_15_FN, GPSR6_15,
4972 GP_6_14_FN, GPSR6_14,
4973 GP_6_13_FN, GPSR6_13,
4974 GP_6_12_FN, GPSR6_12,
4975 GP_6_11_FN, GPSR6_11,
4976 GP_6_10_FN, GPSR6_10,
4986 GP_6_0_FN, GPSR6_0, ))
4988 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
5020 GP_7_0_FN, GPSR7_0, ))
5026 #define FM(x) FN_##x,
5027 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5037 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5047 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5057 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5067 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5077 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5087 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5097 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
5107 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5117 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5127 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5137 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5147 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5157 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5167 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5177 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5187 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5197 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5198 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5199 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5200 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5201 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5202 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5203 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5211 #define FM(x) FN_##x,
5212 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5213 GROUP(1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1,
5214 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1),
5216 0, 0, /* RESERVED 31 */
5238 0, 0, /* RESERVED 0 */ ))
5240 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5241 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5242 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5259 0, 0, 0, 0, /* RESERVED 8, 7 */
5268 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5269 GROUP(1, 1, 1, 1, 4, 4, 4, 4, 4, 4, 1, 2, 1),
5276 /* RESERVED 27, 26, 25, 24 */
5277 0, 0, 0, 0, 0, 0, 0, 0,
5278 0, 0, 0, 0, 0, 0, 0, 0,
5279 /* RESERVED 23, 22, 21, 20 */
5280 0, 0, 0, 0, 0, 0, 0, 0,
5281 0, 0, 0, 0, 0, 0, 0, 0,
5282 /* RESERVED 19, 18, 17, 16 */
5283 0, 0, 0, 0, 0, 0, 0, 0,
5284 0, 0, 0, 0, 0, 0, 0, 0,
5285 /* RESERVED 15, 14, 13, 12 */
5286 0, 0, 0, 0, 0, 0, 0, 0,
5287 0, 0, 0, 0, 0, 0, 0, 0,
5288 /* RESERVED 11, 10, 9, 8 */
5289 0, 0, 0, 0, 0, 0, 0, 0,
5290 0, 0, 0, 0, 0, 0, 0, 0,
5291 /* RESERVED 7, 6, 5, 4 */
5292 0, 0, 0, 0, 0, 0, 0, 0,
5293 0, 0, 0, 0, 0, 0, 0, 0,
5303 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5304 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5305 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5306 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5307 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5308 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5309 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5310 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5311 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5312 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
5314 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5315 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5316 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5317 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5318 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5319 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5320 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5321 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5322 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
5324 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5325 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5326 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5327 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5328 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5329 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5330 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5331 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5332 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
5334 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5335 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5336 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5337 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5338 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5339 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5340 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5341 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5342 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5344 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5345 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5346 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5347 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5348 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5349 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5350 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5351 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5352 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5354 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5355 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5356 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5357 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5358 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5359 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5360 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5361 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5362 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5364 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5365 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5366 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5367 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5368 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5369 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5370 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5371 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5372 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5374 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5375 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5376 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5377 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5378 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5379 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5380 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5381 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5382 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5384 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5385 { PIN_CLKOUT, 28, 3 }, /* CLKOUT */
5386 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5387 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5388 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5389 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5390 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5391 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5392 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5394 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5395 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5396 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
5397 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5398 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5399 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5400 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5401 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5402 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5404 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5405 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5406 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5407 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5408 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5409 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5410 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5411 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5412 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5414 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5415 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5416 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5417 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5418 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5419 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5420 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5421 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5422 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
5424 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5425 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5426 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
5427 { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
5428 { PIN_TMS, 4, 2 }, /* TMS */
5430 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5431 { PIN_TDO, 28, 2 }, /* TDO */
5432 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5433 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5434 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5435 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5436 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5437 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5438 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5440 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5441 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5442 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5443 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5444 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5445 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5446 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5447 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5448 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5450 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5451 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5452 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5453 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5454 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5455 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5456 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5457 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5458 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5460 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5461 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5462 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5463 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5464 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5465 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5466 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5467 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5468 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5470 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5471 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5472 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5473 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5474 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5475 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5476 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5477 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5478 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5480 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5481 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5482 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5483 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5484 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5485 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5486 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5487 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5488 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5490 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5491 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5492 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5493 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5494 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5495 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5496 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5497 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5498 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5500 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5501 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5502 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5503 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5504 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5505 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5506 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5507 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
5508 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5510 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5511 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5512 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5513 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5514 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5515 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5516 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5517 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5518 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5520 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5521 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5522 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5523 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5524 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5525 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5526 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5527 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5528 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5530 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5531 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5532 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5533 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5534 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5535 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5536 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5537 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5538 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5540 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5541 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5542 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5543 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5544 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5545 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5546 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */
5547 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */
5557 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5558 [POCCTRL] = { 0xe6060380, },
5559 [TDSELCTRL] = { 0xe60603c0, },
5563 static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5568 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5570 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5573 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5574 bit = (pin & 0x1f) + 12;
5579 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5580 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5581 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5582 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5583 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5584 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5585 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5586 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5587 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5588 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5589 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5590 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5591 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5592 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5593 [12] = PIN_RPC_INT_N, /* RPC_INT# */
5594 [13] = PIN_RPC_WP_N, /* RPC_WP# */
5595 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
5596 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
5597 [16] = PIN_AVB_RXC, /* AVB_RXC */
5598 [17] = PIN_AVB_RD0, /* AVB_RD0 */
5599 [18] = PIN_AVB_RD1, /* AVB_RD1 */
5600 [19] = PIN_AVB_RD2, /* AVB_RD2 */
5601 [20] = PIN_AVB_RD3, /* AVB_RD3 */
5602 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5603 [22] = PIN_AVB_TXC, /* AVB_TXC */
5604 [23] = PIN_AVB_TD0, /* AVB_TD0 */
5605 [24] = PIN_AVB_TD1, /* AVB_TD1 */
5606 [25] = PIN_AVB_TD2, /* AVB_TD2 */
5607 [26] = PIN_AVB_TD3, /* AVB_TD3 */
5608 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
5609 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
5610 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5611 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5612 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5614 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5615 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5616 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5617 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5618 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5619 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5620 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5621 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5622 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5623 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5624 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5625 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5626 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5627 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5628 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5629 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5630 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5631 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5632 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5633 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5634 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5635 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5636 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5637 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5638 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5639 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5640 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5641 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5642 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5643 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5644 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5645 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5646 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5648 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5649 [ 0] = PIN_CLKOUT, /* CLKOUT */
5650 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5651 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */
5652 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5653 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5654 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5655 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5656 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5657 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5658 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
5659 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5660 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5661 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5662 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5663 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5664 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5665 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5666 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5667 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5668 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5669 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5670 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5671 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5672 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5673 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5674 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5675 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5676 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5677 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
5678 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5679 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
5680 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
5682 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5683 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
5684 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
5685 [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
5686 [ 3] = PIN_EXTALR, /* EXTALR*/
5687 [ 4] = PIN_TRST_N, /* TRST# */
5688 [ 5] = PIN_TCK, /* TCK */
5689 [ 6] = PIN_TMS, /* TMS */
5690 [ 7] = PIN_TDI, /* TDI */
5691 [ 8] = SH_PFC_PIN_NONE,
5692 [ 9] = PIN_ASEBRK, /* ASEBRK */
5693 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5694 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5695 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5696 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5697 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5698 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5699 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5700 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5701 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5702 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5703 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5704 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5705 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5706 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5707 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5708 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5709 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5710 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5711 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5712 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5713 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
5714 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5716 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5717 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
5718 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
5719 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
5720 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
5721 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
5722 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
5723 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
5724 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
5725 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5726 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5727 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5728 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5729 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
5730 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5731 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5732 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5733 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
5734 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5735 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5736 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5737 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
5738 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5739 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5740 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
5741 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
5742 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
5743 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
5744 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
5745 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
5746 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
5747 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
5748 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
5750 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5751 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
5752 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
5753 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
5754 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
5755 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
5756 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
5757 [ 6] = PIN_MLB_REF, /* MLB_REF */
5758 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5759 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5760 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5761 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
5762 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
5763 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5764 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5765 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5766 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
5767 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
5768 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5769 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5770 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5771 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5772 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5773 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5774 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5775 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
5776 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
5777 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
5778 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
5779 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
5780 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
5781 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
5782 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
5784 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5785 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
5786 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
5787 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
5788 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
5789 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
5790 [ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */
5791 [ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */
5792 [ 7] = SH_PFC_PIN_NONE,
5793 [ 8] = SH_PFC_PIN_NONE,
5794 [ 9] = SH_PFC_PIN_NONE,
5795 [10] = SH_PFC_PIN_NONE,
5796 [11] = SH_PFC_PIN_NONE,
5797 [12] = SH_PFC_PIN_NONE,
5798 [13] = SH_PFC_PIN_NONE,
5799 [14] = SH_PFC_PIN_NONE,
5800 [15] = SH_PFC_PIN_NONE,
5801 [16] = SH_PFC_PIN_NONE,
5802 [17] = SH_PFC_PIN_NONE,
5803 [18] = SH_PFC_PIN_NONE,
5804 [19] = SH_PFC_PIN_NONE,
5805 [20] = SH_PFC_PIN_NONE,
5806 [21] = SH_PFC_PIN_NONE,
5807 [22] = SH_PFC_PIN_NONE,
5808 [23] = SH_PFC_PIN_NONE,
5809 [24] = SH_PFC_PIN_NONE,
5810 [25] = SH_PFC_PIN_NONE,
5811 [26] = SH_PFC_PIN_NONE,
5812 [27] = SH_PFC_PIN_NONE,
5813 [28] = SH_PFC_PIN_NONE,
5814 [29] = SH_PFC_PIN_NONE,
5815 [30] = SH_PFC_PIN_NONE,
5816 [31] = SH_PFC_PIN_NONE,
5821 static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
5822 .pin_to_pocctrl = r8a77950_pin_to_pocctrl,
5823 .get_bias = rcar_pinmux_get_bias,
5824 .set_bias = rcar_pinmux_set_bias,
5827 const struct sh_pfc_soc_info r8a77950_pinmux_info = {
5828 .name = "r8a77950_pfc",
5829 .ops = &r8a77950_pinmux_ops,
5830 .unlock_reg = 0xe6060000, /* PMMR */
5832 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5834 .pins = pinmux_pins,
5835 .nr_pins = ARRAY_SIZE(pinmux_pins),
5836 .groups = pinmux_groups,
5837 .nr_groups = ARRAY_SIZE(pinmux_groups),
5838 .functions = pinmux_functions,
5839 .nr_functions = ARRAY_SIZE(pinmux_functions),
5841 .cfg_regs = pinmux_config_regs,
5842 .drive_regs = pinmux_drive_regs,
5843 .bias_regs = pinmux_bias_regs,
5844 .ioctrl_regs = pinmux_ioctrl_regs,
5846 .pinmux_data = pinmux_data,
5847 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
projects / linux-2.6-microblaze.git / blob