drivers/pinctrl/renesas/pfc-r8a7792.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a7792 processor support - PFC hardware block.
   4  *
   5  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   6  * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
   7  */
   8
   9 #include <linux/kernel.h>
  10
  11 #include "sh_pfc.h"
  12
  13 #define CPU_ALL_GP(fn, sfx)                                             \
  14         PORT_GP_CFG_29(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  15         PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  16         PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  17         PORT_GP_CFG_28(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  18         PORT_GP_CFG_17(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  19         PORT_GP_CFG_17(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  20         PORT_GP_CFG_17(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  21         PORT_GP_CFG_17(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  22         PORT_GP_CFG_17(8, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  23         PORT_GP_CFG_17(9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  24         PORT_GP_CFG_32(10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),            \
  25         PORT_GP_CFG_30(11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
  26
  27 #define CPU_ALL_NOGP(fn)                                                \
  28         PIN_NOGP_CFG(DU0_DOTCLKIN, "DU0_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \
  29         PIN_NOGP_CFG(DU0_DOTCLKOUT, "DU0_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP),       \
  30         PIN_NOGP_CFG(DU1_DOTCLKIN, "DU1_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \
  31         PIN_NOGP_CFG(DU1_DOTCLKOUT, "DU1_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP),       \
  32         PIN_NOGP_CFG(EDBGREQ, "EDBGREQ", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
  33         PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),           \
  34         PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),           \
  35         PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),           \
  36         PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
  37
  38 enum {
  39         PINMUX_RESERVED = 0,
  40
  41         PINMUX_DATA_BEGIN,
  42         GP_ALL(DATA),
  43         PINMUX_DATA_END,
  44
  45         PINMUX_FUNCTION_BEGIN,
  46         GP_ALL(FN),
  47
  48         /* GPSR0 */
  49         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  50         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  51         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
  52         FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
  53         FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
  54         FN_IP1_3, FN_IP1_4,
  55
  56         /* GPSR1 */
  57         FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
  58         FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
  59         FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
  60         FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
  61         FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
  62         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
  63
  64         /* GPSR2 */
  65         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
  66         FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
  67         FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
  68         FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
  69
  70         /* GPSR3 */
  71         FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
  72         FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
  73         FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
  74         FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
  75         FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
  76
  77         /* GPSR4 */
  78         FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
  79         FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
  80         FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
  81         FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
  82         FN_VI0_FIELD,
  83
  84         /* GPSR5 */
  85         FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
  86         FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
  87         FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
  88         FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
  89         FN_VI1_FIELD,
  90
  91         /* GPSR6 */
  92         FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
  93         FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
  94         FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
  95
  96         /* GPSR7 */
  97         FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
  98         FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
  99         FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
 100
 101         /* GPSR8 */
 102         FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
 103         FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
 104         FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
 105
 106         /* GPSR9 */
 107         FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
 108         FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
 109         FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
 110
 111         /* GPSR10 */
 112         FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
 113         FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
 114         FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
 115         FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
 116         FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
 117         FN_CAN1_TX, FN_CAN1_RX,
 118
 119         /* GPSR11 */
 120         FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
 121         FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
 122         FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
 123         FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
 124         FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
 125         FN_ADICHS2, FN_AVS1, FN_AVS2,
 126
 127         /* IPSR0 */
 128         FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
 129         FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
 130         FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
 131         FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
 132         FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
 133         FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
 134         FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
 135         FN_DU0_DB7_C5,
 136
 137         /* IPSR1 */
 138         FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
 139         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
 140         FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
 141         FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
 142         FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
 143         FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
 144         FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
 145         FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
 146
 147         /* IPSR2 */
 148         FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
 149         FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
 150         FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
 151         FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
 152         FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
 153         FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
 154         FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
 155         FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
 156         FN_VI2_FIELD, FN_AVB_TXD2,
 157
 158         /* IPSR3 */
 159         FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
 160         FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
 161         FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
 162         FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
 163         FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
 164         FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
 165         FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
 166         FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
 167
 168         /* IPSR4 */
 169         FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
 170         FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
 171         FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
 172         FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
 173         FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
 174         FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
 175         FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
 176         FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
 177         FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
 178         FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
 179         FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
 180         FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
 181         FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
 182
 183         /* IPSR5 */
 184         FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
 185         FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
 186         FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
 187         FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
 188         FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
 189         FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
 190
 191         /* IPSR6 */
 192         FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
 193         FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
 194         FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
 195         FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
 196         FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
 197         FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
 198
 199         /* IPSR7 */
 200         FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
 201         FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
 202         FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
 203         FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
 204         FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
 205         FN_AUDIO_CLKA, FN_AUDIO_CLKB,
 206
 207         /* MOD_SEL */
 208         FN_SEL_VI1_0, FN_SEL_VI1_1,
 209         PINMUX_FUNCTION_END,
 210
 211         PINMUX_MARK_BEGIN,
 212         DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
 213         DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
 214         DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 215         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
 216         DU1_DISP_MARK, DU1_CDE_MARK,
 217
 218         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
 219         D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
 220         D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
 221         A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
 222         A12_MARK, A13_MARK, A14_MARK, A15_MARK,
 223
 224         A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
 225         EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
 226         EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
 227         WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
 228         IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
 229
 230         VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
 231         VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
 232         VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
 233         VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
 234         VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
 235         VI0_FIELD_MARK,
 236
 237         VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
 238         VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
 239         VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
 240         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
 241         VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
 242         VI1_FIELD_MARK,
 243
 244         VI3_D10_Y2_MARK, VI3_FIELD_MARK,
 245
 246         VI4_CLK_MARK,
 247
 248         VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
 249         VI5_FIELD_MARK,
 250
 251         HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
 252         TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
 253         TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
 254         CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
 255
 256         SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
 257         SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
 258         ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
 259         ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
 260
 261         /* IPSR0 */
 262         DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
 263         DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
 264         DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
 265         DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
 266         DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
 267         DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
 268         DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
 269         DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
 270
 271         /* IPSR1 */
 272         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
 273         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
 274         DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
 275         DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
 276         DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
 277         DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
 278         A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
 279         A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
 280
 281         /* IPSR2 */
 282         VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
 283         VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
 284         VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
 285         VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
 286         VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
 287         VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
 288         VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
 289         VI2_D10_Y2_MARK, AVB_TXD0_MARK,
 290         VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
 291
 292         /* IPSR3 */
 293         VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
 294         VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
 295         VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
 296         VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
 297         VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
 298         VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
 299         VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
 300         VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
 301
 302         /* IPSR4 */
 303         VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
 304         VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
 305         RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
 306         VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
 307         VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
 308         VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
 309         VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
 310         VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
 311         VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
 312         VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
 313         VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
 314
 315         /* IPSR5 */
 316         VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
 317         VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
 318         VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
 319         VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
 320         VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
 321         VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
 322         VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
 323
 324         /* IPSR6 */
 325         MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
 326         MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
 327         MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
 328         MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
 329         DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
 330         RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
 331         RX3_MARK,
 332
 333         /* IPSR7 */
 334         PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
 335         FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
 336         PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
 337         SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
 338         SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
 339         AUDIO_CLKB_MARK,
 340         PINMUX_MARK_END,
 341 };
 342
 343 static const u16 pinmux_data[] = {
 344         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 345
 346         PINMUX_SINGLE(DU1_DB2_C0_DATA12),
 347         PINMUX_SINGLE(DU1_DB3_C1_DATA13),
 348         PINMUX_SINGLE(DU1_DB4_C2_DATA14),
 349         PINMUX_SINGLE(DU1_DB5_C3_DATA15),
 350         PINMUX_SINGLE(DU1_DB6_C4),
 351         PINMUX_SINGLE(DU1_DB7_C5),
 352         PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
 353         PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
 354         PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
 355         PINMUX_SINGLE(DU1_DISP),
 356         PINMUX_SINGLE(DU1_CDE),
 357         PINMUX_SINGLE(D0),
 358         PINMUX_SINGLE(D1),
 359         PINMUX_SINGLE(D2),
 360         PINMUX_SINGLE(D3),
 361         PINMUX_SINGLE(D4),
 362         PINMUX_SINGLE(D5),
 363         PINMUX_SINGLE(D6),
 364         PINMUX_SINGLE(D7),
 365         PINMUX_SINGLE(D8),
 366         PINMUX_SINGLE(D9),
 367         PINMUX_SINGLE(D10),
 368         PINMUX_SINGLE(D11),
 369         PINMUX_SINGLE(D12),
 370         PINMUX_SINGLE(D13),
 371         PINMUX_SINGLE(D14),
 372         PINMUX_SINGLE(D15),
 373         PINMUX_SINGLE(A0),
 374         PINMUX_SINGLE(A1),
 375         PINMUX_SINGLE(A2),
 376         PINMUX_SINGLE(A3),
 377         PINMUX_SINGLE(A4),
 378         PINMUX_SINGLE(A5),
 379         PINMUX_SINGLE(A6),
 380         PINMUX_SINGLE(A7),
 381         PINMUX_SINGLE(A8),
 382         PINMUX_SINGLE(A9),
 383         PINMUX_SINGLE(A10),
 384         PINMUX_SINGLE(A11),
 385         PINMUX_SINGLE(A12),
 386         PINMUX_SINGLE(A13),
 387         PINMUX_SINGLE(A14),
 388         PINMUX_SINGLE(A15),
 389         PINMUX_SINGLE(A16),
 390         PINMUX_SINGLE(A17),
 391         PINMUX_SINGLE(A18),
 392         PINMUX_SINGLE(A19),
 393         PINMUX_SINGLE(CS1_N_A26),
 394         PINMUX_SINGLE(EX_CS0_N),
 395         PINMUX_SINGLE(EX_CS1_N),
 396         PINMUX_SINGLE(EX_CS2_N),
 397         PINMUX_SINGLE(EX_CS3_N),
 398         PINMUX_SINGLE(EX_CS4_N),
 399         PINMUX_SINGLE(EX_CS5_N),
 400         PINMUX_SINGLE(BS_N),
 401         PINMUX_SINGLE(RD_N),
 402         PINMUX_SINGLE(RD_WR_N),
 403         PINMUX_SINGLE(WE0_N),
 404         PINMUX_SINGLE(WE1_N),
 405         PINMUX_SINGLE(EX_WAIT0),
 406         PINMUX_SINGLE(IRQ0),
 407         PINMUX_SINGLE(IRQ1),
 408         PINMUX_SINGLE(IRQ2),
 409         PINMUX_SINGLE(IRQ3),
 410         PINMUX_SINGLE(CS0_N),
 411         PINMUX_SINGLE(VI0_CLK),
 412         PINMUX_SINGLE(VI0_CLKENB),
 413         PINMUX_SINGLE(VI0_HSYNC_N),
 414         PINMUX_SINGLE(VI0_VSYNC_N),
 415         PINMUX_SINGLE(VI0_D0_B0_C0),
 416         PINMUX_SINGLE(VI0_D1_B1_C1),
 417         PINMUX_SINGLE(VI0_D2_B2_C2),
 418         PINMUX_SINGLE(VI0_D3_B3_C3),
 419         PINMUX_SINGLE(VI0_D4_B4_C4),
 420         PINMUX_SINGLE(VI0_D5_B5_C5),
 421         PINMUX_SINGLE(VI0_D6_B6_C6),
 422         PINMUX_SINGLE(VI0_D7_B7_C7),
 423         PINMUX_SINGLE(VI0_D8_G0_Y0),
 424         PINMUX_SINGLE(VI0_D9_G1_Y1),
 425         PINMUX_SINGLE(VI0_D10_G2_Y2),
 426         PINMUX_SINGLE(VI0_D11_G3_Y3),
 427         PINMUX_SINGLE(VI0_FIELD),
 428         PINMUX_SINGLE(VI1_CLK),
 429         PINMUX_SINGLE(VI1_CLKENB),
 430         PINMUX_SINGLE(VI1_HSYNC_N),
 431         PINMUX_SINGLE(VI1_VSYNC_N),
 432         PINMUX_SINGLE(VI1_D0_B0_C0),
 433         PINMUX_SINGLE(VI1_D1_B1_C1),
 434         PINMUX_SINGLE(VI1_D2_B2_C2),
 435         PINMUX_SINGLE(VI1_D3_B3_C3),
 436         PINMUX_SINGLE(VI1_D4_B4_C4),
 437         PINMUX_SINGLE(VI1_D5_B5_C5),
 438         PINMUX_SINGLE(VI1_D6_B6_C6),
 439         PINMUX_SINGLE(VI1_D7_B7_C7),
 440         PINMUX_SINGLE(VI1_D8_G0_Y0),
 441         PINMUX_SINGLE(VI1_D9_G1_Y1),
 442         PINMUX_SINGLE(VI1_D10_G2_Y2),
 443         PINMUX_SINGLE(VI1_D11_G3_Y3),
 444         PINMUX_SINGLE(VI1_FIELD),
 445         PINMUX_SINGLE(VI3_D10_Y2),
 446         PINMUX_SINGLE(VI3_FIELD),
 447         PINMUX_SINGLE(VI4_CLK),
 448         PINMUX_SINGLE(VI5_CLK),
 449         PINMUX_SINGLE(VI5_D9_Y1),
 450         PINMUX_SINGLE(VI5_D10_Y2),
 451         PINMUX_SINGLE(VI5_D11_Y3),
 452         PINMUX_SINGLE(VI5_FIELD),
 453         PINMUX_SINGLE(HRTS0_N),
 454         PINMUX_SINGLE(HCTS1_N),
 455         PINMUX_SINGLE(SCK0),
 456         PINMUX_SINGLE(CTS0_N),
 457         PINMUX_SINGLE(RTS0_N),
 458         PINMUX_SINGLE(TX0),
 459         PINMUX_SINGLE(RX0),
 460         PINMUX_SINGLE(SCK1),
 461         PINMUX_SINGLE(CTS1_N),
 462         PINMUX_SINGLE(RTS1_N),
 463         PINMUX_SINGLE(TX1),
 464         PINMUX_SINGLE(RX1),
 465         PINMUX_SINGLE(SCIF_CLK),
 466         PINMUX_SINGLE(CAN0_TX),
 467         PINMUX_SINGLE(CAN0_RX),
 468         PINMUX_SINGLE(CAN_CLK),
 469         PINMUX_SINGLE(CAN1_TX),
 470         PINMUX_SINGLE(CAN1_RX),
 471         PINMUX_SINGLE(SD0_CLK),
 472         PINMUX_SINGLE(SD0_CMD),
 473         PINMUX_SINGLE(SD0_DAT0),
 474         PINMUX_SINGLE(SD0_DAT1),
 475         PINMUX_SINGLE(SD0_DAT2),
 476         PINMUX_SINGLE(SD0_DAT3),
 477         PINMUX_SINGLE(SD0_CD),
 478         PINMUX_SINGLE(SD0_WP),
 479         PINMUX_SINGLE(ADICLK),
 480         PINMUX_SINGLE(ADICS_SAMP),
 481         PINMUX_SINGLE(ADIDATA),
 482         PINMUX_SINGLE(ADICHS0),
 483         PINMUX_SINGLE(ADICHS1),
 484         PINMUX_SINGLE(ADICHS2),
 485         PINMUX_SINGLE(AVS1),
 486         PINMUX_SINGLE(AVS2),
 487
 488         /* IPSR0 */
 489         PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
 490         PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
 491         PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
 492         PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
 493         PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
 494         PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
 495         PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
 496         PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
 497         PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
 498         PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
 499         PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
 500         PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
 501         PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
 502         PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
 503         PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
 504         PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
 505         PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
 506         PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
 507         PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
 508         PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
 509         PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
 510         PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
 511         PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
 512         PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
 513
 514         /* IPSR1 */
 515         PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
 516         PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
 517         PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 518         PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
 519         PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
 520         PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
 521         PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
 522         PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
 523         PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
 524         PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
 525         PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
 526         PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
 527         PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
 528         PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
 529         PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
 530         PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
 531         PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
 532         PINMUX_IPSR_GPSR(IP1_17, A20),
 533         PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
 534         PINMUX_IPSR_GPSR(IP1_18, A21),
 535         PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
 536         PINMUX_IPSR_GPSR(IP1_19, A22),
 537         PINMUX_IPSR_GPSR(IP1_19, IO2),
 538         PINMUX_IPSR_GPSR(IP1_20, A23),
 539         PINMUX_IPSR_GPSR(IP1_20, IO3),
 540         PINMUX_IPSR_GPSR(IP1_21, A24),
 541         PINMUX_IPSR_GPSR(IP1_21, SPCLK),
 542         PINMUX_IPSR_GPSR(IP1_22, A25),
 543         PINMUX_IPSR_GPSR(IP1_22, SSL),
 544
 545         /* IPSR2 */
 546         PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
 547         PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
 548         PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
 549         PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
 550         PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
 551         PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
 552         PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
 553         PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
 554         PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
 555         PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
 556         PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
 557         PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
 558         PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
 559         PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
 560         PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
 561         PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
 562         PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
 563         PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
 564         PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
 565         PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
 566         PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
 567         PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
 568         PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
 569         PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
 570         PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
 571         PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
 572         PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
 573         PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
 574         PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
 575         PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
 576         PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
 577         PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
 578         PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
 579         PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
 580
 581         /* IPSR3 */
 582         PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
 583         PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
 584         PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
 585         PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
 586         PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
 587         PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
 588         PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
 589         PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
 590         PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
 591         PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
 592         PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
 593         PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
 594         PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
 595         PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
 596         PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
 597         PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
 598         PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
 599         PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
 600         PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
 601         PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
 602         PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
 603         PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
 604         PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
 605         PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
 606         PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
 607         PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
 608         PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
 609         PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
 610         PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
 611         PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
 612
 613         /* IPSR4 */
 614         PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
 615         PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
 616         PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
 617         PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
 618         PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
 619         PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
 620         PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
 621         PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
 622         PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
 623         PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
 624         PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
 625         PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
 626         PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
 627         PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
 628         PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
 629         PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
 630         PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
 631         PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
 632         PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
 633         PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
 634         PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
 635         PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
 636         PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
 637         PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
 638         PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
 639         PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
 640         PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
 641         PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
 642         PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
 643         PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
 644         PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
 645         PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
 646         PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
 647         PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
 648         PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
 649         PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
 650         PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
 651         PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
 652         PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
 653         PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
 654
 655         /* IPSR5 */
 656         PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
 657         PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
 658         PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
 659         PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
 660         PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
 661         PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
 662         PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
 663         PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
 664         PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
 665         PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
 666         PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
 667         PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
 668         PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
 669         PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
 670         PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
 671         PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
 672         PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
 673         PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
 674         PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
 675         PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
 676         PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
 677         PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
 678         PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
 679         PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
 680
 681         /* IPSR6 */
 682         PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
 683         PINMUX_IPSR_GPSR(IP6_0, HSCK0),
 684         PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
 685         PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
 686         PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
 687         PINMUX_IPSR_GPSR(IP6_2, HTX0),
 688         PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
 689         PINMUX_IPSR_GPSR(IP6_3, HRX0),
 690         PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
 691         PINMUX_IPSR_GPSR(IP6_4, HSCK1),
 692         PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
 693         PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
 694         PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
 695         PINMUX_IPSR_GPSR(IP6_6, HTX1),
 696         PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
 697         PINMUX_IPSR_GPSR(IP6_7, HRX1),
 698         PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
 699         PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
 700         PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
 701         PINMUX_IPSR_GPSR(IP6_11_10, TX2),
 702         PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
 703         PINMUX_IPSR_GPSR(IP6_13_12, RX2),
 704         PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
 705         PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
 706         PINMUX_IPSR_GPSR(IP6_16, TX3),
 707         PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
 708         PINMUX_IPSR_GPSR(IP6_18_17, RX3),
 709
 710         /* IPSR7 */
 711         PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
 712         PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
 713         PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
 714         PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
 715         PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
 716         PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
 717         PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
 718         PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
 719         PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
 720         PINMUX_IPSR_GPSR(IP7_6, PWM3),
 721         PINMUX_IPSR_GPSR(IP7_7, PWM4),
 722         PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
 723         PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
 724         PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
 725         PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
 726         PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
 727         PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
 728         PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
 729         PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
 730         PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
 731         PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
 732         PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
 733         PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
 734         PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
 735 };
 736
 737 /*
 738  * Pins not associated with a GPIO port.
 739  */
 740 enum {
 741         GP_ASSIGN_LAST(),
 742         NOGP_ALL(),
 743 };
 744
 745 static const struct sh_pfc_pin pinmux_pins[] = {
 746         PINMUX_GPIO_GP_ALL(),
 747         PINMUX_NOGP_ALL(),
 748 };
 749
 750 /* - AVB -------------------------------------------------------------------- */
 751 static const unsigned int avb_link_pins[] = {
 752         RCAR_GP_PIN(7, 9),
 753 };
 754 static const unsigned int avb_link_mux[] = {
 755         AVB_LINK_MARK,
 756 };
 757 static const unsigned int avb_magic_pins[] = {
 758         RCAR_GP_PIN(7, 10),
 759 };
 760 static const unsigned int avb_magic_mux[] = {
 761         AVB_MAGIC_MARK,
 762 };
 763 static const unsigned int avb_phy_int_pins[] = {
 764         RCAR_GP_PIN(7, 11),
 765 };
 766 static const unsigned int avb_phy_int_mux[] = {
 767         AVB_PHY_INT_MARK,
 768 };
 769 static const unsigned int avb_mdio_pins[] = {
 770         RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
 771 };
 772 static const unsigned int avb_mdio_mux[] = {
 773         AVB_MDC_MARK, AVB_MDIO_MARK,
 774 };
 775 static const unsigned int avb_mii_pins[] = {
 776         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
 777         RCAR_GP_PIN(6, 12),
 778
 779         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(6, 4),
 780         RCAR_GP_PIN(6, 5),
 781
 782         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(6, 1),
 783         RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
 784         RCAR_GP_PIN(7, 0),  RCAR_GP_PIN(6, 11),
 785 };
 786 static const unsigned int avb_mii_mux[] = {
 787         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
 788         AVB_TXD3_MARK,
 789
 790         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
 791         AVB_RXD3_MARK,
 792
 793         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
 794         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
 795         AVB_TX_CLK_MARK, AVB_COL_MARK,
 796 };
 797 static const unsigned int avb_gmii_pins[] = {
 798         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
 799         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1),  RCAR_GP_PIN(7, 2),
 800         RCAR_GP_PIN(7, 3),  RCAR_GP_PIN(7, 4),
 801
 802         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
 803         RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
 804         RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 9),
 805
 806         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
 807         RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
 808         RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
 809         RCAR_GP_PIN(6, 11),
 810 };
 811 static const unsigned int avb_gmii_mux[] = {
 812         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
 813         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
 814         AVB_TXD6_MARK, AVB_TXD7_MARK,
 815
 816         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
 817         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
 818         AVB_RXD6_MARK, AVB_RXD7_MARK,
 819
 820         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
 821         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
 822         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
 823         AVB_COL_MARK,
 824 };
 825 static const unsigned int avb_avtp_match_pins[] = {
 826         RCAR_GP_PIN(7, 15),
 827 };
 828 static const unsigned int avb_avtp_match_mux[] = {
 829         AVB_AVTP_MATCH_MARK,
 830 };
 831 /* - CAN -------------------------------------------------------------------- */
 832 static const unsigned int can0_data_pins[] = {
 833         /* TX, RX */
 834         RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
 835 };
 836 static const unsigned int can0_data_mux[] = {
 837         CAN0_TX_MARK, CAN0_RX_MARK,
 838 };
 839 static const unsigned int can1_data_pins[] = {
 840         /* TX, RX */
 841         RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
 842 };
 843 static const unsigned int can1_data_mux[] = {
 844         CAN1_TX_MARK, CAN1_RX_MARK,
 845 };
 846 static const unsigned int can_clk_pins[] = {
 847         /* CAN_CLK */
 848         RCAR_GP_PIN(10, 29),
 849 };
 850 static const unsigned int can_clk_mux[] = {
 851         CAN_CLK_MARK,
 852 };
 853 /* - DU --------------------------------------------------------------------- */
 854 static const unsigned int du0_rgb666_pins[] = {
 855         /* R[7:2], G[7:2], B[7:2] */
 856         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
 857         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 858         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
 859         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 860         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 861         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
 862 };
 863 static const unsigned int du0_rgb666_mux[] = {
 864         DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
 865         DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
 866         DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
 867         DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
 868         DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
 869         DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
 870 };
 871 static const unsigned int du0_rgb888_pins[] = {
 872         /* R[7:0], G[7:0], B[7:0] */
 873         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
 874         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 875         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 876         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
 877         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 878         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
 879         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 880         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
 881         RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
 882 };
 883 static const unsigned int du0_rgb888_mux[] = {
 884         DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
 885         DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
 886         DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
 887         DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
 888         DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
 889         DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
 890         DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
 891         DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
 892         DU0_DB1_MARK, DU0_DB0_MARK,
 893 };
 894 static const unsigned int du0_sync_pins[] = {
 895         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 896         RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
 897 };
 898 static const unsigned int du0_sync_mux[] = {
 899         DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
 900 };
 901 static const unsigned int du0_oddf_pins[] = {
 902         /* EXODDF/ODDF/DISP/CDE */
 903         RCAR_GP_PIN(0, 26),
 904 };
 905 static const unsigned int du0_oddf_mux[] = {
 906         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
 907 };
 908 static const unsigned int du0_disp_pins[] = {
 909         /* DISP */
 910         RCAR_GP_PIN(0, 27),
 911 };
 912 static const unsigned int du0_disp_mux[] = {
 913         DU0_DISP_MARK,
 914 };
 915 static const unsigned int du0_cde_pins[] = {
 916         /* CDE */
 917         RCAR_GP_PIN(0, 28),
 918 };
 919 static const unsigned int du0_cde_mux[] = {
 920         DU0_CDE_MARK,
 921 };
 922 static const unsigned int du1_rgb666_pins[] = {
 923         /* R[7:2], G[7:2], B[7:2] */
 924         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
 925         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
 926         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
 927         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
 928         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
 929         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
 930 };
 931 static const unsigned int du1_rgb666_mux[] = {
 932         DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
 933         DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
 934         DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
 935         DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
 936         DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
 937         DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
 938 };
 939 static const unsigned int du1_sync_pins[] = {
 940         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 941         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 942 };
 943 static const unsigned int du1_sync_mux[] = {
 944         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 945 };
 946 static const unsigned int du1_oddf_pins[] = {
 947         /* EXODDF/ODDF/DISP/CDE */
 948         RCAR_GP_PIN(1, 20),
 949 };
 950 static const unsigned int du1_oddf_mux[] = {
 951         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
 952 };
 953 static const unsigned int du1_disp_pins[] = {
 954         /* DISP */
 955         RCAR_GP_PIN(1, 21),
 956 };
 957 static const unsigned int du1_disp_mux[] = {
 958         DU1_DISP_MARK,
 959 };
 960 static const unsigned int du1_cde_pins[] = {
 961         /* CDE */
 962         RCAR_GP_PIN(1, 22),
 963 };
 964 static const unsigned int du1_cde_mux[] = {
 965         DU1_CDE_MARK,
 966 };
 967 /* - INTC ------------------------------------------------------------------- */
 968 static const unsigned int intc_irq0_pins[] = {
 969         /* IRQ0 */
 970         RCAR_GP_PIN(3, 19),
 971 };
 972 static const unsigned int intc_irq0_mux[] = {
 973         IRQ0_MARK,
 974 };
 975 static const unsigned int intc_irq1_pins[] = {
 976         /* IRQ1 */
 977         RCAR_GP_PIN(3, 20),
 978 };
 979 static const unsigned int intc_irq1_mux[] = {
 980         IRQ1_MARK,
 981 };
 982 static const unsigned int intc_irq2_pins[] = {
 983         /* IRQ2 */
 984         RCAR_GP_PIN(3, 21),
 985 };
 986 static const unsigned int intc_irq2_mux[] = {
 987         IRQ2_MARK,
 988 };
 989 static const unsigned int intc_irq3_pins[] = {
 990         /* IRQ3 */
 991         RCAR_GP_PIN(3, 22),
 992 };
 993 static const unsigned int intc_irq3_mux[] = {
 994         IRQ3_MARK,
 995 };
 996 /* - LBSC ------------------------------------------------------------------- */
 997 static const unsigned int lbsc_cs0_pins[] = {
 998         /* CS0# */
 999         RCAR_GP_PIN(3, 27),
1000 };
1001 static const unsigned int lbsc_cs0_mux[] = {
1002         CS0_N_MARK,
1003 };
1004 static const unsigned int lbsc_cs1_pins[] = {
1005         /* CS1#_A26 */
1006         RCAR_GP_PIN(3, 6),
1007 };
1008 static const unsigned int lbsc_cs1_mux[] = {
1009         CS1_N_A26_MARK,
1010 };
1011 static const unsigned int lbsc_ex_cs0_pins[] = {
1012         /* EX_CS0# */
1013         RCAR_GP_PIN(3, 7),
1014 };
1015 static const unsigned int lbsc_ex_cs0_mux[] = {
1016         EX_CS0_N_MARK,
1017 };
1018 static const unsigned int lbsc_ex_cs1_pins[] = {
1019         /* EX_CS1# */
1020         RCAR_GP_PIN(3, 8),
1021 };
1022 static const unsigned int lbsc_ex_cs1_mux[] = {
1023         EX_CS1_N_MARK,
1024 };
1025 static const unsigned int lbsc_ex_cs2_pins[] = {
1026         /* EX_CS2# */
1027         RCAR_GP_PIN(3, 9),
1028 };
1029 static const unsigned int lbsc_ex_cs2_mux[] = {
1030         EX_CS2_N_MARK,
1031 };
1032 static const unsigned int lbsc_ex_cs3_pins[] = {
1033         /* EX_CS3# */
1034         RCAR_GP_PIN(3, 10),
1035 };
1036 static const unsigned int lbsc_ex_cs3_mux[] = {
1037         EX_CS3_N_MARK,
1038 };
1039 static const unsigned int lbsc_ex_cs4_pins[] = {
1040         /* EX_CS4# */
1041         RCAR_GP_PIN(3, 11),
1042 };
1043 static const unsigned int lbsc_ex_cs4_mux[] = {
1044         EX_CS4_N_MARK,
1045 };
1046 static const unsigned int lbsc_ex_cs5_pins[] = {
1047         /* EX_CS5# */
1048         RCAR_GP_PIN(3, 12),
1049 };
1050 static const unsigned int lbsc_ex_cs5_mux[] = {
1051         EX_CS5_N_MARK,
1052 };
1053 /* - MSIOF0 ----------------------------------------------------------------- */
1054 static const unsigned int msiof0_clk_pins[] = {
1055         /* SCK */
1056         RCAR_GP_PIN(10, 0),
1057 };
1058 static const unsigned int msiof0_clk_mux[] = {
1059         MSIOF0_SCK_MARK,
1060 };
1061 static const unsigned int msiof0_sync_pins[] = {
1062         /* SYNC */
1063         RCAR_GP_PIN(10, 1),
1064 };
1065 static const unsigned int msiof0_sync_mux[] = {
1066         MSIOF0_SYNC_MARK,
1067 };
1068 static const unsigned int msiof0_rx_pins[] = {
1069         /* RXD */
1070         RCAR_GP_PIN(10, 4),
1071 };
1072 static const unsigned int msiof0_rx_mux[] = {
1073         MSIOF0_RXD_MARK,
1074 };
1075 static const unsigned int msiof0_tx_pins[] = {
1076         /* TXD */
1077         RCAR_GP_PIN(10, 3),
1078 };
1079 static const unsigned int msiof0_tx_mux[] = {
1080         MSIOF0_TXD_MARK,
1081 };
1082 /* - MSIOF1 ----------------------------------------------------------------- */
1083 static const unsigned int msiof1_clk_pins[] = {
1084         /* SCK */
1085         RCAR_GP_PIN(10, 5),
1086 };
1087 static const unsigned int msiof1_clk_mux[] = {
1088         MSIOF1_SCK_MARK,
1089 };
1090 static const unsigned int msiof1_sync_pins[] = {
1091         /* SYNC */
1092         RCAR_GP_PIN(10, 6),
1093 };
1094 static const unsigned int msiof1_sync_mux[] = {
1095         MSIOF1_SYNC_MARK,
1096 };
1097 static const unsigned int msiof1_rx_pins[] = {
1098         /* RXD */
1099         RCAR_GP_PIN(10, 9),
1100 };
1101 static const unsigned int msiof1_rx_mux[] = {
1102         MSIOF1_RXD_MARK,
1103 };
1104 static const unsigned int msiof1_tx_pins[] = {
1105         /* TXD */
1106         RCAR_GP_PIN(10, 8),
1107 };
1108 static const unsigned int msiof1_tx_mux[] = {
1109         MSIOF1_TXD_MARK,
1110 };
1111 /* - QSPI ------------------------------------------------------------------- */
1112 static const unsigned int qspi_ctrl_pins[] = {
1113         /* SPCLK, SSL */
1114         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1115 };
1116 static const unsigned int qspi_ctrl_mux[] = {
1117         SPCLK_MARK, SSL_MARK,
1118 };
1119 static const unsigned int qspi_data2_pins[] = {
1120         /* MOSI_IO0, MISO_IO1 */
1121         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1122 };
1123 static const unsigned int qspi_data2_mux[] = {
1124         MOSI_IO0_MARK, MISO_IO1_MARK,
1125 };
1126 static const unsigned int qspi_data4_pins[] = {
1127         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1128         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
1129         RCAR_GP_PIN(3, 24),
1130 };
1131 static const unsigned int qspi_data4_mux[] = {
1132         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
1133 };
1134 /* - SCIF0 ------------------------------------------------------------------ */
1135 static const unsigned int scif0_data_pins[] = {
1136         /* RX, TX */
1137         RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
1138 };
1139 static const unsigned int scif0_data_mux[] = {
1140         RX0_MARK, TX0_MARK,
1141 };
1142 static const unsigned int scif0_clk_pins[] = {
1143         /* SCK */
1144         RCAR_GP_PIN(10, 10),
1145 };
1146 static const unsigned int scif0_clk_mux[] = {
1147         SCK0_MARK,
1148 };
1149 static const unsigned int scif0_ctrl_pins[] = {
1150         /* RTS, CTS */
1151         RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
1152 };
1153 static const unsigned int scif0_ctrl_mux[] = {
1154         RTS0_N_MARK, CTS0_N_MARK,
1155 };
1156 /* - SCIF1 ------------------------------------------------------------------ */
1157 static const unsigned int scif1_data_pins[] = {
1158         /* RX, TX */
1159         RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),
1160 };
1161 static const unsigned int scif1_data_mux[] = {
1162         RX1_MARK, TX1_MARK,
1163 };
1164 static const unsigned int scif1_clk_pins[] = {
1165         /* SCK */
1166         RCAR_GP_PIN(10, 15),
1167 };
1168 static const unsigned int scif1_clk_mux[] = {
1169         SCK1_MARK,
1170 };
1171 static const unsigned int scif1_ctrl_pins[] = {
1172         /* RTS, CTS */
1173         RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),
1174 };
1175 static const unsigned int scif1_ctrl_mux[] = {
1176         RTS1_N_MARK, CTS1_N_MARK,
1177 };
1178 /* - SCIF2 ------------------------------------------------------------------ */
1179 static const unsigned int scif2_data_pins[] = {
1180         /* RX, TX */
1181         RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),
1182 };
1183 static const unsigned int scif2_data_mux[] = {
1184         RX2_MARK, TX2_MARK,
1185 };
1186 static const unsigned int scif2_clk_pins[] = {
1187         /* SCK */
1188         RCAR_GP_PIN(10, 20),
1189 };
1190 static const unsigned int scif2_clk_mux[] = {
1191         SCK2_MARK,
1192 };
1193 /* - SCIF3 ------------------------------------------------------------------ */
1194 static const unsigned int scif3_data_pins[] = {
1195         /* RX, TX */
1196         RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
1197 };
1198 static const unsigned int scif3_data_mux[] = {
1199         RX3_MARK, TX3_MARK,
1200 };
1201 static const unsigned int scif3_clk_pins[] = {
1202         /* SCK */
1203         RCAR_GP_PIN(10, 23),
1204 };
1205 static const unsigned int scif3_clk_mux[] = {
1206         SCK3_MARK,
1207 };
1208 /* - SDHI0 ------------------------------------------------------------------ */
1209 static const unsigned int sdhi0_data1_pins[] = {
1210         /* DAT0 */
1211         RCAR_GP_PIN(11, 7),
1212 };
1213 static const unsigned int sdhi0_data1_mux[] = {
1214         SD0_DAT0_MARK,
1215 };
1216 static const unsigned int sdhi0_data4_pins[] = {
1217         /* DAT[0-3] */
1218         RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
1219         RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
1220 };
1221 static const unsigned int sdhi0_data4_mux[] = {
1222         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1223 };
1224 static const unsigned int sdhi0_ctrl_pins[] = {
1225         /* CLK, CMD */
1226         RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
1227 };
1228 static const unsigned int sdhi0_ctrl_mux[] = {
1229         SD0_CLK_MARK, SD0_CMD_MARK,
1230 };
1231 static const unsigned int sdhi0_cd_pins[] = {
1232         /* CD */
1233         RCAR_GP_PIN(11, 11),
1234 };
1235 static const unsigned int sdhi0_cd_mux[] = {
1236         SD0_CD_MARK,
1237 };
1238 static const unsigned int sdhi0_wp_pins[] = {
1239         /* WP */
1240         RCAR_GP_PIN(11, 12),
1241 };
1242 static const unsigned int sdhi0_wp_mux[] = {
1243         SD0_WP_MARK,
1244 };
1245 /* - VIN0 ------------------------------------------------------------------- */
1246 static const union vin_data vin0_data_pins = {
1247         .data24 = {
1248                 /* B */
1249                 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1250                 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1251                 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1252                 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1253                 /* G */
1254                 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1255                 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1256                 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1257                 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1258                 /* R */
1259                 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1260                 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1261                 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1262                 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1263         },
1264 };
1265 static const union vin_data vin0_data_mux = {
1266         .data24 = {
1267                 /* B */
1268                 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1269                 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1270                 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1271                 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1272                 /* G */
1273                 VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1274                 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1275                 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1276                 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1277                 /* R */
1278                 VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1279                 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1280                 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1281                 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1282         },
1283 };
1284 static const unsigned int vin0_data18_pins[] = {
1285         /* B */
1286         RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1287         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1288         RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1289         /* G */
1290         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1291         RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1292         RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1293         /* R */
1294         RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1295         RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1296         RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1297 };
1298 static const unsigned int vin0_data18_mux[] = {
1299         /* B */
1300         VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1301         VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1302         VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1303         /* G */
1304         VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1305         VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1306         VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1307         /* R */
1308         VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1309         VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1310         VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1311 };
1312 static const unsigned int vin0_sync_pins[] = {
1313         /* HSYNC#, VSYNC# */
1314         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1315 };
1316 static const unsigned int vin0_sync_mux[] = {
1317         VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1318 };
1319 static const unsigned int vin0_field_pins[] = {
1320         RCAR_GP_PIN(4, 16),
1321 };
1322 static const unsigned int vin0_field_mux[] = {
1323         VI0_FIELD_MARK,
1324 };
1325 static const unsigned int vin0_clkenb_pins[] = {
1326         RCAR_GP_PIN(4, 1),
1327 };
1328 static const unsigned int vin0_clkenb_mux[] = {
1329         VI0_CLKENB_MARK,
1330 };
1331 static const unsigned int vin0_clk_pins[] = {
1332         RCAR_GP_PIN(4, 0),
1333 };
1334 static const unsigned int vin0_clk_mux[] = {
1335         VI0_CLK_MARK,
1336 };
1337 /* - VIN1 ------------------------------------------------------------------- */
1338 static const union vin_data vin1_data_pins = {
1339         .data24 = {
1340                 /* B */
1341                 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1342                 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1343                 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1344                 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1345                 /* G */
1346                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1347                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1348                 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1349                 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1350                 /* R */
1351                 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1352                 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1353                 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1354                 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1355         },
1356 };
1357 static const union vin_data vin1_data_mux = {
1358         .data24 = {
1359                 /* B */
1360                 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1361                 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1362                 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1363                 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1364                 /* G */
1365                 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1366                 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1367                 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1368                 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1369                 /* R */
1370                 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1371                 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1372                 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1373                 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1374         },
1375 };
1376 static const unsigned int vin1_data18_pins[] = {
1377         /* B */
1378         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1379         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1380         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1381         /* G */
1382         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1383         RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1384         RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1385         /* R */
1386         RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1387         RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1388         RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1389 };
1390 static const unsigned int vin1_data18_mux[] = {
1391         /* B */
1392         VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1393         VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1394         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1395         /* G */
1396         VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1397         VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1398         VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1399         /* R */
1400         VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1401         VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1402         VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1403 };
1404 static const union vin_data vin1_data_b_pins = {
1405         .data24 = {
1406                 /* B */
1407                 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1408                 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1409                 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1410                 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1411                 /* G */
1412                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1413                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1414                 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1415                 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1416                 /* R */
1417                 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1418                 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1419                 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1420                 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1421         },
1422 };
1423 static const union vin_data vin1_data_b_mux = {
1424         .data24 = {
1425                 /* B */
1426                 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1427                 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1428                 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1429                 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1430                 /* G */
1431                 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1432                 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1433                 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1434                 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1435                 /* R */
1436                 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1437                 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1438                 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1439                 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1440         },
1441 };
1442 static const unsigned int vin1_data18_b_pins[] = {
1443         /* B */
1444         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1445         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1446         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1447         /* G */
1448         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1449         RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1450         RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1451         /* R */
1452         RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1453         RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1454         RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1455 };
1456 static const unsigned int vin1_data18_b_mux[] = {
1457         /* B */
1458         VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1459         VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1460         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1461         /* G */
1462         VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1463         VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1464         VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1465         /* R */
1466         VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1467         VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1468         VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1469 };
1470 static const unsigned int vin1_sync_pins[] = {
1471         /* HSYNC#, VSYNC# */
1472         RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1473 };
1474 static const unsigned int vin1_sync_mux[] = {
1475         VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1476 };
1477 static const unsigned int vin1_field_pins[] = {
1478         RCAR_GP_PIN(5, 16),
1479 };
1480 static const unsigned int vin1_field_mux[] = {
1481         VI1_FIELD_MARK,
1482 };
1483 static const unsigned int vin1_clkenb_pins[] = {
1484         RCAR_GP_PIN(5, 1),
1485 };
1486 static const unsigned int vin1_clkenb_mux[] = {
1487         VI1_CLKENB_MARK,
1488 };
1489 static const unsigned int vin1_clk_pins[] = {
1490         RCAR_GP_PIN(5, 0),
1491 };
1492 static const unsigned int vin1_clk_mux[] = {
1493         VI1_CLK_MARK,
1494 };
1495 /* - VIN2 ------------------------------------------------------------------- */
1496 static const union vin_data16 vin2_data_pins = {
1497         .data16 = {
1498                 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1499                 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1500                 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1501                 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1502                 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1503                 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1504                 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1505                 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1506         },
1507 };
1508 static const union vin_data16 vin2_data_mux = {
1509         .data16 = {
1510                 VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1511                 VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1512                 VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1513                 VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1514                 VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1515                 VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1516                 VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1517                 VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
1518         },
1519 };
1520 static const unsigned int vin2_sync_pins[] = {
1521         /* HSYNC#, VSYNC# */
1522         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1523 };
1524 static const unsigned int vin2_sync_mux[] = {
1525         VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
1526 };
1527 static const unsigned int vin2_field_pins[] = {
1528         RCAR_GP_PIN(6, 16),
1529 };
1530 static const unsigned int vin2_field_mux[] = {
1531         VI2_FIELD_MARK,
1532 };
1533 static const unsigned int vin2_clkenb_pins[] = {
1534         RCAR_GP_PIN(6, 1),
1535 };
1536 static const unsigned int vin2_clkenb_mux[] = {
1537         VI2_CLKENB_MARK,
1538 };
1539 static const unsigned int vin2_clk_pins[] = {
1540         RCAR_GP_PIN(6, 0),
1541 };
1542 static const unsigned int vin2_clk_mux[] = {
1543         VI2_CLK_MARK,
1544 };
1545 /* - VIN3 ------------------------------------------------------------------- */
1546 static const union vin_data16 vin3_data_pins = {
1547         .data16 = {
1548                 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1549                 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1550                 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1551                 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1552                 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1553                 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1554                 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1555                 RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
1556         },
1557 };
1558 static const union vin_data16 vin3_data_mux = {
1559         .data16 = {
1560                 VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1561                 VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1562                 VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1563                 VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1564                 VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1565                 VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1566                 VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1567                 VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
1568         },
1569 };
1570 static const unsigned int vin3_sync_pins[] = {
1571         /* HSYNC#, VSYNC# */
1572         RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1573 };
1574 static const unsigned int vin3_sync_mux[] = {
1575         VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
1576 };
1577 static const unsigned int vin3_field_pins[] = {
1578         RCAR_GP_PIN(7, 16),
1579 };
1580 static const unsigned int vin3_field_mux[] = {
1581         VI3_FIELD_MARK,
1582 };
1583 static const unsigned int vin3_clkenb_pins[] = {
1584         RCAR_GP_PIN(7, 1),
1585 };
1586 static const unsigned int vin3_clkenb_mux[] = {
1587         VI3_CLKENB_MARK,
1588 };
1589 static const unsigned int vin3_clk_pins[] = {
1590         RCAR_GP_PIN(7, 0),
1591 };
1592 static const unsigned int vin3_clk_mux[] = {
1593         VI3_CLK_MARK,
1594 };
1595 /* - VIN4 ------------------------------------------------------------------- */
1596 static const union vin_data12 vin4_data_pins = {
1597         .data12 = {
1598                 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1599                 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1600                 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1601                 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1602                 RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1603                 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
1604         },
1605 };
1606 static const union vin_data12 vin4_data_mux = {
1607         .data12 = {
1608                 VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1609                 VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1610                 VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1611                 VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1612                 VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1613                 VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
1614         },
1615 };
1616 static const unsigned int vin4_sync_pins[] = {
1617          /* HSYNC#, VSYNC# */
1618         RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1619 };
1620 static const unsigned int vin4_sync_mux[] = {
1621         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1622 };
1623 static const unsigned int vin4_field_pins[] = {
1624         RCAR_GP_PIN(8, 16),
1625 };
1626 static const unsigned int vin4_field_mux[] = {
1627         VI4_FIELD_MARK,
1628 };
1629 static const unsigned int vin4_clkenb_pins[] = {
1630         RCAR_GP_PIN(8, 1),
1631 };
1632 static const unsigned int vin4_clkenb_mux[] = {
1633         VI4_CLKENB_MARK,
1634 };
1635 static const unsigned int vin4_clk_pins[] = {
1636         RCAR_GP_PIN(8, 0),
1637 };
1638 static const unsigned int vin4_clk_mux[] = {
1639         VI4_CLK_MARK,
1640 };
1641 /* - VIN5 ------------------------------------------------------------------- */
1642 static const union vin_data12 vin5_data_pins = {
1643         .data12 = {
1644                 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1645                 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1646                 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1647                 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1648                 RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1649                 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
1650         },
1651 };
1652 static const union vin_data12 vin5_data_mux = {
1653         .data12 = {
1654                 VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1655                 VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1656                 VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1657                 VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1658                 VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1659                 VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
1660         },
1661 };
1662 static const unsigned int vin5_sync_pins[] = {
1663         /* HSYNC#, VSYNC# */
1664         RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1665 };
1666 static const unsigned int vin5_sync_mux[] = {
1667         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
1668 };
1669 static const unsigned int vin5_field_pins[] = {
1670         RCAR_GP_PIN(9, 16),
1671 };
1672 static const unsigned int vin5_field_mux[] = {
1673         VI5_FIELD_MARK,
1674 };
1675 static const unsigned int vin5_clkenb_pins[] = {
1676         RCAR_GP_PIN(9, 1),
1677 };
1678 static const unsigned int vin5_clkenb_mux[] = {
1679         VI5_CLKENB_MARK,
1680 };
1681 static const unsigned int vin5_clk_pins[] = {
1682         RCAR_GP_PIN(9, 0),
1683 };
1684 static const unsigned int vin5_clk_mux[] = {
1685         VI5_CLK_MARK,
1686 };
1687
1688 static const struct sh_pfc_pin_group pinmux_groups[] = {
1689         SH_PFC_PIN_GROUP(avb_link),
1690         SH_PFC_PIN_GROUP(avb_magic),
1691         SH_PFC_PIN_GROUP(avb_phy_int),
1692         SH_PFC_PIN_GROUP(avb_mdio),
1693         SH_PFC_PIN_GROUP(avb_mii),
1694         SH_PFC_PIN_GROUP(avb_gmii),
1695         SH_PFC_PIN_GROUP(avb_avtp_match),
1696         SH_PFC_PIN_GROUP(can0_data),
1697         SH_PFC_PIN_GROUP(can1_data),
1698         SH_PFC_PIN_GROUP(can_clk),
1699         SH_PFC_PIN_GROUP(du0_rgb666),
1700         SH_PFC_PIN_GROUP(du0_rgb888),
1701         SH_PFC_PIN_GROUP(du0_sync),
1702         SH_PFC_PIN_GROUP(du0_oddf),
1703         SH_PFC_PIN_GROUP(du0_disp),
1704         SH_PFC_PIN_GROUP(du0_cde),
1705         SH_PFC_PIN_GROUP(du1_rgb666),
1706         SH_PFC_PIN_GROUP(du1_sync),
1707         SH_PFC_PIN_GROUP(du1_oddf),
1708         SH_PFC_PIN_GROUP(du1_disp),
1709         SH_PFC_PIN_GROUP(du1_cde),
1710         SH_PFC_PIN_GROUP(intc_irq0),
1711         SH_PFC_PIN_GROUP(intc_irq1),
1712         SH_PFC_PIN_GROUP(intc_irq2),
1713         SH_PFC_PIN_GROUP(intc_irq3),
1714         SH_PFC_PIN_GROUP(lbsc_cs0),
1715         SH_PFC_PIN_GROUP(lbsc_cs1),
1716         SH_PFC_PIN_GROUP(lbsc_ex_cs0),
1717         SH_PFC_PIN_GROUP(lbsc_ex_cs1),
1718         SH_PFC_PIN_GROUP(lbsc_ex_cs2),
1719         SH_PFC_PIN_GROUP(lbsc_ex_cs3),
1720         SH_PFC_PIN_GROUP(lbsc_ex_cs4),
1721         SH_PFC_PIN_GROUP(lbsc_ex_cs5),
1722         SH_PFC_PIN_GROUP(msiof0_clk),
1723         SH_PFC_PIN_GROUP(msiof0_sync),
1724         SH_PFC_PIN_GROUP(msiof0_rx),
1725         SH_PFC_PIN_GROUP(msiof0_tx),
1726         SH_PFC_PIN_GROUP(msiof1_clk),
1727         SH_PFC_PIN_GROUP(msiof1_sync),
1728         SH_PFC_PIN_GROUP(msiof1_rx),
1729         SH_PFC_PIN_GROUP(msiof1_tx),
1730         SH_PFC_PIN_GROUP(qspi_ctrl),
1731         SH_PFC_PIN_GROUP(qspi_data2),
1732         SH_PFC_PIN_GROUP(qspi_data4),
1733         SH_PFC_PIN_GROUP(scif0_data),
1734         SH_PFC_PIN_GROUP(scif0_clk),
1735         SH_PFC_PIN_GROUP(scif0_ctrl),
1736         SH_PFC_PIN_GROUP(scif1_data),
1737         SH_PFC_PIN_GROUP(scif1_clk),
1738         SH_PFC_PIN_GROUP(scif1_ctrl),
1739         SH_PFC_PIN_GROUP(scif2_data),
1740         SH_PFC_PIN_GROUP(scif2_clk),
1741         SH_PFC_PIN_GROUP(scif3_data),
1742         SH_PFC_PIN_GROUP(scif3_clk),
1743         SH_PFC_PIN_GROUP(sdhi0_data1),
1744         SH_PFC_PIN_GROUP(sdhi0_data4),
1745         SH_PFC_PIN_GROUP(sdhi0_ctrl),
1746         SH_PFC_PIN_GROUP(sdhi0_cd),
1747         SH_PFC_PIN_GROUP(sdhi0_wp),
1748         VIN_DATA_PIN_GROUP(vin0_data, 24),
1749         VIN_DATA_PIN_GROUP(vin0_data, 20),
1750         SH_PFC_PIN_GROUP(vin0_data18),
1751         VIN_DATA_PIN_GROUP(vin0_data, 16),
1752         VIN_DATA_PIN_GROUP(vin0_data, 12),
1753         VIN_DATA_PIN_GROUP(vin0_data, 10),
1754         VIN_DATA_PIN_GROUP(vin0_data, 8),
1755         SH_PFC_PIN_GROUP(vin0_sync),
1756         SH_PFC_PIN_GROUP(vin0_field),
1757         SH_PFC_PIN_GROUP(vin0_clkenb),
1758         SH_PFC_PIN_GROUP(vin0_clk),
1759         VIN_DATA_PIN_GROUP(vin1_data, 24),
1760         VIN_DATA_PIN_GROUP(vin1_data, 20),
1761         SH_PFC_PIN_GROUP(vin1_data18),
1762         VIN_DATA_PIN_GROUP(vin1_data, 16),
1763         VIN_DATA_PIN_GROUP(vin1_data, 12),
1764         VIN_DATA_PIN_GROUP(vin1_data, 10),
1765         VIN_DATA_PIN_GROUP(vin1_data, 8),
1766         VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
1767         VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
1768         SH_PFC_PIN_GROUP(vin1_data18_b),
1769         VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
1770         SH_PFC_PIN_GROUP(vin1_sync),
1771         SH_PFC_PIN_GROUP(vin1_field),
1772         SH_PFC_PIN_GROUP(vin1_clkenb),
1773         SH_PFC_PIN_GROUP(vin1_clk),
1774         VIN_DATA_PIN_GROUP(vin2_data, 16),
1775         VIN_DATA_PIN_GROUP(vin2_data, 12),
1776         VIN_DATA_PIN_GROUP(vin2_data, 10),
1777         VIN_DATA_PIN_GROUP(vin2_data, 8),
1778         SH_PFC_PIN_GROUP(vin2_sync),
1779         SH_PFC_PIN_GROUP(vin2_field),
1780         SH_PFC_PIN_GROUP(vin2_clkenb),
1781         SH_PFC_PIN_GROUP(vin2_clk),
1782         VIN_DATA_PIN_GROUP(vin3_data, 16),
1783         VIN_DATA_PIN_GROUP(vin3_data, 12),
1784         VIN_DATA_PIN_GROUP(vin3_data, 10),
1785         VIN_DATA_PIN_GROUP(vin3_data, 8),
1786         SH_PFC_PIN_GROUP(vin3_sync),
1787         SH_PFC_PIN_GROUP(vin3_field),
1788         SH_PFC_PIN_GROUP(vin3_clkenb),
1789         SH_PFC_PIN_GROUP(vin3_clk),
1790         VIN_DATA_PIN_GROUP(vin4_data, 12),
1791         VIN_DATA_PIN_GROUP(vin4_data, 10),
1792         VIN_DATA_PIN_GROUP(vin4_data, 8),
1793         SH_PFC_PIN_GROUP(vin4_sync),
1794         SH_PFC_PIN_GROUP(vin4_field),
1795         SH_PFC_PIN_GROUP(vin4_clkenb),
1796         SH_PFC_PIN_GROUP(vin4_clk),
1797         VIN_DATA_PIN_GROUP(vin5_data, 12),
1798         VIN_DATA_PIN_GROUP(vin5_data, 10),
1799         VIN_DATA_PIN_GROUP(vin5_data, 8),
1800         SH_PFC_PIN_GROUP(vin5_sync),
1801         SH_PFC_PIN_GROUP(vin5_field),
1802         SH_PFC_PIN_GROUP(vin5_clkenb),
1803         SH_PFC_PIN_GROUP(vin5_clk),
1804 };
1805
1806 static const char * const avb_groups[] = {
1807         "avb_link",
1808         "avb_magic",
1809         "avb_phy_int",
1810         "avb_mdio",
1811         "avb_mii",
1812         "avb_gmii",
1813         "avb_avtp_match",
1814 };
1815
1816 static const char * const can0_groups[] = {
1817         "can0_data",
1818         "can_clk",
1819 };
1820
1821 static const char * const can1_groups[] = {
1822         "can1_data",
1823         "can_clk",
1824 };
1825
1826 static const char * const du0_groups[] = {
1827         "du0_rgb666",
1828         "du0_rgb888",
1829         "du0_sync",
1830         "du0_oddf",
1831         "du0_disp",
1832         "du0_cde",
1833 };
1834
1835 static const char * const du1_groups[] = {
1836         "du1_rgb666",
1837         "du1_sync",
1838         "du1_oddf",
1839         "du1_disp",
1840         "du1_cde",
1841 };
1842
1843 static const char * const intc_groups[] = {
1844         "intc_irq0",
1845         "intc_irq1",
1846         "intc_irq2",
1847         "intc_irq3",
1848 };
1849
1850 static const char * const lbsc_groups[] = {
1851         "lbsc_cs0",
1852         "lbsc_cs1",
1853         "lbsc_ex_cs0",
1854         "lbsc_ex_cs1",
1855         "lbsc_ex_cs2",
1856         "lbsc_ex_cs3",
1857         "lbsc_ex_cs4",
1858         "lbsc_ex_cs5",
1859 };
1860
1861 static const char * const msiof0_groups[] = {
1862         "msiof0_clk",
1863         "msiof0_sync",
1864         "msiof0_rx",
1865         "msiof0_tx",
1866 };
1867
1868 static const char * const msiof1_groups[] = {
1869         "msiof1_clk",
1870         "msiof1_sync",
1871         "msiof1_rx",
1872         "msiof1_tx",
1873 };
1874
1875 static const char * const qspi_groups[] = {
1876         "qspi_ctrl",
1877         "qspi_data2",
1878         "qspi_data4",
1879 };
1880
1881 static const char * const scif0_groups[] = {
1882         "scif0_data",
1883         "scif0_clk",
1884         "scif0_ctrl",
1885 };
1886
1887 static const char * const scif1_groups[] = {
1888         "scif1_data",
1889         "scif1_clk",
1890         "scif1_ctrl",
1891 };
1892
1893 static const char * const scif2_groups[] = {
1894         "scif2_data",
1895         "scif2_clk",
1896 };
1897
1898 static const char * const scif3_groups[] = {
1899         "scif3_data",
1900         "scif3_clk",
1901 };
1902
1903 static const char * const sdhi0_groups[] = {
1904         "sdhi0_data1",
1905         "sdhi0_data4",
1906         "sdhi0_ctrl",
1907         "sdhi0_cd",
1908         "sdhi0_wp",
1909 };
1910
1911 static const char * const vin0_groups[] = {
1912         "vin0_data24",
1913         "vin0_data20",
1914         "vin0_data18",
1915         "vin0_data16",
1916         "vin0_data12",
1917         "vin0_data10",
1918         "vin0_data8",
1919         "vin0_sync",
1920         "vin0_field",
1921         "vin0_clkenb",
1922         "vin0_clk",
1923 };
1924
1925 static const char * const vin1_groups[] = {
1926         "vin1_data24",
1927         "vin1_data20",
1928         "vin1_data18",
1929         "vin1_data16",
1930         "vin1_data12",
1931         "vin1_data10",
1932         "vin1_data8",
1933         "vin1_data24_b",
1934         "vin1_data20_b",
1935         "vin1_data18_b",
1936         "vin1_data16_b",
1937         "vin1_sync",
1938         "vin1_field",
1939         "vin1_clkenb",
1940         "vin1_clk",
1941 };
1942
1943 static const char * const vin2_groups[] = {
1944         "vin2_data16",
1945         "vin2_data12",
1946         "vin2_data10",
1947         "vin2_data8",
1948         "vin2_sync",
1949         "vin2_field",
1950         "vin2_clkenb",
1951         "vin2_clk",
1952 };
1953
1954 static const char * const vin3_groups[] = {
1955         "vin3_data16",
1956         "vin3_data12",
1957         "vin3_data10",
1958         "vin3_data8",
1959         "vin3_sync",
1960         "vin3_field",
1961         "vin3_clkenb",
1962         "vin3_clk",
1963 };
1964
1965 static const char * const vin4_groups[] = {
1966         "vin4_data12",
1967         "vin4_data10",
1968         "vin4_data8",
1969         "vin4_sync",
1970         "vin4_field",
1971         "vin4_clkenb",
1972         "vin4_clk",
1973 };
1974
1975 static const char * const vin5_groups[] = {
1976         "vin5_data12",
1977         "vin5_data10",
1978         "vin5_data8",
1979         "vin5_sync",
1980         "vin5_field",
1981         "vin5_clkenb",
1982         "vin5_clk",
1983 };
1984
1985 static const struct sh_pfc_function pinmux_functions[] = {
1986         SH_PFC_FUNCTION(avb),
1987         SH_PFC_FUNCTION(can0),
1988         SH_PFC_FUNCTION(can1),
1989         SH_PFC_FUNCTION(du0),
1990         SH_PFC_FUNCTION(du1),
1991         SH_PFC_FUNCTION(intc),
1992         SH_PFC_FUNCTION(lbsc),
1993         SH_PFC_FUNCTION(msiof0),
1994         SH_PFC_FUNCTION(msiof1),
1995         SH_PFC_FUNCTION(qspi),
1996         SH_PFC_FUNCTION(scif0),
1997         SH_PFC_FUNCTION(scif1),
1998         SH_PFC_FUNCTION(scif2),
1999         SH_PFC_FUNCTION(scif3),
2000         SH_PFC_FUNCTION(sdhi0),
2001         SH_PFC_FUNCTION(vin0),
2002         SH_PFC_FUNCTION(vin1),
2003         SH_PFC_FUNCTION(vin2),
2004         SH_PFC_FUNCTION(vin3),
2005         SH_PFC_FUNCTION(vin4),
2006         SH_PFC_FUNCTION(vin5),
2007 };
2008
2009 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2010         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
2011                 0, 0,
2012                 0, 0,
2013                 0, 0,
2014                 GP_0_28_FN, FN_IP1_4,
2015                 GP_0_27_FN, FN_IP1_3,
2016                 GP_0_26_FN, FN_IP1_2,
2017                 GP_0_25_FN, FN_IP1_1,
2018                 GP_0_24_FN, FN_IP1_0,
2019                 GP_0_23_FN, FN_IP0_23,
2020                 GP_0_22_FN, FN_IP0_22,
2021                 GP_0_21_FN, FN_IP0_21,
2022                 GP_0_20_FN, FN_IP0_20,
2023                 GP_0_19_FN, FN_IP0_19,
2024                 GP_0_18_FN, FN_IP0_18,
2025                 GP_0_17_FN, FN_IP0_17,
2026                 GP_0_16_FN, FN_IP0_16,
2027                 GP_0_15_FN, FN_IP0_15,
2028                 GP_0_14_FN, FN_IP0_14,
2029                 GP_0_13_FN, FN_IP0_13,
2030                 GP_0_12_FN, FN_IP0_12,
2031                 GP_0_11_FN, FN_IP0_11,
2032                 GP_0_10_FN, FN_IP0_10,
2033                 GP_0_9_FN, FN_IP0_9,
2034                 GP_0_8_FN, FN_IP0_8,
2035                 GP_0_7_FN, FN_IP0_7,
2036                 GP_0_6_FN, FN_IP0_6,
2037                 GP_0_5_FN, FN_IP0_5,
2038                 GP_0_4_FN, FN_IP0_4,
2039                 GP_0_3_FN, FN_IP0_3,
2040                 GP_0_2_FN, FN_IP0_2,
2041                 GP_0_1_FN, FN_IP0_1,
2042                 GP_0_0_FN, FN_IP0_0 ))
2043         },
2044         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
2045                 0, 0,
2046                 0, 0,
2047                 0, 0,
2048                 0, 0,
2049                 0, 0,
2050                 0, 0,
2051                 0, 0,
2052                 0, 0,
2053                 0, 0,
2054                 GP_1_22_FN, FN_DU1_CDE,
2055                 GP_1_21_FN, FN_DU1_DISP,
2056                 GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2057                 GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
2058                 GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
2059                 GP_1_17_FN, FN_DU1_DB7_C5,
2060                 GP_1_16_FN, FN_DU1_DB6_C4,
2061                 GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
2062                 GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
2063                 GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
2064                 GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
2065                 GP_1_11_FN, FN_IP1_16,
2066                 GP_1_10_FN, FN_IP1_15,
2067                 GP_1_9_FN, FN_IP1_14,
2068                 GP_1_8_FN, FN_IP1_13,
2069                 GP_1_7_FN, FN_IP1_12,
2070                 GP_1_6_FN, FN_IP1_11,
2071                 GP_1_5_FN, FN_IP1_10,
2072                 GP_1_4_FN, FN_IP1_9,
2073                 GP_1_3_FN, FN_IP1_8,
2074                 GP_1_2_FN, FN_IP1_7,
2075                 GP_1_1_FN, FN_IP1_6,
2076                 GP_1_0_FN, FN_IP1_5, ))
2077         },
2078         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
2079                 GP_2_31_FN, FN_A15,
2080                 GP_2_30_FN, FN_A14,
2081                 GP_2_29_FN, FN_A13,
2082                 GP_2_28_FN, FN_A12,
2083                 GP_2_27_FN, FN_A11,
2084                 GP_2_26_FN, FN_A10,
2085                 GP_2_25_FN, FN_A9,
2086                 GP_2_24_FN, FN_A8,
2087                 GP_2_23_FN, FN_A7,
2088                 GP_2_22_FN, FN_A6,
2089                 GP_2_21_FN, FN_A5,
2090                 GP_2_20_FN, FN_A4,
2091                 GP_2_19_FN, FN_A3,
2092                 GP_2_18_FN, FN_A2,
2093                 GP_2_17_FN, FN_A1,
2094                 GP_2_16_FN, FN_A0,
2095                 GP_2_15_FN, FN_D15,
2096                 GP_2_14_FN, FN_D14,
2097                 GP_2_13_FN, FN_D13,
2098                 GP_2_12_FN, FN_D12,
2099                 GP_2_11_FN, FN_D11,
2100                 GP_2_10_FN, FN_D10,
2101                 GP_2_9_FN, FN_D9,
2102                 GP_2_8_FN, FN_D8,
2103                 GP_2_7_FN, FN_D7,
2104                 GP_2_6_FN, FN_D6,
2105                 GP_2_5_FN, FN_D5,
2106                 GP_2_4_FN, FN_D4,
2107                 GP_2_3_FN, FN_D3,
2108                 GP_2_2_FN, FN_D2,
2109                 GP_2_1_FN, FN_D1,
2110                 GP_2_0_FN, FN_D0 ))
2111         },
2112         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
2113                 0, 0,
2114                 0, 0,
2115                 0, 0,
2116                 0, 0,
2117                 GP_3_27_FN, FN_CS0_N,
2118                 GP_3_26_FN, FN_IP1_22,
2119                 GP_3_25_FN, FN_IP1_21,
2120                 GP_3_24_FN, FN_IP1_20,
2121                 GP_3_23_FN, FN_IP1_19,
2122                 GP_3_22_FN, FN_IRQ3,
2123                 GP_3_21_FN, FN_IRQ2,
2124                 GP_3_20_FN, FN_IRQ1,
2125                 GP_3_19_FN, FN_IRQ0,
2126                 GP_3_18_FN, FN_EX_WAIT0,
2127                 GP_3_17_FN, FN_WE1_N,
2128                 GP_3_16_FN, FN_WE0_N,
2129                 GP_3_15_FN, FN_RD_WR_N,
2130                 GP_3_14_FN, FN_RD_N,
2131                 GP_3_13_FN, FN_BS_N,
2132                 GP_3_12_FN, FN_EX_CS5_N,
2133                 GP_3_11_FN, FN_EX_CS4_N,
2134                 GP_3_10_FN, FN_EX_CS3_N,
2135                 GP_3_9_FN, FN_EX_CS2_N,
2136                 GP_3_8_FN, FN_EX_CS1_N,
2137                 GP_3_7_FN, FN_EX_CS0_N,
2138                 GP_3_6_FN, FN_CS1_N_A26,
2139                 GP_3_5_FN, FN_IP1_18,
2140                 GP_3_4_FN, FN_IP1_17,
2141                 GP_3_3_FN, FN_A19,
2142                 GP_3_2_FN, FN_A18,
2143                 GP_3_1_FN, FN_A17,
2144                 GP_3_0_FN, FN_A16 ))
2145         },
2146         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
2147                 0, 0,
2148                 0, 0,
2149                 0, 0,
2150                 0, 0,
2151                 0, 0,
2152                 0, 0,
2153                 0, 0,
2154                 0, 0,
2155                 0, 0,
2156                 0, 0,
2157                 0, 0,
2158                 0, 0,
2159                 0, 0,
2160                 0, 0,
2161                 0, 0,
2162                 GP_4_16_FN, FN_VI0_FIELD,
2163                 GP_4_15_FN, FN_VI0_D11_G3_Y3,
2164                 GP_4_14_FN, FN_VI0_D10_G2_Y2,
2165                 GP_4_13_FN, FN_VI0_D9_G1_Y1,
2166                 GP_4_12_FN, FN_VI0_D8_G0_Y0,
2167                 GP_4_11_FN, FN_VI0_D7_B7_C7,
2168                 GP_4_10_FN, FN_VI0_D6_B6_C6,
2169                 GP_4_9_FN, FN_VI0_D5_B5_C5,
2170                 GP_4_8_FN, FN_VI0_D4_B4_C4,
2171                 GP_4_7_FN, FN_VI0_D3_B3_C3,
2172                 GP_4_6_FN, FN_VI0_D2_B2_C2,
2173                 GP_4_5_FN, FN_VI0_D1_B1_C1,
2174                 GP_4_4_FN, FN_VI0_D0_B0_C0,
2175                 GP_4_3_FN, FN_VI0_VSYNC_N,
2176                 GP_4_2_FN, FN_VI0_HSYNC_N,
2177                 GP_4_1_FN, FN_VI0_CLKENB,
2178                 GP_4_0_FN, FN_VI0_CLK ))
2179         },
2180         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
2181                 0, 0,
2182                 0, 0,
2183                 0, 0,
2184                 0, 0,
2185                 0, 0,
2186                 0, 0,
2187                 0, 0,
2188                 0, 0,
2189                 0, 0,
2190                 0, 0,
2191                 0, 0,
2192                 0, 0,
2193                 0, 0,
2194                 0, 0,
2195                 0, 0,
2196                 GP_5_16_FN, FN_VI1_FIELD,
2197                 GP_5_15_FN, FN_VI1_D11_G3_Y3,
2198                 GP_5_14_FN, FN_VI1_D10_G2_Y2,
2199                 GP_5_13_FN, FN_VI1_D9_G1_Y1,
2200                 GP_5_12_FN, FN_VI1_D8_G0_Y0,
2201                 GP_5_11_FN, FN_VI1_D7_B7_C7,
2202                 GP_5_10_FN, FN_VI1_D6_B6_C6,
2203                 GP_5_9_FN, FN_VI1_D5_B5_C5,
2204                 GP_5_8_FN, FN_VI1_D4_B4_C4,
2205                 GP_5_7_FN, FN_VI1_D3_B3_C3,
2206                 GP_5_6_FN, FN_VI1_D2_B2_C2,
2207                 GP_5_5_FN, FN_VI1_D1_B1_C1,
2208                 GP_5_4_FN, FN_VI1_D0_B0_C0,
2209                 GP_5_3_FN, FN_VI1_VSYNC_N,
2210                 GP_5_2_FN, FN_VI1_HSYNC_N,
2211                 GP_5_1_FN, FN_VI1_CLKENB,
2212                 GP_5_0_FN, FN_VI1_CLK ))
2213         },
2214         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
2215                 0, 0,
2216                 0, 0,
2217                 0, 0,
2218                 0, 0,
2219                 0, 0,
2220                 0, 0,
2221                 0, 0,
2222                 0, 0,
2223                 0, 0,
2224                 0, 0,
2225                 0, 0,
2226                 0, 0,
2227                 0, 0,
2228                 0, 0,
2229                 0, 0,
2230                 GP_6_16_FN, FN_IP2_16,
2231                 GP_6_15_FN, FN_IP2_15,
2232                 GP_6_14_FN, FN_IP2_14,
2233                 GP_6_13_FN, FN_IP2_13,
2234                 GP_6_12_FN, FN_IP2_12,
2235                 GP_6_11_FN, FN_IP2_11,
2236                 GP_6_10_FN, FN_IP2_10,
2237                 GP_6_9_FN, FN_IP2_9,
2238                 GP_6_8_FN, FN_IP2_8,
2239                 GP_6_7_FN, FN_IP2_7,
2240                 GP_6_6_FN, FN_IP2_6,
2241                 GP_6_5_FN, FN_IP2_5,
2242                 GP_6_4_FN, FN_IP2_4,
2243                 GP_6_3_FN, FN_IP2_3,
2244                 GP_6_2_FN, FN_IP2_2,
2245                 GP_6_1_FN, FN_IP2_1,
2246                 GP_6_0_FN, FN_IP2_0 ))
2247         },
2248         { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP(
2249                 0, 0,
2250                 0, 0,
2251                 0, 0,
2252                 0, 0,
2253                 0, 0,
2254                 0, 0,
2255                 0, 0,
2256                 0, 0,
2257                 0, 0,
2258                 0, 0,
2259                 0, 0,
2260                 0, 0,
2261                 0, 0,
2262                 0, 0,
2263                 0, 0,
2264                 GP_7_16_FN, FN_VI3_FIELD,
2265                 GP_7_15_FN, FN_IP3_14,
2266                 GP_7_14_FN, FN_VI3_D10_Y2,
2267                 GP_7_13_FN, FN_IP3_13,
2268                 GP_7_12_FN, FN_IP3_12,
2269                 GP_7_11_FN, FN_IP3_11,
2270                 GP_7_10_FN, FN_IP3_10,
2271                 GP_7_9_FN, FN_IP3_9,
2272                 GP_7_8_FN, FN_IP3_8,
2273                 GP_7_7_FN, FN_IP3_7,
2274                 GP_7_6_FN, FN_IP3_6,
2275                 GP_7_5_FN, FN_IP3_5,
2276                 GP_7_4_FN, FN_IP3_4,
2277                 GP_7_3_FN, FN_IP3_3,
2278                 GP_7_2_FN, FN_IP3_2,
2279                 GP_7_1_FN, FN_IP3_1,
2280                 GP_7_0_FN, FN_IP3_0 ))
2281         },
2282         { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP(
2283                 0, 0,
2284                 0, 0,
2285                 0, 0,
2286                 0, 0,
2287                 0, 0,
2288                 0, 0,
2289                 0, 0,
2290                 0, 0,
2291                 0, 0,
2292                 0, 0,
2293                 0, 0,
2294                 0, 0,
2295                 0, 0,
2296                 0, 0,
2297                 0, 0,
2298                 GP_8_16_FN, FN_IP4_24,
2299                 GP_8_15_FN, FN_IP4_23,
2300                 GP_8_14_FN, FN_IP4_22,
2301                 GP_8_13_FN, FN_IP4_21,
2302                 GP_8_12_FN, FN_IP4_20_19,
2303                 GP_8_11_FN, FN_IP4_18_17,
2304                 GP_8_10_FN, FN_IP4_16_15,
2305                 GP_8_9_FN, FN_IP4_14_13,
2306                 GP_8_8_FN, FN_IP4_12_11,
2307                 GP_8_7_FN, FN_IP4_10_9,
2308                 GP_8_6_FN, FN_IP4_8_7,
2309                 GP_8_5_FN, FN_IP4_6_5,
2310                 GP_8_4_FN, FN_IP4_4,
2311                 GP_8_3_FN, FN_IP4_3_2,
2312                 GP_8_2_FN, FN_IP4_1,
2313                 GP_8_1_FN, FN_IP4_0,
2314                 GP_8_0_FN, FN_VI4_CLK ))
2315         },
2316         { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP(
2317                 0, 0,
2318                 0, 0,
2319                 0, 0,
2320                 0, 0,
2321                 0, 0,
2322                 0, 0,
2323                 0, 0,
2324                 0, 0,
2325                 0, 0,
2326                 0, 0,
2327                 0, 0,
2328                 0, 0,
2329                 0, 0,
2330                 0, 0,
2331                 0, 0,
2332                 GP_9_16_FN, FN_VI5_FIELD,
2333                 GP_9_15_FN, FN_VI5_D11_Y3,
2334                 GP_9_14_FN, FN_VI5_D10_Y2,
2335                 GP_9_13_FN, FN_VI5_D9_Y1,
2336                 GP_9_12_FN, FN_IP5_11,
2337                 GP_9_11_FN, FN_IP5_10,
2338                 GP_9_10_FN, FN_IP5_9,
2339                 GP_9_9_FN, FN_IP5_8,
2340                 GP_9_8_FN, FN_IP5_7,
2341                 GP_9_7_FN, FN_IP5_6,
2342                 GP_9_6_FN, FN_IP5_5,
2343                 GP_9_5_FN, FN_IP5_4,
2344                 GP_9_4_FN, FN_IP5_3,
2345                 GP_9_3_FN, FN_IP5_2,
2346                 GP_9_2_FN, FN_IP5_1,
2347                 GP_9_1_FN, FN_IP5_0,
2348                 GP_9_0_FN, FN_VI5_CLK ))
2349         },
2350         { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP(
2351                 GP_10_31_FN, FN_CAN1_RX,
2352                 GP_10_30_FN, FN_CAN1_TX,
2353                 GP_10_29_FN, FN_CAN_CLK,
2354                 GP_10_28_FN, FN_CAN0_RX,
2355                 GP_10_27_FN, FN_CAN0_TX,
2356                 GP_10_26_FN, FN_SCIF_CLK,
2357                 GP_10_25_FN, FN_IP6_18_17,
2358                 GP_10_24_FN, FN_IP6_16,
2359                 GP_10_23_FN, FN_IP6_15_14,
2360                 GP_10_22_FN, FN_IP6_13_12,
2361                 GP_10_21_FN, FN_IP6_11_10,
2362                 GP_10_20_FN, FN_IP6_9_8,
2363                 GP_10_19_FN, FN_RX1,
2364                 GP_10_18_FN, FN_TX1,
2365                 GP_10_17_FN, FN_RTS1_N,
2366                 GP_10_16_FN, FN_CTS1_N,
2367                 GP_10_15_FN, FN_SCK1,
2368                 GP_10_14_FN, FN_RX0,
2369                 GP_10_13_FN, FN_TX0,
2370                 GP_10_12_FN, FN_RTS0_N,
2371                 GP_10_11_FN, FN_CTS0_N,
2372                 GP_10_10_FN, FN_SCK0,
2373                 GP_10_9_FN, FN_IP6_7,
2374                 GP_10_8_FN, FN_IP6_6,
2375                 GP_10_7_FN, FN_HCTS1_N,
2376                 GP_10_6_FN, FN_IP6_5,
2377                 GP_10_5_FN, FN_IP6_4,
2378                 GP_10_4_FN, FN_IP6_3,
2379                 GP_10_3_FN, FN_IP6_2,
2380                 GP_10_2_FN, FN_HRTS0_N,
2381                 GP_10_1_FN, FN_IP6_1,
2382                 GP_10_0_FN, FN_IP6_0 ))
2383         },
2384         { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP(
2385                 0, 0,
2386                 0, 0,
2387                 GP_11_29_FN, FN_AVS2,
2388                 GP_11_28_FN, FN_AVS1,
2389                 GP_11_27_FN, FN_ADICHS2,
2390                 GP_11_26_FN, FN_ADICHS1,
2391                 GP_11_25_FN, FN_ADICHS0,
2392                 GP_11_24_FN, FN_ADIDATA,
2393                 GP_11_23_FN, FN_ADICS_SAMP,
2394                 GP_11_22_FN, FN_ADICLK,
2395                 GP_11_21_FN, FN_IP7_20,
2396                 GP_11_20_FN, FN_IP7_19,
2397                 GP_11_19_FN, FN_IP7_18,
2398                 GP_11_18_FN, FN_IP7_17,
2399                 GP_11_17_FN, FN_IP7_16,
2400                 GP_11_16_FN, FN_IP7_15_14,
2401                 GP_11_15_FN, FN_IP7_13_12,
2402                 GP_11_14_FN, FN_IP7_11_10,
2403                 GP_11_13_FN, FN_IP7_9_8,
2404                 GP_11_12_FN, FN_SD0_WP,
2405                 GP_11_11_FN, FN_SD0_CD,
2406                 GP_11_10_FN, FN_SD0_DAT3,
2407                 GP_11_9_FN, FN_SD0_DAT2,
2408                 GP_11_8_FN, FN_SD0_DAT1,
2409                 GP_11_7_FN, FN_SD0_DAT0,
2410                 GP_11_6_FN, FN_SD0_CMD,
2411                 GP_11_5_FN, FN_SD0_CLK,
2412                 GP_11_4_FN, FN_IP7_7,
2413                 GP_11_3_FN, FN_IP7_6,
2414                 GP_11_2_FN, FN_IP7_5_4,
2415                 GP_11_1_FN, FN_IP7_3_2,
2416                 GP_11_0_FN, FN_IP7_1_0 ))
2417         },
2418         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2419                              GROUP(4, 4,
2420                                    1, 1, 1, 1, 1, 1, 1, 1,
2421                                    1, 1, 1, 1, 1, 1, 1, 1,
2422                                    1, 1, 1, 1, 1, 1, 1, 1),
2423                              GROUP(
2424                 /* IP0_31_28 [4] */
2425                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2426                 /* IP0_27_24 [4] */
2427                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2428                 /* IP0_23 [1] */
2429                 FN_DU0_DB7_C5, 0,
2430                 /* IP0_22 [1] */
2431                 FN_DU0_DB6_C4, 0,
2432                 /* IP0_21 [1] */
2433                 FN_DU0_DB5_C3, 0,
2434                 /* IP0_20 [1] */
2435                 FN_DU0_DB4_C2, 0,
2436                 /* IP0_19 [1] */
2437                 FN_DU0_DB3_C1, 0,
2438                 /* IP0_18 [1] */
2439                 FN_DU0_DB2_C0, 0,
2440                 /* IP0_17 [1] */
2441                 FN_DU0_DB1, 0,
2442                 /* IP0_16 [1] */
2443                 FN_DU0_DB0, 0,
2444                 /* IP0_15 [1] */
2445                 FN_DU0_DG7_Y3_DATA15, 0,
2446                 /* IP0_14 [1] */
2447                 FN_DU0_DG6_Y2_DATA14, 0,
2448                 /* IP0_13 [1] */
2449                 FN_DU0_DG5_Y1_DATA13, 0,
2450                 /* IP0_12 [1] */
2451                 FN_DU0_DG4_Y0_DATA12, 0,
2452                 /* IP0_11 [1] */
2453                 FN_DU0_DG3_C7_DATA11, 0,
2454                 /* IP0_10 [1] */
2455                 FN_DU0_DG2_C6_DATA10, 0,
2456                 /* IP0_9 [1] */
2457                 FN_DU0_DG1_DATA9, 0,
2458                 /* IP0_8 [1] */
2459                 FN_DU0_DG0_DATA8, 0,
2460                 /* IP0_7 [1] */
2461                 FN_DU0_DR7_Y9_DATA7, 0,
2462                 /* IP0_6 [1] */
2463                 FN_DU0_DR6_Y8_DATA6, 0,
2464                 /* IP0_5 [1] */
2465                 FN_DU0_DR5_Y7_DATA5, 0,
2466                 /* IP0_4 [1] */
2467                 FN_DU0_DR4_Y6_DATA4, 0,
2468                 /* IP0_3 [1] */
2469                 FN_DU0_DR3_Y5_DATA3, 0,
2470                 /* IP0_2 [1] */
2471                 FN_DU0_DR2_Y4_DATA2, 0,
2472                 /* IP0_1 [1] */
2473                 FN_DU0_DR1_DATA1, 0,
2474                 /* IP0_0 [1] */
2475                 FN_DU0_DR0_DATA0, 0 ))
2476         },
2477         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2478                              GROUP(4, 4,
2479                                    1, 1, 1, 1, 1, 1, 1, 1,
2480                                    1, 1, 1, 1, 1, 1, 1, 1,
2481                                    1, 1, 1, 1, 1, 1, 1, 1),
2482                              GROUP(
2483                 /* IP1_31_28 [4] */
2484                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2485                 /* IP1_27_24 [4] */
2486                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2487                 /* IP1_23 [1] */
2488                 0, 0,
2489                 /* IP1_22 [1] */
2490                 FN_A25, FN_SSL,
2491                 /* IP1_21 [1] */
2492                 FN_A24, FN_SPCLK,
2493                 /* IP1_20 [1] */
2494                 FN_A23, FN_IO3,
2495                 /* IP1_19 [1] */
2496                 FN_A22, FN_IO2,
2497                 /* IP1_18 [1] */
2498                 FN_A21, FN_MISO_IO1,
2499                 /* IP1_17 [1] */
2500                 FN_A20, FN_MOSI_IO0,
2501                 /* IP1_16 [1] */
2502                 FN_DU1_DG7_Y3_DATA11, 0,
2503                 /* IP1_15 [1] */
2504                 FN_DU1_DG6_Y2_DATA10, 0,
2505                 /* IP1_14 [1] */
2506                 FN_DU1_DG5_Y1_DATA9, 0,
2507                 /* IP1_13 [1] */
2508                 FN_DU1_DG4_Y0_DATA8, 0,
2509                 /* IP1_12 [1] */
2510                 FN_DU1_DG3_C7_DATA7, 0,
2511                 /* IP1_11 [1] */
2512                 FN_DU1_DG2_C6_DATA6, 0,
2513                 /* IP1_10 [1] */
2514                 FN_DU1_DR7_DATA5, 0,
2515                 /* IP1_9 [1] */
2516                 FN_DU1_DR6_DATA4, 0,
2517                 /* IP1_8 [1] */
2518                 FN_DU1_DR5_Y7_DATA3, 0,
2519                 /* IP1_7 [1] */
2520                 FN_DU1_DR4_Y6_DATA2, 0,
2521                 /* IP1_6 [1] */
2522                 FN_DU1_DR3_Y5_DATA1, 0,
2523                 /* IP1_5 [1] */
2524                 FN_DU1_DR2_Y4_DATA0, 0,
2525                 /* IP1_4 [1] */
2526                 FN_DU0_CDE, 0,
2527                 /* IP1_3 [1] */
2528                 FN_DU0_DISP, 0,
2529                 /* IP1_2 [1] */
2530                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
2531                 /* IP1_1 [1] */
2532                 FN_DU0_EXVSYNC_DU0_VSYNC, 0,
2533                 /* IP1_0 [1] */
2534                 FN_DU0_EXHSYNC_DU0_HSYNC, 0 ))
2535         },
2536         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2537                              GROUP(4, 4,
2538                                    4, 3, 1,
2539                                    1, 1, 1, 1, 1, 1, 1, 1,
2540                                    1, 1, 1, 1, 1, 1, 1, 1),
2541                              GROUP(
2542                 /* IP2_31_28 [4] */
2543                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2544                 /* IP2_27_24 [4] */
2545                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2546                 /* IP2_23_20 [4] */
2547                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2548                 /* IP2_19_17 [3] */
2549                 0, 0, 0, 0, 0, 0, 0, 0,
2550                 /* IP2_16 [1] */
2551                 FN_VI2_FIELD, FN_AVB_TXD2,
2552                 /* IP2_15 [1] */
2553                 FN_VI2_D11_Y3, FN_AVB_TXD1,
2554                 /* IP2_14 [1] */
2555                 FN_VI2_D10_Y2, FN_AVB_TXD0,
2556                 /* IP2_13 [1] */
2557                 FN_VI2_D9_Y1, FN_AVB_TX_EN,
2558                 /* IP2_12 [1] */
2559                 FN_VI2_D8_Y0, FN_AVB_TXD3,
2560                 /* IP2_11 [1] */
2561                 FN_VI2_D7_C7, FN_AVB_COL,
2562                 /* IP2_10 [1] */
2563                 FN_VI2_D6_C6, FN_AVB_RX_ER,
2564                 /* IP2_9 [1] */
2565                 FN_VI2_D5_C5, FN_AVB_RXD7,
2566                 /* IP2_8 [1] */
2567                 FN_VI2_D4_C4, FN_AVB_RXD6,
2568                 /* IP2_7 [1] */
2569                 FN_VI2_D3_C3, FN_AVB_RXD5,
2570                 /* IP2_6 [1] */
2571                 FN_VI2_D2_C2, FN_AVB_RXD4,
2572                 /* IP2_5 [1] */
2573                 FN_VI2_D1_C1, FN_AVB_RXD3,
2574                 /* IP2_4 [1] */
2575                 FN_VI2_D0_C0, FN_AVB_RXD2,
2576                 /* IP2_3 [1] */
2577                 FN_VI2_VSYNC_N, FN_AVB_RXD1,
2578                 /* IP2_2 [1] */
2579                 FN_VI2_HSYNC_N, FN_AVB_RXD0,
2580                 /* IP2_1 [1] */
2581                 FN_VI2_CLKENB, FN_AVB_RX_DV,
2582                 /* IP2_0 [1] */
2583                 FN_VI2_CLK, FN_AVB_RX_CLK ))
2584         },
2585         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2586                              GROUP(4, 4,
2587                                    4, 4,
2588                                    1, 1, 1, 1, 1, 1, 1, 1,
2589                                    1, 1, 1, 1, 1, 1, 1, 1),
2590                              GROUP(
2591                 /* IP3_31_28 [4] */
2592                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2593                 /* IP3_27_24 [4] */
2594                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2595                 /* IP3_23_20 [4] */
2596                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2597                 /* IP3_19_16 [4] */
2598                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2599                 /* IP3_15 [1] */
2600                 0, 0,
2601                 /* IP3_14 [1] */
2602                 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
2603                 /* IP3_13 [1] */
2604                 FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
2605                 /* IP3_12 [1] */
2606                 FN_VI3_D8_Y0, FN_AVB_CRS,
2607                 /* IP3_11 [1] */
2608                 FN_VI3_D7_C7, FN_AVB_PHY_INT,
2609                 /* IP3_10 [1] */
2610                 FN_VI3_D6_C6, FN_AVB_MAGIC,
2611                 /* IP3_9 [1] */
2612                 FN_VI3_D5_C5, FN_AVB_LINK,
2613                 /* IP3_8 [1] */
2614                 FN_VI3_D4_C4, FN_AVB_MDIO,
2615                 /* IP3_7 [1] */
2616                 FN_VI3_D3_C3, FN_AVB_MDC,
2617                 /* IP3_6 [1] */
2618                 FN_VI3_D2_C2, FN_AVB_GTX_CLK,
2619                 /* IP3_5 [1] */
2620                 FN_VI3_D1_C1, FN_AVB_TX_ER,
2621                 /* IP3_4 [1] */
2622                 FN_VI3_D0_C0, FN_AVB_TXD7,
2623                 /* IP3_3 [1] */
2624                 FN_VI3_VSYNC_N, FN_AVB_TXD6,
2625                 /* IP3_2 [1] */
2626                 FN_VI3_HSYNC_N, FN_AVB_TXD5,
2627                 /* IP3_1 [1] */
2628                 FN_VI3_CLKENB, FN_AVB_TXD4,
2629                 /* IP3_0 [1] */
2630                 FN_VI3_CLK, FN_AVB_TX_CLK ))
2631         },
2632         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2633                              GROUP(4, 3, 1,
2634                                    1, 1, 1, 2, 2, 2,
2635                                    2, 2, 2, 2, 2, 1, 2, 1, 1),
2636                              GROUP(
2637                 /* IP4_31_28 [4] */
2638                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2639                 /* IP4_27_25 [3] */
2640                 0, 0, 0, 0, 0, 0, 0, 0,
2641                 /* IP4_24 [1] */
2642                 FN_VI4_FIELD, FN_VI3_D15_Y7,
2643                 /* IP4_23 [1] */
2644                 FN_VI4_D11_Y3, FN_VI3_D14_Y6,
2645                 /* IP4_22 [1] */
2646                 FN_VI4_D10_Y2, FN_VI3_D13_Y5,
2647                 /* IP4_21 [1] */
2648                 FN_VI4_D9_Y1, FN_VI3_D12_Y4,
2649                 /* IP4_20_19 [2] */
2650                 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
2651                 /* IP4_18_17 [2] */
2652                 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
2653                 /* IP4_16_15 [2] */
2654                 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
2655                 /* IP4_14_13 [2] */
2656                 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
2657                 /* IP4_12_11 [2] */
2658                 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
2659                 /* IP4_10_9 [2] */
2660                 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
2661                 /* IP4_8_7 [2] */
2662                 FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
2663                 /* IP4_6_5 [2] */
2664                 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
2665                 /* IP4_4 [1] */
2666                 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
2667                 /* IP4_3_2 [2] */
2668                 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
2669                 /* IP4_1 [1] */
2670                 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
2671                 /* IP4_0 [1] */
2672                 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 ))
2673         },
2674         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2675                              GROUP(4, 4,
2676                                    4, 4,
2677                                    4, 1, 1, 1, 1,
2678                                    1, 1, 1, 1, 1, 1, 1, 1),
2679                              GROUP(
2680                 /* IP5_31_28 [4] */
2681                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2682                 /* IP5_27_24 [4] */
2683                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2684                 /* IP5_23_20 [4] */
2685                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2686                 /* IP5_19_16 [4] */
2687                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2688                 /* IP5_15_12 [4] */
2689                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2690                 /* IP5_11 [1] */
2691                 FN_VI5_D8_Y0, FN_VI1_D23_R7,
2692                 /* IP5_10 [1] */
2693                 FN_VI5_D7_C7, FN_VI1_D22_R6,
2694                 /* IP5_9 [1] */
2695                 FN_VI5_D6_C6, FN_VI1_D21_R5,
2696                 /* IP5_8 [1] */
2697                 FN_VI5_D5_C5, FN_VI1_D20_R4,
2698                 /* IP5_7 [1] */
2699                 FN_VI5_D4_C4, FN_VI1_D19_R3,
2700                 /* IP5_6 [1] */
2701                 FN_VI5_D3_C3, FN_VI1_D18_R2,
2702                 /* IP5_5 [1] */
2703                 FN_VI5_D2_C2, FN_VI1_D17_R1,
2704                 /* IP5_4 [1] */
2705                 FN_VI5_D1_C1, FN_VI1_D16_R0,
2706                 /* IP5_3 [1] */
2707                 FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
2708                 /* IP5_2 [1] */
2709                 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
2710                 /* IP5_1 [1] */
2711                 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
2712                 /* IP5_0 [1] */
2713                 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B ))
2714         },
2715         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2716                              GROUP(4, 4,
2717                                    4, 1, 2, 1,
2718                                    2, 2, 2, 2,
2719                                    1, 1, 1, 1, 1, 1, 1, 1),
2720                              GROUP(
2721                 /* IP6_31_28 [4] */
2722                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2723                 /* IP6_27_24 [4] */
2724                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2725                 /* IP6_23_20 [4] */
2726                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2727                 /* IP6_19 [1] */
2728                 0, 0,
2729                 /* IP6_18_17 [2] */
2730                 FN_DREQ1_N, FN_RX3, 0, 0,
2731                 /* IP6_16 [1] */
2732                 FN_TX3, 0,
2733                 /* IP6_15_14 [2] */
2734                 FN_DACK1, FN_SCK3, 0, 0,
2735                 /* IP6_13_12 [2] */
2736                 FN_DREQ0_N, FN_RX2, 0, 0,
2737                 /* IP6_11_10 [2] */
2738                 FN_DACK0, FN_TX2, 0, 0,
2739                 /* IP6_9_8 [2] */
2740                 FN_DRACK0, FN_SCK2, 0, 0,
2741                 /* IP6_7 [1] */
2742                 FN_MSIOF1_RXD, FN_HRX1,
2743                 /* IP6_6 [1] */
2744                 FN_MSIOF1_TXD, FN_HTX1,
2745                 /* IP6_5 [1] */
2746                 FN_MSIOF1_SYNC, FN_HRTS1_N,
2747                 /* IP6_4 [1] */
2748                 FN_MSIOF1_SCK, FN_HSCK1,
2749                 /* IP6_3 [1] */
2750                 FN_MSIOF0_RXD, FN_HRX0,
2751                 /* IP6_2 [1] */
2752                 FN_MSIOF0_TXD, FN_HTX0,
2753                 /* IP6_1 [1] */
2754                 FN_MSIOF0_SYNC, FN_HCTS0_N,
2755                 /* IP6_0 [1] */
2756                 FN_MSIOF0_SCK, FN_HSCK0 ))
2757         },
2758         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2759                              GROUP(4, 4,
2760                                    3, 1, 1, 1, 1, 1,
2761                                    2, 2, 2, 2,
2762                                    1, 1, 2, 2, 2),
2763                              GROUP(
2764                 /* IP7_31_28 [4] */
2765                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2766                 /* IP7_27_24 [4] */
2767                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2768                 /* IP7_23_21 [3] */
2769                 0, 0, 0, 0, 0, 0, 0, 0,
2770                 /* IP7_20 [1] */
2771                 FN_AUDIO_CLKB, 0,
2772                 /* IP7_19 [1] */
2773                 FN_AUDIO_CLKA, 0,
2774                 /* IP7_18 [1] */
2775                 FN_AUDIO_CLKOUT, 0,
2776                 /* IP7_17 [1] */
2777                 FN_SSI_SDATA4, 0,
2778                 /* IP7_16 [1] */
2779                 FN_SSI_WS4, 0,
2780                 /* IP7_15_14 [2] */
2781                 FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
2782                 /* IP7_13_12 [2] */
2783                 FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
2784                 /* IP7_11_10 [2] */
2785                 FN_SSI_WS34, FN_TPU0TO1, 0, 0,
2786                 /* IP7_9_8 [2] */
2787                 FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
2788                 /* IP7_7 [1] */
2789                 FN_PWM4, 0,
2790                 /* IP7_6 [1] */
2791                 FN_PWM3, 0,
2792                 /* IP7_5_4 [2] */
2793                 FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
2794                 /* IP7_3_2 [2] */
2795                 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
2796                 /* IP7_1_0 [2] */
2797                 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
2798         },
2799         { },
2800 };
2801
2802 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2803         { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
2804                 [ 0] = RCAR_GP_PIN(0, 0),       /* DU0_DR0_DATA0 */
2805                 [ 1] = RCAR_GP_PIN(0, 1),       /* DU0_DR1_DATA1 */
2806                 [ 2] = RCAR_GP_PIN(0, 2),       /* DU0_DR2_Y4_DATA2 */
2807                 [ 3] = RCAR_GP_PIN(0, 3),       /* DU0_DR3_Y5_DATA3 */
2808                 [ 4] = RCAR_GP_PIN(0, 4),       /* DU0_DR4_Y6_DATA4 */
2809                 [ 5] = RCAR_GP_PIN(0, 5),       /* DU0_DR5_Y7_DATA5 */
2810                 [ 6] = RCAR_GP_PIN(0, 6),       /* DU0_DR6_Y8_DATA6 */
2811                 [ 7] = RCAR_GP_PIN(0, 7),       /* DU0_DR7_Y9_DATA7 */
2812                 [ 8] = RCAR_GP_PIN(0, 8),       /* DU0_DG0_DATA8 */
2813                 [ 9] = RCAR_GP_PIN(0, 9),       /* DU0_DG1_DATA9 */
2814                 [10] = RCAR_GP_PIN(0, 10),      /* DU0_DG2_C6_DATA10 */
2815                 [11] = RCAR_GP_PIN(0, 11),      /* DU0_DG3_C7_DATA11 */
2816                 [12] = RCAR_GP_PIN(0, 12),      /* DU0_DG4_Y0_DATA12 */
2817                 [13] = RCAR_GP_PIN(0, 13),      /* DU0_DG5_Y1_DATA13 */
2818                 [14] = RCAR_GP_PIN(0, 14),      /* DU0_DG6_Y2_DATA14 */
2819                 [15] = RCAR_GP_PIN(0, 15),      /* DU0_DG7_Y3_DATA15 */
2820                 [16] = RCAR_GP_PIN(0, 16),      /* DU0_DB0 */
2821                 [17] = RCAR_GP_PIN(0, 17),      /* DU0_DB1 */
2822                 [18] = RCAR_GP_PIN(0, 18),      /* DU0_DB2_C0 */
2823                 [19] = RCAR_GP_PIN(0, 19),      /* DU0_DB3_C1 */
2824                 [20] = RCAR_GP_PIN(0, 20),      /* DU0_DB4_C2 */
2825                 [21] = RCAR_GP_PIN(0, 21),      /* DU0_DB5_C3 */
2826                 [22] = RCAR_GP_PIN(0, 22),      /* DU0_DB6_C4 */
2827                 [23] = RCAR_GP_PIN(0, 23),      /* DU0_DB7_C5 */
2828                 [24] = RCAR_GP_PIN(0, 24),      /* DU0_EXHSYNC/DU0_HSYNC */
2829                 [25] = RCAR_GP_PIN(0, 25),      /* DU0_EXVSYNC/DU0_VSYNC */
2830                 [26] = RCAR_GP_PIN(0, 26),      /* DU0_EXODDF/DU0_ODDF_DISP_CDE */
2831                 [27] = RCAR_GP_PIN(0, 27),      /* DU0_DISP */
2832                 [28] = RCAR_GP_PIN(0, 28),      /* DU0_CDE */
2833                 [29] = SH_PFC_PIN_NONE,
2834                 [30] = SH_PFC_PIN_NONE,
2835                 [31] = SH_PFC_PIN_NONE,
2836         } },
2837         { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
2838                 [ 0] = RCAR_GP_PIN(1, 0),       /* DU1_DR2_Y4_DATA0 */
2839                 [ 1] = RCAR_GP_PIN(1, 1),       /* DU1_DR3_Y5_DATA1 */
2840                 [ 2] = RCAR_GP_PIN(1, 2),       /* DU1_DR4_Y6_DATA2 */
2841                 [ 3] = RCAR_GP_PIN(1, 3),       /* DU1_DR5_Y7_DATA3 */
2842                 [ 4] = RCAR_GP_PIN(1, 4),       /* DU1_DR6_DATA4 */
2843                 [ 5] = RCAR_GP_PIN(1, 5),       /* DU1_DR7_DATA5 */
2844                 [ 6] = RCAR_GP_PIN(1, 6),       /* DU1_DG2_C6_DATA6 */
2845                 [ 7] = RCAR_GP_PIN(1, 7),       /* DU1_DG3_C7_DATA7 */
2846                 [ 8] = RCAR_GP_PIN(1, 8),       /* DU1_DG4_Y0_DATA8 */
2847                 [ 9] = RCAR_GP_PIN(1, 9),       /* DU1_DG5_Y1_DATA9 */
2848                 [10] = RCAR_GP_PIN(1, 10),      /* DU1_DG6_Y2_DATA10 */
2849                 [11] = RCAR_GP_PIN(1, 11),      /* DU1_DG7_Y3_DATA11 */
2850                 [12] = RCAR_GP_PIN(1, 12),      /* DU1_DB2_C0_DATA12 */
2851                 [13] = RCAR_GP_PIN(1, 13),      /* DU1_DB3_C1_DATA13 */
2852                 [14] = RCAR_GP_PIN(1, 14),      /* DU1_DB4_C2_DATA14 */
2853                 [15] = RCAR_GP_PIN(1, 15),      /* DU1_DB5_C3_DATA15 */
2854                 [16] = RCAR_GP_PIN(1, 16),      /* DU1_DB6_C4 */
2855                 [17] = RCAR_GP_PIN(1, 17),      /* DU1_DB7_C5 */
2856                 [18] = RCAR_GP_PIN(1, 18),      /* DU1_EXHSYNC/DU1_HSYNC */
2857                 [19] = RCAR_GP_PIN(1, 19),      /* DU1_EXVSYNC/DU1_VSYNC */
2858                 [20] = RCAR_GP_PIN(1, 20),      /* DU1_EXODDF/DU1_ODDF_DISP_CDE */
2859                 [21] = RCAR_GP_PIN(1, 21),      /* DU1_DISP */
2860                 [22] = RCAR_GP_PIN(1, 22),      /* DU1_CDE */
2861                 [23] = SH_PFC_PIN_NONE,
2862                 [24] = SH_PFC_PIN_NONE,
2863                 [25] = SH_PFC_PIN_NONE,
2864                 [26] = SH_PFC_PIN_NONE,
2865                 [27] = SH_PFC_PIN_NONE,
2866                 [28] = SH_PFC_PIN_NONE,
2867                 [29] = SH_PFC_PIN_NONE,
2868                 [30] = SH_PFC_PIN_NONE,
2869                 [31] = SH_PFC_PIN_NONE,
2870         } },
2871         { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
2872                 [ 0] = RCAR_GP_PIN(2, 0),       /* D0 */
2873                 [ 1] = RCAR_GP_PIN(2, 1),       /* D1 */
2874                 [ 2] = RCAR_GP_PIN(2, 2),       /* D2 */
2875                 [ 3] = RCAR_GP_PIN(2, 3),       /* D3 */
2876                 [ 4] = RCAR_GP_PIN(2, 4),       /* D4 */
2877                 [ 5] = RCAR_GP_PIN(2, 5),       /* D5 */
2878                 [ 6] = RCAR_GP_PIN(2, 6),       /* D6 */
2879                 [ 7] = RCAR_GP_PIN(2, 7),       /* D7 */
2880                 [ 8] = RCAR_GP_PIN(2, 8),       /* D8 */
2881                 [ 9] = RCAR_GP_PIN(2, 9),       /* D9 */
2882                 [10] = RCAR_GP_PIN(2, 10),      /* D10 */
2883                 [11] = RCAR_GP_PIN(2, 11),      /* D11 */
2884                 [12] = RCAR_GP_PIN(2, 12),      /* D12 */
2885                 [13] = RCAR_GP_PIN(2, 13),      /* D13 */
2886                 [14] = RCAR_GP_PIN(2, 14),      /* D14 */
2887                 [15] = RCAR_GP_PIN(2, 15),      /* D15 */
2888                 [16] = RCAR_GP_PIN(2, 16),      /* A0 */
2889                 [17] = RCAR_GP_PIN(2, 17),      /* A1 */
2890                 [18] = RCAR_GP_PIN(2, 18),      /* A2 */
2891                 [19] = RCAR_GP_PIN(2, 19),      /* A3 */
2892                 [20] = RCAR_GP_PIN(2, 20),      /* A4 */
2893                 [21] = RCAR_GP_PIN(2, 21),      /* A5 */
2894                 [22] = RCAR_GP_PIN(2, 22),      /* A6 */
2895                 [23] = RCAR_GP_PIN(2, 23),      /* A7 */
2896                 [24] = RCAR_GP_PIN(2, 24),      /* A8 */
2897                 [25] = RCAR_GP_PIN(2, 25),      /* A9 */
2898                 [26] = RCAR_GP_PIN(2, 26),      /* A10 */
2899                 [27] = RCAR_GP_PIN(2, 27),      /* A11 */
2900                 [28] = RCAR_GP_PIN(2, 28),      /* A12 */
2901                 [29] = RCAR_GP_PIN(2, 29),      /* A13 */
2902                 [30] = RCAR_GP_PIN(2, 30),      /* A14 */
2903                 [31] = RCAR_GP_PIN(2, 31),      /* A15 */
2904         } },
2905         { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
2906                 [ 0] = RCAR_GP_PIN(3, 0),       /* A16 */
2907                 [ 1] = RCAR_GP_PIN(3, 1),       /* A17 */
2908                 [ 2] = RCAR_GP_PIN(3, 2),       /* A18 */
2909                 [ 3] = RCAR_GP_PIN(3, 3),       /* A19 */
2910                 [ 4] = RCAR_GP_PIN(3, 4),       /* A20 */
2911                 [ 5] = RCAR_GP_PIN(3, 5),       /* A21 */
2912                 [ 6] = RCAR_GP_PIN(3, 6),       /* CS1#/A26 */
2913                 [ 7] = RCAR_GP_PIN(3, 7),       /* EX_CS0# */
2914                 [ 8] = RCAR_GP_PIN(3, 8),       /* EX_CS1# */
2915                 [ 9] = RCAR_GP_PIN(3, 9),       /* EX_CS2# */
2916                 [10] = RCAR_GP_PIN(3, 10),      /* EX_CS3# */
2917                 [11] = RCAR_GP_PIN(3, 11),      /* EX_CS4# */
2918                 [12] = RCAR_GP_PIN(3, 12),      /* EX_CS5# */
2919                 [13] = RCAR_GP_PIN(3, 13),      /* BS# */
2920                 [14] = RCAR_GP_PIN(3, 14),      /* RD# */
2921                 [15] = RCAR_GP_PIN(3, 15),      /* RD/WR# */
2922                 [16] = RCAR_GP_PIN(3, 16),      /* WE0# */
2923                 [17] = RCAR_GP_PIN(3, 17),      /* WE1# */
2924                 [18] = RCAR_GP_PIN(3, 18),      /* EX_WAIT0 */
2925                 [19] = RCAR_GP_PIN(3, 19),      /* IRQ0 */
2926                 [20] = RCAR_GP_PIN(3, 20),      /* IRQ1 */
2927                 [21] = RCAR_GP_PIN(3, 21),      /* IRQ2 */
2928                 [22] = RCAR_GP_PIN(3, 22),      /* IRQ3 */
2929                 [23] = RCAR_GP_PIN(3, 23),      /* A22 */
2930                 [24] = RCAR_GP_PIN(3, 24),      /* A23 */
2931                 [25] = RCAR_GP_PIN(3, 25),      /* A24 */
2932                 [26] = RCAR_GP_PIN(3, 26),      /* A25 */
2933                 [27] = RCAR_GP_PIN(3, 27),      /* CS0# */
2934                 [28] = SH_PFC_PIN_NONE,
2935                 [29] = SH_PFC_PIN_NONE,
2936                 [30] = SH_PFC_PIN_NONE,
2937                 [31] = SH_PFC_PIN_NONE,
2938         } },
2939         { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
2940                 [ 0] = RCAR_GP_PIN(4, 0),       /* VI0_CLK */
2941                 [ 1] = RCAR_GP_PIN(4, 1),       /* VI0_CLKENB */
2942                 [ 2] = RCAR_GP_PIN(4, 2),       /* VI0_HSYNC# */
2943                 [ 3] = RCAR_GP_PIN(4, 3),       /* VI0_VSYNC# */
2944                 [ 4] = RCAR_GP_PIN(4, 4),       /* VI0_D0_B0_C0 */
2945                 [ 5] = RCAR_GP_PIN(4, 5),       /* VI0_D1_B1_C1 */
2946                 [ 6] = RCAR_GP_PIN(4, 6),       /* VI0_D2_B2_C2 */
2947                 [ 7] = RCAR_GP_PIN(4, 7),       /* VI0_D3_B3_C3 */
2948                 [ 8] = RCAR_GP_PIN(4, 8),       /* VI0_D4_B4_C4 */
2949                 [ 9] = RCAR_GP_PIN(4, 9),       /* VI0_D5_B5_C5 */
2950                 [10] = RCAR_GP_PIN(4, 10),      /* VI0_D6_B6_C6 */
2951                 [11] = RCAR_GP_PIN(4, 11),      /* VI0_D7_B7_C7 */
2952                 [12] = RCAR_GP_PIN(4, 12),      /* VI0_D8_G0_Y0 */
2953                 [13] = RCAR_GP_PIN(4, 13),      /* VI0_D9_G1_Y1 */
2954                 [14] = RCAR_GP_PIN(4, 14),      /* VI0_D10_G2_Y2 */
2955                 [15] = RCAR_GP_PIN(4, 15),      /* VI0_D11_G3_Y3 */
2956                 [16] = RCAR_GP_PIN(4, 16),      /* VI0_FIELD */
2957                 [17] = SH_PFC_PIN_NONE,
2958                 [18] = SH_PFC_PIN_NONE,
2959                 [19] = SH_PFC_PIN_NONE,
2960                 [20] = SH_PFC_PIN_NONE,
2961                 [21] = SH_PFC_PIN_NONE,
2962                 [22] = SH_PFC_PIN_NONE,
2963                 [23] = SH_PFC_PIN_NONE,
2964                 [24] = SH_PFC_PIN_NONE,
2965                 [25] = SH_PFC_PIN_NONE,
2966                 [26] = SH_PFC_PIN_NONE,
2967                 [27] = SH_PFC_PIN_NONE,
2968                 [28] = SH_PFC_PIN_NONE,
2969                 [29] = SH_PFC_PIN_NONE,
2970                 [30] = SH_PFC_PIN_NONE,
2971                 [31] = SH_PFC_PIN_NONE,
2972         } },
2973         { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
2974                 [ 0] = RCAR_GP_PIN(5, 0),       /* VI1_CLK */
2975                 [ 1] = RCAR_GP_PIN(5, 1),       /* VI1_CLKENB */
2976                 [ 2] = RCAR_GP_PIN(5, 2),       /* VI1_HSYNC# */
2977                 [ 3] = RCAR_GP_PIN(5, 3),       /* VI1_VSYNC# */
2978                 [ 4] = RCAR_GP_PIN(5, 4),       /* VI1_D0_B0_C0 */
2979                 [ 5] = RCAR_GP_PIN(5, 5),       /* VI1_D1_B1_C1 */
2980                 [ 6] = RCAR_GP_PIN(5, 6),       /* VI1_D2_B2_C2 */
2981                 [ 7] = RCAR_GP_PIN(5, 7),       /* VI1_D3_B3_C3 */
2982                 [ 8] = RCAR_GP_PIN(5, 8),       /* VI1_D4_B4_C4 */
2983                 [ 9] = RCAR_GP_PIN(5, 9),       /* VI1_D5_B5_C5 */
2984                 [10] = RCAR_GP_PIN(5, 10),      /* VI1_D6_B6_C6 */
2985                 [11] = RCAR_GP_PIN(5, 11),      /* VI1_D7_B7_C7 */
2986                 [12] = RCAR_GP_PIN(5, 12),      /* VI1_D8_G0_Y0 */
2987                 [13] = RCAR_GP_PIN(5, 13),      /* VI1_D9_G1_Y1 */
2988                 [14] = RCAR_GP_PIN(5, 14),      /* VI1_D10_G2_Y2 */
2989                 [15] = RCAR_GP_PIN(5, 15),      /* VI1_D11_G3_Y3 */
2990                 [16] = RCAR_GP_PIN(5, 16),      /* VI1_FIELD */
2991                 [17] = SH_PFC_PIN_NONE,
2992                 [18] = SH_PFC_PIN_NONE,
2993                 [19] = SH_PFC_PIN_NONE,
2994                 [20] = SH_PFC_PIN_NONE,
2995                 [21] = SH_PFC_PIN_NONE,
2996                 [22] = SH_PFC_PIN_NONE,
2997                 [23] = SH_PFC_PIN_NONE,
2998                 [24] = SH_PFC_PIN_NONE,
2999                 [25] = SH_PFC_PIN_NONE,
3000                 [26] = SH_PFC_PIN_NONE,
3001                 [27] = SH_PFC_PIN_NONE,
3002                 [28] = SH_PFC_PIN_NONE,
3003                 [29] = SH_PFC_PIN_NONE,
3004                 [30] = SH_PFC_PIN_NONE,
3005                 [31] = SH_PFC_PIN_NONE,
3006         } },
3007         { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
3008                 [ 0] = RCAR_GP_PIN(6, 0),       /* VI2_CLK */
3009                 [ 1] = RCAR_GP_PIN(6, 1),       /* VI2_CLKENB */
3010                 [ 2] = RCAR_GP_PIN(6, 2),       /* VI2_HSYNC# */
3011                 [ 3] = RCAR_GP_PIN(6, 3),       /* VI2_VSYNC# */
3012                 [ 4] = RCAR_GP_PIN(6, 4),       /* VI2_D0_C0 */
3013                 [ 5] = RCAR_GP_PIN(6, 5),       /* VI2_D1_C1 */
3014                 [ 6] = RCAR_GP_PIN(6, 6),       /* VI2_D2_C2 */
3015                 [ 7] = RCAR_GP_PIN(6, 7),       /* VI2_D3_C3 */
3016                 [ 8] = RCAR_GP_PIN(6, 8),       /* VI2_D4_C4 */
3017                 [ 9] = RCAR_GP_PIN(6, 9),       /* VI2_D5_C5 */
3018                 [10] = RCAR_GP_PIN(6, 10),      /* VI2_D6_C6 */
3019                 [11] = RCAR_GP_PIN(6, 11),      /* VI2_D7_C7 */
3020                 [12] = RCAR_GP_PIN(6, 12),      /* VI2_D8_Y0 */
3021                 [13] = RCAR_GP_PIN(6, 13),      /* VI2_D9_Y1 */
3022                 [14] = RCAR_GP_PIN(6, 14),      /* VI2_D10_Y2 */
3023                 [15] = RCAR_GP_PIN(6, 15),      /* VI2_D11_Y3 */
3024                 [16] = RCAR_GP_PIN(6, 16),      /* VI2_FIELD */
3025                 [17] = SH_PFC_PIN_NONE,
3026                 [18] = SH_PFC_PIN_NONE,
3027                 [19] = SH_PFC_PIN_NONE,
3028                 [20] = SH_PFC_PIN_NONE,
3029                 [21] = SH_PFC_PIN_NONE,
3030                 [22] = SH_PFC_PIN_NONE,
3031                 [23] = SH_PFC_PIN_NONE,
3032                 [24] = SH_PFC_PIN_NONE,
3033                 [25] = SH_PFC_PIN_NONE,
3034                 [26] = SH_PFC_PIN_NONE,
3035                 [27] = SH_PFC_PIN_NONE,
3036                 [28] = SH_PFC_PIN_NONE,
3037                 [29] = SH_PFC_PIN_NONE,
3038                 [30] = SH_PFC_PIN_NONE,
3039                 [31] = SH_PFC_PIN_NONE,
3040         } },
3041         { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
3042                 [ 0] = RCAR_GP_PIN(7, 0),       /* VI3_CLK */
3043                 [ 1] = RCAR_GP_PIN(7, 1),       /* VI3_CLKENB */
3044                 [ 2] = RCAR_GP_PIN(7, 2),       /* VI3_HSYNC# */
3045                 [ 3] = RCAR_GP_PIN(7, 3),       /* VI3_VSYNC# */
3046                 [ 4] = RCAR_GP_PIN(7, 4),       /* VI3_D0_C0 */
3047                 [ 5] = RCAR_GP_PIN(7, 5),       /* VI3_D1_C1 */
3048                 [ 6] = RCAR_GP_PIN(7, 6),       /* VI3_D2_C2 */
3049                 [ 7] = RCAR_GP_PIN(7, 7),       /* VI3_D3_C3 */
3050                 [ 8] = RCAR_GP_PIN(7, 8),       /* VI3_D4_C4 */
3051                 [ 9] = RCAR_GP_PIN(7, 9),       /* VI3_D5_C5 */
3052                 [10] = RCAR_GP_PIN(7, 10),      /* VI3_D6_C6 */
3053                 [11] = RCAR_GP_PIN(7, 11),      /* VI3_D7_C7 */
3054                 [12] = RCAR_GP_PIN(7, 12),      /* VI3_D8_Y0 */
3055                 [13] = RCAR_GP_PIN(7, 13),      /* VI3_D9_Y1 */
3056                 [14] = RCAR_GP_PIN(7, 14),      /* VI3_D10_Y2 */
3057                 [15] = RCAR_GP_PIN(7, 15),      /* VI3_D11_Y3 */
3058                 [16] = RCAR_GP_PIN(7, 16),      /* VI3_FIELD */
3059                 [17] = SH_PFC_PIN_NONE,
3060                 [18] = SH_PFC_PIN_NONE,
3061                 [19] = SH_PFC_PIN_NONE,
3062                 [20] = SH_PFC_PIN_NONE,
3063                 [21] = SH_PFC_PIN_NONE,
3064                 [22] = SH_PFC_PIN_NONE,
3065                 [23] = SH_PFC_PIN_NONE,
3066                 [24] = SH_PFC_PIN_NONE,
3067                 [25] = SH_PFC_PIN_NONE,
3068                 [26] = SH_PFC_PIN_NONE,
3069                 [27] = SH_PFC_PIN_NONE,
3070                 [28] = SH_PFC_PIN_NONE,
3071                 [29] = SH_PFC_PIN_NONE,
3072                 [30] = SH_PFC_PIN_NONE,
3073                 [31] = SH_PFC_PIN_NONE,
3074         } },
3075         { PINMUX_BIAS_REG("PUPR8", 0xe6060120, "N/A", 0) {
3076                 [ 0] = RCAR_GP_PIN(8, 0),       /* VI4_CLK */
3077                 [ 1] = RCAR_GP_PIN(8, 1),       /* VI4_CLKENB */
3078                 [ 2] = RCAR_GP_PIN(8, 2),       /* VI4_HSYNC# */
3079                 [ 3] = RCAR_GP_PIN(8, 3),       /* VI4_VSYNC# */
3080                 [ 4] = RCAR_GP_PIN(8, 4),       /* VI4_D0_C0 */
3081                 [ 5] = RCAR_GP_PIN(8, 5),       /* VI4_D1_C1 */
3082                 [ 6] = RCAR_GP_PIN(8, 6),       /* VI4_D2_C2 */
3083                 [ 7] = RCAR_GP_PIN(8, 7),       /* VI4_D3_C3 */
3084                 [ 8] = RCAR_GP_PIN(8, 8),       /* VI4_D4_C4 */
3085                 [ 9] = RCAR_GP_PIN(8, 9),       /* VI4_D5_C5 */
3086                 [10] = RCAR_GP_PIN(8, 10),      /* VI4_D6_C6 */
3087                 [11] = RCAR_GP_PIN(8, 11),      /* VI4_D7_C7 */
3088                 [12] = RCAR_GP_PIN(8, 12),      /* VI4_D8_Y0 */
3089                 [13] = RCAR_GP_PIN(8, 13),      /* VI4_D9_Y1 */
3090                 [14] = RCAR_GP_PIN(8, 14),      /* VI4_D10_Y2 */
3091                 [15] = RCAR_GP_PIN(8, 15),      /* VI4_D11_Y3 */
3092                 [16] = RCAR_GP_PIN(8, 16),      /* VI4_FIELD */
3093                 [17] = SH_PFC_PIN_NONE,
3094                 [18] = SH_PFC_PIN_NONE,
3095                 [19] = SH_PFC_PIN_NONE,
3096                 [20] = SH_PFC_PIN_NONE,
3097                 [21] = SH_PFC_PIN_NONE,
3098                 [22] = SH_PFC_PIN_NONE,
3099                 [23] = SH_PFC_PIN_NONE,
3100                 [24] = SH_PFC_PIN_NONE,
3101                 [25] = SH_PFC_PIN_NONE,
3102                 [26] = SH_PFC_PIN_NONE,
3103                 [27] = SH_PFC_PIN_NONE,
3104                 [28] = SH_PFC_PIN_NONE,
3105                 [29] = SH_PFC_PIN_NONE,
3106                 [30] = SH_PFC_PIN_NONE,
3107                 [31] = SH_PFC_PIN_NONE,
3108         } },
3109         { PINMUX_BIAS_REG("PUPR9", 0xe6060124, "N/A", 0) {
3110                 [ 0] = RCAR_GP_PIN(9, 0),       /* VI5_CLK */
3111                 [ 1] = RCAR_GP_PIN(9, 1),       /* VI5_CLKENB */
3112                 [ 2] = RCAR_GP_PIN(9, 2),       /* VI5_HSYNC# */
3113                 [ 3] = RCAR_GP_PIN(9, 3),       /* VI5_VSYNC# */
3114                 [ 4] = RCAR_GP_PIN(9, 4),       /* VI5_D0_C0 */
3115                 [ 5] = RCAR_GP_PIN(9, 5),       /* VI5_D1_C1 */
3116                 [ 6] = RCAR_GP_PIN(9, 6),       /* VI5_D2_C2 */
3117                 [ 7] = RCAR_GP_PIN(9, 7),       /* VI5_D3_C3 */
3118                 [ 8] = RCAR_GP_PIN(9, 8),       /* VI5_D4_C4 */
3119                 [ 9] = RCAR_GP_PIN(9, 9),       /* VI5_D5_C5 */
3120                 [10] = RCAR_GP_PIN(9, 10),      /* VI5_D6_C6 */
3121                 [11] = RCAR_GP_PIN(9, 11),      /* VI5_D7_C7 */
3122                 [12] = RCAR_GP_PIN(9, 12),      /* VI5_D8_Y0 */
3123                 [13] = RCAR_GP_PIN(9, 13),      /* VI5_D9_Y1 */
3124                 [14] = RCAR_GP_PIN(9, 14),      /* VI5_D10_Y2 */
3125                 [15] = RCAR_GP_PIN(9, 15),      /* VI5_D11_Y3 */
3126                 [16] = RCAR_GP_PIN(9, 16),      /* VI5_FIELD */
3127                 [17] = SH_PFC_PIN_NONE,
3128                 [18] = SH_PFC_PIN_NONE,
3129                 [19] = SH_PFC_PIN_NONE,
3130                 [20] = SH_PFC_PIN_NONE,
3131                 [21] = SH_PFC_PIN_NONE,
3132                 [22] = SH_PFC_PIN_NONE,
3133                 [23] = SH_PFC_PIN_NONE,
3134                 [24] = SH_PFC_PIN_NONE,
3135                 [25] = SH_PFC_PIN_NONE,
3136                 [26] = SH_PFC_PIN_NONE,
3137                 [27] = SH_PFC_PIN_NONE,
3138                 [28] = SH_PFC_PIN_NONE,
3139                 [29] = SH_PFC_PIN_NONE,
3140                 [30] = SH_PFC_PIN_NONE,
3141                 [31] = SH_PFC_PIN_NONE,
3142         } },
3143         { PINMUX_BIAS_REG("PUPR10", 0xe6060128, "N/A", 0) {
3144                 [ 0] = RCAR_GP_PIN(10, 0),      /* HSCK0 */
3145                 [ 1] = RCAR_GP_PIN(10, 1),      /* HCTS0# */
3146                 [ 2] = RCAR_GP_PIN(10, 2),      /* HRTS0# */
3147                 [ 3] = RCAR_GP_PIN(10, 3),      /* HTX0 */
3148                 [ 4] = RCAR_GP_PIN(10, 4),      /* HRX0 */
3149                 [ 5] = RCAR_GP_PIN(10, 5),      /* HSCK1 */
3150                 [ 6] = RCAR_GP_PIN(10, 6),      /* HRTS1# */
3151                 [ 7] = RCAR_GP_PIN(10, 7),      /* HCTS1# */
3152                 [ 8] = RCAR_GP_PIN(10, 8),      /* HTX1 */
3153                 [ 9] = RCAR_GP_PIN(10, 9),      /* HRX1 */
3154                 [10] = RCAR_GP_PIN(10, 10),     /* SCK0 */
3155                 [11] = RCAR_GP_PIN(10, 11),     /* CTS0# */
3156                 [12] = RCAR_GP_PIN(10, 12),     /* RTS0# */
3157                 [13] = RCAR_GP_PIN(10, 13),     /* TX0 */
3158                 [14] = RCAR_GP_PIN(10, 14),     /* RX0 */
3159                 [15] = RCAR_GP_PIN(10, 15),     /* SCK1 */
3160                 [16] = RCAR_GP_PIN(10, 16),     /* CTS1# */
3161                 [17] = RCAR_GP_PIN(10, 17),     /* RTS1# */
3162                 [18] = RCAR_GP_PIN(10, 18),     /* TX1 */
3163                 [19] = RCAR_GP_PIN(10, 19),     /* RX1 */
3164                 [20] = RCAR_GP_PIN(10, 20),     /* SCK2 */
3165                 [21] = RCAR_GP_PIN(10, 21),     /* TX2 */
3166                 [22] = RCAR_GP_PIN(10, 22),     /* RX2 */
3167                 [23] = RCAR_GP_PIN(10, 23),     /* SCK3 */
3168                 [24] = RCAR_GP_PIN(10, 24),     /* TX3 */
3169                 [25] = RCAR_GP_PIN(10, 25),     /* RX3 */
3170                 [26] = RCAR_GP_PIN(10, 26),     /* SCIF_CLK */
3171                 [27] = RCAR_GP_PIN(10, 27),     /* CAN0_TX */
3172                 [28] = RCAR_GP_PIN(10, 28),     /* CAN0_RX */
3173                 [29] = RCAR_GP_PIN(10, 29),     /* CAN_CLK */
3174                 [30] = RCAR_GP_PIN(10, 30),     /* CAN1_TX */
3175                 [31] = RCAR_GP_PIN(10, 31),     /* CAN1_RX */
3176         } },
3177         { PINMUX_BIAS_REG("PUPR11", 0xe606012c, "N/A", 0) {
3178                 [ 0] = RCAR_GP_PIN(11, 0),      /* PWM0 */
3179                 [ 1] = RCAR_GP_PIN(11, 1),      /* PWM1 */
3180                 [ 2] = RCAR_GP_PIN(11, 2),      /* PWM2 */
3181                 [ 3] = RCAR_GP_PIN(11, 3),      /* PWM3 */
3182                 [ 4] = RCAR_GP_PIN(11, 4),      /* PWM4 */
3183                 [ 5] = RCAR_GP_PIN(11, 5),      /* SD0_CLK */
3184                 [ 6] = RCAR_GP_PIN(11, 6),      /* SD0_CMD */
3185                 [ 7] = RCAR_GP_PIN(11, 7),      /* SD0_DAT0 */
3186                 [ 8] = RCAR_GP_PIN(11, 8),      /* SD0_DAT1 */
3187                 [ 9] = RCAR_GP_PIN(11, 9),      /* SD0_DAT2 */
3188                 [10] = RCAR_GP_PIN(11, 10),     /* SD0_DAT3 */
3189                 [11] = RCAR_GP_PIN(11, 11),     /* SD0_CD */
3190                 [12] = RCAR_GP_PIN(11, 12),     /* SD0_WP */
3191                 [13] = RCAR_GP_PIN(11, 13),     /* SSI_SCK3 */
3192                 [14] = RCAR_GP_PIN(11, 14),     /* SSI_WS3 */
3193                 [15] = RCAR_GP_PIN(11, 15),     /* SSI_SDATA3 */
3194                 [16] = RCAR_GP_PIN(11, 16),     /* SSI_SCK4 */
3195                 [17] = RCAR_GP_PIN(11, 17),     /* SSI_WS4 */
3196                 [18] = RCAR_GP_PIN(11, 18),     /* SSI_SDATA4 */
3197                 [19] = RCAR_GP_PIN(11, 19),     /* AUDIO_CLKOUT */
3198                 [20] = RCAR_GP_PIN(11, 20),     /* AUDIO_CLKA */
3199                 [21] = RCAR_GP_PIN(11, 21),     /* AUDIO_CLKB */
3200                 [22] = RCAR_GP_PIN(11, 22),     /* ADICLK */
3201                 [23] = RCAR_GP_PIN(11, 23),     /* ADICS_SAMP */
3202                 [24] = RCAR_GP_PIN(11, 24),     /* ADIDATA */
3203                 [25] = RCAR_GP_PIN(11, 25),     /* ADICHS0 */
3204                 [26] = RCAR_GP_PIN(11, 26),     /* ADICHS1 */
3205                 [27] = RCAR_GP_PIN(11, 27),     /* ADICHS2 */
3206                 [28] = RCAR_GP_PIN(11, 28),     /* AVS1 */
3207                 [29] = RCAR_GP_PIN(11, 29),     /* AVS2 */
3208                 [30] = SH_PFC_PIN_NONE,
3209                 [31] = SH_PFC_PIN_NONE,
3210         } },
3211         { PINMUX_BIAS_REG("PUPR12", 0xe6060130, "N/A", 0) {
3212                 /* PUPR12 pull-up pins */
3213                 [ 0] = PIN_DU0_DOTCLKIN,        /* DU0_DOTCLKIN */
3214                 [ 1] = PIN_DU0_DOTCLKOUT,       /* DU0_DOTCLKOUT */
3215                 [ 2] = PIN_DU1_DOTCLKIN,        /* DU1_DOTCLKIN */
3216                 [ 3] = PIN_DU1_DOTCLKOUT,       /* DU1_DOTCLKOUT */
3217                 [ 4] = PIN_TRST_N,              /* TRST# */
3218                 [ 5] = PIN_TCK,                 /* TCK */
3219                 [ 6] = PIN_TMS,                 /* TMS */
3220                 [ 7] = PIN_TDI,                 /* TDI */
3221                 [ 8] = SH_PFC_PIN_NONE,
3222                 [ 9] = SH_PFC_PIN_NONE,
3223                 [10] = SH_PFC_PIN_NONE,
3224                 [11] = SH_PFC_PIN_NONE,
3225                 [12] = SH_PFC_PIN_NONE,
3226                 [13] = SH_PFC_PIN_NONE,
3227                 [14] = SH_PFC_PIN_NONE,
3228                 [15] = SH_PFC_PIN_NONE,
3229                 [16] = SH_PFC_PIN_NONE,
3230                 [17] = SH_PFC_PIN_NONE,
3231                 [18] = SH_PFC_PIN_NONE,
3232                 [19] = SH_PFC_PIN_NONE,
3233                 [20] = SH_PFC_PIN_NONE,
3234                 [21] = SH_PFC_PIN_NONE,
3235                 [22] = SH_PFC_PIN_NONE,
3236                 [23] = SH_PFC_PIN_NONE,
3237                 [24] = SH_PFC_PIN_NONE,
3238                 [25] = SH_PFC_PIN_NONE,
3239                 [26] = SH_PFC_PIN_NONE,
3240                 [27] = SH_PFC_PIN_NONE,
3241                 [28] = SH_PFC_PIN_NONE,
3242                 [29] = SH_PFC_PIN_NONE,
3243                 [30] = SH_PFC_PIN_NONE,
3244                 [31] = SH_PFC_PIN_NONE,
3245         } },
3246         { PINMUX_BIAS_REG("N/A", 0, "PUPR12", 0xe6060130) {
3247                 /* PUPR12 pull-down pins */
3248                 [ 0] = SH_PFC_PIN_NONE,
3249                 [ 1] = SH_PFC_PIN_NONE,
3250                 [ 2] = SH_PFC_PIN_NONE,
3251                 [ 3] = SH_PFC_PIN_NONE,
3252                 [ 4] = SH_PFC_PIN_NONE,
3253                 [ 5] = SH_PFC_PIN_NONE,
3254                 [ 6] = SH_PFC_PIN_NONE,
3255                 [ 7] = SH_PFC_PIN_NONE,
3256                 [ 8] = PIN_EDBGREQ,             /* EDBGREQ */
3257                 [ 9] = SH_PFC_PIN_NONE,
3258                 [10] = SH_PFC_PIN_NONE,
3259                 [11] = SH_PFC_PIN_NONE,
3260                 [12] = SH_PFC_PIN_NONE,
3261                 [13] = SH_PFC_PIN_NONE,
3262                 [14] = SH_PFC_PIN_NONE,
3263                 [15] = SH_PFC_PIN_NONE,
3264                 [16] = SH_PFC_PIN_NONE,
3265                 [17] = SH_PFC_PIN_NONE,
3266                 [18] = SH_PFC_PIN_NONE,
3267                 [19] = SH_PFC_PIN_NONE,
3268                 [20] = SH_PFC_PIN_NONE,
3269                 [21] = SH_PFC_PIN_NONE,
3270                 [22] = SH_PFC_PIN_NONE,
3271                 [23] = SH_PFC_PIN_NONE,
3272                 [24] = SH_PFC_PIN_NONE,
3273                 [25] = SH_PFC_PIN_NONE,
3274                 [26] = SH_PFC_PIN_NONE,
3275                 [27] = SH_PFC_PIN_NONE,
3276                 [28] = SH_PFC_PIN_NONE,
3277                 [29] = SH_PFC_PIN_NONE,
3278                 [30] = SH_PFC_PIN_NONE,
3279                 [31] = SH_PFC_PIN_NONE,
3280         } },
3281         { /* sentinel */ }
3282 };
3283
3284 static const struct sh_pfc_soc_operations r8a7792_pinmux_ops = {
3285         .get_bias = rcar_pinmux_get_bias,
3286         .set_bias = rcar_pinmux_set_bias,
3287 };
3288
3289 const struct sh_pfc_soc_info r8a7792_pinmux_info = {
3290         .name = "r8a77920_pfc",
3291         .ops = &r8a7792_pinmux_ops,
3292         .unlock_reg = 0xe6060000, /* PMMR */
3293
3294         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3295
3296         .pins = pinmux_pins,
3297         .nr_pins = ARRAY_SIZE(pinmux_pins),
3298         .groups = pinmux_groups,
3299         .nr_groups = ARRAY_SIZE(pinmux_groups),
3300         .functions = pinmux_functions,
3301         .nr_functions = ARRAY_SIZE(pinmux_functions),
3302
3303         .cfg_regs = pinmux_config_regs,
3304         .bias_regs = pinmux_bias_regs,
3305
3306         .pinmux_data = pinmux_data,
3307         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3308 };