1 // SPDX-License-Identifier: GPL-2.0
3 * R8A7790 processor support
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Magnus Damm
7 * Copyright (C) 2012 Renesas Solutions Corp.
8 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
11 #include <linux/errno.h>
13 #include <linux/kernel.h>
14 #include <linux/sys_soc.h>
20 * All pins assigned to GPIO bank 3 can be used for SD interfaces in
21 * which case they support both 3.3V and 1.8V signalling.
23 #define CPU_ALL_GP(fn, sfx) \
24 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
25 PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
26 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
27 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
28 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
29 PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
31 #define CPU_ALL_NOGP(fn) \
32 PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
33 PIN_NOGP(IIC0_SDA, "AF15", fn), \
34 PIN_NOGP(IIC0_SCL, "AG15", fn), \
35 PIN_NOGP(IIC3_SDA, "AH15", fn), \
36 PIN_NOGP(IIC3_SCL, "AJ15", fn), \
37 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
38 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
39 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
40 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
49 PINMUX_FUNCTION_BEGIN,
53 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
54 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
55 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
56 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
57 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
58 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
59 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
60 FN_IP3_14_12, FN_IP3_17_15,
63 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
64 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
65 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
66 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
67 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
68 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
69 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
72 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
73 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
74 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
75 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
76 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
77 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
78 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
81 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
82 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
83 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
84 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
85 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
86 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
87 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
90 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
91 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
92 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
93 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
94 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
95 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
96 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
97 FN_IP14_15_12, FN_IP14_18_16,
100 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
101 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
102 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
103 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
104 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
105 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
106 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
109 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
110 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
111 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
112 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
113 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
114 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
115 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
116 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
117 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
118 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
119 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
120 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
121 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
122 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
125 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
126 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
127 FN_SCIFA1_TXD_C, FN_AVB_TXD2,
128 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
129 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
130 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
131 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
132 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
133 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
134 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
135 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
136 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
137 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
138 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
139 FN_A0, FN_PWM3, FN_A1, FN_PWM4,
142 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
143 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
144 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
145 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
146 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
147 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
148 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
149 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
150 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
151 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
152 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
155 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
156 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
157 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
158 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
159 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
160 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
161 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
162 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
163 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
164 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
165 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
166 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
167 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
170 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
171 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
172 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
173 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
174 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
175 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
176 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
177 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
178 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
179 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
180 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
181 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
182 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
183 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
184 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
187 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
188 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
189 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
190 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
191 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
192 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
193 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
194 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
195 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
196 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
197 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
198 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
199 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
200 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
201 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3,
202 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
203 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
204 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
208 FN_DACK0, FN_IRQ0, FN_SSI_SCK6_B,
209 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
210 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
211 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
212 FN_SSI_WS6_B, FN_SSI_SDATA8_C,
213 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
214 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2,
215 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
216 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
217 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
218 FN_I2C2_SCL_E, FN_ETH_RX_ER,
219 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
220 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
221 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
222 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
223 FN_HRX0_E, FN_STP_ISSYNC_0_B,
224 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
225 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
226 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
227 FN_ETH_REF_CLK, FN_HCTS0_N_E,
228 FN_STP_IVCXO27_1_B, FN_HRX0_F,
231 FN_ETH_MDIO, FN_HRTS0_N_E,
232 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
233 FN_HTX0_F, FN_BPFCLK_G,
234 FN_ETH_TX_EN, FN_SIM0_CLK_C,
235 FN_HRTS0_N_F, FN_ETH_MAGIC,
236 FN_SIM0_RST_C, FN_ETH_TXD0,
237 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
238 FN_ETH_MDC, FN_STP_ISD_1_B,
239 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
240 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
241 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
242 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
243 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
244 FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
245 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
246 FN_ATACS00_N, FN_AVB_RXD1,
247 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
250 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
251 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
252 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
253 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
254 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
255 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
256 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
257 FN_VI1_CLK, FN_AVB_RX_DV,
258 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
259 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
260 FN_SCIFA1_RXD_D, FN_AVB_MDC,
261 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
262 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
263 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
264 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
265 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
266 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
267 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
270 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
271 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
272 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
273 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
274 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
275 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
276 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
277 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
278 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
279 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
280 FN_AVB_TX_EN, FN_SD1_CMD,
281 FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
282 FN_SD1_DAT0, FN_AVB_TX_CLK,
283 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
284 FN_SCIFB0_TXD_B, FN_SD1_DAT2,
285 FN_AVB_COL, FN_SCIFB0_CTS_N_B,
286 FN_SD1_DAT3, FN_AVB_RXD0,
287 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
288 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
289 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
293 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
294 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
295 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
296 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
297 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
298 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
299 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
300 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
301 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
302 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
303 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
304 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
305 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
306 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
307 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
308 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
309 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
310 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
311 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
312 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
313 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
314 FN_GLO_I0_B, FN_VI3_DATA6_B,
317 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
318 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
319 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
320 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
321 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
322 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
323 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
324 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
325 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
326 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
327 FN_FMIN_E, FN_FMIN_F,
328 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
329 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
330 FN_I2C2_SDA_B, FN_MLB_DAT,
331 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
332 FN_SSI_SCK0129, FN_CAN_CLK_B,
336 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
337 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
338 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
339 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
340 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
341 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
342 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
343 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
344 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
345 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
346 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
347 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
348 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
349 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
350 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
351 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
352 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
353 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
357 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
358 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
359 FN_SCIFB1_CTS_N, FN_BPFCLK_D,
360 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
361 FN_BPFCLK_F, FN_SSI_WS6,
362 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
363 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
364 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
365 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
366 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
367 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
368 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
369 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
370 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
371 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
372 FN_BPFCLK_E, FN_SSI_SDATA7_B,
373 FN_FMIN_G, FN_SSI_SDATA8,
374 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
375 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
376 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
377 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
378 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
381 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
382 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
383 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
384 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
385 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
386 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
387 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
388 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
389 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
390 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
391 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
392 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
393 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
394 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
395 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
396 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
397 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
398 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
402 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
403 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
404 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
405 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
406 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
407 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
408 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
409 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
410 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
411 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
412 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
413 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
414 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
415 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
416 FN_DU2_DG6, FN_LCDOUT14,
419 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
420 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
421 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
422 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
423 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
426 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
428 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
429 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
430 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
432 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
433 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
434 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
435 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
436 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
437 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
438 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
439 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
440 FN_SEL_VI3_0, FN_SEL_VI3_1,
441 FN_SEL_VI2_0, FN_SEL_VI2_1,
442 FN_SEL_VI1_0, FN_SEL_VI1_1,
443 FN_SEL_VI0_0, FN_SEL_VI0_1,
444 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
445 FN_SEL_LBS_0, FN_SEL_LBS_1,
446 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
447 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
448 FN_SEL_SOF0_0, FN_SEL_SOF0_1,
450 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
451 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
452 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
453 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
454 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
455 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
456 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
457 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
458 FN_SEL_ADI_0, FN_SEL_ADI_1,
459 FN_SEL_SSP_0, FN_SEL_SSP_1,
460 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
461 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
462 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
463 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
464 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
465 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
466 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
468 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
469 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
470 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
471 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
473 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
474 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
476 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
481 VI1_DATA7_VI1_B7_MARK,
483 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
484 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
485 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
487 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
488 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
489 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
490 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
491 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
492 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
493 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
494 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
495 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
496 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
497 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
498 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
499 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
500 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
502 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
503 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
504 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
505 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
506 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
507 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
508 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
509 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
510 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
511 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
512 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
513 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
514 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
515 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
516 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
518 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
519 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
520 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
521 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
522 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
523 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
524 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
525 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
526 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
527 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
528 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
530 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
531 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
532 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
533 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
534 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
535 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
536 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
537 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
538 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
539 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
540 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
541 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
542 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
544 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
545 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
546 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
547 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
548 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
549 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
550 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
551 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
552 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
553 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
554 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
555 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
556 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
557 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
558 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
560 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
561 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
562 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
563 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
564 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
565 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
566 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
567 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
568 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
569 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
570 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
571 WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
572 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
573 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
574 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
575 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK,
576 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
577 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
578 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
581 DACK0_MARK, IRQ0_MARK, SSI_SCK6_B_MARK,
582 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
583 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
584 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
585 SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
586 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
587 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK,
588 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
589 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
590 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
591 I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
592 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
593 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
594 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
595 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
596 HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
597 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
598 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
599 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
600 ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
601 STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
603 ETH_MDIO_MARK, HRTS0_N_E_MARK,
604 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
605 HTX0_F_MARK, BPFCLK_G_MARK,
606 ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
607 HRTS0_N_F_MARK, ETH_MAGIC_MARK,
608 SIM0_RST_C_MARK, ETH_TXD0_MARK,
609 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
610 ETH_MDC_MARK, STP_ISD_1_B_MARK,
611 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
612 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
613 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
614 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
615 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
616 PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
617 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
618 ATACS00_N_MARK, AVB_RXD1_MARK,
619 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
621 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
622 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
623 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
624 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
625 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
626 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
627 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
628 VI1_CLK_MARK, AVB_RX_DV_MARK,
629 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
630 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
631 SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
632 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
633 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
634 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
635 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
636 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
637 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
638 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
640 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
641 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
642 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
643 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
644 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
645 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
646 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
647 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
648 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
649 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
650 AVB_TX_EN_MARK, SD1_CMD_MARK,
651 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
652 SD1_DAT0_MARK, AVB_TX_CLK_MARK,
653 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
654 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
655 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
656 SD1_DAT3_MARK, AVB_RXD0_MARK,
657 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
658 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
659 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
662 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
663 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
664 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
665 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
666 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
667 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
668 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
669 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
670 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
671 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
672 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
673 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
674 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
675 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
676 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
677 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
678 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
679 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
680 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
681 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
682 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
683 GLO_I0_B_MARK, VI3_DATA6_B_MARK,
685 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
686 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
687 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
688 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
689 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
690 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
691 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
692 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
693 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
694 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
695 FMIN_E_MARK, FMIN_F_MARK,
696 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
697 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
698 I2C2_SDA_B_MARK, MLB_DAT_MARK,
699 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
700 SSI_SCK0129_MARK, CAN_CLK_B_MARK,
703 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
704 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
705 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
706 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
707 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
708 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
709 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
710 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
711 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
712 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
713 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
714 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
715 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
716 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
717 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
718 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
719 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
720 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
723 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
724 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
725 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
726 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
727 BPFCLK_F_MARK, SSI_WS6_MARK,
728 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
729 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
730 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
731 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
732 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
733 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
734 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
735 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
736 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
737 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
738 BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
739 FMIN_G_MARK, SSI_SDATA8_MARK,
740 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
741 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
742 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
743 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
744 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
746 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
747 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
748 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
749 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
750 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
751 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
752 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
753 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
754 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
755 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
756 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
757 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
758 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
759 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
760 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
761 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
762 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
763 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
766 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
767 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
768 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
769 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
770 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
771 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
772 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
773 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
774 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
775 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
776 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
777 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
778 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
779 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
780 DU2_DG6_MARK, LCDOUT14_MARK,
782 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
783 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
784 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
785 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
786 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
789 IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
790 IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
794 static const u16 pinmux_data[] = {
795 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
797 PINMUX_SINGLE(VI1_DATA7_VI1_B7),
798 PINMUX_SINGLE(USB0_PWEN),
799 PINMUX_SINGLE(USB0_OVC_VBUS),
800 PINMUX_SINGLE(USB2_PWEN),
801 PINMUX_SINGLE(USB2_OVC),
804 PINMUX_SINGLE(DU_DOTCLKIN0),
805 PINMUX_SINGLE(DU_DOTCLKIN2),
807 PINMUX_IPSR_GPSR(IP0_2_0, D0),
808 PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
809 PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
810 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
811 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
812 PINMUX_IPSR_GPSR(IP0_5_3, D1),
813 PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
814 PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
815 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
816 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
817 PINMUX_IPSR_GPSR(IP0_8_6, D2),
818 PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
819 PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
820 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
821 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
822 PINMUX_IPSR_GPSR(IP0_11_9, D3),
823 PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
824 PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
825 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
826 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
827 PINMUX_IPSR_GPSR(IP0_15_12, D4),
828 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
829 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
830 PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
831 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
832 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
833 PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
834 PINMUX_IPSR_GPSR(IP0_19_16, D5),
835 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
836 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
837 PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
838 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
839 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
840 PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
841 PINMUX_IPSR_GPSR(IP0_22_20, D6),
842 PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
843 PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
844 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
845 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
846 PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
847 PINMUX_IPSR_GPSR(IP0_26_23, D7),
848 PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
849 PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
850 PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
851 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0),
852 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
853 PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
854 PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
855 PINMUX_IPSR_GPSR(IP0_30_27, D8),
856 PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
857 PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
858 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
859 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
860 PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
862 PINMUX_IPSR_GPSR(IP1_3_0, D9),
863 PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
864 PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
865 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
866 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
867 PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
868 PINMUX_IPSR_GPSR(IP1_7_4, D10),
869 PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
870 PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
871 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
872 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
873 PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
874 PINMUX_IPSR_GPSR(IP1_11_8, D11),
875 PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
876 PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
877 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
878 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
879 PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
880 PINMUX_IPSR_GPSR(IP1_14_12, D12),
881 PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
882 PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
883 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
884 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
885 PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
886 PINMUX_IPSR_GPSR(IP1_17_15, D13),
887 PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
888 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
889 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
890 PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
891 PINMUX_IPSR_GPSR(IP1_21_18, D14),
892 PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
893 PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
894 PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
895 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
896 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
897 PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
898 PINMUX_IPSR_GPSR(IP1_25_22, D15),
899 PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
900 PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
901 PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
902 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
903 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
904 PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
905 PINMUX_IPSR_GPSR(IP1_27_26, A0),
906 PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
907 PINMUX_IPSR_GPSR(IP1_29_28, A1),
908 PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
910 PINMUX_IPSR_GPSR(IP2_2_0, A2),
911 PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
912 PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
913 PINMUX_IPSR_GPSR(IP2_5_3, A3),
914 PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
915 PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
916 PINMUX_IPSR_GPSR(IP2_8_6, A4),
917 PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
918 PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
919 PINMUX_IPSR_GPSR(IP2_11_9, A5),
920 PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
921 PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
922 PINMUX_IPSR_GPSR(IP2_14_12, A6),
923 PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
924 PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
925 PINMUX_IPSR_GPSR(IP2_17_15, A7),
926 PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
927 PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
928 PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
929 PINMUX_IPSR_GPSR(IP2_21_18, A8),
930 PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
931 PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
932 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
933 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1),
934 PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
935 PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
936 PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
937 PINMUX_IPSR_GPSR(IP2_25_22, A9),
938 PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
939 PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
940 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
941 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1),
942 PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
943 PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
944 PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
945 PINMUX_IPSR_GPSR(IP2_28_26, A10),
946 PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
947 PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
948 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
949 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
950 PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
952 PINMUX_IPSR_GPSR(IP3_3_0, A11),
953 PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
954 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
955 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
956 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
957 PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
958 PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
959 PINMUX_IPSR_GPSR(IP3_7_4, A12),
960 PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
961 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
962 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
963 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
964 PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
965 PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
966 PINMUX_IPSR_GPSR(IP3_11_8, A13),
967 PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
968 PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
969 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
970 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
971 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
972 PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
973 PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
974 PINMUX_IPSR_GPSR(IP3_14_12, A14),
975 PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
976 PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
977 PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
978 PINMUX_IPSR_GPSR(IP3_17_15, A15),
979 PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
980 PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
981 PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
982 PINMUX_IPSR_GPSR(IP3_19_18, A16),
983 PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
984 PINMUX_IPSR_GPSR(IP3_22_20, A17),
985 PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
986 PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
987 PINMUX_IPSR_GPSR(IP3_25_23, A18),
988 PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
989 PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
990 PINMUX_IPSR_GPSR(IP3_28_26, A19),
991 PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
992 PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
993 PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
994 PINMUX_IPSR_GPSR(IP3_31_29, A20),
995 PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
996 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
997 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
998 PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
1000 PINMUX_IPSR_GPSR(IP4_2_0, A21),
1001 PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
1002 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
1003 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
1004 PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
1005 PINMUX_IPSR_GPSR(IP4_5_3, A22),
1006 PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
1007 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
1008 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1009 PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
1010 PINMUX_IPSR_GPSR(IP4_8_6, A23),
1011 PINMUX_IPSR_GPSR(IP4_8_6, IO2),
1012 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
1013 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1014 PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
1015 PINMUX_IPSR_GPSR(IP4_11_9, A24),
1016 PINMUX_IPSR_GPSR(IP4_11_9, IO3),
1017 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
1018 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1019 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1020 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1021 PINMUX_IPSR_GPSR(IP4_14_12, A25),
1022 PINMUX_IPSR_GPSR(IP4_14_12, SSL),
1023 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
1024 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1025 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1026 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1027 PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
1028 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
1029 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1030 PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
1031 PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1032 PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
1033 PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
1034 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
1035 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1036 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
1037 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1038 PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
1039 PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1040 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
1041 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1042 PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
1043 PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1044 PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1045 PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
1046 PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
1047 PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1048 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1049 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1050 PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
1051 PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
1052 PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
1053 PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1054 PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
1055 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
1056 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1057 PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
1059 PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
1060 PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
1061 PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
1062 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
1063 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1064 PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
1065 PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
1066 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1067 PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
1068 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1069 PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1070 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1071 PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
1072 PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1073 PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
1074 PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1075 PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1076 PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
1077 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
1078 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1079 PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
1080 PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1081 PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
1082 PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1083 PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
1084 PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
1085 PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1086 PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1087 PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
1088 PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
1089 PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
1090 PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1091 PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1092 PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
1093 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
1094 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1095 PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
1096 PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1097 PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
1098 PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
1099 PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1100 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1101 PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1102 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1103 PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
1104 PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
1105 PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1106 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
1107 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1108 PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
1109 PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1110 PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
1111 PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1112 PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
1113 PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
1114 PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1115 PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1116 PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1117 PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
1118 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1119 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1120 PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
1121 PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1122 PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1124 PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
1125 PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
1126 PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1127 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1128 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1129 PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1130 PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
1131 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1132 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1133 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1134 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1135 PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
1136 PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
1137 PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1138 PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1139 PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
1140 PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1141 PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1142 PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1143 PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
1144 PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
1145 PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1146 PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1147 PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1148 PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
1149 PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1150 PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1151 PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1152 PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1153 PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1154 PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
1155 PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1156 PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1157 PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1158 PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1159 PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1160 PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
1161 PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1162 PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1163 PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1164 PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1165 PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1166 PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
1167 PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1168 PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1169 PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1170 PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1171 PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1172 PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
1173 PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
1174 PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1175 PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1176 PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1177 PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
1178 PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
1179 PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1180 PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1181 PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1183 PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
1184 PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1185 PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1186 PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1187 PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
1188 PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1189 PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
1190 PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
1191 PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1192 PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1193 PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
1194 PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1195 PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
1196 PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1197 PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1198 PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1199 PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
1200 PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1201 PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1202 PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1203 PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
1204 PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1205 PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1206 PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1207 PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1208 PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
1209 PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1210 PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1211 PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1212 PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1213 PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
1214 PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
1215 PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
1216 PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1217 PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
1218 PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
1219 PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
1220 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
1221 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
1222 PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
1223 PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
1224 PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
1225 PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1226 PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
1227 PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
1229 PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1230 PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
1231 PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
1232 PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1233 PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
1234 PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
1235 PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1236 PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
1237 PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
1238 PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1239 PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
1240 PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
1241 PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1242 PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
1243 PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
1244 PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1245 PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
1246 PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1247 PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
1248 PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
1249 PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
1250 PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1251 PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1252 PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
1253 PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1254 PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1255 PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
1256 PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1257 PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1258 PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
1259 PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1260 PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1261 PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
1262 PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1263 PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1264 PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
1265 PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1266 PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
1267 PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1268 PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
1269 PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
1270 PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1271 PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
1272 PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1273 PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1275 PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
1276 PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1277 PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1278 PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
1279 PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1280 PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1281 PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
1282 PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1283 PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1284 PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
1285 PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1286 PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1287 PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
1288 PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
1289 PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1290 PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
1291 PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1292 PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1293 PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1294 PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1295 PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1296 PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
1297 PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
1298 PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1299 PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
1300 PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1301 PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1302 PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1303 PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1304 PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1305 PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
1306 PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
1307 PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
1308 PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
1309 PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1310 PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
1311 PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
1312 PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1313 PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
1314 PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
1315 PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1316 PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
1317 PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
1318 PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1319 PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
1320 PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
1321 PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1322 PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
1323 PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
1324 PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1325 PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
1326 PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
1327 PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1328 PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1329 PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1330 PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1331 PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1333 PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
1334 PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
1335 PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1336 PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
1337 PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
1338 PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1339 PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1340 PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1341 PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1342 PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
1343 PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
1344 PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1345 PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1346 PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1347 PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1348 PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1349 PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
1350 PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
1351 PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
1352 PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1353 PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1354 PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1355 PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1356 PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1357 PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1358 PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
1359 PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
1360 PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
1361 PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1362 PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1363 PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3),
1364 PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1365 PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1366 PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1367 PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
1368 PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
1369 PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
1370 PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1371 PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1372 PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3),
1373 PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1374 PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1375 PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1376 PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
1377 PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
1378 PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
1379 PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1380 PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1381 PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1382 PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1383 PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1384 PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
1385 PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
1386 PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
1387 PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1388 PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1389 PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1390 PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1391 PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1392 PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
1393 PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
1394 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1395 PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
1396 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
1397 PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1398 PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1399 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1400 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1401 PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1403 PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
1404 PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
1405 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1406 PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
1407 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
1408 PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1409 PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1410 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1411 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1412 PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1413 PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
1414 PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
1415 PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
1416 PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
1417 PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
1418 PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
1419 PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
1420 PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
1421 PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
1422 PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
1423 PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
1424 PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
1425 PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
1426 PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
1427 PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
1428 PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
1429 PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
1430 PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
1431 PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
1432 PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1433 PINMUX_IPSR_GPSR(IP11_17_15, VSP),
1434 PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
1435 PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1436 PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
1437 PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
1438 PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1439 PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
1440 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
1441 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
1442 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
1443 PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
1444 PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1445 PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1446 PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
1447 PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1448 PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
1449 PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1450 PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1451 PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
1452 PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1453 PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
1454 PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
1455 PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
1456 PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1457 PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
1459 PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
1460 PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1461 PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
1462 PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
1463 PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1464 PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
1465 PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
1466 PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1467 PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
1468 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
1469 PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1470 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
1471 PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
1472 PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
1473 PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
1474 PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1475 PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1476 PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1477 PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
1478 PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1479 PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1480 PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
1481 PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
1482 PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
1483 PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1484 PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1485 PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1486 PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
1487 PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
1488 PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1489 PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1490 PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1491 PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1492 PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
1493 PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
1494 PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1495 PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1496 PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1497 PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1498 PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
1499 PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
1500 PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1501 PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1502 PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
1503 PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1504 PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1505 PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
1506 PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1507 PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
1508 PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
1509 PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1510 PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1511 PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
1512 PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1513 PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
1514 PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
1516 PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1517 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1518 PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
1519 PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
1520 PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
1521 PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
1522 PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1523 PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1524 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
1525 PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
1526 PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
1527 PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
1528 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
1529 PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1530 PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1531 PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1532 PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
1533 PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
1534 PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
1535 PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1536 PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
1537 PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
1538 PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
1539 PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
1540 PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1541 PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1542 PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
1543 PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1544 PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
1545 PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
1546 PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
1547 PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1548 PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1549 PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1550 PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
1551 PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
1552 PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
1553 PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
1554 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1555 PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1556 PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1557 PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
1558 PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
1559 PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
1560 PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
1561 PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
1562 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1563 PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
1564 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1565 PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1566 PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1567 PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1568 PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
1569 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1570 PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
1571 PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1572 PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1573 PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
1574 PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1575 PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
1576 PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
1577 PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1578 PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
1580 PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
1581 PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1582 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1583 PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
1584 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1585 PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
1586 PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
1587 PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1588 PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1589 PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
1590 PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
1591 PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
1592 PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
1593 PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1594 PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1595 PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1596 PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
1597 PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
1598 PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
1599 PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
1600 PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1601 PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
1602 PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
1603 PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
1604 PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
1605 PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1606 PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1607 PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
1608 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1609 PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
1610 PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
1611 PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
1612 PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1613 PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1614 PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1615 PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1616 PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
1617 PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
1618 PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
1619 PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
1620 PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
1621 PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1622 PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
1623 PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
1624 PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1625 PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
1626 PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1627 PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
1628 PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
1629 PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
1630 PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
1631 PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1632 PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
1633 PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
1634 PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1635 PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
1636 PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
1637 PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1638 PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1639 PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
1640 PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1641 PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
1642 PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
1643 PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1645 PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1646 PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
1647 PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
1648 PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1649 PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
1650 PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
1651 PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1652 PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1653 PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
1654 PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
1655 PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
1656 PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
1657 PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1658 PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1659 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1660 PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
1661 PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
1662 PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
1663 PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
1664 PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1665 PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1666 PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
1667 PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1668 PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
1669 PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
1670 PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1671 PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
1672 PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
1673 PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
1674 PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
1675 PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
1676 PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
1677 PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1678 PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
1679 PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
1680 PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
1681 PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1682 PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
1683 PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
1684 PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
1685 PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1686 PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1687 PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
1688 PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
1689 PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
1690 PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
1691 PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1692 PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
1693 PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
1694 PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
1695 PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
1696 PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1697 PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1698 PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
1699 PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
1700 PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
1701 PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1702 PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
1703 PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
1704 PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
1706 PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1707 PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
1708 PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
1709 PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
1710 PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
1711 PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1712 PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1713 PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1714 PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1715 PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
1716 PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
1717 PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
1718 PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
1719 PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1720 PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
1721 PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
1722 PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
1723 PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
1725 PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
1726 PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
1727 PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
1728 PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
1730 PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
1731 PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
1732 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1733 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1737 * Pins not associated with a GPIO port.
1744 static const struct sh_pfc_pin pinmux_pins[] = {
1745 PINMUX_GPIO_GP_ALL(),
1749 /* - AUDIO CLOCK ------------------------------------------------------------ */
1750 static const unsigned int audio_clk_a_pins[] = {
1754 static const unsigned int audio_clk_a_mux[] = {
1757 static const unsigned int audio_clk_b_pins[] = {
1761 static const unsigned int audio_clk_b_mux[] = {
1764 static const unsigned int audio_clk_c_pins[] = {
1768 static const unsigned int audio_clk_c_mux[] = {
1771 static const unsigned int audio_clkout_pins[] = {
1775 static const unsigned int audio_clkout_mux[] = {
1778 static const unsigned int audio_clkout_b_pins[] = {
1782 static const unsigned int audio_clkout_b_mux[] = {
1783 AUDIO_CLKOUT_B_MARK,
1785 static const unsigned int audio_clkout_c_pins[] = {
1789 static const unsigned int audio_clkout_c_mux[] = {
1790 AUDIO_CLKOUT_C_MARK,
1792 static const unsigned int audio_clkout_d_pins[] = {
1796 static const unsigned int audio_clkout_d_mux[] = {
1797 AUDIO_CLKOUT_D_MARK,
1799 /* - AVB -------------------------------------------------------------------- */
1800 static const unsigned int avb_link_pins[] = {
1803 static const unsigned int avb_link_mux[] = {
1806 static const unsigned int avb_magic_pins[] = {
1809 static const unsigned int avb_magic_mux[] = {
1812 static const unsigned int avb_phy_int_pins[] = {
1815 static const unsigned int avb_phy_int_mux[] = {
1818 static const unsigned int avb_mdio_pins[] = {
1819 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1821 static const unsigned int avb_mdio_mux[] = {
1822 AVB_MDC_MARK, AVB_MDIO_MARK,
1824 static const unsigned int avb_mii_pins[] = {
1825 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1828 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1831 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1832 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1833 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
1835 static const unsigned int avb_mii_mux[] = {
1836 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1839 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1842 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1843 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1844 AVB_TX_CLK_MARK, AVB_COL_MARK,
1846 static const unsigned int avb_gmii_pins[] = {
1847 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1848 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1849 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1851 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1852 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1853 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1855 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1856 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
1857 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1860 static const unsigned int avb_gmii_mux[] = {
1861 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1862 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1863 AVB_TXD6_MARK, AVB_TXD7_MARK,
1865 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1866 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1867 AVB_RXD6_MARK, AVB_RXD7_MARK,
1869 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1870 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1871 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1874 /* - CAN0 ----------------------------------------------------------------- */
1875 static const unsigned int can0_data_pins[] = {
1881 static const unsigned int can0_data_mux[] = {
1885 static const unsigned int can0_data_b_pins[] = {
1891 static const unsigned int can0_data_b_mux[] = {
1895 static const unsigned int can0_data_c_pins[] = {
1901 static const unsigned int can0_data_c_mux[] = {
1905 static const unsigned int can0_data_d_pins[] = {
1911 static const unsigned int can0_data_d_mux[] = {
1915 /* - CAN1 ----------------------------------------------------------------- */
1916 static const unsigned int can1_data_pins[] = {
1922 static const unsigned int can1_data_mux[] = {
1926 static const unsigned int can1_data_b_pins[] = {
1932 static const unsigned int can1_data_b_mux[] = {
1936 /* - CAN Clock -------------------------------------------------------------- */
1937 static const unsigned int can_clk_pins[] = {
1942 static const unsigned int can_clk_mux[] = {
1946 static const unsigned int can_clk_b_pins[] = {
1951 static const unsigned int can_clk_b_mux[] = {
1954 /* - DU RGB ----------------------------------------------------------------- */
1955 static const unsigned int du_rgb666_pins[] = {
1956 /* R[7:2], G[7:2], B[7:2] */
1957 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1958 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1959 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1960 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1961 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1962 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
1964 static const unsigned int du_rgb666_mux[] = {
1965 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1966 DU2_DR3_MARK, DU2_DR2_MARK,
1967 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1968 DU2_DG3_MARK, DU2_DG2_MARK,
1969 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1970 DU2_DB3_MARK, DU2_DB2_MARK,
1972 static const unsigned int du_rgb888_pins[] = {
1973 /* R[7:0], G[7:0], B[7:0] */
1974 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1975 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1976 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1977 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1978 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1979 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1980 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1981 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1983 static const unsigned int du_rgb888_mux[] = {
1984 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1985 DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1986 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1987 DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1988 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1989 DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1991 static const unsigned int du_clk_out_0_pins[] = {
1995 static const unsigned int du_clk_out_0_mux[] = {
1998 static const unsigned int du_clk_out_1_pins[] = {
2002 static const unsigned int du_clk_out_1_mux[] = {
2005 static const unsigned int du_sync_0_pins[] = {
2006 /* VSYNC, HSYNC, DISP */
2007 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
2009 static const unsigned int du_sync_0_mux[] = {
2010 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
2011 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
2013 static const unsigned int du_sync_1_pins[] = {
2014 /* VSYNC, HSYNC, DISP */
2015 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
2017 static const unsigned int du_sync_1_mux[] = {
2018 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
2021 static const unsigned int du_cde_pins[] = {
2025 static const unsigned int du_cde_mux[] = {
2028 /* - DU0 -------------------------------------------------------------------- */
2029 static const unsigned int du0_clk_in_pins[] = {
2033 static const unsigned int du0_clk_in_mux[] = {
2036 /* - DU1 -------------------------------------------------------------------- */
2037 static const unsigned int du1_clk_in_pins[] = {
2041 static const unsigned int du1_clk_in_mux[] = {
2044 /* - DU2 -------------------------------------------------------------------- */
2045 static const unsigned int du2_clk_in_pins[] = {
2049 static const unsigned int du2_clk_in_mux[] = {
2052 /* - ETH -------------------------------------------------------------------- */
2053 static const unsigned int eth_link_pins[] = {
2057 static const unsigned int eth_link_mux[] = {
2060 static const unsigned int eth_magic_pins[] = {
2064 static const unsigned int eth_magic_mux[] = {
2067 static const unsigned int eth_mdio_pins[] = {
2069 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
2071 static const unsigned int eth_mdio_mux[] = {
2072 ETH_MDC_MARK, ETH_MDIO_MARK,
2074 static const unsigned int eth_rmii_pins[] = {
2075 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2076 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
2077 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
2078 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
2080 static const unsigned int eth_rmii_mux[] = {
2081 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2082 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
2084 /* - HSCIF0 ----------------------------------------------------------------- */
2085 static const unsigned int hscif0_data_pins[] = {
2087 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2089 static const unsigned int hscif0_data_mux[] = {
2090 HRX0_MARK, HTX0_MARK,
2092 static const unsigned int hscif0_clk_pins[] = {
2096 static const unsigned int hscif0_clk_mux[] = {
2099 static const unsigned int hscif0_ctrl_pins[] = {
2101 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2103 static const unsigned int hscif0_ctrl_mux[] = {
2104 HRTS0_N_MARK, HCTS0_N_MARK,
2106 static const unsigned int hscif0_data_b_pins[] = {
2108 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
2110 static const unsigned int hscif0_data_b_mux[] = {
2111 HRX0_B_MARK, HTX0_B_MARK,
2113 static const unsigned int hscif0_ctrl_b_pins[] = {
2115 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
2117 static const unsigned int hscif0_ctrl_b_mux[] = {
2118 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2120 static const unsigned int hscif0_data_c_pins[] = {
2122 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2124 static const unsigned int hscif0_data_c_mux[] = {
2125 HRX0_C_MARK, HTX0_C_MARK,
2127 static const unsigned int hscif0_ctrl_c_pins[] = {
2129 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
2131 static const unsigned int hscif0_ctrl_c_mux[] = {
2132 HRTS0_N_C_MARK, HCTS0_N_C_MARK,
2134 static const unsigned int hscif0_data_d_pins[] = {
2136 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2138 static const unsigned int hscif0_data_d_mux[] = {
2139 HRX0_D_MARK, HTX0_D_MARK,
2141 static const unsigned int hscif0_ctrl_d_pins[] = {
2143 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
2145 static const unsigned int hscif0_ctrl_d_mux[] = {
2146 HRTS0_N_D_MARK, HCTS0_N_D_MARK,
2148 static const unsigned int hscif0_data_e_pins[] = {
2150 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2152 static const unsigned int hscif0_data_e_mux[] = {
2153 HRX0_E_MARK, HTX0_E_MARK,
2155 static const unsigned int hscif0_ctrl_e_pins[] = {
2157 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2159 static const unsigned int hscif0_ctrl_e_mux[] = {
2160 HRTS0_N_E_MARK, HCTS0_N_E_MARK,
2162 static const unsigned int hscif0_data_f_pins[] = {
2164 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2166 static const unsigned int hscif0_data_f_mux[] = {
2167 HRX0_F_MARK, HTX0_F_MARK,
2169 static const unsigned int hscif0_ctrl_f_pins[] = {
2171 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2173 static const unsigned int hscif0_ctrl_f_mux[] = {
2174 HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2176 /* - HSCIF1 ----------------------------------------------------------------- */
2177 static const unsigned int hscif1_data_pins[] = {
2179 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2181 static const unsigned int hscif1_data_mux[] = {
2182 HRX1_MARK, HTX1_MARK,
2184 static const unsigned int hscif1_clk_pins[] = {
2188 static const unsigned int hscif1_clk_mux[] = {
2191 static const unsigned int hscif1_ctrl_pins[] = {
2193 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2195 static const unsigned int hscif1_ctrl_mux[] = {
2196 HRTS1_N_MARK, HCTS1_N_MARK,
2198 static const unsigned int hscif1_data_b_pins[] = {
2200 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2202 static const unsigned int hscif1_data_b_mux[] = {
2203 HRX1_B_MARK, HTX1_B_MARK,
2205 static const unsigned int hscif1_clk_b_pins[] = {
2209 static const unsigned int hscif1_clk_b_mux[] = {
2212 static const unsigned int hscif1_ctrl_b_pins[] = {
2214 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2216 static const unsigned int hscif1_ctrl_b_mux[] = {
2217 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2219 /* - I2C0 ------------------------------------------------------------------- */
2220 static const unsigned int i2c0_pins[] = {
2222 PIN_IIC0_SCL, PIN_IIC0_SDA,
2224 static const unsigned int i2c0_mux[] = {
2225 I2C0_SCL_MARK, I2C0_SDA_MARK,
2227 /* - I2C1 ------------------------------------------------------------------- */
2228 static const unsigned int i2c1_pins[] = {
2230 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2232 static const unsigned int i2c1_mux[] = {
2233 I2C1_SCL_MARK, I2C1_SDA_MARK,
2235 static const unsigned int i2c1_b_pins[] = {
2237 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2239 static const unsigned int i2c1_b_mux[] = {
2240 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2242 static const unsigned int i2c1_c_pins[] = {
2244 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2246 static const unsigned int i2c1_c_mux[] = {
2247 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2249 /* - I2C2 ------------------------------------------------------------------- */
2250 static const unsigned int i2c2_pins[] = {
2252 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2254 static const unsigned int i2c2_mux[] = {
2255 I2C2_SCL_MARK, I2C2_SDA_MARK,
2257 static const unsigned int i2c2_b_pins[] = {
2259 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2261 static const unsigned int i2c2_b_mux[] = {
2262 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2264 static const unsigned int i2c2_c_pins[] = {
2266 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2268 static const unsigned int i2c2_c_mux[] = {
2269 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2271 static const unsigned int i2c2_d_pins[] = {
2273 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2275 static const unsigned int i2c2_d_mux[] = {
2276 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2278 static const unsigned int i2c2_e_pins[] = {
2280 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2282 static const unsigned int i2c2_e_mux[] = {
2283 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2285 /* - I2C3 ------------------------------------------------------------------- */
2286 static const unsigned int i2c3_pins[] = {
2288 PIN_IIC3_SCL, PIN_IIC3_SDA,
2290 static const unsigned int i2c3_mux[] = {
2291 I2C3_SCL_MARK, I2C3_SDA_MARK,
2293 /* - IIC0 (I2C4) ------------------------------------------------------------ */
2294 static const unsigned int iic0_pins[] = {
2296 PIN_IIC0_SCL, PIN_IIC0_SDA,
2298 static const unsigned int iic0_mux[] = {
2299 IIC0_SCL_MARK, IIC0_SDA_MARK,
2301 /* - IIC1 (I2C5) ------------------------------------------------------------ */
2302 static const unsigned int iic1_pins[] = {
2304 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2306 static const unsigned int iic1_mux[] = {
2307 IIC1_SCL_MARK, IIC1_SDA_MARK,
2309 static const unsigned int iic1_b_pins[] = {
2311 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2313 static const unsigned int iic1_b_mux[] = {
2314 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2316 static const unsigned int iic1_c_pins[] = {
2318 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2320 static const unsigned int iic1_c_mux[] = {
2321 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2323 /* - IIC2 (I2C6) ------------------------------------------------------------ */
2324 static const unsigned int iic2_pins[] = {
2326 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2328 static const unsigned int iic2_mux[] = {
2329 IIC2_SCL_MARK, IIC2_SDA_MARK,
2331 static const unsigned int iic2_b_pins[] = {
2333 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2335 static const unsigned int iic2_b_mux[] = {
2336 IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
2338 static const unsigned int iic2_c_pins[] = {
2340 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2342 static const unsigned int iic2_c_mux[] = {
2343 IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
2345 static const unsigned int iic2_d_pins[] = {
2347 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2349 static const unsigned int iic2_d_mux[] = {
2350 IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
2352 static const unsigned int iic2_e_pins[] = {
2354 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2356 static const unsigned int iic2_e_mux[] = {
2357 IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
2359 /* - IIC3 (I2C7) ------------------------------------------------------------ */
2360 static const unsigned int iic3_pins[] = {
2362 PIN_IIC3_SCL, PIN_IIC3_SDA,
2364 static const unsigned int iic3_mux[] = {
2365 IIC3_SCL_MARK, IIC3_SDA_MARK,
2367 /* - INTC ------------------------------------------------------------------- */
2368 static const unsigned int intc_irq0_pins[] = {
2372 static const unsigned int intc_irq0_mux[] = {
2375 static const unsigned int intc_irq1_pins[] = {
2379 static const unsigned int intc_irq1_mux[] = {
2382 static const unsigned int intc_irq2_pins[] = {
2386 static const unsigned int intc_irq2_mux[] = {
2389 static const unsigned int intc_irq3_pins[] = {
2393 static const unsigned int intc_irq3_mux[] = {
2397 #ifdef CONFIG_PINCTRL_PFC_R8A7790
2398 /* - MLB+ ------------------------------------------------------------------- */
2399 static const unsigned int mlb_3pin_pins[] = {
2400 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2402 static const unsigned int mlb_3pin_mux[] = {
2403 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2405 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
2407 /* - MMCIF0 ----------------------------------------------------------------- */
2408 static const unsigned int mmc0_data_pins[] = {
2410 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2411 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2412 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2413 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2415 static const unsigned int mmc0_data_mux[] = {
2416 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2417 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2419 static const unsigned int mmc0_ctrl_pins[] = {
2421 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2423 static const unsigned int mmc0_ctrl_mux[] = {
2424 MMC0_CLK_MARK, MMC0_CMD_MARK,
2426 /* - MMCIF1 ----------------------------------------------------------------- */
2427 static const unsigned int mmc1_data_pins[] = {
2429 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2430 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2431 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2432 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2434 static const unsigned int mmc1_data_mux[] = {
2435 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2436 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2438 static const unsigned int mmc1_ctrl_pins[] = {
2440 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2442 static const unsigned int mmc1_ctrl_mux[] = {
2443 MMC1_CLK_MARK, MMC1_CMD_MARK,
2445 /* - MSIOF0 ----------------------------------------------------------------- */
2446 static const unsigned int msiof0_clk_pins[] = {
2450 static const unsigned int msiof0_clk_mux[] = {
2453 static const unsigned int msiof0_sync_pins[] = {
2457 static const unsigned int msiof0_sync_mux[] = {
2460 static const unsigned int msiof0_ss1_pins[] = {
2464 static const unsigned int msiof0_ss1_mux[] = {
2467 static const unsigned int msiof0_ss2_pins[] = {
2471 static const unsigned int msiof0_ss2_mux[] = {
2474 static const unsigned int msiof0_rx_pins[] = {
2478 static const unsigned int msiof0_rx_mux[] = {
2481 static const unsigned int msiof0_tx_pins[] = {
2485 static const unsigned int msiof0_tx_mux[] = {
2489 static const unsigned int msiof0_clk_b_pins[] = {
2493 static const unsigned int msiof0_clk_b_mux[] = {
2496 static const unsigned int msiof0_ss1_b_pins[] = {
2500 static const unsigned int msiof0_ss1_b_mux[] = {
2503 static const unsigned int msiof0_ss2_b_pins[] = {
2507 static const unsigned int msiof0_ss2_b_mux[] = {
2510 static const unsigned int msiof0_rx_b_pins[] = {
2514 static const unsigned int msiof0_rx_b_mux[] = {
2517 static const unsigned int msiof0_tx_b_pins[] = {
2521 static const unsigned int msiof0_tx_b_mux[] = {
2524 /* - MSIOF1 ----------------------------------------------------------------- */
2525 static const unsigned int msiof1_clk_pins[] = {
2529 static const unsigned int msiof1_clk_mux[] = {
2532 static const unsigned int msiof1_sync_pins[] = {
2536 static const unsigned int msiof1_sync_mux[] = {
2539 static const unsigned int msiof1_ss1_pins[] = {
2543 static const unsigned int msiof1_ss1_mux[] = {
2546 static const unsigned int msiof1_ss2_pins[] = {
2550 static const unsigned int msiof1_ss2_mux[] = {
2553 static const unsigned int msiof1_rx_pins[] = {
2557 static const unsigned int msiof1_rx_mux[] = {
2560 static const unsigned int msiof1_tx_pins[] = {
2564 static const unsigned int msiof1_tx_mux[] = {
2568 static const unsigned int msiof1_clk_b_pins[] = {
2572 static const unsigned int msiof1_clk_b_mux[] = {
2575 static const unsigned int msiof1_ss1_b_pins[] = {
2579 static const unsigned int msiof1_ss1_b_mux[] = {
2582 static const unsigned int msiof1_ss2_b_pins[] = {
2586 static const unsigned int msiof1_ss2_b_mux[] = {
2589 static const unsigned int msiof1_rx_b_pins[] = {
2593 static const unsigned int msiof1_rx_b_mux[] = {
2596 static const unsigned int msiof1_tx_b_pins[] = {
2600 static const unsigned int msiof1_tx_b_mux[] = {
2603 /* - MSIOF2 ----------------------------------------------------------------- */
2604 static const unsigned int msiof2_clk_pins[] = {
2608 static const unsigned int msiof2_clk_mux[] = {
2611 static const unsigned int msiof2_sync_pins[] = {
2615 static const unsigned int msiof2_sync_mux[] = {
2618 static const unsigned int msiof2_ss1_pins[] = {
2622 static const unsigned int msiof2_ss1_mux[] = {
2625 static const unsigned int msiof2_ss2_pins[] = {
2629 static const unsigned int msiof2_ss2_mux[] = {
2632 static const unsigned int msiof2_rx_pins[] = {
2636 static const unsigned int msiof2_rx_mux[] = {
2639 static const unsigned int msiof2_tx_pins[] = {
2643 static const unsigned int msiof2_tx_mux[] = {
2646 /* - MSIOF3 ----------------------------------------------------------------- */
2647 static const unsigned int msiof3_clk_pins[] = {
2651 static const unsigned int msiof3_clk_mux[] = {
2654 static const unsigned int msiof3_sync_pins[] = {
2658 static const unsigned int msiof3_sync_mux[] = {
2661 static const unsigned int msiof3_ss1_pins[] = {
2665 static const unsigned int msiof3_ss1_mux[] = {
2668 static const unsigned int msiof3_ss2_pins[] = {
2672 static const unsigned int msiof3_ss2_mux[] = {
2675 static const unsigned int msiof3_rx_pins[] = {
2679 static const unsigned int msiof3_rx_mux[] = {
2682 static const unsigned int msiof3_tx_pins[] = {
2686 static const unsigned int msiof3_tx_mux[] = {
2690 static const unsigned int msiof3_clk_b_pins[] = {
2694 static const unsigned int msiof3_clk_b_mux[] = {
2697 static const unsigned int msiof3_sync_b_pins[] = {
2701 static const unsigned int msiof3_sync_b_mux[] = {
2704 static const unsigned int msiof3_rx_b_pins[] = {
2708 static const unsigned int msiof3_rx_b_mux[] = {
2711 static const unsigned int msiof3_tx_b_pins[] = {
2715 static const unsigned int msiof3_tx_b_mux[] = {
2718 /* - PWM -------------------------------------------------------------------- */
2719 static const unsigned int pwm0_pins[] = {
2722 static const unsigned int pwm0_mux[] = {
2725 static const unsigned int pwm0_b_pins[] = {
2728 static const unsigned int pwm0_b_mux[] = {
2731 static const unsigned int pwm1_pins[] = {
2734 static const unsigned int pwm1_mux[] = {
2737 static const unsigned int pwm1_b_pins[] = {
2740 static const unsigned int pwm1_b_mux[] = {
2743 static const unsigned int pwm2_pins[] = {
2746 static const unsigned int pwm2_mux[] = {
2749 static const unsigned int pwm3_pins[] = {
2752 static const unsigned int pwm3_mux[] = {
2755 static const unsigned int pwm4_pins[] = {
2758 static const unsigned int pwm4_mux[] = {
2761 static const unsigned int pwm5_pins[] = {
2764 static const unsigned int pwm5_mux[] = {
2767 static const unsigned int pwm6_pins[] = {
2770 static const unsigned int pwm6_mux[] = {
2773 /* - QSPI ------------------------------------------------------------------- */
2774 static const unsigned int qspi_ctrl_pins[] = {
2776 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2778 static const unsigned int qspi_ctrl_mux[] = {
2779 SPCLK_MARK, SSL_MARK,
2781 static const unsigned int qspi_data2_pins[] = {
2782 /* MOSI_IO0, MISO_IO1 */
2783 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2785 static const unsigned int qspi_data2_mux[] = {
2786 MOSI_IO0_MARK, MISO_IO1_MARK,
2788 static const unsigned int qspi_data4_pins[] = {
2789 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2790 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2793 static const unsigned int qspi_data4_mux[] = {
2794 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2796 /* - SCIF0 ------------------------------------------------------------------ */
2797 static const unsigned int scif0_data_pins[] = {
2799 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2801 static const unsigned int scif0_data_mux[] = {
2804 static const unsigned int scif0_clk_pins[] = {
2808 static const unsigned int scif0_clk_mux[] = {
2811 static const unsigned int scif0_ctrl_pins[] = {
2813 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2815 static const unsigned int scif0_ctrl_mux[] = {
2816 RTS0_N_MARK, CTS0_N_MARK,
2818 static const unsigned int scif0_data_b_pins[] = {
2820 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2822 static const unsigned int scif0_data_b_mux[] = {
2823 RX0_B_MARK, TX0_B_MARK,
2825 /* - SCIF1 ------------------------------------------------------------------ */
2826 static const unsigned int scif1_data_pins[] = {
2828 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2830 static const unsigned int scif1_data_mux[] = {
2833 static const unsigned int scif1_clk_pins[] = {
2837 static const unsigned int scif1_clk_mux[] = {
2840 static const unsigned int scif1_ctrl_pins[] = {
2842 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2844 static const unsigned int scif1_ctrl_mux[] = {
2845 RTS1_N_MARK, CTS1_N_MARK,
2847 static const unsigned int scif1_data_b_pins[] = {
2849 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2851 static const unsigned int scif1_data_b_mux[] = {
2852 RX1_B_MARK, TX1_B_MARK,
2854 static const unsigned int scif1_data_c_pins[] = {
2856 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2858 static const unsigned int scif1_data_c_mux[] = {
2859 RX1_C_MARK, TX1_C_MARK,
2861 static const unsigned int scif1_data_d_pins[] = {
2863 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2865 static const unsigned int scif1_data_d_mux[] = {
2866 RX1_D_MARK, TX1_D_MARK,
2868 static const unsigned int scif1_clk_d_pins[] = {
2872 static const unsigned int scif1_clk_d_mux[] = {
2875 static const unsigned int scif1_data_e_pins[] = {
2877 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2879 static const unsigned int scif1_data_e_mux[] = {
2880 RX1_E_MARK, TX1_E_MARK,
2882 static const unsigned int scif1_clk_e_pins[] = {
2886 static const unsigned int scif1_clk_e_mux[] = {
2889 /* - SCIF2 ------------------------------------------------------------------ */
2890 static const unsigned int scif2_data_pins[] = {
2892 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2894 static const unsigned int scif2_data_mux[] = {
2897 static const unsigned int scif2_clk_pins[] = {
2901 static const unsigned int scif2_clk_mux[] = {
2904 static const unsigned int scif2_data_b_pins[] = {
2906 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2908 static const unsigned int scif2_data_b_mux[] = {
2909 RX2_B_MARK, TX2_B_MARK,
2911 /* - SCIFA0 ----------------------------------------------------------------- */
2912 static const unsigned int scifa0_data_pins[] = {
2914 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2916 static const unsigned int scifa0_data_mux[] = {
2917 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2919 static const unsigned int scifa0_clk_pins[] = {
2923 static const unsigned int scifa0_clk_mux[] = {
2926 static const unsigned int scifa0_ctrl_pins[] = {
2928 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2930 static const unsigned int scifa0_ctrl_mux[] = {
2931 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2933 static const unsigned int scifa0_data_b_pins[] = {
2935 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2937 static const unsigned int scifa0_data_b_mux[] = {
2938 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2940 static const unsigned int scifa0_clk_b_pins[] = {
2944 static const unsigned int scifa0_clk_b_mux[] = {
2947 static const unsigned int scifa0_ctrl_b_pins[] = {
2949 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2951 static const unsigned int scifa0_ctrl_b_mux[] = {
2952 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2954 /* - SCIFA1 ----------------------------------------------------------------- */
2955 static const unsigned int scifa1_data_pins[] = {
2957 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2959 static const unsigned int scifa1_data_mux[] = {
2960 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2962 static const unsigned int scifa1_clk_pins[] = {
2966 static const unsigned int scifa1_clk_mux[] = {
2969 static const unsigned int scifa1_ctrl_pins[] = {
2971 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2973 static const unsigned int scifa1_ctrl_mux[] = {
2974 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2976 static const unsigned int scifa1_data_b_pins[] = {
2978 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2980 static const unsigned int scifa1_data_b_mux[] = {
2981 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2983 static const unsigned int scifa1_clk_b_pins[] = {
2987 static const unsigned int scifa1_clk_b_mux[] = {
2990 static const unsigned int scifa1_ctrl_b_pins[] = {
2992 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2994 static const unsigned int scifa1_ctrl_b_mux[] = {
2995 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2997 static const unsigned int scifa1_data_c_pins[] = {
2999 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
3001 static const unsigned int scifa1_data_c_mux[] = {
3002 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3004 static const unsigned int scifa1_clk_c_pins[] = {
3008 static const unsigned int scifa1_clk_c_mux[] = {
3011 static const unsigned int scifa1_ctrl_c_pins[] = {
3013 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
3015 static const unsigned int scifa1_ctrl_c_mux[] = {
3016 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
3018 static const unsigned int scifa1_data_d_pins[] = {
3020 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3022 static const unsigned int scifa1_data_d_mux[] = {
3023 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
3025 static const unsigned int scifa1_clk_d_pins[] = {
3029 static const unsigned int scifa1_clk_d_mux[] = {
3032 static const unsigned int scifa1_ctrl_d_pins[] = {
3034 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3036 static const unsigned int scifa1_ctrl_d_mux[] = {
3037 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
3039 /* - SCIFA2 ----------------------------------------------------------------- */
3040 static const unsigned int scifa2_data_pins[] = {
3042 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3044 static const unsigned int scifa2_data_mux[] = {
3045 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3047 static const unsigned int scifa2_clk_pins[] = {
3051 static const unsigned int scifa2_clk_mux[] = {
3054 static const unsigned int scifa2_ctrl_pins[] = {
3056 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
3058 static const unsigned int scifa2_ctrl_mux[] = {
3059 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
3061 static const unsigned int scifa2_data_b_pins[] = {
3063 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
3065 static const unsigned int scifa2_data_b_mux[] = {
3066 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3068 static const unsigned int scifa2_data_c_pins[] = {
3070 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
3072 static const unsigned int scifa2_data_c_mux[] = {
3073 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
3075 static const unsigned int scifa2_clk_c_pins[] = {
3079 static const unsigned int scifa2_clk_c_mux[] = {
3082 /* - SCIFB0 ----------------------------------------------------------------- */
3083 static const unsigned int scifb0_data_pins[] = {
3085 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3087 static const unsigned int scifb0_data_mux[] = {
3088 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3090 static const unsigned int scifb0_clk_pins[] = {
3094 static const unsigned int scifb0_clk_mux[] = {
3097 static const unsigned int scifb0_ctrl_pins[] = {
3099 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
3101 static const unsigned int scifb0_ctrl_mux[] = {
3102 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3104 static const unsigned int scifb0_data_b_pins[] = {
3106 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3108 static const unsigned int scifb0_data_b_mux[] = {
3109 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3111 static const unsigned int scifb0_clk_b_pins[] = {
3115 static const unsigned int scifb0_clk_b_mux[] = {
3118 static const unsigned int scifb0_ctrl_b_pins[] = {
3120 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
3122 static const unsigned int scifb0_ctrl_b_mux[] = {
3123 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3125 static const unsigned int scifb0_data_c_pins[] = {
3127 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3129 static const unsigned int scifb0_data_c_mux[] = {
3130 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3132 /* - SCIFB1 ----------------------------------------------------------------- */
3133 static const unsigned int scifb1_data_pins[] = {
3135 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3137 static const unsigned int scifb1_data_mux[] = {
3138 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3140 static const unsigned int scifb1_clk_pins[] = {
3144 static const unsigned int scifb1_clk_mux[] = {
3147 static const unsigned int scifb1_ctrl_pins[] = {
3149 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
3151 static const unsigned int scifb1_ctrl_mux[] = {
3152 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3154 static const unsigned int scifb1_data_b_pins[] = {
3156 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3158 static const unsigned int scifb1_data_b_mux[] = {
3159 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3161 static const unsigned int scifb1_clk_b_pins[] = {
3165 static const unsigned int scifb1_clk_b_mux[] = {
3168 static const unsigned int scifb1_ctrl_b_pins[] = {
3170 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
3172 static const unsigned int scifb1_ctrl_b_mux[] = {
3173 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
3175 static const unsigned int scifb1_data_c_pins[] = {
3177 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3179 static const unsigned int scifb1_data_c_mux[] = {
3180 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3182 static const unsigned int scifb1_data_d_pins[] = {
3184 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
3186 static const unsigned int scifb1_data_d_mux[] = {
3187 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3189 static const unsigned int scifb1_data_e_pins[] = {
3191 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
3193 static const unsigned int scifb1_data_e_mux[] = {
3194 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
3196 static const unsigned int scifb1_clk_e_pins[] = {
3200 static const unsigned int scifb1_clk_e_mux[] = {
3203 static const unsigned int scifb1_data_f_pins[] = {
3205 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3207 static const unsigned int scifb1_data_f_mux[] = {
3208 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
3210 static const unsigned int scifb1_data_g_pins[] = {
3212 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3214 static const unsigned int scifb1_data_g_mux[] = {
3215 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
3217 static const unsigned int scifb1_clk_g_pins[] = {
3221 static const unsigned int scifb1_clk_g_mux[] = {
3224 /* - SCIFB2 ----------------------------------------------------------------- */
3225 static const unsigned int scifb2_data_pins[] = {
3227 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3229 static const unsigned int scifb2_data_mux[] = {
3230 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3232 static const unsigned int scifb2_clk_pins[] = {
3236 static const unsigned int scifb2_clk_mux[] = {
3239 static const unsigned int scifb2_ctrl_pins[] = {
3241 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
3243 static const unsigned int scifb2_ctrl_mux[] = {
3244 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3246 static const unsigned int scifb2_data_b_pins[] = {
3248 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
3250 static const unsigned int scifb2_data_b_mux[] = {
3251 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3253 static const unsigned int scifb2_clk_b_pins[] = {
3257 static const unsigned int scifb2_clk_b_mux[] = {
3260 static const unsigned int scifb2_ctrl_b_pins[] = {
3262 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
3264 static const unsigned int scifb2_ctrl_b_mux[] = {
3265 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3267 static const unsigned int scifb2_data_c_pins[] = {
3269 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3271 static const unsigned int scifb2_data_c_mux[] = {
3272 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3274 /* - SCIF Clock ------------------------------------------------------------- */
3275 static const unsigned int scif_clk_pins[] = {
3279 static const unsigned int scif_clk_mux[] = {
3282 static const unsigned int scif_clk_b_pins[] = {
3286 static const unsigned int scif_clk_b_mux[] = {
3289 /* - SDHI0 ------------------------------------------------------------------ */
3290 static const unsigned int sdhi0_data1_pins[] = {
3294 static const unsigned int sdhi0_data1_mux[] = {
3297 static const unsigned int sdhi0_data4_pins[] = {
3299 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3301 static const unsigned int sdhi0_data4_mux[] = {
3302 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
3304 static const unsigned int sdhi0_ctrl_pins[] = {
3306 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3308 static const unsigned int sdhi0_ctrl_mux[] = {
3309 SD0_CLK_MARK, SD0_CMD_MARK,
3311 static const unsigned int sdhi0_cd_pins[] = {
3315 static const unsigned int sdhi0_cd_mux[] = {
3318 static const unsigned int sdhi0_wp_pins[] = {
3322 static const unsigned int sdhi0_wp_mux[] = {
3325 /* - SDHI1 ------------------------------------------------------------------ */
3326 static const unsigned int sdhi1_data1_pins[] = {
3330 static const unsigned int sdhi1_data1_mux[] = {
3333 static const unsigned int sdhi1_data4_pins[] = {
3335 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3337 static const unsigned int sdhi1_data4_mux[] = {
3338 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
3340 static const unsigned int sdhi1_ctrl_pins[] = {
3342 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3344 static const unsigned int sdhi1_ctrl_mux[] = {
3345 SD1_CLK_MARK, SD1_CMD_MARK,
3347 static const unsigned int sdhi1_cd_pins[] = {
3351 static const unsigned int sdhi1_cd_mux[] = {
3354 static const unsigned int sdhi1_wp_pins[] = {
3358 static const unsigned int sdhi1_wp_mux[] = {
3361 /* - SDHI2 ------------------------------------------------------------------ */
3362 static const unsigned int sdhi2_data1_pins[] = {
3366 static const unsigned int sdhi2_data1_mux[] = {
3369 static const unsigned int sdhi2_data4_pins[] = {
3371 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3373 static const unsigned int sdhi2_data4_mux[] = {
3374 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
3376 static const unsigned int sdhi2_ctrl_pins[] = {
3378 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3380 static const unsigned int sdhi2_ctrl_mux[] = {
3381 SD2_CLK_MARK, SD2_CMD_MARK,
3383 static const unsigned int sdhi2_cd_pins[] = {
3387 static const unsigned int sdhi2_cd_mux[] = {
3390 static const unsigned int sdhi2_wp_pins[] = {
3394 static const unsigned int sdhi2_wp_mux[] = {
3397 /* - SDHI3 ------------------------------------------------------------------ */
3398 static const unsigned int sdhi3_data1_pins[] = {
3402 static const unsigned int sdhi3_data1_mux[] = {
3405 static const unsigned int sdhi3_data4_pins[] = {
3407 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3409 static const unsigned int sdhi3_data4_mux[] = {
3410 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
3412 static const unsigned int sdhi3_ctrl_pins[] = {
3414 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3416 static const unsigned int sdhi3_ctrl_mux[] = {
3417 SD3_CLK_MARK, SD3_CMD_MARK,
3419 static const unsigned int sdhi3_cd_pins[] = {
3423 static const unsigned int sdhi3_cd_mux[] = {
3426 static const unsigned int sdhi3_wp_pins[] = {
3430 static const unsigned int sdhi3_wp_mux[] = {
3433 /* - SSI -------------------------------------------------------------------- */
3434 static const unsigned int ssi0_data_pins[] = {
3438 static const unsigned int ssi0_data_mux[] = {
3441 static const unsigned int ssi0129_ctrl_pins[] = {
3443 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3445 static const unsigned int ssi0129_ctrl_mux[] = {
3446 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3448 static const unsigned int ssi1_data_pins[] = {
3452 static const unsigned int ssi1_data_mux[] = {
3455 static const unsigned int ssi1_ctrl_pins[] = {
3457 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3459 static const unsigned int ssi1_ctrl_mux[] = {
3460 SSI_SCK1_MARK, SSI_WS1_MARK,
3462 static const unsigned int ssi2_data_pins[] = {
3466 static const unsigned int ssi2_data_mux[] = {
3469 static const unsigned int ssi2_ctrl_pins[] = {
3471 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3473 static const unsigned int ssi2_ctrl_mux[] = {
3474 SSI_SCK2_MARK, SSI_WS2_MARK,
3476 static const unsigned int ssi3_data_pins[] = {
3480 static const unsigned int ssi3_data_mux[] = {
3483 static const unsigned int ssi34_ctrl_pins[] = {
3485 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3487 static const unsigned int ssi34_ctrl_mux[] = {
3488 SSI_SCK34_MARK, SSI_WS34_MARK,
3490 static const unsigned int ssi4_data_pins[] = {
3494 static const unsigned int ssi4_data_mux[] = {
3497 static const unsigned int ssi4_ctrl_pins[] = {
3499 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3501 static const unsigned int ssi4_ctrl_mux[] = {
3502 SSI_SCK4_MARK, SSI_WS4_MARK,
3504 static const unsigned int ssi5_pins[] = {
3505 /* SDATA5, SCK, WS */
3506 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3508 static const unsigned int ssi5_mux[] = {
3509 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3511 static const unsigned int ssi5_b_pins[] = {
3512 /* SDATA5, SCK, WS */
3513 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3515 static const unsigned int ssi5_b_mux[] = {
3516 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3518 static const unsigned int ssi5_c_pins[] = {
3519 /* SDATA5, SCK, WS */
3520 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3522 static const unsigned int ssi5_c_mux[] = {
3523 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3525 static const unsigned int ssi6_pins[] = {
3526 /* SDATA6, SCK, WS */
3527 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3529 static const unsigned int ssi6_mux[] = {
3530 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3532 static const unsigned int ssi6_b_pins[] = {
3533 /* SDATA6, SCK, WS */
3534 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3536 static const unsigned int ssi6_b_mux[] = {
3537 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3539 static const unsigned int ssi7_data_pins[] = {
3543 static const unsigned int ssi7_data_mux[] = {
3546 static const unsigned int ssi7_b_data_pins[] = {
3550 static const unsigned int ssi7_b_data_mux[] = {
3553 static const unsigned int ssi7_c_data_pins[] = {
3557 static const unsigned int ssi7_c_data_mux[] = {
3560 static const unsigned int ssi78_ctrl_pins[] = {
3562 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3564 static const unsigned int ssi78_ctrl_mux[] = {
3565 SSI_SCK78_MARK, SSI_WS78_MARK,
3567 static const unsigned int ssi78_b_ctrl_pins[] = {
3569 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3571 static const unsigned int ssi78_b_ctrl_mux[] = {
3572 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3574 static const unsigned int ssi78_c_ctrl_pins[] = {
3576 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3578 static const unsigned int ssi78_c_ctrl_mux[] = {
3579 SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3581 static const unsigned int ssi8_data_pins[] = {
3585 static const unsigned int ssi8_data_mux[] = {
3588 static const unsigned int ssi8_b_data_pins[] = {
3592 static const unsigned int ssi8_b_data_mux[] = {
3595 static const unsigned int ssi8_c_data_pins[] = {
3599 static const unsigned int ssi8_c_data_mux[] = {
3602 static const unsigned int ssi9_data_pins[] = {
3606 static const unsigned int ssi9_data_mux[] = {
3609 static const unsigned int ssi9_ctrl_pins[] = {
3611 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3613 static const unsigned int ssi9_ctrl_mux[] = {
3614 SSI_SCK9_MARK, SSI_WS9_MARK,
3616 /* - TPU0 ------------------------------------------------------------------- */
3617 static const unsigned int tpu0_to0_pins[] = {
3621 static const unsigned int tpu0_to0_mux[] = {
3624 static const unsigned int tpu0_to1_pins[] = {
3628 static const unsigned int tpu0_to1_mux[] = {
3631 static const unsigned int tpu0_to2_pins[] = {
3635 static const unsigned int tpu0_to2_mux[] = {
3638 static const unsigned int tpu0_to3_pins[] = {
3642 static const unsigned int tpu0_to3_mux[] = {
3645 /* - USB0 ------------------------------------------------------------------- */
3646 static const unsigned int usb0_pins[] = {
3647 /* PWEN, OVC/VBUS */
3648 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3650 static const unsigned int usb0_mux[] = {
3651 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3653 static const unsigned int usb0_ovc_vbus_pins[] = {
3657 static const unsigned int usb0_ovc_vbus_mux[] = {
3660 /* - USB1 ------------------------------------------------------------------- */
3661 static const unsigned int usb1_pins[] = {
3663 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3665 static const unsigned int usb1_mux[] = {
3666 USB1_PWEN_MARK, USB1_OVC_MARK,
3668 static const unsigned int usb1_pwen_pins[] = {
3672 static const unsigned int usb1_pwen_mux[] = {
3675 /* - USB2 ------------------------------------------------------------------- */
3676 static const unsigned int usb2_pins[] = {
3678 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3680 static const unsigned int usb2_mux[] = {
3681 USB2_PWEN_MARK, USB2_OVC_MARK,
3683 /* - VIN0 ------------------------------------------------------------------- */
3684 static const unsigned int vin0_data_pins[] = {
3686 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3687 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3688 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3689 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3691 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3692 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3693 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3694 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3696 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3697 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3698 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3699 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3701 static const unsigned int vin0_data_mux[] = {
3703 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3704 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3705 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3706 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3708 VI0_G0_MARK, VI0_G1_MARK,
3709 VI0_G2_MARK, VI0_G3_MARK,
3710 VI0_G4_MARK, VI0_G5_MARK,
3711 VI0_G6_MARK, VI0_G7_MARK,
3713 VI0_R0_MARK, VI0_R1_MARK,
3714 VI0_R2_MARK, VI0_R3_MARK,
3715 VI0_R4_MARK, VI0_R5_MARK,
3716 VI0_R6_MARK, VI0_R7_MARK,
3718 static const unsigned int vin0_data18_pins[] = {
3720 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3721 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3722 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3724 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3725 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3726 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3728 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3729 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3730 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3732 static const unsigned int vin0_data18_mux[] = {
3734 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3735 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3736 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3738 VI0_G2_MARK, VI0_G3_MARK,
3739 VI0_G4_MARK, VI0_G5_MARK,
3740 VI0_G6_MARK, VI0_G7_MARK,
3742 VI0_R2_MARK, VI0_R3_MARK,
3743 VI0_R4_MARK, VI0_R5_MARK,
3744 VI0_R6_MARK, VI0_R7_MARK,
3746 static const unsigned int vin0_sync_pins[] = {
3747 RCAR_GP_PIN(0, 12), /* HSYNC */
3748 RCAR_GP_PIN(0, 13), /* VSYNC */
3750 static const unsigned int vin0_sync_mux[] = {
3754 static const unsigned int vin0_field_pins[] = {
3757 static const unsigned int vin0_field_mux[] = {
3760 static const unsigned int vin0_clkenb_pins[] = {
3763 static const unsigned int vin0_clkenb_mux[] = {
3766 static const unsigned int vin0_clk_pins[] = {
3769 static const unsigned int vin0_clk_mux[] = {
3772 /* - VIN1 ------------------------------------------------------------------- */
3773 static const unsigned int vin1_data_pins[] = {
3775 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3776 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3777 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3778 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3780 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3781 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3782 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3783 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3785 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3786 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3787 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3788 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3790 static const unsigned int vin1_data_mux[] = {
3792 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3793 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3794 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3795 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3797 VI1_G0_MARK, VI1_G1_MARK,
3798 VI1_G2_MARK, VI1_G3_MARK,
3799 VI1_G4_MARK, VI1_G5_MARK,
3800 VI1_G6_MARK, VI1_G7_MARK,
3802 VI1_R0_MARK, VI1_R1_MARK,
3803 VI1_R2_MARK, VI1_R3_MARK,
3804 VI1_R4_MARK, VI1_R5_MARK,
3805 VI1_R6_MARK, VI1_R7_MARK,
3807 static const unsigned int vin1_data18_pins[] = {
3809 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3810 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3811 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3813 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3814 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3815 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3817 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3818 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3819 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3821 static const unsigned int vin1_data18_mux[] = {
3823 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3824 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3825 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3827 VI1_G2_MARK, VI1_G3_MARK,
3828 VI1_G4_MARK, VI1_G5_MARK,
3829 VI1_G6_MARK, VI1_G7_MARK,
3831 VI1_R2_MARK, VI1_R3_MARK,
3832 VI1_R4_MARK, VI1_R5_MARK,
3833 VI1_R6_MARK, VI1_R7_MARK,
3835 static const unsigned int vin1_data_b_pins[] = {
3837 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3838 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3839 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3840 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3842 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3843 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3844 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3845 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3847 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3848 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3849 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3850 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3852 static const unsigned int vin1_data_b_mux[] = {
3854 VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
3855 VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
3856 VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
3857 VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
3859 VI1_G0_B_MARK, VI1_G1_B_MARK,
3860 VI1_G2_B_MARK, VI1_G3_B_MARK,
3861 VI1_G4_B_MARK, VI1_G5_B_MARK,
3862 VI1_G6_B_MARK, VI1_G7_B_MARK,
3864 VI1_R0_B_MARK, VI1_R1_B_MARK,
3865 VI1_R2_B_MARK, VI1_R3_B_MARK,
3866 VI1_R4_B_MARK, VI1_R5_B_MARK,
3867 VI1_R6_B_MARK, VI1_R7_B_MARK,
3869 static const unsigned int vin1_data18_b_pins[] = {
3871 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3872 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3873 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3875 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3876 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3877 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3879 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3880 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3881 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3883 static const unsigned int vin1_data18_b_mux[] = {
3885 VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
3886 VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
3887 VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
3889 VI1_G2_B_MARK, VI1_G3_B_MARK,
3890 VI1_G4_B_MARK, VI1_G5_B_MARK,
3891 VI1_G6_B_MARK, VI1_G7_B_MARK,
3893 VI1_R2_B_MARK, VI1_R3_B_MARK,
3894 VI1_R4_B_MARK, VI1_R5_B_MARK,
3895 VI1_R6_B_MARK, VI1_R7_B_MARK,
3897 static const unsigned int vin1_sync_pins[] = {
3898 RCAR_GP_PIN(1, 24), /* HSYNC */
3899 RCAR_GP_PIN(1, 25), /* VSYNC */
3901 static const unsigned int vin1_sync_mux[] = {
3905 static const unsigned int vin1_sync_b_pins[] = {
3906 RCAR_GP_PIN(1, 24), /* HSYNC */
3907 RCAR_GP_PIN(1, 25), /* VSYNC */
3909 static const unsigned int vin1_sync_b_mux[] = {
3913 static const unsigned int vin1_field_pins[] = {
3916 static const unsigned int vin1_field_mux[] = {
3919 static const unsigned int vin1_field_b_pins[] = {
3922 static const unsigned int vin1_field_b_mux[] = {
3925 static const unsigned int vin1_clkenb_pins[] = {
3928 static const unsigned int vin1_clkenb_mux[] = {
3931 static const unsigned int vin1_clkenb_b_pins[] = {
3934 static const unsigned int vin1_clkenb_b_mux[] = {
3937 static const unsigned int vin1_clk_pins[] = {
3940 static const unsigned int vin1_clk_mux[] = {
3943 static const unsigned int vin1_clk_b_pins[] = {
3946 static const unsigned int vin1_clk_b_mux[] = {
3949 /* - VIN2 ----------------------------------------------------------------- */
3950 static const unsigned int vin2_data_pins[] = {
3952 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3953 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3954 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3955 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3957 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3958 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3959 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3960 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3962 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3963 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3964 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3965 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3967 static const unsigned int vin2_data_mux[] = {
3969 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3970 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3971 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3972 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3974 VI2_G0_MARK, VI2_G1_MARK,
3975 VI2_G2_MARK, VI2_G3_MARK,
3976 VI2_G4_MARK, VI2_G5_MARK,
3977 VI2_G6_MARK, VI2_G7_MARK,
3979 VI2_R0_MARK, VI2_R1_MARK,
3980 VI2_R2_MARK, VI2_R3_MARK,
3981 VI2_R4_MARK, VI2_R5_MARK,
3982 VI2_R6_MARK, VI2_R7_MARK,
3984 static const unsigned int vin2_data18_pins[] = {
3986 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3987 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3988 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3990 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3991 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3992 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3994 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3995 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3996 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3998 static const unsigned int vin2_data18_mux[] = {
4000 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
4001 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
4002 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
4004 VI2_G2_MARK, VI2_G3_MARK,
4005 VI2_G4_MARK, VI2_G5_MARK,
4006 VI2_G6_MARK, VI2_G7_MARK,
4008 VI2_R2_MARK, VI2_R3_MARK,
4009 VI2_R4_MARK, VI2_R5_MARK,
4010 VI2_R6_MARK, VI2_R7_MARK,
4012 static const unsigned int vin2_g8_pins[] = {
4013 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
4014 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
4015 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4016 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4018 static const unsigned int vin2_g8_mux[] = {
4019 VI2_G0_MARK, VI2_G1_MARK,
4020 VI2_G2_MARK, VI2_G3_MARK,
4021 VI2_G4_MARK, VI2_G5_MARK,
4022 VI2_G6_MARK, VI2_G7_MARK,
4024 static const unsigned int vin2_sync_pins[] = {
4025 RCAR_GP_PIN(1, 16), /* HSYNC */
4026 RCAR_GP_PIN(1, 21), /* VSYNC */
4028 static const unsigned int vin2_sync_mux[] = {
4032 static const unsigned int vin2_field_pins[] = {
4035 static const unsigned int vin2_field_mux[] = {
4038 static const unsigned int vin2_clkenb_pins[] = {
4041 static const unsigned int vin2_clkenb_mux[] = {
4044 static const unsigned int vin2_clk_pins[] = {
4047 static const unsigned int vin2_clk_mux[] = {
4050 /* - VIN3 ----------------------------------------------------------------- */
4051 static const unsigned int vin3_data8_pins[] = {
4052 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4053 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4054 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4055 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4057 static const unsigned int vin3_data8_mux[] = {
4058 VI3_DATA0_MARK, VI3_DATA1_MARK,
4059 VI3_DATA2_MARK, VI3_DATA3_MARK,
4060 VI3_DATA4_MARK, VI3_DATA5_MARK,
4061 VI3_DATA6_MARK, VI3_DATA7_MARK,
4063 static const unsigned int vin3_sync_pins[] = {
4064 RCAR_GP_PIN(1, 16), /* HSYNC */
4065 RCAR_GP_PIN(1, 17), /* VSYNC */
4067 static const unsigned int vin3_sync_mux[] = {
4071 static const unsigned int vin3_field_pins[] = {
4074 static const unsigned int vin3_field_mux[] = {
4077 static const unsigned int vin3_clkenb_pins[] = {
4080 static const unsigned int vin3_clkenb_mux[] = {
4083 static const unsigned int vin3_clk_pins[] = {
4086 static const unsigned int vin3_clk_mux[] = {
4090 static const struct {
4091 struct sh_pfc_pin_group common[311];
4092 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4093 struct sh_pfc_pin_group automotive[1];
4097 SH_PFC_PIN_GROUP(audio_clk_a),
4098 SH_PFC_PIN_GROUP(audio_clk_b),
4099 SH_PFC_PIN_GROUP(audio_clk_c),
4100 SH_PFC_PIN_GROUP(audio_clkout),
4101 SH_PFC_PIN_GROUP(audio_clkout_b),
4102 SH_PFC_PIN_GROUP(audio_clkout_c),
4103 SH_PFC_PIN_GROUP(audio_clkout_d),
4104 SH_PFC_PIN_GROUP(avb_link),
4105 SH_PFC_PIN_GROUP(avb_magic),
4106 SH_PFC_PIN_GROUP(avb_phy_int),
4107 SH_PFC_PIN_GROUP(avb_mdio),
4108 SH_PFC_PIN_GROUP(avb_mii),
4109 SH_PFC_PIN_GROUP(avb_gmii),
4110 SH_PFC_PIN_GROUP(can0_data),
4111 SH_PFC_PIN_GROUP(can0_data_b),
4112 SH_PFC_PIN_GROUP(can0_data_c),
4113 SH_PFC_PIN_GROUP(can0_data_d),
4114 SH_PFC_PIN_GROUP(can1_data),
4115 SH_PFC_PIN_GROUP(can1_data_b),
4116 SH_PFC_PIN_GROUP(can_clk),
4117 SH_PFC_PIN_GROUP(can_clk_b),
4118 SH_PFC_PIN_GROUP(du_rgb666),
4119 SH_PFC_PIN_GROUP(du_rgb888),
4120 SH_PFC_PIN_GROUP(du_clk_out_0),
4121 SH_PFC_PIN_GROUP(du_clk_out_1),
4122 SH_PFC_PIN_GROUP(du_sync_0),
4123 SH_PFC_PIN_GROUP(du_sync_1),
4124 SH_PFC_PIN_GROUP(du_cde),
4125 SH_PFC_PIN_GROUP(du0_clk_in),
4126 SH_PFC_PIN_GROUP(du1_clk_in),
4127 SH_PFC_PIN_GROUP(du2_clk_in),
4128 SH_PFC_PIN_GROUP(eth_link),
4129 SH_PFC_PIN_GROUP(eth_magic),
4130 SH_PFC_PIN_GROUP(eth_mdio),
4131 SH_PFC_PIN_GROUP(eth_rmii),
4132 SH_PFC_PIN_GROUP(hscif0_data),
4133 SH_PFC_PIN_GROUP(hscif0_clk),
4134 SH_PFC_PIN_GROUP(hscif0_ctrl),
4135 SH_PFC_PIN_GROUP(hscif0_data_b),
4136 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4137 SH_PFC_PIN_GROUP(hscif0_data_c),
4138 SH_PFC_PIN_GROUP(hscif0_ctrl_c),
4139 SH_PFC_PIN_GROUP(hscif0_data_d),
4140 SH_PFC_PIN_GROUP(hscif0_ctrl_d),
4141 SH_PFC_PIN_GROUP(hscif0_data_e),
4142 SH_PFC_PIN_GROUP(hscif0_ctrl_e),
4143 SH_PFC_PIN_GROUP(hscif0_data_f),
4144 SH_PFC_PIN_GROUP(hscif0_ctrl_f),
4145 SH_PFC_PIN_GROUP(hscif1_data),
4146 SH_PFC_PIN_GROUP(hscif1_clk),
4147 SH_PFC_PIN_GROUP(hscif1_ctrl),
4148 SH_PFC_PIN_GROUP(hscif1_data_b),
4149 SH_PFC_PIN_GROUP(hscif1_clk_b),
4150 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4151 SH_PFC_PIN_GROUP(i2c0),
4152 SH_PFC_PIN_GROUP(i2c1),
4153 SH_PFC_PIN_GROUP(i2c1_b),
4154 SH_PFC_PIN_GROUP(i2c1_c),
4155 SH_PFC_PIN_GROUP(i2c2),
4156 SH_PFC_PIN_GROUP(i2c2_b),
4157 SH_PFC_PIN_GROUP(i2c2_c),
4158 SH_PFC_PIN_GROUP(i2c2_d),
4159 SH_PFC_PIN_GROUP(i2c2_e),
4160 SH_PFC_PIN_GROUP(i2c3),
4161 SH_PFC_PIN_GROUP(iic0),
4162 SH_PFC_PIN_GROUP(iic1),
4163 SH_PFC_PIN_GROUP(iic1_b),
4164 SH_PFC_PIN_GROUP(iic1_c),
4165 SH_PFC_PIN_GROUP(iic2),
4166 SH_PFC_PIN_GROUP(iic2_b),
4167 SH_PFC_PIN_GROUP(iic2_c),
4168 SH_PFC_PIN_GROUP(iic2_d),
4169 SH_PFC_PIN_GROUP(iic2_e),
4170 SH_PFC_PIN_GROUP(iic3),
4171 SH_PFC_PIN_GROUP(intc_irq0),
4172 SH_PFC_PIN_GROUP(intc_irq1),
4173 SH_PFC_PIN_GROUP(intc_irq2),
4174 SH_PFC_PIN_GROUP(intc_irq3),
4175 BUS_DATA_PIN_GROUP(mmc0_data, 1),
4176 BUS_DATA_PIN_GROUP(mmc0_data, 4),
4177 BUS_DATA_PIN_GROUP(mmc0_data, 8),
4178 SH_PFC_PIN_GROUP(mmc0_ctrl),
4179 BUS_DATA_PIN_GROUP(mmc1_data, 1),
4180 BUS_DATA_PIN_GROUP(mmc1_data, 4),
4181 BUS_DATA_PIN_GROUP(mmc1_data, 8),
4182 SH_PFC_PIN_GROUP(mmc1_ctrl),
4183 SH_PFC_PIN_GROUP(msiof0_clk),
4184 SH_PFC_PIN_GROUP(msiof0_sync),
4185 SH_PFC_PIN_GROUP(msiof0_ss1),
4186 SH_PFC_PIN_GROUP(msiof0_ss2),
4187 SH_PFC_PIN_GROUP(msiof0_rx),
4188 SH_PFC_PIN_GROUP(msiof0_tx),
4189 SH_PFC_PIN_GROUP(msiof0_clk_b),
4190 SH_PFC_PIN_GROUP(msiof0_ss1_b),
4191 SH_PFC_PIN_GROUP(msiof0_ss2_b),
4192 SH_PFC_PIN_GROUP(msiof0_rx_b),
4193 SH_PFC_PIN_GROUP(msiof0_tx_b),
4194 SH_PFC_PIN_GROUP(msiof1_clk),
4195 SH_PFC_PIN_GROUP(msiof1_sync),
4196 SH_PFC_PIN_GROUP(msiof1_ss1),
4197 SH_PFC_PIN_GROUP(msiof1_ss2),
4198 SH_PFC_PIN_GROUP(msiof1_rx),
4199 SH_PFC_PIN_GROUP(msiof1_tx),
4200 SH_PFC_PIN_GROUP(msiof1_clk_b),
4201 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4202 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4203 SH_PFC_PIN_GROUP(msiof1_rx_b),
4204 SH_PFC_PIN_GROUP(msiof1_tx_b),
4205 SH_PFC_PIN_GROUP(msiof2_clk),
4206 SH_PFC_PIN_GROUP(msiof2_sync),
4207 SH_PFC_PIN_GROUP(msiof2_ss1),
4208 SH_PFC_PIN_GROUP(msiof2_ss2),
4209 SH_PFC_PIN_GROUP(msiof2_rx),
4210 SH_PFC_PIN_GROUP(msiof2_tx),
4211 SH_PFC_PIN_GROUP(msiof3_clk),
4212 SH_PFC_PIN_GROUP(msiof3_sync),
4213 SH_PFC_PIN_GROUP(msiof3_ss1),
4214 SH_PFC_PIN_GROUP(msiof3_ss2),
4215 SH_PFC_PIN_GROUP(msiof3_rx),
4216 SH_PFC_PIN_GROUP(msiof3_tx),
4217 SH_PFC_PIN_GROUP(msiof3_clk_b),
4218 SH_PFC_PIN_GROUP(msiof3_sync_b),
4219 SH_PFC_PIN_GROUP(msiof3_rx_b),
4220 SH_PFC_PIN_GROUP(msiof3_tx_b),
4221 SH_PFC_PIN_GROUP(pwm0),
4222 SH_PFC_PIN_GROUP(pwm0_b),
4223 SH_PFC_PIN_GROUP(pwm1),
4224 SH_PFC_PIN_GROUP(pwm1_b),
4225 SH_PFC_PIN_GROUP(pwm2),
4226 SH_PFC_PIN_GROUP(pwm3),
4227 SH_PFC_PIN_GROUP(pwm4),
4228 SH_PFC_PIN_GROUP(pwm5),
4229 SH_PFC_PIN_GROUP(pwm6),
4230 SH_PFC_PIN_GROUP(qspi_ctrl),
4231 SH_PFC_PIN_GROUP(qspi_data2),
4232 SH_PFC_PIN_GROUP(qspi_data4),
4233 SH_PFC_PIN_GROUP(scif0_data),
4234 SH_PFC_PIN_GROUP(scif0_clk),
4235 SH_PFC_PIN_GROUP(scif0_ctrl),
4236 SH_PFC_PIN_GROUP(scif0_data_b),
4237 SH_PFC_PIN_GROUP(scif1_data),
4238 SH_PFC_PIN_GROUP(scif1_clk),
4239 SH_PFC_PIN_GROUP(scif1_ctrl),
4240 SH_PFC_PIN_GROUP(scif1_data_b),
4241 SH_PFC_PIN_GROUP(scif1_data_c),
4242 SH_PFC_PIN_GROUP(scif1_data_d),
4243 SH_PFC_PIN_GROUP(scif1_clk_d),
4244 SH_PFC_PIN_GROUP(scif1_data_e),
4245 SH_PFC_PIN_GROUP(scif1_clk_e),
4246 SH_PFC_PIN_GROUP(scif2_data),
4247 SH_PFC_PIN_GROUP(scif2_clk),
4248 SH_PFC_PIN_GROUP(scif2_data_b),
4249 SH_PFC_PIN_GROUP(scifa0_data),
4250 SH_PFC_PIN_GROUP(scifa0_clk),
4251 SH_PFC_PIN_GROUP(scifa0_ctrl),
4252 SH_PFC_PIN_GROUP(scifa0_data_b),
4253 SH_PFC_PIN_GROUP(scifa0_clk_b),
4254 SH_PFC_PIN_GROUP(scifa0_ctrl_b),
4255 SH_PFC_PIN_GROUP(scifa1_data),
4256 SH_PFC_PIN_GROUP(scifa1_clk),
4257 SH_PFC_PIN_GROUP(scifa1_ctrl),
4258 SH_PFC_PIN_GROUP(scifa1_data_b),
4259 SH_PFC_PIN_GROUP(scifa1_clk_b),
4260 SH_PFC_PIN_GROUP(scifa1_ctrl_b),
4261 SH_PFC_PIN_GROUP(scifa1_data_c),
4262 SH_PFC_PIN_GROUP(scifa1_clk_c),
4263 SH_PFC_PIN_GROUP(scifa1_ctrl_c),
4264 SH_PFC_PIN_GROUP(scifa1_data_d),
4265 SH_PFC_PIN_GROUP(scifa1_clk_d),
4266 SH_PFC_PIN_GROUP(scifa1_ctrl_d),
4267 SH_PFC_PIN_GROUP(scifa2_data),
4268 SH_PFC_PIN_GROUP(scifa2_clk),
4269 SH_PFC_PIN_GROUP(scifa2_ctrl),
4270 SH_PFC_PIN_GROUP(scifa2_data_b),
4271 SH_PFC_PIN_GROUP(scifa2_data_c),
4272 SH_PFC_PIN_GROUP(scifa2_clk_c),
4273 SH_PFC_PIN_GROUP(scifb0_data),
4274 SH_PFC_PIN_GROUP(scifb0_clk),
4275 SH_PFC_PIN_GROUP(scifb0_ctrl),
4276 SH_PFC_PIN_GROUP(scifb0_data_b),
4277 SH_PFC_PIN_GROUP(scifb0_clk_b),
4278 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4279 SH_PFC_PIN_GROUP(scifb0_data_c),
4280 SH_PFC_PIN_GROUP(scifb1_data),
4281 SH_PFC_PIN_GROUP(scifb1_clk),
4282 SH_PFC_PIN_GROUP(scifb1_ctrl),
4283 SH_PFC_PIN_GROUP(scifb1_data_b),
4284 SH_PFC_PIN_GROUP(scifb1_clk_b),
4285 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
4286 SH_PFC_PIN_GROUP(scifb1_data_c),
4287 SH_PFC_PIN_GROUP(scifb1_data_d),
4288 SH_PFC_PIN_GROUP(scifb1_data_e),
4289 SH_PFC_PIN_GROUP(scifb1_clk_e),
4290 SH_PFC_PIN_GROUP(scifb1_data_f),
4291 SH_PFC_PIN_GROUP(scifb1_data_g),
4292 SH_PFC_PIN_GROUP(scifb1_clk_g),
4293 SH_PFC_PIN_GROUP(scifb2_data),
4294 SH_PFC_PIN_GROUP(scifb2_clk),
4295 SH_PFC_PIN_GROUP(scifb2_ctrl),
4296 SH_PFC_PIN_GROUP(scifb2_data_b),
4297 SH_PFC_PIN_GROUP(scifb2_clk_b),
4298 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4299 SH_PFC_PIN_GROUP(scifb2_data_c),
4300 SH_PFC_PIN_GROUP(scif_clk),
4301 SH_PFC_PIN_GROUP(scif_clk_b),
4302 SH_PFC_PIN_GROUP(sdhi0_data1),
4303 SH_PFC_PIN_GROUP(sdhi0_data4),
4304 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4305 SH_PFC_PIN_GROUP(sdhi0_cd),
4306 SH_PFC_PIN_GROUP(sdhi0_wp),
4307 SH_PFC_PIN_GROUP(sdhi1_data1),
4308 SH_PFC_PIN_GROUP(sdhi1_data4),
4309 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4310 SH_PFC_PIN_GROUP(sdhi1_cd),
4311 SH_PFC_PIN_GROUP(sdhi1_wp),
4312 SH_PFC_PIN_GROUP(sdhi2_data1),
4313 SH_PFC_PIN_GROUP(sdhi2_data4),
4314 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4315 SH_PFC_PIN_GROUP(sdhi2_cd),
4316 SH_PFC_PIN_GROUP(sdhi2_wp),
4317 SH_PFC_PIN_GROUP(sdhi3_data1),
4318 SH_PFC_PIN_GROUP(sdhi3_data4),
4319 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4320 SH_PFC_PIN_GROUP(sdhi3_cd),
4321 SH_PFC_PIN_GROUP(sdhi3_wp),
4322 SH_PFC_PIN_GROUP(ssi0_data),
4323 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4324 SH_PFC_PIN_GROUP(ssi1_data),
4325 SH_PFC_PIN_GROUP(ssi1_ctrl),
4326 SH_PFC_PIN_GROUP(ssi2_data),
4327 SH_PFC_PIN_GROUP(ssi2_ctrl),
4328 SH_PFC_PIN_GROUP(ssi3_data),
4329 SH_PFC_PIN_GROUP(ssi34_ctrl),
4330 SH_PFC_PIN_GROUP(ssi4_data),
4331 SH_PFC_PIN_GROUP(ssi4_ctrl),
4332 SH_PFC_PIN_GROUP(ssi5),
4333 SH_PFC_PIN_GROUP(ssi5_b),
4334 SH_PFC_PIN_GROUP(ssi5_c),
4335 SH_PFC_PIN_GROUP(ssi6),
4336 SH_PFC_PIN_GROUP(ssi6_b),
4337 SH_PFC_PIN_GROUP(ssi7_data),
4338 SH_PFC_PIN_GROUP(ssi7_b_data),
4339 SH_PFC_PIN_GROUP(ssi7_c_data),
4340 SH_PFC_PIN_GROUP(ssi78_ctrl),
4341 SH_PFC_PIN_GROUP(ssi78_b_ctrl),
4342 SH_PFC_PIN_GROUP(ssi78_c_ctrl),
4343 SH_PFC_PIN_GROUP(ssi8_data),
4344 SH_PFC_PIN_GROUP(ssi8_b_data),
4345 SH_PFC_PIN_GROUP(ssi8_c_data),
4346 SH_PFC_PIN_GROUP(ssi9_data),
4347 SH_PFC_PIN_GROUP(ssi9_ctrl),
4348 SH_PFC_PIN_GROUP(tpu0_to0),
4349 SH_PFC_PIN_GROUP(tpu0_to1),
4350 SH_PFC_PIN_GROUP(tpu0_to2),
4351 SH_PFC_PIN_GROUP(tpu0_to3),
4352 SH_PFC_PIN_GROUP(usb0),
4353 SH_PFC_PIN_GROUP(usb0_ovc_vbus),
4354 SH_PFC_PIN_GROUP(usb1),
4355 SH_PFC_PIN_GROUP(usb1_pwen),
4356 SH_PFC_PIN_GROUP(usb2),
4357 BUS_DATA_PIN_GROUP(vin0_data, 24),
4358 BUS_DATA_PIN_GROUP(vin0_data, 20),
4359 SH_PFC_PIN_GROUP(vin0_data18),
4360 BUS_DATA_PIN_GROUP(vin0_data, 16),
4361 BUS_DATA_PIN_GROUP(vin0_data, 12),
4362 BUS_DATA_PIN_GROUP(vin0_data, 10),
4363 BUS_DATA_PIN_GROUP(vin0_data, 8),
4364 BUS_DATA_PIN_GROUP(vin0_data, 4),
4365 SH_PFC_PIN_GROUP(vin0_sync),
4366 SH_PFC_PIN_GROUP(vin0_field),
4367 SH_PFC_PIN_GROUP(vin0_clkenb),
4368 SH_PFC_PIN_GROUP(vin0_clk),
4369 BUS_DATA_PIN_GROUP(vin1_data, 24),
4370 BUS_DATA_PIN_GROUP(vin1_data, 20),
4371 SH_PFC_PIN_GROUP(vin1_data18),
4372 BUS_DATA_PIN_GROUP(vin1_data, 16),
4373 BUS_DATA_PIN_GROUP(vin1_data, 12),
4374 BUS_DATA_PIN_GROUP(vin1_data, 10),
4375 BUS_DATA_PIN_GROUP(vin1_data, 8),
4376 BUS_DATA_PIN_GROUP(vin1_data, 4),
4377 BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
4378 BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
4379 SH_PFC_PIN_GROUP(vin1_data18_b),
4380 BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
4381 BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
4382 BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
4383 BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
4384 BUS_DATA_PIN_GROUP(vin1_data, 4, _b),
4385 SH_PFC_PIN_GROUP(vin1_sync),
4386 SH_PFC_PIN_GROUP(vin1_sync_b),
4387 SH_PFC_PIN_GROUP(vin1_field),
4388 SH_PFC_PIN_GROUP(vin1_field_b),
4389 SH_PFC_PIN_GROUP(vin1_clkenb),
4390 SH_PFC_PIN_GROUP(vin1_clkenb_b),
4391 SH_PFC_PIN_GROUP(vin1_clk),
4392 SH_PFC_PIN_GROUP(vin1_clk_b),
4393 BUS_DATA_PIN_GROUP(vin2_data, 24),
4394 SH_PFC_PIN_GROUP(vin2_data18),
4395 BUS_DATA_PIN_GROUP(vin2_data, 16),
4396 BUS_DATA_PIN_GROUP(vin2_data, 8),
4397 BUS_DATA_PIN_GROUP(vin2_data, 4),
4398 SH_PFC_PIN_GROUP(vin2_g8),
4399 SH_PFC_PIN_GROUP(vin2_sync),
4400 SH_PFC_PIN_GROUP(vin2_field),
4401 SH_PFC_PIN_GROUP(vin2_clkenb),
4402 SH_PFC_PIN_GROUP(vin2_clk),
4403 SH_PFC_PIN_GROUP(vin3_data8),
4404 SH_PFC_PIN_GROUP(vin3_sync),
4405 SH_PFC_PIN_GROUP(vin3_field),
4406 SH_PFC_PIN_GROUP(vin3_clkenb),
4407 SH_PFC_PIN_GROUP(vin3_clk),
4409 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4411 SH_PFC_PIN_GROUP(mlb_3pin),
4413 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
4416 static const char * const audio_clk_groups[] = {
4426 static const char * const avb_groups[] = {
4435 static const char * const can0_groups[] = {
4442 static const char * const can1_groups[] = {
4447 static const char * const can_clk_groups[] = {
4452 static const char * const du_groups[] = {
4462 static const char * const du0_groups[] = {
4466 static const char * const du1_groups[] = {
4470 static const char * const du2_groups[] = {
4474 static const char * const eth_groups[] = {
4481 static const char * const hscif0_groups[] = {
4497 static const char * const hscif1_groups[] = {
4506 static const char * const i2c0_groups[] = {
4510 static const char * const i2c1_groups[] = {
4516 static const char * const i2c2_groups[] = {
4524 static const char * const i2c3_groups[] = {
4528 static const char * const iic0_groups[] = {
4532 static const char * const iic1_groups[] = {
4538 static const char * const iic2_groups[] = {
4546 static const char * const iic3_groups[] = {
4550 static const char * const intc_groups[] = {
4557 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4558 static const char * const mlb_groups[] = {
4561 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
4563 static const char * const mmc0_groups[] = {
4570 static const char * const mmc1_groups[] = {
4577 static const char * const msiof0_groups[] = {
4591 static const char * const msiof1_groups[] = {
4605 static const char * const msiof2_groups[] = {
4614 static const char * const msiof3_groups[] = {
4627 static const char * const pwm0_groups[] = {
4632 static const char * const pwm1_groups[] = {
4637 static const char * const pwm2_groups[] = {
4641 static const char * const pwm3_groups[] = {
4645 static const char * const pwm4_groups[] = {
4649 static const char * const pwm5_groups[] = {
4653 static const char * const pwm6_groups[] = {
4657 static const char * const qspi_groups[] = {
4663 static const char * const scif0_groups[] = {
4670 static const char * const scif1_groups[] = {
4682 static const char * const scif2_groups[] = {
4688 static const char * const scifa0_groups[] = {
4697 static const char * const scifa1_groups[] = {
4712 static const char * const scifa2_groups[] = {
4721 static const char * const scifb0_groups[] = {
4731 static const char * const scifb1_groups[] = {
4747 static const char * const scifb2_groups[] = {
4757 static const char * const scif_clk_groups[] = {
4762 static const char * const sdhi0_groups[] = {
4770 static const char * const sdhi1_groups[] = {
4778 static const char * const sdhi2_groups[] = {
4786 static const char * const sdhi3_groups[] = {
4794 static const char * const ssi_groups[] = {
4823 static const char * const tpu0_groups[] = {
4830 static const char * const usb0_groups[] = {
4835 static const char * const usb1_groups[] = {
4840 static const char * const usb2_groups[] = {
4844 static const char * const vin0_groups[] = {
4859 static const char * const vin1_groups[] = {
4886 static const char * const vin2_groups[] = {
4899 static const char * const vin3_groups[] = {
4907 static const struct {
4908 struct sh_pfc_function common[58];
4909 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4910 struct sh_pfc_function automotive[1];
4912 } pinmux_functions = {
4914 SH_PFC_FUNCTION(audio_clk),
4915 SH_PFC_FUNCTION(avb),
4916 SH_PFC_FUNCTION(can0),
4917 SH_PFC_FUNCTION(can1),
4918 SH_PFC_FUNCTION(can_clk),
4919 SH_PFC_FUNCTION(du),
4920 SH_PFC_FUNCTION(du0),
4921 SH_PFC_FUNCTION(du1),
4922 SH_PFC_FUNCTION(du2),
4923 SH_PFC_FUNCTION(eth),
4924 SH_PFC_FUNCTION(hscif0),
4925 SH_PFC_FUNCTION(hscif1),
4926 SH_PFC_FUNCTION(i2c0),
4927 SH_PFC_FUNCTION(i2c1),
4928 SH_PFC_FUNCTION(i2c2),
4929 SH_PFC_FUNCTION(i2c3),
4930 SH_PFC_FUNCTION(iic0),
4931 SH_PFC_FUNCTION(iic1),
4932 SH_PFC_FUNCTION(iic2),
4933 SH_PFC_FUNCTION(iic3),
4934 SH_PFC_FUNCTION(intc),
4935 SH_PFC_FUNCTION(mmc0),
4936 SH_PFC_FUNCTION(mmc1),
4937 SH_PFC_FUNCTION(msiof0),
4938 SH_PFC_FUNCTION(msiof1),
4939 SH_PFC_FUNCTION(msiof2),
4940 SH_PFC_FUNCTION(msiof3),
4941 SH_PFC_FUNCTION(pwm0),
4942 SH_PFC_FUNCTION(pwm1),
4943 SH_PFC_FUNCTION(pwm2),
4944 SH_PFC_FUNCTION(pwm3),
4945 SH_PFC_FUNCTION(pwm4),
4946 SH_PFC_FUNCTION(pwm5),
4947 SH_PFC_FUNCTION(pwm6),
4948 SH_PFC_FUNCTION(qspi),
4949 SH_PFC_FUNCTION(scif0),
4950 SH_PFC_FUNCTION(scif1),
4951 SH_PFC_FUNCTION(scif2),
4952 SH_PFC_FUNCTION(scifa0),
4953 SH_PFC_FUNCTION(scifa1),
4954 SH_PFC_FUNCTION(scifa2),
4955 SH_PFC_FUNCTION(scifb0),
4956 SH_PFC_FUNCTION(scifb1),
4957 SH_PFC_FUNCTION(scifb2),
4958 SH_PFC_FUNCTION(scif_clk),
4959 SH_PFC_FUNCTION(sdhi0),
4960 SH_PFC_FUNCTION(sdhi1),
4961 SH_PFC_FUNCTION(sdhi2),
4962 SH_PFC_FUNCTION(sdhi3),
4963 SH_PFC_FUNCTION(ssi),
4964 SH_PFC_FUNCTION(tpu0),
4965 SH_PFC_FUNCTION(usb0),
4966 SH_PFC_FUNCTION(usb1),
4967 SH_PFC_FUNCTION(usb2),
4968 SH_PFC_FUNCTION(vin0),
4969 SH_PFC_FUNCTION(vin1),
4970 SH_PFC_FUNCTION(vin2),
4971 SH_PFC_FUNCTION(vin3),
4973 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4975 SH_PFC_FUNCTION(mlb),
4977 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
4980 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4981 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
4982 GP_0_31_FN, FN_IP3_17_15,
4983 GP_0_30_FN, FN_IP3_14_12,
4984 GP_0_29_FN, FN_IP3_11_8,
4985 GP_0_28_FN, FN_IP3_7_4,
4986 GP_0_27_FN, FN_IP3_3_0,
4987 GP_0_26_FN, FN_IP2_28_26,
4988 GP_0_25_FN, FN_IP2_25_22,
4989 GP_0_24_FN, FN_IP2_21_18,
4990 GP_0_23_FN, FN_IP2_17_15,
4991 GP_0_22_FN, FN_IP2_14_12,
4992 GP_0_21_FN, FN_IP2_11_9,
4993 GP_0_20_FN, FN_IP2_8_6,
4994 GP_0_19_FN, FN_IP2_5_3,
4995 GP_0_18_FN, FN_IP2_2_0,
4996 GP_0_17_FN, FN_IP1_29_28,
4997 GP_0_16_FN, FN_IP1_27_26,
4998 GP_0_15_FN, FN_IP1_25_22,
4999 GP_0_14_FN, FN_IP1_21_18,
5000 GP_0_13_FN, FN_IP1_17_15,
5001 GP_0_12_FN, FN_IP1_14_12,
5002 GP_0_11_FN, FN_IP1_11_8,
5003 GP_0_10_FN, FN_IP1_7_4,
5004 GP_0_9_FN, FN_IP1_3_0,
5005 GP_0_8_FN, FN_IP0_30_27,
5006 GP_0_7_FN, FN_IP0_26_23,
5007 GP_0_6_FN, FN_IP0_22_20,
5008 GP_0_5_FN, FN_IP0_19_16,
5009 GP_0_4_FN, FN_IP0_15_12,
5010 GP_0_3_FN, FN_IP0_11_9,
5011 GP_0_2_FN, FN_IP0_8_6,
5012 GP_0_1_FN, FN_IP0_5_3,
5013 GP_0_0_FN, FN_IP0_2_0 ))
5015 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
5018 GP_1_29_FN, FN_IP6_13_11,
5019 GP_1_28_FN, FN_IP6_10_9,
5020 GP_1_27_FN, FN_IP6_8_6,
5021 GP_1_26_FN, FN_IP6_5_3,
5022 GP_1_25_FN, FN_IP6_2_0,
5023 GP_1_24_FN, FN_IP5_29_27,
5024 GP_1_23_FN, FN_IP5_26_24,
5025 GP_1_22_FN, FN_IP5_23_21,
5026 GP_1_21_FN, FN_IP5_20_18,
5027 GP_1_20_FN, FN_IP5_17_15,
5028 GP_1_19_FN, FN_IP5_14_13,
5029 GP_1_18_FN, FN_IP5_12_10,
5030 GP_1_17_FN, FN_IP5_9_6,
5031 GP_1_16_FN, FN_IP5_5_3,
5032 GP_1_15_FN, FN_IP5_2_0,
5033 GP_1_14_FN, FN_IP4_29_27,
5034 GP_1_13_FN, FN_IP4_26_24,
5035 GP_1_12_FN, FN_IP4_23_21,
5036 GP_1_11_FN, FN_IP4_20_18,
5037 GP_1_10_FN, FN_IP4_17_15,
5038 GP_1_9_FN, FN_IP4_14_12,
5039 GP_1_8_FN, FN_IP4_11_9,
5040 GP_1_7_FN, FN_IP4_8_6,
5041 GP_1_6_FN, FN_IP4_5_3,
5042 GP_1_5_FN, FN_IP4_2_0,
5043 GP_1_4_FN, FN_IP3_31_29,
5044 GP_1_3_FN, FN_IP3_28_26,
5045 GP_1_2_FN, FN_IP3_25_23,
5046 GP_1_1_FN, FN_IP3_22_20,
5047 GP_1_0_FN, FN_IP3_19_18, ))
5049 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
5052 GP_2_29_FN, FN_IP7_15_13,
5053 GP_2_28_FN, FN_IP7_12_10,
5054 GP_2_27_FN, FN_IP7_9_8,
5055 GP_2_26_FN, FN_IP7_7_6,
5056 GP_2_25_FN, FN_IP7_5_3,
5057 GP_2_24_FN, FN_IP7_2_0,
5058 GP_2_23_FN, FN_IP6_31_29,
5059 GP_2_22_FN, FN_IP6_28_26,
5060 GP_2_21_FN, FN_IP6_25_23,
5061 GP_2_20_FN, FN_IP6_22_20,
5062 GP_2_19_FN, FN_IP6_19_17,
5063 GP_2_18_FN, FN_IP6_16_14,
5064 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
5065 GP_2_16_FN, FN_IP8_27,
5066 GP_2_15_FN, FN_IP8_26,
5067 GP_2_14_FN, FN_IP8_25_24,
5068 GP_2_13_FN, FN_IP8_23_22,
5069 GP_2_12_FN, FN_IP8_21_20,
5070 GP_2_11_FN, FN_IP8_19_18,
5071 GP_2_10_FN, FN_IP8_17_16,
5072 GP_2_9_FN, FN_IP8_15_14,
5073 GP_2_8_FN, FN_IP8_13_12,
5074 GP_2_7_FN, FN_IP8_11_10,
5075 GP_2_6_FN, FN_IP8_9_8,
5076 GP_2_5_FN, FN_IP8_7_6,
5077 GP_2_4_FN, FN_IP8_5_4,
5078 GP_2_3_FN, FN_IP8_3_2,
5079 GP_2_2_FN, FN_IP8_1_0,
5080 GP_2_1_FN, FN_IP7_30_29,
5081 GP_2_0_FN, FN_IP7_28_27 ))
5083 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
5084 GP_3_31_FN, FN_IP11_21_18,
5085 GP_3_30_FN, FN_IP11_17_15,
5086 GP_3_29_FN, FN_IP11_14_13,
5087 GP_3_28_FN, FN_IP11_12_11,
5088 GP_3_27_FN, FN_IP11_10_9,
5089 GP_3_26_FN, FN_IP11_8_7,
5090 GP_3_25_FN, FN_IP11_6_5,
5091 GP_3_24_FN, FN_IP11_4,
5092 GP_3_23_FN, FN_IP11_3_0,
5093 GP_3_22_FN, FN_IP10_29_26,
5094 GP_3_21_FN, FN_IP10_25_23,
5095 GP_3_20_FN, FN_IP10_22_19,
5096 GP_3_19_FN, FN_IP10_18_15,
5097 GP_3_18_FN, FN_IP10_14_11,
5098 GP_3_17_FN, FN_IP10_10_7,
5099 GP_3_16_FN, FN_IP10_6_4,
5100 GP_3_15_FN, FN_IP10_3_0,
5101 GP_3_14_FN, FN_IP9_31_28,
5102 GP_3_13_FN, FN_IP9_27_26,
5103 GP_3_12_FN, FN_IP9_25_24,
5104 GP_3_11_FN, FN_IP9_23_22,
5105 GP_3_10_FN, FN_IP9_21_20,
5106 GP_3_9_FN, FN_IP9_19_18,
5107 GP_3_8_FN, FN_IP9_17_16,
5108 GP_3_7_FN, FN_IP9_15_12,
5109 GP_3_6_FN, FN_IP9_11_8,
5110 GP_3_5_FN, FN_IP9_7_6,
5111 GP_3_4_FN, FN_IP9_5_4,
5112 GP_3_3_FN, FN_IP9_3_2,
5113 GP_3_2_FN, FN_IP9_1_0,
5114 GP_3_1_FN, FN_IP8_30_29,
5115 GP_3_0_FN, FN_IP8_28 ))
5117 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
5118 GP_4_31_FN, FN_IP14_18_16,
5119 GP_4_30_FN, FN_IP14_15_12,
5120 GP_4_29_FN, FN_IP14_11_9,
5121 GP_4_28_FN, FN_IP14_8_6,
5122 GP_4_27_FN, FN_IP14_5_3,
5123 GP_4_26_FN, FN_IP14_2_0,
5124 GP_4_25_FN, FN_IP13_30_29,
5125 GP_4_24_FN, FN_IP13_28_26,
5126 GP_4_23_FN, FN_IP13_25_23,
5127 GP_4_22_FN, FN_IP13_22_19,
5128 GP_4_21_FN, FN_IP13_18_16,
5129 GP_4_20_FN, FN_IP13_15_13,
5130 GP_4_19_FN, FN_IP13_12_10,
5131 GP_4_18_FN, FN_IP13_9_7,
5132 GP_4_17_FN, FN_IP13_6_3,
5133 GP_4_16_FN, FN_IP13_2_0,
5134 GP_4_15_FN, FN_IP12_30_28,
5135 GP_4_14_FN, FN_IP12_27_25,
5136 GP_4_13_FN, FN_IP12_24_23,
5137 GP_4_12_FN, FN_IP12_22_20,
5138 GP_4_11_FN, FN_IP12_19_17,
5139 GP_4_10_FN, FN_IP12_16_14,
5140 GP_4_9_FN, FN_IP12_13_11,
5141 GP_4_8_FN, FN_IP12_10_8,
5142 GP_4_7_FN, FN_IP12_7_6,
5143 GP_4_6_FN, FN_IP12_5_4,
5144 GP_4_5_FN, FN_IP12_3_2,
5145 GP_4_4_FN, FN_IP12_1_0,
5146 GP_4_3_FN, FN_IP11_31_30,
5147 GP_4_2_FN, FN_IP11_29_27,
5148 GP_4_1_FN, FN_IP11_26_24,
5149 GP_4_0_FN, FN_IP11_23_22 ))
5151 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
5152 GP_5_31_FN, FN_IP7_24_22,
5153 GP_5_30_FN, FN_IP7_21_19,
5154 GP_5_29_FN, FN_IP7_18_16,
5155 GP_5_28_FN, FN_DU_DOTCLKIN2,
5156 GP_5_27_FN, FN_IP7_26_25,
5157 GP_5_26_FN, FN_DU_DOTCLKIN0,
5158 GP_5_25_FN, FN_AVS2,
5159 GP_5_24_FN, FN_AVS1,
5160 GP_5_23_FN, FN_USB2_OVC,
5161 GP_5_22_FN, FN_USB2_PWEN,
5162 GP_5_21_FN, FN_IP16_7,
5163 GP_5_20_FN, FN_IP16_6,
5164 GP_5_19_FN, FN_USB0_OVC_VBUS,
5165 GP_5_18_FN, FN_USB0_PWEN,
5166 GP_5_17_FN, FN_IP16_5_3,
5167 GP_5_16_FN, FN_IP16_2_0,
5168 GP_5_15_FN, FN_IP15_29_28,
5169 GP_5_14_FN, FN_IP15_27_26,
5170 GP_5_13_FN, FN_IP15_25_23,
5171 GP_5_12_FN, FN_IP15_22_20,
5172 GP_5_11_FN, FN_IP15_19_18,
5173 GP_5_10_FN, FN_IP15_17_16,
5174 GP_5_9_FN, FN_IP15_15_14,
5175 GP_5_8_FN, FN_IP15_13_12,
5176 GP_5_7_FN, FN_IP15_11_9,
5177 GP_5_6_FN, FN_IP15_8_6,
5178 GP_5_5_FN, FN_IP15_5_3,
5179 GP_5_4_FN, FN_IP15_2_0,
5180 GP_5_3_FN, FN_IP14_30_28,
5181 GP_5_2_FN, FN_IP14_27_25,
5182 GP_5_1_FN, FN_IP14_24_22,
5183 GP_5_0_FN, FN_IP14_21_19 ))
5185 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5186 GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
5191 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
5192 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
5193 0, 0, 0, 0, 0, 0, 0, 0, 0,
5195 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
5196 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
5197 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
5199 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
5200 FN_I2C2_SCL_C, 0, 0,
5202 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
5203 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
5204 0, 0, 0, 0, 0, 0, 0, 0, 0,
5206 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
5207 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
5208 0, 0, 0, 0, 0, 0, 0, 0, 0,
5210 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
5213 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
5216 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
5219 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
5222 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5223 GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
5228 FN_A1, FN_PWM4, 0, 0,
5230 FN_A0, FN_PWM3, 0, 0,
5232 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
5233 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
5234 0, 0, 0, 0, 0, 0, 0, 0, 0,
5236 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
5237 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
5238 0, 0, 0, 0, 0, 0, 0, 0, 0,
5240 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
5241 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
5244 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
5245 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
5248 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
5249 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
5250 0, 0, 0, 0, 0, 0, 0, 0, 0,
5252 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
5253 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
5254 0, 0, 0, 0, 0, 0, 0, 0, 0,
5256 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
5257 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
5258 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
5260 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5261 GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
5264 0, 0, 0, 0, 0, 0, 0, 0,
5266 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
5267 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
5269 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
5270 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
5271 0, 0, 0, 0, 0, 0, 0, 0,
5273 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
5274 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
5275 0, 0, 0, 0, 0, 0, 0, 0,
5277 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
5280 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
5282 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
5284 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
5286 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
5288 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, ))
5290 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5291 GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4),
5294 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
5297 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
5300 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
5302 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
5304 FN_A16, FN_ATAWR1_N, 0, 0,
5306 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
5309 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
5312 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
5313 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
5314 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
5316 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
5317 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
5318 0, 0, 0, 0, 0, 0, 0, 0, 0,
5320 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
5321 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
5322 0, 0, 0, 0, 0, 0, 0, 0, ))
5324 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5325 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5330 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
5331 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
5333 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
5334 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
5336 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
5337 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
5339 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
5340 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
5342 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
5345 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
5346 FN_VI2_FIELD_B, 0, 0,
5348 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
5349 FN_VI2_CLKENB_B, 0, 0,
5351 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
5353 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
5355 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
5358 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5359 GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
5364 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
5365 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
5367 FN_EX_WAIT0, FN_IRQ3, 0, FN_VI3_CLK, FN_SCIFA0_RTS_N_B,
5368 FN_HRX0_B, FN_MSIOF0_SCK_B, 0,
5370 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
5371 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
5373 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
5374 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
5376 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
5379 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
5381 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
5384 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
5385 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
5386 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
5388 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
5389 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
5390 FN_INTC_EN0_N, FN_I2C1_SCL,
5392 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
5395 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5396 GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3),
5399 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
5400 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
5402 FN_ETH_LINK, 0, FN_HTX0_E,
5403 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
5405 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
5406 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
5408 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
5409 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
5411 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
5412 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
5414 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
5415 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
5418 FN_DACK2, FN_IRQ2, 0, FN_SSI_SDATA6_B, FN_HRTS0_N_B,
5419 FN_MSIOF0_RXD_B, 0, 0,
5421 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
5423 FN_DACK1, FN_IRQ1, 0, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 0, 0, 0,
5425 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
5426 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
5428 FN_DACK0, FN_IRQ0, 0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N,
5429 FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
5431 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5432 GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
5437 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
5439 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
5441 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
5443 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
5446 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
5447 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
5449 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
5450 FN_GLO_SS_C, 0, 0, 0,
5452 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
5453 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
5455 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
5456 FN_GLO_SCLK_C, 0, 0, 0,
5458 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
5460 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
5462 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
5464 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
5465 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
5467 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5468 GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
5474 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
5476 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
5478 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
5480 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
5482 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
5485 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
5487 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
5489 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
5491 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
5493 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
5495 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
5497 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
5499 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
5501 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
5503 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
5505 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
5507 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, ))
5509 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5510 GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2),
5513 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
5514 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
5515 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
5517 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
5519 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
5521 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
5523 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
5525 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
5527 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
5529 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
5530 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
5531 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
5533 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
5534 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
5535 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
5537 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
5539 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
5541 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
5543 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
5545 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5546 GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
5548 /* IP10_31_30 [2] */
5550 /* IP10_29_26 [4] */
5551 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
5552 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
5553 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
5554 /* IP10_25_23 [3] */
5555 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
5556 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
5557 /* IP10_22_19 [4] */
5558 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
5559 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
5560 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
5561 /* IP10_18_15 [4] */
5562 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
5563 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
5564 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
5566 /* IP10_14_11 [4] */
5567 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
5568 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
5569 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
5570 0, 0, 0, 0, 0, 0, 0,
5572 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
5573 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
5574 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
5575 0, 0, 0, 0, 0, 0, 0,
5577 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
5578 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
5581 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
5582 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
5583 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, ))
5585 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5586 GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4),
5588 /* IP11_31_30 [2] */
5589 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5590 /* IP11_29_27 [3] */
5591 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
5593 /* IP11_26_24 [3] */
5594 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
5596 /* IP11_23_22 [2] */
5597 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
5598 /* IP11_21_18 [4] */
5599 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
5600 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
5601 /* IP11_17_15 [3] */
5602 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
5603 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
5604 /* IP11_14_13 [2] */
5605 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
5606 /* IP11_12_11 [2] */
5607 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
5609 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
5611 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
5613 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
5615 FN_SD3_CLK, FN_MMC1_CLK,
5617 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
5618 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
5619 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
5621 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5622 GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
5626 /* IP12_30_28 [3] */
5627 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
5628 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
5629 FN_CAN_DEBUGOUT4, 0, 0,
5630 /* IP12_27_25 [3] */
5631 FN_SSI_SCK5, FN_SCIFB1_SCK,
5632 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
5633 FN_CAN_DEBUGOUT3, 0, 0,
5634 /* IP12_24_23 [2] */
5635 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
5637 /* IP12_22_20 [3] */
5638 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
5639 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
5640 /* IP12_19_17 [3] */
5641 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
5642 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
5643 /* IP12_16_14 [3] */
5644 FN_SSI_SDATA3, FN_STP_ISCLK_0,
5645 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
5646 /* IP12_13_11 [3] */
5647 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
5648 FN_CAN_STEP0, 0, 0, 0,
5650 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
5651 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
5653 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
5655 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
5657 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5659 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
5661 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5662 GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
5666 /* IP13_30_29 [2] */
5667 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
5668 /* IP13_28_26 [3] */
5669 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
5670 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
5671 /* IP13_25_23 [3] */
5672 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
5673 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
5674 /* IP13_22_19 [4] */
5675 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
5676 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
5677 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
5678 /* IP13_18_16 [3] */
5679 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
5680 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
5681 /* IP13_15_13 [3] */
5682 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
5683 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
5684 /* IP13_12_10 [3] */
5685 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
5686 FN_CAN_DEBUGOUT8, 0, 0,
5688 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
5689 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
5691 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
5692 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
5693 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
5695 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
5696 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
5698 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5699 GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
5703 /* IP14_30_28 [3] */
5704 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
5705 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
5707 /* IP14_27_25 [3] */
5708 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
5709 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
5710 /* IP14_24_22 [3] */
5711 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
5712 FN_LCDOUT9, 0, 0, 0,
5713 /* IP14_21_19 [3] */
5714 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
5715 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
5716 /* IP14_18_16 [3] */
5717 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
5718 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
5719 /* IP14_15_12 [4] */
5720 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
5721 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
5722 0, 0, 0, 0, 0, 0, 0,
5724 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
5727 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
5730 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
5731 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
5733 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
5734 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
5737 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5738 GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
5740 /* IP15_31_30 [2] */
5742 /* IP15_29_28 [2] */
5743 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
5744 /* IP15_27_26 [2] */
5745 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
5746 /* IP15_25_23 [3] */
5747 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
5748 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
5749 /* IP15_22_20 [3] */
5750 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
5751 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
5752 /* IP15_19_18 [2] */
5753 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
5754 /* IP15_17_16 [2] */
5755 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
5756 /* IP15_15_14 [2] */
5757 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5758 /* IP15_13_12 [2] */
5759 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5761 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
5764 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
5765 FN_IIC2_SDA, FN_I2C2_SDA, 0,
5767 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
5768 FN_IIC2_SCL, FN_I2C2_SCL, 0,
5770 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
5771 FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
5773 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5774 GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
5776 /* IP16_31_28 [4] */
5777 0, 0, 0, 0, 0, 0, 0, 0,
5778 0, 0, 0, 0, 0, 0, 0, 0,
5779 /* IP16_27_24 [4] */
5780 0, 0, 0, 0, 0, 0, 0, 0,
5781 0, 0, 0, 0, 0, 0, 0, 0,
5782 /* IP16_23_20 [4] */
5783 0, 0, 0, 0, 0, 0, 0, 0,
5784 0, 0, 0, 0, 0, 0, 0, 0,
5785 /* IP16_19_16 [4] */
5786 0, 0, 0, 0, 0, 0, 0, 0,
5787 0, 0, 0, 0, 0, 0, 0, 0,
5788 /* IP16_15_12 [4] */
5789 0, 0, 0, 0, 0, 0, 0, 0,
5790 0, 0, 0, 0, 0, 0, 0, 0,
5792 0, 0, 0, 0, 0, 0, 0, 0,
5793 0, 0, 0, 0, 0, 0, 0, 0,
5795 FN_USB1_OVC, FN_TCLK1_B,
5797 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
5799 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5800 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
5802 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5803 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, ))
5805 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5806 GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
5807 1, 1, 1, 2, 1, 1, 2, 1, 1),
5810 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5811 FN_SEL_SCIF1_4, 0, 0, 0,
5813 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5814 /* SEL_SCIFB2 [2] */
5815 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5816 /* SEL_SCIFB1 [3] */
5817 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
5818 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
5820 /* SEL_SCIFA1 [2] */
5821 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
5824 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
5826 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5828 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
5830 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5832 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5834 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5836 FN_SEL_VI3_0, FN_SEL_VI3_1,
5838 FN_SEL_VI2_0, FN_SEL_VI2_1,
5840 FN_SEL_VI1_0, FN_SEL_VI1_1,
5842 FN_SEL_VI0_0, FN_SEL_VI0_1,
5844 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5848 FN_SEL_LBS_0, FN_SEL_LBS_1,
5850 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5852 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5854 FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
5856 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5857 GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
5861 0, 0, 0, 0, 0, 0, 0, 0,
5863 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5864 /* SEL_HSCIF1 [1] */
5865 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5866 /* SEL_SCIFCLK [1] */
5867 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
5869 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5870 /* SEL_CANCLK [1] */
5871 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5872 /* SEL_SCIFA2 [2] */
5873 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5875 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
5879 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
5881 FN_SEL_ADI_0, FN_SEL_ADI_1,
5883 FN_SEL_SSP_0, FN_SEL_SSP_1,
5885 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
5886 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5887 /* SEL_HSCIF0 [3] */
5888 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
5889 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5891 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
5893 0, 0, 0, 0, 0, 0, 0, 0,
5895 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5897 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
5899 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5900 GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
5902 /* SEL_IICDVFS [1] */
5903 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5905 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
5909 0, 0, 0, 0, 0, 0, 0, 0,
5910 0, 0, 0, 0, 0, 0, 0, 0,
5912 0, 0, 0, 0, 0, 0, 0, 0,
5913 0, 0, 0, 0, 0, 0, 0, 0,
5917 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5919 0, 0, 0, 0, 0, 0, 0, 0,
5920 0, 0, 0, 0, 0, 0, 0, 0,
5924 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5925 FN_SEL_IIC2_4, 0, 0, 0,
5927 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5929 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5930 FN_SEL_I2C2_4, 0, 0, 0,
5932 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
5937 static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5939 if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
5942 *pocctrl = 0xe606008c;
5944 return 31 - (pin & 0x1f);
5947 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5948 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
5949 [ 0] = RCAR_GP_PIN(0, 16), /* A0 */
5950 [ 1] = RCAR_GP_PIN(0, 17), /* A1 */
5951 [ 2] = RCAR_GP_PIN(0, 18), /* A2 */
5952 [ 3] = RCAR_GP_PIN(0, 19), /* A3 */
5953 [ 4] = RCAR_GP_PIN(0, 20), /* A4 */
5954 [ 5] = RCAR_GP_PIN(0, 21), /* A5 */
5955 [ 6] = RCAR_GP_PIN(0, 22), /* A6 */
5956 [ 7] = RCAR_GP_PIN(0, 23), /* A7 */
5957 [ 8] = RCAR_GP_PIN(0, 24), /* A8 */
5958 [ 9] = RCAR_GP_PIN(0, 25), /* A9 */
5959 [10] = RCAR_GP_PIN(0, 26), /* A10 */
5960 [11] = RCAR_GP_PIN(0, 27), /* A11 */
5961 [12] = RCAR_GP_PIN(0, 28), /* A12 */
5962 [13] = RCAR_GP_PIN(0, 29), /* A13 */
5963 [14] = RCAR_GP_PIN(0, 30), /* A14 */
5964 [15] = RCAR_GP_PIN(0, 31), /* A15 */
5965 [16] = RCAR_GP_PIN(1, 0), /* A16 */
5966 [17] = RCAR_GP_PIN(1, 1), /* A17 */
5967 [18] = RCAR_GP_PIN(1, 2), /* A18 */
5968 [19] = RCAR_GP_PIN(1, 3), /* A19 */
5969 [20] = RCAR_GP_PIN(1, 4), /* A20 */
5970 [21] = RCAR_GP_PIN(1, 5), /* A21 */
5971 [22] = RCAR_GP_PIN(1, 6), /* A22 */
5972 [23] = RCAR_GP_PIN(1, 7), /* A23 */
5973 [24] = RCAR_GP_PIN(1, 8), /* A24 */
5974 [25] = RCAR_GP_PIN(1, 9), /* A25 */
5975 [26] = RCAR_GP_PIN(1, 12), /* EX_CS0# */
5976 [27] = RCAR_GP_PIN(1, 13), /* EX_CS1# */
5977 [28] = RCAR_GP_PIN(1, 14), /* EX_CS2# */
5978 [29] = RCAR_GP_PIN(1, 15), /* EX_CS3# */
5979 [30] = RCAR_GP_PIN(1, 16), /* EX_CS4# */
5980 [31] = RCAR_GP_PIN(1, 17), /* EX_CS5# */
5982 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
5983 /* PUPR1 pull-up pins */
5984 [ 0] = RCAR_GP_PIN(1, 18), /* BS# */
5985 [ 1] = RCAR_GP_PIN(1, 19), /* RD# */
5986 [ 2] = RCAR_GP_PIN(1, 20), /* RD/WR# */
5987 [ 3] = RCAR_GP_PIN(1, 21), /* WE0# */
5988 [ 4] = RCAR_GP_PIN(1, 22), /* WE1# */
5989 [ 5] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */
5990 [ 6] = RCAR_GP_PIN(5, 24), /* AVS1 */
5991 [ 7] = RCAR_GP_PIN(5, 25), /* AVS2 */
5992 [ 8] = RCAR_GP_PIN(1, 10), /* CS0# */
5993 [ 9] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */
5994 [10] = PIN_TRST_N, /* TRST# */
5995 [11] = PIN_TCK, /* TCK */
5996 [12] = PIN_TMS, /* TMS */
5997 [13] = PIN_TDI, /* TDI */
5998 [14] = SH_PFC_PIN_NONE,
5999 [15] = SH_PFC_PIN_NONE,
6000 [16] = RCAR_GP_PIN(0, 0), /* D0 */
6001 [17] = RCAR_GP_PIN(0, 1), /* D1 */
6002 [18] = RCAR_GP_PIN(0, 2), /* D2 */
6003 [19] = RCAR_GP_PIN(0, 3), /* D3 */
6004 [20] = RCAR_GP_PIN(0, 4), /* D4 */
6005 [21] = RCAR_GP_PIN(0, 5), /* D5 */
6006 [22] = RCAR_GP_PIN(0, 6), /* D6 */
6007 [23] = RCAR_GP_PIN(0, 7), /* D7 */
6008 [24] = RCAR_GP_PIN(0, 8), /* D8 */
6009 [25] = RCAR_GP_PIN(0, 9), /* D9 */
6010 [26] = RCAR_GP_PIN(0, 10), /* D10 */
6011 [27] = RCAR_GP_PIN(0, 11), /* D11 */
6012 [28] = RCAR_GP_PIN(0, 12), /* D12 */
6013 [29] = RCAR_GP_PIN(0, 13), /* D13 */
6014 [30] = RCAR_GP_PIN(0, 14), /* D14 */
6015 [31] = RCAR_GP_PIN(0, 15), /* D15 */
6017 { PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) {
6018 /* PUPR1 pull-down pins */
6019 [ 0] = SH_PFC_PIN_NONE,
6020 [ 1] = SH_PFC_PIN_NONE,
6021 [ 2] = SH_PFC_PIN_NONE,
6022 [ 3] = SH_PFC_PIN_NONE,
6023 [ 4] = SH_PFC_PIN_NONE,
6024 [ 5] = SH_PFC_PIN_NONE,
6025 [ 6] = SH_PFC_PIN_NONE,
6026 [ 7] = SH_PFC_PIN_NONE,
6027 [ 8] = SH_PFC_PIN_NONE,
6028 [ 9] = SH_PFC_PIN_NONE,
6029 [10] = SH_PFC_PIN_NONE,
6030 [11] = SH_PFC_PIN_NONE,
6031 [12] = SH_PFC_PIN_NONE,
6032 [13] = SH_PFC_PIN_NONE,
6033 [14] = SH_PFC_PIN_NONE,
6034 [15] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
6035 [16] = SH_PFC_PIN_NONE,
6036 [17] = SH_PFC_PIN_NONE,
6037 [18] = SH_PFC_PIN_NONE,
6038 [19] = SH_PFC_PIN_NONE,
6039 [20] = SH_PFC_PIN_NONE,
6040 [21] = SH_PFC_PIN_NONE,
6041 [22] = SH_PFC_PIN_NONE,
6042 [23] = SH_PFC_PIN_NONE,
6043 [24] = SH_PFC_PIN_NONE,
6044 [25] = SH_PFC_PIN_NONE,
6045 [26] = SH_PFC_PIN_NONE,
6046 [27] = SH_PFC_PIN_NONE,
6047 [28] = SH_PFC_PIN_NONE,
6048 [29] = SH_PFC_PIN_NONE,
6049 [30] = SH_PFC_PIN_NONE,
6050 [31] = SH_PFC_PIN_NONE,
6052 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
6053 [ 0] = RCAR_GP_PIN(5, 28), /* DU_DOTCLKIN2 */
6054 [ 1] = SH_PFC_PIN_NONE,
6055 [ 2] = SH_PFC_PIN_NONE,
6056 [ 3] = SH_PFC_PIN_NONE,
6057 [ 4] = SH_PFC_PIN_NONE,
6058 [ 5] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
6059 [ 6] = RCAR_GP_PIN(2, 1), /* VI0_DATA0_VI0_B0 */
6060 [ 7] = RCAR_GP_PIN(2, 2), /* VI0_DATA1_VI0_B1 */
6061 [ 8] = RCAR_GP_PIN(2, 3), /* VI0_DATA2_VI0_B2 */
6062 [ 9] = RCAR_GP_PIN(2, 4), /* VI0_DATA3_VI0_B3 */
6063 [10] = RCAR_GP_PIN(2, 5), /* VI0_DATA4_VI0_B4 */
6064 [11] = RCAR_GP_PIN(2, 6), /* VI0_DATA5_VI0_B5 */
6065 [12] = RCAR_GP_PIN(2, 7), /* VI0_DATA6_VI0_B6 */
6066 [13] = RCAR_GP_PIN(2, 8), /* VI0_DATA7_VI0_B7 */
6067 [14] = RCAR_GP_PIN(2, 9), /* VI1_CLK */
6068 [15] = RCAR_GP_PIN(2, 10), /* VI1_DATA0_VI1_B0 */
6069 [16] = RCAR_GP_PIN(2, 11), /* VI1_DATA1_VI1_B1 */
6070 [17] = RCAR_GP_PIN(2, 12), /* VI1_DATA2_VI1_B2 */
6071 [18] = RCAR_GP_PIN(2, 13), /* VI1_DATA3_VI1_B3 */
6072 [19] = RCAR_GP_PIN(2, 14), /* VI1_DATA4_VI1_B4 */
6073 [20] = RCAR_GP_PIN(2, 15), /* VI1_DATA5_VI1_B5 */
6074 [21] = RCAR_GP_PIN(2, 16), /* VI1_DATA6_VI1_B6 */
6075 [22] = RCAR_GP_PIN(2, 17), /* VI1_DATA7_VI1_B7 */
6076 [23] = RCAR_GP_PIN(5, 27), /* DU_DOTCLKIN1 */
6077 [24] = SH_PFC_PIN_NONE,
6078 [25] = SH_PFC_PIN_NONE,
6079 [26] = SH_PFC_PIN_NONE,
6080 [27] = RCAR_GP_PIN(4, 0), /* MLB_CLK */
6081 [28] = RCAR_GP_PIN(4, 1), /* MLB_SIG */
6082 [29] = RCAR_GP_PIN(4, 2), /* MLB_DAT */
6083 [30] = SH_PFC_PIN_NONE,
6084 [31] = RCAR_GP_PIN(5, 26), /* DU_DOTCLKIN0 */
6086 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
6087 [ 0] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6088 [ 1] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6089 [ 2] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6090 [ 3] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6091 [ 4] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6092 [ 5] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6093 [ 6] = RCAR_GP_PIN(3, 6), /* SD0_CD */
6094 [ 7] = RCAR_GP_PIN(3, 7), /* SD0_WP */
6095 [ 8] = RCAR_GP_PIN(3, 8), /* SD1_CLK */
6096 [ 9] = RCAR_GP_PIN(3, 9), /* SD1_CMD */
6097 [10] = RCAR_GP_PIN(3, 10), /* SD1_DAT0 */
6098 [11] = RCAR_GP_PIN(3, 11), /* SD1_DAT1 */
6099 [12] = RCAR_GP_PIN(3, 12), /* SD1_DAT2 */
6100 [13] = RCAR_GP_PIN(3, 13), /* SD1_DAT3 */
6101 [14] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6102 [15] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6103 [16] = RCAR_GP_PIN(3, 16), /* SD2_CLK */
6104 [17] = RCAR_GP_PIN(3, 17), /* SD2_CMD */
6105 [18] = RCAR_GP_PIN(3, 18), /* SD2_DAT0 */
6106 [19] = RCAR_GP_PIN(3, 19), /* SD2_DAT1 */
6107 [20] = RCAR_GP_PIN(3, 20), /* SD2_DAT2 */
6108 [21] = RCAR_GP_PIN(3, 21), /* SD2_DAT3 */
6109 [22] = RCAR_GP_PIN(3, 22), /* SD2_CD */
6110 [23] = RCAR_GP_PIN(3, 23), /* SD2_WP */
6111 [24] = RCAR_GP_PIN(3, 24), /* SD3_CLK */
6112 [25] = RCAR_GP_PIN(3, 25), /* SD3_CMD */
6113 [26] = RCAR_GP_PIN(3, 26), /* SD3_DAT0 */
6114 [27] = RCAR_GP_PIN(3, 27), /* SD3_DAT1 */
6115 [28] = RCAR_GP_PIN(3, 28), /* SD3_DAT2 */
6116 [29] = RCAR_GP_PIN(3, 29), /* SD3_DAT3 */
6117 [30] = RCAR_GP_PIN(3, 30), /* SD3_CD */
6118 [31] = RCAR_GP_PIN(3, 31), /* SD3_WP */
6120 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
6121 [ 0] = RCAR_GP_PIN(4, 3), /* SSI_SCK0129 */
6122 [ 1] = RCAR_GP_PIN(4, 4), /* SSI_WS0129 */
6123 [ 2] = RCAR_GP_PIN(4, 5), /* SSI_SDATA0 */
6124 [ 3] = RCAR_GP_PIN(4, 6), /* SSI_SDATA1 */
6125 [ 4] = RCAR_GP_PIN(4, 7), /* SSI_SDATA2 */
6126 [ 5] = RCAR_GP_PIN(4, 8), /* SSI_SCK34 */
6127 [ 6] = RCAR_GP_PIN(4, 9), /* SSI_WS34 */
6128 [ 7] = RCAR_GP_PIN(4, 10), /* SSI_SDATA3 */
6129 [ 8] = RCAR_GP_PIN(4, 11), /* SSI_SCK4 */
6130 [ 9] = RCAR_GP_PIN(4, 12), /* SSI_WS4 */
6131 [10] = RCAR_GP_PIN(4, 13), /* SSI_SDATA4 */
6132 [11] = RCAR_GP_PIN(4, 14), /* SSI_SCK5 */
6133 [12] = RCAR_GP_PIN(4, 15), /* SSI_WS5 */
6134 [13] = RCAR_GP_PIN(4, 16), /* SSI_SDATA5 */
6135 [14] = RCAR_GP_PIN(4, 17), /* SSI_SCK6 */
6136 [15] = RCAR_GP_PIN(4, 18), /* SSI_WS6 */
6137 [16] = RCAR_GP_PIN(4, 19), /* SSI_SDATA6 */
6138 [17] = RCAR_GP_PIN(4, 20), /* SSI_SCK78 */
6139 [18] = RCAR_GP_PIN(4, 21), /* SSI_WS78 */
6140 [19] = RCAR_GP_PIN(4, 22), /* SSI_SDATA7 */
6141 [20] = RCAR_GP_PIN(4, 23), /* SSI_SDATA8 */
6142 [21] = RCAR_GP_PIN(4, 24), /* SSI_SDATA9 */
6143 [22] = RCAR_GP_PIN(4, 25), /* AUDIO_CLKA */
6144 [23] = RCAR_GP_PIN(4, 26), /* AUDIO_CLKB */
6145 [24] = RCAR_GP_PIN(1, 24), /* DREQ0 */
6146 [25] = RCAR_GP_PIN(1, 25), /* DACK0 */
6147 [26] = RCAR_GP_PIN(1, 26), /* DREQ1 */
6148 [27] = RCAR_GP_PIN(1, 27), /* DACK1 */
6149 [28] = RCAR_GP_PIN(1, 28), /* DREQ2 */
6150 [29] = RCAR_GP_PIN(1, 29), /* DACK2 */
6151 [30] = RCAR_GP_PIN(2, 18), /* ETH_CRS_DV */
6152 [31] = RCAR_GP_PIN(2, 19), /* ETH_RX_ER */
6154 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
6155 [ 0] = RCAR_GP_PIN(4, 27), /* SCIFA0_SCK */
6156 [ 1] = RCAR_GP_PIN(4, 28), /* SCIFA0_RXD */
6157 [ 2] = RCAR_GP_PIN(4, 29), /* SCIFA0_TXD */
6158 [ 3] = RCAR_GP_PIN(4, 30), /* SCIFA0_CTS# */
6159 [ 4] = RCAR_GP_PIN(4, 31), /* SCIFA0_RTS# */
6160 [ 5] = RCAR_GP_PIN(5, 0), /* SCIFA1_RXD */
6161 [ 6] = RCAR_GP_PIN(5, 1), /* SCIFA1_TXD */
6162 [ 7] = RCAR_GP_PIN(5, 2), /* SCIFA1_CTS# */
6163 [ 8] = RCAR_GP_PIN(5, 3), /* SCIFA1_RTS# */
6164 [ 9] = RCAR_GP_PIN(5, 4), /* SCIFA2_SCK */
6165 [10] = RCAR_GP_PIN(5, 5), /* SCIFA2_RXD */
6166 [11] = RCAR_GP_PIN(5, 6), /* SCIFA2_TXD */
6167 [12] = RCAR_GP_PIN(5, 7), /* HSCK0 */
6168 [13] = RCAR_GP_PIN(5, 8), /* HRX0 */
6169 [14] = RCAR_GP_PIN(5, 9), /* HTX0 */
6170 [15] = RCAR_GP_PIN(5, 10), /* HCTS0# */
6171 [16] = RCAR_GP_PIN(5, 11), /* HRTS0# */
6172 [17] = RCAR_GP_PIN(5, 12), /* MSIOF0_SCK */
6173 [18] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */
6174 [19] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */
6175 [20] = RCAR_GP_PIN(5, 15), /* MSIOF0_TXD */
6176 [21] = RCAR_GP_PIN(5, 16), /* MSIOF0_SS2 */
6177 [22] = RCAR_GP_PIN(5, 17), /* MSIOF0_RXD */
6178 [23] = RCAR_GP_PIN(5, 18), /* USB0_PWEN */
6179 [24] = RCAR_GP_PIN(5, 19), /* USB0_OVC_VBUS */
6180 [25] = RCAR_GP_PIN(5, 20), /* USB1_PWEN */
6181 [26] = RCAR_GP_PIN(5, 21), /* USB1_OVC */
6182 [27] = RCAR_GP_PIN(5, 22), /* USB2_PWEN */
6183 [28] = RCAR_GP_PIN(5, 23), /* USB2_OVC */
6184 [29] = RCAR_GP_PIN(2, 20), /* ETH_RXD0 */
6185 [30] = RCAR_GP_PIN(2, 21), /* ETH_RXD1 */
6186 [31] = RCAR_GP_PIN(2, 22), /* ETH_LINK */
6188 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
6189 [ 0] = RCAR_GP_PIN(2, 23), /* ETH_REF_CLK */
6190 [ 1] = RCAR_GP_PIN(2, 24), /* ETH_MDIO */
6191 [ 2] = RCAR_GP_PIN(2, 25), /* ETH_TXD1 */
6192 [ 3] = RCAR_GP_PIN(2, 26), /* ETH_TX_EN */
6193 [ 4] = RCAR_GP_PIN(2, 27), /* ETH_MAGIC */
6194 [ 5] = RCAR_GP_PIN(2, 28), /* ETH_TXD0 */
6195 [ 6] = RCAR_GP_PIN(2, 29), /* ETH_MDC */
6196 [ 7] = RCAR_GP_PIN(5, 29), /* PWM0 */
6197 [ 8] = RCAR_GP_PIN(5, 30), /* PWM1 */
6198 [ 9] = RCAR_GP_PIN(5, 31), /* PWM2 */
6199 [10] = SH_PFC_PIN_NONE,
6200 [11] = SH_PFC_PIN_NONE,
6201 [12] = SH_PFC_PIN_NONE,
6202 [13] = SH_PFC_PIN_NONE,
6203 [14] = SH_PFC_PIN_NONE,
6204 [15] = SH_PFC_PIN_NONE,
6205 [16] = SH_PFC_PIN_NONE,
6206 [17] = SH_PFC_PIN_NONE,
6207 [18] = SH_PFC_PIN_NONE,
6208 [19] = SH_PFC_PIN_NONE,
6209 [20] = SH_PFC_PIN_NONE,
6210 [21] = SH_PFC_PIN_NONE,
6211 [22] = SH_PFC_PIN_NONE,
6212 [23] = SH_PFC_PIN_NONE,
6213 [24] = SH_PFC_PIN_NONE,
6214 [25] = SH_PFC_PIN_NONE,
6215 [26] = SH_PFC_PIN_NONE,
6216 [27] = SH_PFC_PIN_NONE,
6217 [28] = SH_PFC_PIN_NONE,
6218 [29] = SH_PFC_PIN_NONE,
6219 [30] = SH_PFC_PIN_NONE,
6220 [31] = SH_PFC_PIN_NONE,
6225 static const struct soc_device_attribute r8a7790_tdsel[] = {
6226 { .soc_id = "r8a7790", .revision = "ES1.0" },
6230 static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
6232 /* Initialize TDSEL on old revisions */
6233 if (soc_device_match(r8a7790_tdsel))
6234 sh_pfc_write(pfc, 0xe6060088, 0x00155554);
6239 static const struct sh_pfc_soc_operations r8a7790_pfc_ops = {
6240 .init = r8a7790_pinmux_soc_init,
6241 .pin_to_pocctrl = r8a7790_pin_to_pocctrl,
6242 .get_bias = rcar_pinmux_get_bias,
6243 .set_bias = rcar_pinmux_set_bias,
6246 #ifdef CONFIG_PINCTRL_PFC_R8A7742
6247 const struct sh_pfc_soc_info r8a7742_pinmux_info = {
6248 .name = "r8a77420_pfc",
6249 .ops = &r8a7790_pfc_ops,
6250 .unlock_reg = 0xe6060000, /* PMMR */
6252 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6254 .pins = pinmux_pins,
6255 .nr_pins = ARRAY_SIZE(pinmux_pins),
6256 .groups = pinmux_groups.common,
6257 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6258 .functions = pinmux_functions.common,
6259 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6261 .cfg_regs = pinmux_config_regs,
6262 .bias_regs = pinmux_bias_regs,
6264 .pinmux_data = pinmux_data,
6265 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6269 #ifdef CONFIG_PINCTRL_PFC_R8A7790
6270 const struct sh_pfc_soc_info r8a7790_pinmux_info = {
6271 .name = "r8a77900_pfc",
6272 .ops = &r8a7790_pfc_ops,
6273 .unlock_reg = 0xe6060000, /* PMMR */
6275 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6277 .pins = pinmux_pins,
6278 .nr_pins = ARRAY_SIZE(pinmux_pins),
6279 .groups = pinmux_groups.common,
6280 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6281 ARRAY_SIZE(pinmux_groups.automotive),
6282 .functions = pinmux_functions.common,
6283 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6284 ARRAY_SIZE(pinmux_functions.automotive),
6286 .cfg_regs = pinmux_config_regs,
6287 .bias_regs = pinmux_bias_regs,
6289 .pinmux_data = pinmux_data,
6290 .pinmux_data_size = ARRAY_SIZE(pinmux_data),