1 // SPDX-License-Identifier: GPL-2.0
3 * Pin Control and GPIO driver for SuperH Pin Function Controller.
5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
7 * Copyright (C) 2008 Magnus Damm
8 * Copyright (C) 2009 - 2012 Paul Mundt
11 #define DRV_NAME "sh-pfc"
13 #include <linux/bitops.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
21 #include <linux/of_device.h>
22 #include <linux/pinctrl/machine.h>
23 #include <linux/platform_device.h>
24 #include <linux/psci.h>
25 #include <linux/slab.h>
26 #include <linux/sys_soc.h>
30 static int sh_pfc_map_resources(struct sh_pfc *pfc,
31 struct platform_device *pdev)
33 struct sh_pfc_window *windows;
34 unsigned int *irqs = NULL;
35 unsigned int num_windows;
40 /* Count the MEM and IRQ resources. */
41 for (num_windows = 0;; num_windows++) {
42 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
49 num_irqs = platform_irq_count(pdev);
53 /* Allocate memory windows and IRQs arrays. */
54 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
59 pfc->num_windows = num_windows;
60 pfc->windows = windows;
63 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
68 pfc->num_irqs = num_irqs;
73 for (i = 0; i < num_windows; i++) {
74 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
75 windows->phys = res->start;
76 windows->size = resource_size(res);
77 windows->virt = devm_ioremap_resource(pfc->dev, res);
78 if (IS_ERR(windows->virt))
82 for (i = 0; i < num_irqs; i++)
83 *irqs++ = platform_get_irq(pdev, i);
88 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
90 struct sh_pfc_window *window;
91 phys_addr_t address = reg;
94 /* scan through physical windows and convert address */
95 for (i = 0; i < pfc->num_windows; i++) {
96 window = pfc->windows + i;
98 if (address < window->phys)
101 if (address >= (window->phys + window->size))
104 return window->virt + (address - window->phys);
111 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
116 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
117 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
119 if (pin <= range->end)
120 return pin >= range->start
121 ? offset + pin - range->start : -1;
123 offset += range->end - range->start + 1;
129 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
131 if (enum_id < r->begin)
134 if (enum_id > r->end)
140 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
144 return ioread8(mapped_reg);
146 return ioread16(mapped_reg);
148 return ioread32(mapped_reg);
155 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
160 iowrite8(data, mapped_reg);
163 iowrite16(data, mapped_reg);
166 iowrite32(data, mapped_reg);
173 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
175 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
178 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
180 if (pfc->info->unlock_reg)
181 sh_pfc_write_raw_reg(
182 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
185 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
188 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
189 const struct pinmux_cfg_reg *crp,
191 void __iomem **mapped_regp, u32 *maskp,
196 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
198 if (crp->field_width) {
199 *maskp = (1 << crp->field_width) - 1;
200 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
202 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
203 *posp = crp->reg_width;
204 for (k = 0; k <= in_pos; k++)
205 *posp -= crp->var_field_width[k];
209 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
210 const struct pinmux_cfg_reg *crp,
211 unsigned int field, u32 value)
213 void __iomem *mapped_reg;
217 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
219 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
220 "r_width = %u, f_width = %u\n",
221 crp->reg, value, field, crp->reg_width, hweight32(mask));
223 mask = ~(mask << pos);
224 value = value << pos;
226 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
230 if (pfc->info->unlock_reg)
231 sh_pfc_write_raw_reg(
232 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
235 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
238 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
239 const struct pinmux_cfg_reg **crp,
240 unsigned int *fieldp, u32 *valuep)
245 const struct pinmux_cfg_reg *config_reg =
246 pfc->info->cfg_regs + k;
247 unsigned int r_width = config_reg->reg_width;
248 unsigned int f_width = config_reg->field_width;
249 unsigned int curr_width;
250 unsigned int bit_pos;
251 unsigned int pos = 0;
257 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
262 curr_width = f_width;
264 curr_width = config_reg->var_field_width[m];
266 ncomb = 1 << curr_width;
267 for (n = 0; n < ncomb; n++) {
268 if (config_reg->enum_ids[pos + n] == enum_id) {
284 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
287 const u16 *data = pfc->info->pinmux_data;
291 *enum_idp = data[pos + 1];
295 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
296 if (data[k] == mark) {
297 *enum_idp = data[k + 1];
302 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
307 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
309 const struct pinmux_range *range;
312 switch (pinmux_type) {
313 case PINMUX_TYPE_GPIO:
314 case PINMUX_TYPE_FUNCTION:
318 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
319 case PINMUX_TYPE_OUTPUT:
320 range = &pfc->info->output;
323 case PINMUX_TYPE_INPUT:
324 range = &pfc->info->input;
326 #endif /* CONFIG_PINCTRL_SH_PFC_GPIO */
332 /* Iterate over all the configuration fields we need to update. */
334 const struct pinmux_cfg_reg *cr;
341 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
348 /* Check if the configuration field selects a function. If it
349 * doesn't, skip the field if it's not applicable to the
350 * requested pinmux type.
352 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
354 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
355 /* Functions are allowed to modify all
359 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
360 /* Input/output types can only modify fields
361 * that correspond to their respective ranges.
363 in_range = sh_pfc_enum_in_range(enum_id, range);
366 * special case pass through for fixed
367 * input-only or output-only pins without
368 * function enum register association.
370 if (in_range && enum_id == range->force)
373 /* GPIOs are only allowed to modify function fields. */
379 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
383 sh_pfc_write_config_reg(pfc, cr, field, value);
389 const struct pinmux_bias_reg *
390 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
395 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
396 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
397 if (pfc->info->bias_regs[i].pins[j] == pin) {
399 return &pfc->info->bias_regs[i];
404 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
409 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
411 struct sh_pfc_pin_range *range;
412 unsigned int nr_ranges;
415 if (pfc->info->pins[0].pin == (u16)-1) {
416 /* Pin number -1 denotes that the SoC doesn't report pin numbers
417 * in its pin arrays yet. Consider the pin numbers range as
418 * continuous and allocate a single range.
421 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
423 if (pfc->ranges == NULL)
426 pfc->ranges->start = 0;
427 pfc->ranges->end = pfc->info->nr_pins - 1;
428 pfc->nr_gpio_pins = pfc->info->nr_pins;
433 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
434 * be sorted by pin numbers, and pins without a GPIO port must come
437 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
438 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
442 pfc->nr_ranges = nr_ranges;
443 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
445 if (pfc->ranges == NULL)
449 range->start = pfc->info->pins[0].pin;
451 for (i = 1; i < pfc->info->nr_pins; ++i) {
452 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
455 range->end = pfc->info->pins[i-1].pin;
456 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
457 pfc->nr_gpio_pins = range->end + 1;
460 range->start = pfc->info->pins[i].pin;
463 range->end = pfc->info->pins[i-1].pin;
464 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
465 pfc->nr_gpio_pins = range->end + 1;
471 static const struct of_device_id sh_pfc_of_table[] = {
472 #ifdef CONFIG_PINCTRL_PFC_EMEV2
474 .compatible = "renesas,pfc-emev2",
475 .data = &emev2_pinmux_info,
478 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
480 .compatible = "renesas,pfc-r8a73a4",
481 .data = &r8a73a4_pinmux_info,
484 #ifdef CONFIG_PINCTRL_PFC_R8A7740
486 .compatible = "renesas,pfc-r8a7740",
487 .data = &r8a7740_pinmux_info,
490 #ifdef CONFIG_PINCTRL_PFC_R8A7742
492 .compatible = "renesas,pfc-r8a7742",
493 .data = &r8a7742_pinmux_info,
496 #ifdef CONFIG_PINCTRL_PFC_R8A7743
498 .compatible = "renesas,pfc-r8a7743",
499 .data = &r8a7743_pinmux_info,
502 #ifdef CONFIG_PINCTRL_PFC_R8A7744
504 .compatible = "renesas,pfc-r8a7744",
505 .data = &r8a7744_pinmux_info,
508 #ifdef CONFIG_PINCTRL_PFC_R8A7745
510 .compatible = "renesas,pfc-r8a7745",
511 .data = &r8a7745_pinmux_info,
514 #ifdef CONFIG_PINCTRL_PFC_R8A77470
516 .compatible = "renesas,pfc-r8a77470",
517 .data = &r8a77470_pinmux_info,
520 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
522 .compatible = "renesas,pfc-r8a774a1",
523 .data = &r8a774a1_pinmux_info,
526 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
528 .compatible = "renesas,pfc-r8a774b1",
529 .data = &r8a774b1_pinmux_info,
532 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
534 .compatible = "renesas,pfc-r8a774c0",
535 .data = &r8a774c0_pinmux_info,
538 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
540 .compatible = "renesas,pfc-r8a774e1",
541 .data = &r8a774e1_pinmux_info,
544 #ifdef CONFIG_PINCTRL_PFC_R8A7778
546 .compatible = "renesas,pfc-r8a7778",
547 .data = &r8a7778_pinmux_info,
550 #ifdef CONFIG_PINCTRL_PFC_R8A7779
552 .compatible = "renesas,pfc-r8a7779",
553 .data = &r8a7779_pinmux_info,
556 #ifdef CONFIG_PINCTRL_PFC_R8A7790
558 .compatible = "renesas,pfc-r8a7790",
559 .data = &r8a7790_pinmux_info,
562 #ifdef CONFIG_PINCTRL_PFC_R8A7791
564 .compatible = "renesas,pfc-r8a7791",
565 .data = &r8a7791_pinmux_info,
568 #ifdef CONFIG_PINCTRL_PFC_R8A7792
570 .compatible = "renesas,pfc-r8a7792",
571 .data = &r8a7792_pinmux_info,
574 #ifdef CONFIG_PINCTRL_PFC_R8A7793
576 .compatible = "renesas,pfc-r8a7793",
577 .data = &r8a7793_pinmux_info,
580 #ifdef CONFIG_PINCTRL_PFC_R8A7794
582 .compatible = "renesas,pfc-r8a7794",
583 .data = &r8a7794_pinmux_info,
586 /* Both r8a7795 entries must be present to make sanity checks work */
587 #ifdef CONFIG_PINCTRL_PFC_R8A77950
589 .compatible = "renesas,pfc-r8a7795",
590 .data = &r8a77950_pinmux_info,
593 #ifdef CONFIG_PINCTRL_PFC_R8A77951
595 .compatible = "renesas,pfc-r8a7795",
596 .data = &r8a77951_pinmux_info,
599 #ifdef CONFIG_PINCTRL_PFC_R8A77960
601 .compatible = "renesas,pfc-r8a7796",
602 .data = &r8a77960_pinmux_info,
605 #ifdef CONFIG_PINCTRL_PFC_R8A77961
607 .compatible = "renesas,pfc-r8a77961",
608 .data = &r8a77961_pinmux_info,
611 #ifdef CONFIG_PINCTRL_PFC_R8A77965
613 .compatible = "renesas,pfc-r8a77965",
614 .data = &r8a77965_pinmux_info,
617 #ifdef CONFIG_PINCTRL_PFC_R8A77970
619 .compatible = "renesas,pfc-r8a77970",
620 .data = &r8a77970_pinmux_info,
623 #ifdef CONFIG_PINCTRL_PFC_R8A77980
625 .compatible = "renesas,pfc-r8a77980",
626 .data = &r8a77980_pinmux_info,
629 #ifdef CONFIG_PINCTRL_PFC_R8A77990
631 .compatible = "renesas,pfc-r8a77990",
632 .data = &r8a77990_pinmux_info,
635 #ifdef CONFIG_PINCTRL_PFC_R8A77995
637 .compatible = "renesas,pfc-r8a77995",
638 .data = &r8a77995_pinmux_info,
641 #ifdef CONFIG_PINCTRL_PFC_SH73A0
643 .compatible = "renesas,pfc-sh73a0",
644 .data = &sh73a0_pinmux_info,
651 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
652 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
656 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
658 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
661 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
663 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
666 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
667 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
669 unsigned int i, n = 0;
671 if (pfc->info->cfg_regs)
672 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
673 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
675 if (pfc->info->drive_regs)
676 for (i = 0; pfc->info->drive_regs[i].reg; i++)
677 do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
679 if (pfc->info->bias_regs)
680 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
681 do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
682 if (pfc->info->bias_regs[i].pud)
683 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
686 if (pfc->info->ioctrl_regs)
687 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
688 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
693 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
697 /* This is the best we can do to check for the presence of PSCI */
698 if (!psci_ops.cpu_suspend)
701 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
705 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
706 sizeof(*pfc->saved_regs),
708 if (!pfc->saved_regs)
711 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
715 static int sh_pfc_suspend_noirq(struct device *dev)
717 struct sh_pfc *pfc = dev_get_drvdata(dev);
720 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
724 static int sh_pfc_resume_noirq(struct device *dev)
726 struct sh_pfc *pfc = dev_get_drvdata(dev);
729 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
733 static const struct dev_pm_ops sh_pfc_pm = {
734 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
736 #define DEV_PM_OPS &sh_pfc_pm
738 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
739 #define DEV_PM_OPS NULL
740 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
743 #define SH_PFC_MAX_REGS 300
744 #define SH_PFC_MAX_ENUMS 3000
746 static unsigned int sh_pfc_errors __initdata = 0;
747 static unsigned int sh_pfc_warnings __initdata = 0;
748 static u32 *sh_pfc_regs __initdata = NULL;
749 static u32 sh_pfc_num_regs __initdata = 0;
750 static u16 *sh_pfc_enums __initdata = NULL;
751 static u32 sh_pfc_num_enums __initdata = 0;
753 #define sh_pfc_err(fmt, ...) \
755 pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \
758 #define sh_pfc_warn(fmt, ...) \
760 pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \
764 static bool __init is0s(const u16 *enum_ids, unsigned int n)
768 for (i = 0; i < n; i++)
775 static bool __init same_name(const char *a, const char *b)
780 return !strcmp(a, b);
783 static void __init sh_pfc_check_reg(const char *drvname, u32 reg)
787 for (i = 0; i < sh_pfc_num_regs; i++)
788 if (reg == sh_pfc_regs[i]) {
789 sh_pfc_err("reg 0x%x conflict\n", reg);
793 if (sh_pfc_num_regs == SH_PFC_MAX_REGS) {
794 pr_warn_once("%s: Please increase SH_PFC_MAX_REGS\n", drvname);
798 sh_pfc_regs[sh_pfc_num_regs++] = reg;
801 static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id)
805 for (i = 0; i < sh_pfc_num_enums; i++) {
806 if (enum_id == sh_pfc_enums[i])
810 if (sh_pfc_num_enums == SH_PFC_MAX_ENUMS) {
811 pr_warn_once("%s: Please increase SH_PFC_MAX_ENUMS\n", drvname);
815 sh_pfc_enums[sh_pfc_num_enums++] = enum_id;
819 static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg,
820 const u16 *enums, unsigned int n)
824 for (i = 0; i < n; i++) {
825 if (enums[i] && sh_pfc_check_enum(drvname, enums[i]))
826 sh_pfc_err("reg 0x%x enum_id %u conflict\n", reg,
831 static void __init sh_pfc_check_pin(const struct sh_pfc_soc_info *info,
832 u32 reg, unsigned int pin)
834 const char *drvname = info->name;
837 if (pin == SH_PFC_PIN_NONE)
840 for (i = 0; i < info->nr_pins; i++) {
841 if (pin == info->pins[i].pin)
845 sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);
848 static void __init sh_pfc_check_cfg_reg(const char *drvname,
849 const struct pinmux_cfg_reg *cfg_reg)
851 unsigned int i, n, rw, fw;
853 sh_pfc_check_reg(drvname, cfg_reg->reg);
855 if (cfg_reg->field_width) {
856 n = cfg_reg->reg_width / cfg_reg->field_width;
857 /* Skip field checks (done at build time) */
861 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
862 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw))
863 sh_pfc_warn("reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
864 cfg_reg->reg, rw, rw + fw - 1);
869 if (rw != cfg_reg->reg_width)
870 sh_pfc_err("reg 0x%x: var_field_width declares %u instead of %u bits\n",
871 cfg_reg->reg, rw, cfg_reg->reg_width);
873 if (n != cfg_reg->nr_enum_ids)
874 sh_pfc_err("reg 0x%x: enum_ids[] has %u instead of %u values\n",
875 cfg_reg->reg, cfg_reg->nr_enum_ids, n);
878 sh_pfc_check_reg_enums(drvname, cfg_reg->reg, cfg_reg->enum_ids, n);
881 static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
882 const struct pinmux_drive_reg *drive)
884 const char *drvname = info->name;
885 unsigned long seen = 0, mask;
888 sh_pfc_check_reg(info->name, drive->reg);
889 for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
890 const struct pinmux_drive_reg_field *field = &drive->fields[i];
892 if (!field->pin && !field->offset && !field->size)
895 mask = GENMASK(field->offset + field->size, field->offset);
897 sh_pfc_err("drive_reg 0x%x: field %u overlap\n",
901 sh_pfc_check_pin(info, drive->reg, field->pin);
905 static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
906 const struct pinmux_bias_reg *bias)
910 sh_pfc_check_reg(info->name, bias->puen);
912 sh_pfc_check_reg(info->name, bias->pud);
913 for (i = 0; i < ARRAY_SIZE(bias->pins); i++)
914 sh_pfc_check_pin(info, bias->puen, bias->pins[i]);
917 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
919 const char *drvname = info->name;
920 unsigned int *refcnts;
921 unsigned int i, j, k;
923 pr_info("Checking %s\n", drvname);
925 sh_pfc_num_enums = 0;
928 for (i = 0; i < info->nr_pins; i++) {
929 const struct sh_pfc_pin *pin = &info->pins[i];
932 sh_pfc_err("empty pin %u\n", i);
935 for (j = 0; j < i; j++) {
936 const struct sh_pfc_pin *pin2 = &info->pins[j];
938 if (same_name(pin->name, pin2->name))
939 sh_pfc_err("pin %s: name conflict\n",
942 if (pin->pin != (u16)-1 && pin->pin == pin2->pin)
943 sh_pfc_err("pin %s/%s: pin %u conflict\n",
944 pin->name, pin2->name, pin->pin);
946 if (pin->enum_id && pin->enum_id == pin2->enum_id)
947 sh_pfc_err("pin %s/%s: enum_id %u conflict\n",
948 pin->name, pin2->name,
953 /* Check groups and functions */
954 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
958 for (i = 0; i < info->nr_functions; i++) {
959 const struct sh_pfc_function *func = &info->functions[i];
962 sh_pfc_err("empty function %u\n", i);
965 for (j = 0; j < i; j++) {
966 if (same_name(func->name, info->functions[j].name))
967 sh_pfc_err("function %s: name conflict\n",
970 for (j = 0; j < func->nr_groups; j++) {
971 for (k = 0; k < info->nr_groups; k++) {
972 if (same_name(func->groups[j],
973 info->groups[k].name)) {
979 if (k == info->nr_groups)
980 sh_pfc_err("function %s: group %s not found\n",
981 func->name, func->groups[j]);
985 for (i = 0; i < info->nr_groups; i++) {
986 const struct sh_pfc_pin_group *group = &info->groups[i];
989 sh_pfc_err("empty group %u\n", i);
992 for (j = 0; j < i; j++) {
993 if (same_name(group->name, info->groups[j].name))
994 sh_pfc_err("group %s: name conflict\n",
998 sh_pfc_err("orphan group %s\n", group->name);
999 else if (refcnts[i] > 1)
1000 sh_pfc_warn("group %s referenced by %u functions\n",
1001 group->name, refcnts[i]);
1006 /* Check config register descriptions */
1007 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
1008 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
1010 /* Check drive strength registers */
1011 for (i = 0; info->drive_regs && info->drive_regs[i].reg; i++)
1012 sh_pfc_check_drive_reg(info, &info->drive_regs[i]);
1014 /* Check bias registers */
1015 for (i = 0; info->bias_regs && info->bias_regs[i].puen; i++)
1016 sh_pfc_check_bias_reg(info, &info->bias_regs[i]);
1018 /* Check ioctrl registers */
1019 for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
1020 sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg);
1022 /* Check data registers */
1023 for (i = 0; info->data_regs && info->data_regs[i].reg; i++) {
1024 sh_pfc_check_reg(drvname, info->data_regs[i].reg);
1025 sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg,
1026 info->data_regs[i].enum_ids,
1027 info->data_regs[i].reg_width);
1030 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
1031 /* Check function GPIOs */
1032 for (i = 0; i < info->nr_func_gpios; i++) {
1033 const struct pinmux_func *func = &info->func_gpios[i];
1036 sh_pfc_err("empty function gpio %u\n", i);
1039 for (j = 0; j < i; j++) {
1040 if (same_name(func->name, info->func_gpios[j].name))
1041 sh_pfc_err("func_gpio %s: name conflict\n",
1044 if (sh_pfc_check_enum(drvname, func->enum_id))
1045 sh_pfc_err("%s enum_id %u conflict\n", func->name,
1051 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
1055 sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs),
1060 sh_pfc_enums = kcalloc(SH_PFC_MAX_ENUMS, sizeof(*sh_pfc_enums),
1065 pr_warn("Checking builtin pinmux tables\n");
1067 for (i = 0; pdrv->id_table[i].name[0]; i++)
1068 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
1071 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
1072 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
1075 pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
1078 kfree(sh_pfc_enums);
1084 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
1088 static const void *sh_pfc_quirk_match(void)
1090 #if defined(CONFIG_PINCTRL_PFC_R8A77950) || \
1091 defined(CONFIG_PINCTRL_PFC_R8A77951)
1092 const struct soc_device_attribute *match;
1093 static const struct soc_device_attribute quirks[] = {
1095 .soc_id = "r8a7795", .revision = "ES1.*",
1096 .data = &r8a77950_pinmux_info,
1099 .soc_id = "r8a7795",
1100 .data = &r8a77951_pinmux_info,
1106 match = soc_device_match(quirks);
1108 return match->data ?: ERR_PTR(-ENODEV);
1109 #endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */
1113 #endif /* CONFIG_OF */
1115 static int sh_pfc_probe(struct platform_device *pdev)
1117 const struct sh_pfc_soc_info *info;
1122 if (pdev->dev.of_node) {
1123 info = sh_pfc_quirk_match();
1125 return PTR_ERR(info);
1128 info = of_device_get_match_data(&pdev->dev);
1131 info = (const void *)platform_get_device_id(pdev)->driver_data;
1133 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
1138 pfc->dev = &pdev->dev;
1140 ret = sh_pfc_map_resources(pfc, pdev);
1141 if (unlikely(ret < 0))
1144 spin_lock_init(&pfc->lock);
1146 if (info->ops && info->ops->init) {
1147 ret = info->ops->init(pfc);
1151 /* .init() may have overridden pfc->info */
1155 ret = sh_pfc_suspend_init(pfc);
1159 /* Enable dummy states for those platforms without pinctrl support */
1160 if (!of_have_populated_dt())
1161 pinctrl_provide_dummies();
1163 ret = sh_pfc_init_ranges(pfc);
1168 * Initialize pinctrl bindings first
1170 ret = sh_pfc_register_pinctrl(pfc);
1171 if (unlikely(ret != 0))
1174 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
1176 * Then the GPIO chip
1178 ret = sh_pfc_register_gpiochip(pfc);
1179 if (unlikely(ret != 0)) {
1181 * If the GPIO chip fails to come up we still leave the
1182 * PFC state as it is, given that there are already
1183 * extant users of it that have succeeded by this point.
1185 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
1189 platform_set_drvdata(pdev, pfc);
1191 dev_info(pfc->dev, "%s support registered\n", info->name);
1196 static const struct platform_device_id sh_pfc_id_table[] = {
1197 #ifdef CONFIG_PINCTRL_PFC_SH7203
1198 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
1200 #ifdef CONFIG_PINCTRL_PFC_SH7264
1201 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
1203 #ifdef CONFIG_PINCTRL_PFC_SH7269
1204 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
1206 #ifdef CONFIG_PINCTRL_PFC_SH7720
1207 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
1209 #ifdef CONFIG_PINCTRL_PFC_SH7722
1210 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
1212 #ifdef CONFIG_PINCTRL_PFC_SH7723
1213 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
1215 #ifdef CONFIG_PINCTRL_PFC_SH7724
1216 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
1218 #ifdef CONFIG_PINCTRL_PFC_SH7734
1219 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
1221 #ifdef CONFIG_PINCTRL_PFC_SH7757
1222 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
1224 #ifdef CONFIG_PINCTRL_PFC_SH7785
1225 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
1227 #ifdef CONFIG_PINCTRL_PFC_SH7786
1228 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
1230 #ifdef CONFIG_PINCTRL_PFC_SHX3
1231 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
1236 static struct platform_driver sh_pfc_driver = {
1237 .probe = sh_pfc_probe,
1238 .id_table = sh_pfc_id_table,
1241 .of_match_table = of_match_ptr(sh_pfc_of_table),
1246 static int __init sh_pfc_init(void)
1248 sh_pfc_check_driver(&sh_pfc_driver);
1249 return platform_driver_register(&sh_pfc_driver);
1251 postcore_initcall(sh_pfc_init);