drivers/pinctrl/renesas/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pin Control and GPIO driver for SuperH Pin Function Controller.
   4  *
   5  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   6  *
   7  * Copyright (C) 2008 Magnus Damm
   8  * Copyright (C) 2009 - 2012 Paul Mundt
   9  */
  10
  11 #define DRV_NAME "sh-pfc"
  12
  13 #include <linux/bitops.h>
  14 #include <linux/err.h>
  15 #include <linux/errno.h>
  16 #include <linux/io.h>
  17 #include <linux/ioport.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/pinctrl/machine.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/psci.h>
  25 #include <linux/slab.h>
  26 #include <linux/sys_soc.h>
  27
  28 #include "core.h"
  29
  30 static int sh_pfc_map_resources(struct sh_pfc *pfc,
  31                                 struct platform_device *pdev)
  32 {
  33         struct sh_pfc_window *windows;
  34         unsigned int *irqs = NULL;
  35         unsigned int num_windows;
  36         struct resource *res;
  37         unsigned int i;
  38         int num_irqs;
  39
  40         /* Count the MEM and IRQ resources. */
  41         for (num_windows = 0;; num_windows++) {
  42                 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
  43                 if (!res)
  44                         break;
  45         }
  46         if (num_windows == 0)
  47                 return -EINVAL;
  48
  49         num_irqs = platform_irq_count(pdev);
  50         if (num_irqs < 0)
  51                 return num_irqs;
  52
  53         /* Allocate memory windows and IRQs arrays. */
  54         windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
  55                                GFP_KERNEL);
  56         if (windows == NULL)
  57                 return -ENOMEM;
  58
  59         pfc->num_windows = num_windows;
  60         pfc->windows = windows;
  61
  62         if (num_irqs) {
  63                 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
  64                                     GFP_KERNEL);
  65                 if (irqs == NULL)
  66                         return -ENOMEM;
  67
  68                 pfc->num_irqs = num_irqs;
  69                 pfc->irqs = irqs;
  70         }
  71
  72         /* Fill them. */
  73         for (i = 0; i < num_windows; i++) {
  74                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
  75                 windows->phys = res->start;
  76                 windows->size = resource_size(res);
  77                 windows->virt = devm_ioremap_resource(pfc->dev, res);
  78                 if (IS_ERR(windows->virt))
  79                         return -ENOMEM;
  80                 windows++;
  81         }
  82         for (i = 0; i < num_irqs; i++)
  83                 *irqs++ = platform_get_irq(pdev, i);
  84
  85         return 0;
  86 }
  87
  88 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
  89 {
  90         struct sh_pfc_window *window;
  91         phys_addr_t address = reg;
  92         unsigned int i;
  93
  94         /* scan through physical windows and convert address */
  95         for (i = 0; i < pfc->num_windows; i++) {
  96                 window = pfc->windows + i;
  97
  98                 if (address < window->phys)
  99                         continue;
 100
 101                 if (address >= (window->phys + window->size))
 102                         continue;
 103
 104                 return window->virt + (address - window->phys);
 105         }
 106
 107         BUG();
 108         return NULL;
 109 }
 110
 111 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
 112 {
 113         unsigned int offset;
 114         unsigned int i;
 115
 116         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
 117                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
 118
 119                 if (pin <= range->end)
 120                         return pin >= range->start
 121                              ? offset + pin - range->start : -1;
 122
 123                 offset += range->end - range->start + 1;
 124         }
 125
 126         return -EINVAL;
 127 }
 128
 129 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
 130 {
 131         if (enum_id < r->begin)
 132                 return 0;
 133
 134         if (enum_id > r->end)
 135                 return 0;
 136
 137         return 1;
 138 }
 139
 140 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
 141 {
 142         switch (reg_width) {
 143         case 8:
 144                 return ioread8(mapped_reg);
 145         case 16:
 146                 return ioread16(mapped_reg);
 147         case 32:
 148                 return ioread32(mapped_reg);
 149         }
 150
 151         BUG();
 152         return 0;
 153 }
 154
 155 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 156                           u32 data)
 157 {
 158         switch (reg_width) {
 159         case 8:
 160                 iowrite8(data, mapped_reg);
 161                 return;
 162         case 16:
 163                 iowrite16(data, mapped_reg);
 164                 return;
 165         case 32:
 166                 iowrite32(data, mapped_reg);
 167                 return;
 168         }
 169
 170         BUG();
 171 }
 172
 173 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
 174 {
 175         return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
 176 }
 177
 178 static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
 179 {
 180         u32 unlock;
 181
 182         if (!pfc->info->unlock_reg)
 183                 return;
 184
 185         if (pfc->info->unlock_reg >= 0x80000000UL)
 186                 unlock = pfc->info->unlock_reg;
 187         else
 188                 /* unlock_reg is a mask */
 189                 unlock = reg & ~pfc->info->unlock_reg;
 190
 191         sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data);
 192 }
 193
 194 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
 195 {
 196         sh_pfc_unlock_reg(pfc, reg, data);
 197         sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
 198 }
 199
 200 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 201                                      const struct pinmux_cfg_reg *crp,
 202                                      unsigned int in_pos,
 203                                      void __iomem **mapped_regp, u32 *maskp,
 204                                      unsigned int *posp)
 205 {
 206         unsigned int k;
 207
 208         *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
 209
 210         if (crp->field_width) {
 211                 *maskp = (1 << crp->field_width) - 1;
 212                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 213         } else {
 214                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 215                 *posp = crp->reg_width;
 216                 for (k = 0; k <= in_pos; k++)
 217                         *posp -= crp->var_field_width[k];
 218         }
 219 }
 220
 221 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 222                                     const struct pinmux_cfg_reg *crp,
 223                                     unsigned int field, u32 value)
 224 {
 225         void __iomem *mapped_reg;
 226         unsigned int pos;
 227         u32 mask, data;
 228
 229         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 230
 231         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 232                 "r_width = %u, f_width = %u\n",
 233                 crp->reg, value, field, crp->reg_width, hweight32(mask));
 234
 235         mask = ~(mask << pos);
 236         value = value << pos;
 237
 238         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 239         data &= mask;
 240         data |= value;
 241
 242         sh_pfc_unlock_reg(pfc, crp->reg, data);
 243         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 244 }
 245
 246 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 247                                  const struct pinmux_cfg_reg **crp,
 248                                  unsigned int *fieldp, u32 *valuep)
 249 {
 250         unsigned int k = 0;
 251
 252         while (1) {
 253                 const struct pinmux_cfg_reg *config_reg =
 254                         pfc->info->cfg_regs + k;
 255                 unsigned int r_width = config_reg->reg_width;
 256                 unsigned int f_width = config_reg->field_width;
 257                 unsigned int curr_width;
 258                 unsigned int bit_pos;
 259                 unsigned int pos = 0;
 260                 unsigned int m = 0;
 261
 262                 if (!r_width)
 263                         break;
 264
 265                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 266                         u32 ncomb;
 267                         u32 n;
 268
 269                         if (f_width)
 270                                 curr_width = f_width;
 271                         else
 272                                 curr_width = config_reg->var_field_width[m];
 273
 274                         ncomb = 1 << curr_width;
 275                         for (n = 0; n < ncomb; n++) {
 276                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 277                                         *crp = config_reg;
 278                                         *fieldp = m;
 279                                         *valuep = n;
 280                                         return 0;
 281                                 }
 282                         }
 283                         pos += ncomb;
 284                         m++;
 285                 }
 286                 k++;
 287         }
 288
 289         return -EINVAL;
 290 }
 291
 292 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 293                               u16 *enum_idp)
 294 {
 295         const u16 *data = pfc->info->pinmux_data;
 296         unsigned int k;
 297
 298         if (pos) {
 299                 *enum_idp = data[pos + 1];
 300                 return pos + 1;
 301         }
 302
 303         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 304                 if (data[k] == mark) {
 305                         *enum_idp = data[k + 1];
 306                         return k + 1;
 307                 }
 308         }
 309
 310         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 311                 mark);
 312         return -EINVAL;
 313 }
 314
 315 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 316 {
 317         const struct pinmux_range *range;
 318         int pos = 0;
 319
 320         switch (pinmux_type) {
 321         case PINMUX_TYPE_GPIO:
 322         case PINMUX_TYPE_FUNCTION:
 323                 range = NULL;
 324                 break;
 325
 326 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
 327         case PINMUX_TYPE_OUTPUT:
 328                 range = &pfc->info->output;
 329                 break;
 330
 331         case PINMUX_TYPE_INPUT:
 332                 range = &pfc->info->input;
 333                 break;
 334 #endif /* CONFIG_PINCTRL_SH_PFC_GPIO */
 335
 336         default:
 337                 return -EINVAL;
 338         }
 339
 340         /* Iterate over all the configuration fields we need to update. */
 341         while (1) {
 342                 const struct pinmux_cfg_reg *cr;
 343                 unsigned int field;
 344                 u16 enum_id;
 345                 u32 value;
 346                 int in_range;
 347                 int ret;
 348
 349                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 350                 if (pos < 0)
 351                         return pos;
 352
 353                 if (!enum_id)
 354                         break;
 355
 356                 /* Check if the configuration field selects a function. If it
 357                  * doesn't, skip the field if it's not applicable to the
 358                  * requested pinmux type.
 359                  */
 360                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 361                 if (!in_range) {
 362                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 363                                 /* Functions are allowed to modify all
 364                                  * fields.
 365                                  */
 366                                 in_range = 1;
 367                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 368                                 /* Input/output types can only modify fields
 369                                  * that correspond to their respective ranges.
 370                                  */
 371                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 372
 373                                 /*
 374                                  * special case pass through for fixed
 375                                  * input-only or output-only pins without
 376                                  * function enum register association.
 377                                  */
 378                                 if (in_range && enum_id == range->force)
 379                                         continue;
 380                         }
 381                         /* GPIOs are only allowed to modify function fields. */
 382                 }
 383
 384                 if (!in_range)
 385                         continue;
 386
 387                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 388                 if (ret < 0)
 389                         return ret;
 390
 391                 sh_pfc_write_config_reg(pfc, cr, field, value);
 392         }
 393
 394         return 0;
 395 }
 396
 397 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 398 {
 399         struct sh_pfc_pin_range *range;
 400         unsigned int nr_ranges;
 401         unsigned int i;
 402
 403         if (pfc->info->pins[0].pin == (u16)-1) {
 404                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 405                  * in its pin arrays yet. Consider the pin numbers range as
 406                  * continuous and allocate a single range.
 407                  */
 408                 pfc->nr_ranges = 1;
 409                 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
 410                                            GFP_KERNEL);
 411                 if (pfc->ranges == NULL)
 412                         return -ENOMEM;
 413
 414                 pfc->ranges->start = 0;
 415                 pfc->ranges->end = pfc->info->nr_pins - 1;
 416                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 417
 418                 return 0;
 419         }
 420
 421         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 422          * be sorted by pin numbers, and pins without a GPIO port must come
 423          * last.
 424          */
 425         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 426                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 427                         nr_ranges++;
 428         }
 429
 430         pfc->nr_ranges = nr_ranges;
 431         pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
 432                                    GFP_KERNEL);
 433         if (pfc->ranges == NULL)
 434                 return -ENOMEM;
 435
 436         range = pfc->ranges;
 437         range->start = pfc->info->pins[0].pin;
 438
 439         for (i = 1; i < pfc->info->nr_pins; ++i) {
 440                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 441                         continue;
 442
 443                 range->end = pfc->info->pins[i-1].pin;
 444                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 445                         pfc->nr_gpio_pins = range->end + 1;
 446
 447                 range++;
 448                 range->start = pfc->info->pins[i].pin;
 449         }
 450
 451         range->end = pfc->info->pins[i-1].pin;
 452         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 453                 pfc->nr_gpio_pins = range->end + 1;
 454
 455         return 0;
 456 }
 457
 458 #ifdef CONFIG_OF
 459 static const struct of_device_id sh_pfc_of_table[] = {
 460 #ifdef CONFIG_PINCTRL_PFC_EMEV2
 461         {
 462                 .compatible = "renesas,pfc-emev2",
 463                 .data = &emev2_pinmux_info,
 464         },
 465 #endif
 466 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
 467         {
 468                 .compatible = "renesas,pfc-r8a73a4",
 469                 .data = &r8a73a4_pinmux_info,
 470         },
 471 #endif
 472 #ifdef CONFIG_PINCTRL_PFC_R8A7740
 473         {
 474                 .compatible = "renesas,pfc-r8a7740",
 475                 .data = &r8a7740_pinmux_info,
 476         },
 477 #endif
 478 #ifdef CONFIG_PINCTRL_PFC_R8A7742
 479         {
 480                 .compatible = "renesas,pfc-r8a7742",
 481                 .data = &r8a7742_pinmux_info,
 482         },
 483 #endif
 484 #ifdef CONFIG_PINCTRL_PFC_R8A7743
 485         {
 486                 .compatible = "renesas,pfc-r8a7743",
 487                 .data = &r8a7743_pinmux_info,
 488         },
 489 #endif
 490 #ifdef CONFIG_PINCTRL_PFC_R8A7744
 491         {
 492                 .compatible = "renesas,pfc-r8a7744",
 493                 .data = &r8a7744_pinmux_info,
 494         },
 495 #endif
 496 #ifdef CONFIG_PINCTRL_PFC_R8A7745
 497         {
 498                 .compatible = "renesas,pfc-r8a7745",
 499                 .data = &r8a7745_pinmux_info,
 500         },
 501 #endif
 502 #ifdef CONFIG_PINCTRL_PFC_R8A77470
 503         {
 504                 .compatible = "renesas,pfc-r8a77470",
 505                 .data = &r8a77470_pinmux_info,
 506         },
 507 #endif
 508 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
 509         {
 510                 .compatible = "renesas,pfc-r8a774a1",
 511                 .data = &r8a774a1_pinmux_info,
 512         },
 513 #endif
 514 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
 515         {
 516                 .compatible = "renesas,pfc-r8a774b1",
 517                 .data = &r8a774b1_pinmux_info,
 518         },
 519 #endif
 520 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
 521         {
 522                 .compatible = "renesas,pfc-r8a774c0",
 523                 .data = &r8a774c0_pinmux_info,
 524         },
 525 #endif
 526 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
 527         {
 528                 .compatible = "renesas,pfc-r8a774e1",
 529                 .data = &r8a774e1_pinmux_info,
 530         },
 531 #endif
 532 #ifdef CONFIG_PINCTRL_PFC_R8A7778
 533         {
 534                 .compatible = "renesas,pfc-r8a7778",
 535                 .data = &r8a7778_pinmux_info,
 536         },
 537 #endif
 538 #ifdef CONFIG_PINCTRL_PFC_R8A7779
 539         {
 540                 .compatible = "renesas,pfc-r8a7779",
 541                 .data = &r8a7779_pinmux_info,
 542         },
 543 #endif
 544 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 545         {
 546                 .compatible = "renesas,pfc-r8a7790",
 547                 .data = &r8a7790_pinmux_info,
 548         },
 549 #endif
 550 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 551         {
 552                 .compatible = "renesas,pfc-r8a7791",
 553                 .data = &r8a7791_pinmux_info,
 554         },
 555 #endif
 556 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 557         {
 558                 .compatible = "renesas,pfc-r8a7792",
 559                 .data = &r8a7792_pinmux_info,
 560         },
 561 #endif
 562 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 563         {
 564                 .compatible = "renesas,pfc-r8a7793",
 565                 .data = &r8a7793_pinmux_info,
 566         },
 567 #endif
 568 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 569         {
 570                 .compatible = "renesas,pfc-r8a7794",
 571                 .data = &r8a7794_pinmux_info,
 572         },
 573 #endif
 574 /* Both r8a7795 entries must be present to make sanity checks work */
 575 #ifdef CONFIG_PINCTRL_PFC_R8A77950
 576         {
 577                 .compatible = "renesas,pfc-r8a7795",
 578                 .data = &r8a77950_pinmux_info,
 579         },
 580 #endif
 581 #ifdef CONFIG_PINCTRL_PFC_R8A77951
 582         {
 583                 .compatible = "renesas,pfc-r8a7795",
 584                 .data = &r8a77951_pinmux_info,
 585         },
 586 #endif
 587 #ifdef CONFIG_PINCTRL_PFC_R8A77960
 588         {
 589                 .compatible = "renesas,pfc-r8a7796",
 590                 .data = &r8a77960_pinmux_info,
 591         },
 592 #endif
 593 #ifdef CONFIG_PINCTRL_PFC_R8A77961
 594         {
 595                 .compatible = "renesas,pfc-r8a77961",
 596                 .data = &r8a77961_pinmux_info,
 597         },
 598 #endif
 599 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 600         {
 601                 .compatible = "renesas,pfc-r8a77965",
 602                 .data = &r8a77965_pinmux_info,
 603         },
 604 #endif
 605 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 606         {
 607                 .compatible = "renesas,pfc-r8a77970",
 608                 .data = &r8a77970_pinmux_info,
 609         },
 610 #endif
 611 #ifdef CONFIG_PINCTRL_PFC_R8A77980
 612         {
 613                 .compatible = "renesas,pfc-r8a77980",
 614                 .data = &r8a77980_pinmux_info,
 615         },
 616 #endif
 617 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 618         {
 619                 .compatible = "renesas,pfc-r8a77990",
 620                 .data = &r8a77990_pinmux_info,
 621         },
 622 #endif
 623 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 624         {
 625                 .compatible = "renesas,pfc-r8a77995",
 626                 .data = &r8a77995_pinmux_info,
 627         },
 628 #endif
 629 #ifdef CONFIG_PINCTRL_PFC_R8A779A0
 630         {
 631                 .compatible = "renesas,pfc-r8a779a0",
 632                 .data = &r8a779a0_pinmux_info,
 633         },
 634 #endif
 635 #ifdef CONFIG_PINCTRL_PFC_SH73A0
 636         {
 637                 .compatible = "renesas,pfc-sh73a0",
 638                 .data = &sh73a0_pinmux_info,
 639         },
 640 #endif
 641         { },
 642 };
 643 #endif
 644
 645 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
 646 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 647 {
 648 }
 649
 650 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 651 {
 652         pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
 653 }
 654
 655 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 656 {
 657         sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
 658 }
 659
 660 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
 661         void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
 662 {
 663         unsigned int i, n = 0;
 664
 665         if (pfc->info->cfg_regs)
 666                 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
 667                         do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
 668
 669         if (pfc->info->drive_regs)
 670                 for (i = 0; pfc->info->drive_regs[i].reg; i++)
 671                         do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
 672
 673         if (pfc->info->bias_regs)
 674                 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
 675                         do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
 676                         if (pfc->info->bias_regs[i].pud)
 677                                 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
 678                 }
 679
 680         if (pfc->info->ioctrl_regs)
 681                 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
 682                         do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
 683
 684         return n;
 685 }
 686
 687 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
 688 {
 689         unsigned int n;
 690
 691         /* This is the best we can do to check for the presence of PSCI */
 692         if (!psci_ops.cpu_suspend)
 693                 return 0;
 694
 695         n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
 696         if (!n)
 697                 return 0;
 698
 699         pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
 700                                              sizeof(*pfc->saved_regs),
 701                                              GFP_KERNEL);
 702         if (!pfc->saved_regs)
 703                 return -ENOMEM;
 704
 705         dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
 706         return 0;
 707 }
 708
 709 static int sh_pfc_suspend_noirq(struct device *dev)
 710 {
 711         struct sh_pfc *pfc = dev_get_drvdata(dev);
 712
 713         if (pfc->saved_regs)
 714                 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
 715         return 0;
 716 }
 717
 718 static int sh_pfc_resume_noirq(struct device *dev)
 719 {
 720         struct sh_pfc *pfc = dev_get_drvdata(dev);
 721
 722         if (pfc->saved_regs)
 723                 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
 724         return 0;
 725 }
 726
 727 static const struct dev_pm_ops sh_pfc_pm  = {
 728         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
 729 };
 730 #define DEV_PM_OPS      &sh_pfc_pm
 731 #else
 732 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
 733 #define DEV_PM_OPS      NULL
 734 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
 735
 736 #ifdef DEBUG
 737 #define SH_PFC_MAX_REGS         300
 738 #define SH_PFC_MAX_ENUMS        3000
 739
 740 static unsigned int sh_pfc_errors __initdata = 0;
 741 static unsigned int sh_pfc_warnings __initdata = 0;
 742 static u32 *sh_pfc_regs __initdata = NULL;
 743 static u32 sh_pfc_num_regs __initdata = 0;
 744 static u16 *sh_pfc_enums __initdata = NULL;
 745 static u32 sh_pfc_num_enums __initdata = 0;
 746
 747 #define sh_pfc_err(fmt, ...)                                    \
 748         do {                                                    \
 749                 pr_err("%s: " fmt, drvname, ##__VA_ARGS__);     \
 750                 sh_pfc_errors++;                                \
 751         } while (0)
 752 #define sh_pfc_warn(fmt, ...)                                   \
 753         do {                                                    \
 754                 pr_warn("%s: " fmt, drvname, ##__VA_ARGS__);    \
 755                 sh_pfc_warnings++;                              \
 756         } while (0)
 757
 758 static bool __init is0s(const u16 *enum_ids, unsigned int n)
 759 {
 760         unsigned int i;
 761
 762         for (i = 0; i < n; i++)
 763                 if (enum_ids[i])
 764                         return false;
 765
 766         return true;
 767 }
 768
 769 static bool __init same_name(const char *a, const char *b)
 770 {
 771         if (!a || !b)
 772                 return false;
 773
 774         return !strcmp(a, b);
 775 }
 776
 777 static void __init sh_pfc_check_reg(const char *drvname, u32 reg)
 778 {
 779         unsigned int i;
 780
 781         for (i = 0; i < sh_pfc_num_regs; i++)
 782                 if (reg == sh_pfc_regs[i]) {
 783                         sh_pfc_err("reg 0x%x conflict\n", reg);
 784                         return;
 785                 }
 786
 787         if (sh_pfc_num_regs == SH_PFC_MAX_REGS) {
 788                 pr_warn_once("%s: Please increase SH_PFC_MAX_REGS\n", drvname);
 789                 return;
 790         }
 791
 792         sh_pfc_regs[sh_pfc_num_regs++] = reg;
 793 }
 794
 795 static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id)
 796 {
 797         unsigned int i;
 798
 799         for (i = 0; i < sh_pfc_num_enums; i++) {
 800                 if (enum_id == sh_pfc_enums[i])
 801                         return -EINVAL;
 802         }
 803
 804         if (sh_pfc_num_enums == SH_PFC_MAX_ENUMS) {
 805                 pr_warn_once("%s: Please increase SH_PFC_MAX_ENUMS\n", drvname);
 806                 return 0;
 807         }
 808
 809         sh_pfc_enums[sh_pfc_num_enums++] = enum_id;
 810         return 0;
 811 }
 812
 813 static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg,
 814                                           const u16 *enums, unsigned int n)
 815 {
 816         unsigned int i;
 817
 818         for (i = 0; i < n; i++) {
 819                 if (enums[i] && sh_pfc_check_enum(drvname, enums[i]))
 820                         sh_pfc_err("reg 0x%x enum_id %u conflict\n", reg,
 821                                    enums[i]);
 822         }
 823 }
 824
 825 static void __init sh_pfc_check_pin(const struct sh_pfc_soc_info *info,
 826                                     u32 reg, unsigned int pin)
 827 {
 828         const char *drvname = info->name;
 829         unsigned int i;
 830
 831         if (pin == SH_PFC_PIN_NONE)
 832                 return;
 833
 834         for (i = 0; i < info->nr_pins; i++) {
 835                 if (pin == info->pins[i].pin)
 836                         return;
 837         }
 838
 839         sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);
 840 }
 841
 842 static void __init sh_pfc_check_cfg_reg(const char *drvname,
 843                                         const struct pinmux_cfg_reg *cfg_reg)
 844 {
 845         unsigned int i, n, rw, fw;
 846
 847         sh_pfc_check_reg(drvname, cfg_reg->reg);
 848
 849         if (cfg_reg->field_width) {
 850                 n = cfg_reg->reg_width / cfg_reg->field_width;
 851                 /* Skip field checks (done at build time) */
 852                 goto check_enum_ids;
 853         }
 854
 855         for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
 856                 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw))
 857                         sh_pfc_warn("reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
 858                                     cfg_reg->reg, rw, rw + fw - 1);
 859                 n += 1 << fw;
 860                 rw += fw;
 861         }
 862
 863         if (rw != cfg_reg->reg_width)
 864                 sh_pfc_err("reg 0x%x: var_field_width declares %u instead of %u bits\n",
 865                            cfg_reg->reg, rw, cfg_reg->reg_width);
 866
 867         if (n != cfg_reg->nr_enum_ids)
 868                 sh_pfc_err("reg 0x%x: enum_ids[] has %u instead of %u values\n",
 869                            cfg_reg->reg, cfg_reg->nr_enum_ids, n);
 870
 871 check_enum_ids:
 872         sh_pfc_check_reg_enums(drvname, cfg_reg->reg, cfg_reg->enum_ids, n);
 873 }
 874
 875 static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
 876                                           const struct pinmux_drive_reg *drive)
 877 {
 878         const char *drvname = info->name;
 879         unsigned long seen = 0, mask;
 880         unsigned int i;
 881
 882         sh_pfc_check_reg(info->name, drive->reg);
 883         for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
 884                 const struct pinmux_drive_reg_field *field = &drive->fields[i];
 885
 886                 if (!field->pin && !field->offset && !field->size)
 887                         continue;
 888
 889                 mask = GENMASK(field->offset + field->size, field->offset);
 890                 if (mask & seen)
 891                         sh_pfc_err("drive_reg 0x%x: field %u overlap\n",
 892                                    drive->reg, i);
 893                 seen |= mask;
 894
 895                 sh_pfc_check_pin(info, drive->reg, field->pin);
 896         }
 897 }
 898
 899 static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
 900                                          const struct pinmux_bias_reg *bias)
 901 {
 902         unsigned int i;
 903
 904         sh_pfc_check_reg(info->name, bias->puen);
 905         if (bias->pud)
 906                 sh_pfc_check_reg(info->name, bias->pud);
 907         for (i = 0; i < ARRAY_SIZE(bias->pins); i++)
 908                 sh_pfc_check_pin(info, bias->puen, bias->pins[i]);
 909 }
 910
 911 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
 912 {
 913         const char *drvname = info->name;
 914         unsigned int *refcnts;
 915         unsigned int i, j, k;
 916
 917         pr_info("Checking %s\n", drvname);
 918         sh_pfc_num_regs = 0;
 919         sh_pfc_num_enums = 0;
 920
 921         /* Check pins */
 922         for (i = 0; i < info->nr_pins; i++) {
 923                 const struct sh_pfc_pin *pin = &info->pins[i];
 924
 925                 if (!pin->name) {
 926                         sh_pfc_err("empty pin %u\n", i);
 927                         continue;
 928                 }
 929                 for (j = 0; j < i; j++) {
 930                         const struct sh_pfc_pin *pin2 = &info->pins[j];
 931
 932                         if (same_name(pin->name, pin2->name))
 933                                 sh_pfc_err("pin %s: name conflict\n",
 934                                            pin->name);
 935
 936                         if (pin->pin != (u16)-1 && pin->pin == pin2->pin)
 937                                 sh_pfc_err("pin %s/%s: pin %u conflict\n",
 938                                            pin->name, pin2->name, pin->pin);
 939
 940                         if (pin->enum_id && pin->enum_id == pin2->enum_id)
 941                                 sh_pfc_err("pin %s/%s: enum_id %u conflict\n",
 942                                            pin->name, pin2->name,
 943                                            pin->enum_id);
 944                 }
 945         }
 946
 947         /* Check groups and functions */
 948         refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
 949         if (!refcnts)
 950                 return;
 951
 952         for (i = 0; i < info->nr_functions; i++) {
 953                 const struct sh_pfc_function *func = &info->functions[i];
 954
 955                 if (!func->name) {
 956                         sh_pfc_err("empty function %u\n", i);
 957                         continue;
 958                 }
 959                 for (j = 0; j < i; j++) {
 960                         if (same_name(func->name, info->functions[j].name))
 961                                 sh_pfc_err("function %s: name conflict\n",
 962                                            func->name);
 963                 }
 964                 for (j = 0; j < func->nr_groups; j++) {
 965                         for (k = 0; k < info->nr_groups; k++) {
 966                                 if (same_name(func->groups[j],
 967                                               info->groups[k].name)) {
 968                                         refcnts[k]++;
 969                                         break;
 970                                 }
 971                         }
 972
 973                         if (k == info->nr_groups)
 974                                 sh_pfc_err("function %s: group %s not found\n",
 975                                            func->name, func->groups[j]);
 976                 }
 977         }
 978
 979         for (i = 0; i < info->nr_groups; i++) {
 980                 const struct sh_pfc_pin_group *group = &info->groups[i];
 981
 982                 if (!group->name) {
 983                         sh_pfc_err("empty group %u\n", i);
 984                         continue;
 985                 }
 986                 for (j = 0; j < i; j++) {
 987                         if (same_name(group->name, info->groups[j].name))
 988                                 sh_pfc_err("group %s: name conflict\n",
 989                                            group->name);
 990                 }
 991                 if (!refcnts[i])
 992                         sh_pfc_err("orphan group %s\n", group->name);
 993                 else if (refcnts[i] > 1)
 994                         sh_pfc_warn("group %s referenced by %u functions\n",
 995                                     group->name, refcnts[i]);
 996         }
 997
 998         kfree(refcnts);
 999
1000         /* Check config register descriptions */
1001         for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
1002                 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
1003
1004         /* Check drive strength registers */
1005         for (i = 0; info->drive_regs && info->drive_regs[i].reg; i++)
1006                 sh_pfc_check_drive_reg(info, &info->drive_regs[i]);
1007
1008         /* Check bias registers */
1009         for (i = 0; info->bias_regs && info->bias_regs[i].puen; i++)
1010                 sh_pfc_check_bias_reg(info, &info->bias_regs[i]);
1011
1012         /* Check ioctrl registers */
1013         for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
1014                 sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg);
1015
1016         /* Check data registers */
1017         for (i = 0; info->data_regs && info->data_regs[i].reg; i++) {
1018                 sh_pfc_check_reg(drvname, info->data_regs[i].reg);
1019                 sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg,
1020                                        info->data_regs[i].enum_ids,
1021                                        info->data_regs[i].reg_width);
1022         }
1023
1024 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
1025         /* Check function GPIOs */
1026         for (i = 0; i < info->nr_func_gpios; i++) {
1027                 const struct pinmux_func *func = &info->func_gpios[i];
1028
1029                 if (!func->name) {
1030                         sh_pfc_err("empty function gpio %u\n", i);
1031                         continue;
1032                 }
1033                 for (j = 0; j < i; j++) {
1034                         if (same_name(func->name, info->func_gpios[j].name))
1035                                 sh_pfc_err("func_gpio %s: name conflict\n",
1036                                            func->name);
1037                 }
1038                 if (sh_pfc_check_enum(drvname, func->enum_id))
1039                         sh_pfc_err("%s enum_id %u conflict\n", func->name,
1040                                    func->enum_id);
1041         }
1042 #endif
1043 }
1044
1045 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
1046 {
1047         unsigned int i;
1048
1049         if (!IS_ENABLED(CONFIG_SUPERH) &&
1050             !of_find_matching_node(NULL, pdrv->driver.of_match_table))
1051                 return;
1052
1053         sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs),
1054                               GFP_KERNEL);
1055         if (!sh_pfc_regs)
1056                 return;
1057
1058         sh_pfc_enums = kcalloc(SH_PFC_MAX_ENUMS, sizeof(*sh_pfc_enums),
1059                               GFP_KERNEL);
1060         if (!sh_pfc_enums)
1061                 goto free_regs;
1062
1063         pr_warn("Checking builtin pinmux tables\n");
1064
1065         for (i = 0; pdrv->id_table[i].name[0]; i++)
1066                 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
1067
1068 #ifdef CONFIG_OF
1069         for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
1070                 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
1071 #endif
1072
1073         pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
1074                 sh_pfc_warnings);
1075
1076         kfree(sh_pfc_enums);
1077 free_regs:
1078         kfree(sh_pfc_regs);
1079 }
1080
1081 #else /* !DEBUG */
1082 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
1083 #endif /* !DEBUG */
1084
1085 #ifdef CONFIG_OF
1086 static const void *sh_pfc_quirk_match(void)
1087 {
1088 #if defined(CONFIG_PINCTRL_PFC_R8A77950) || \
1089     defined(CONFIG_PINCTRL_PFC_R8A77951)
1090         const struct soc_device_attribute *match;
1091         static const struct soc_device_attribute quirks[] = {
1092                 {
1093                         .soc_id = "r8a7795", .revision = "ES1.*",
1094                         .data = &r8a77950_pinmux_info,
1095                 },
1096                 {
1097                         .soc_id = "r8a7795",
1098                         .data = &r8a77951_pinmux_info,
1099                 },
1100
1101                 { /* sentinel */ }
1102         };
1103
1104         match = soc_device_match(quirks);
1105         if (match)
1106                 return match->data ?: ERR_PTR(-ENODEV);
1107 #endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */
1108
1109         return NULL;
1110 }
1111 #endif /* CONFIG_OF */
1112
1113 static int sh_pfc_probe(struct platform_device *pdev)
1114 {
1115         const struct sh_pfc_soc_info *info;
1116         struct sh_pfc *pfc;
1117         int ret;
1118
1119 #ifdef CONFIG_OF
1120         if (pdev->dev.of_node) {
1121                 info = sh_pfc_quirk_match();
1122                 if (IS_ERR(info))
1123                         return PTR_ERR(info);
1124
1125                 if (!info)
1126                         info = of_device_get_match_data(&pdev->dev);
1127         } else
1128 #endif
1129                 info = (const void *)platform_get_device_id(pdev)->driver_data;
1130
1131         pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
1132         if (pfc == NULL)
1133                 return -ENOMEM;
1134
1135         pfc->info = info;
1136         pfc->dev = &pdev->dev;
1137
1138         ret = sh_pfc_map_resources(pfc, pdev);
1139         if (unlikely(ret < 0))
1140                 return ret;
1141
1142         spin_lock_init(&pfc->lock);
1143
1144         if (info->ops && info->ops->init) {
1145                 ret = info->ops->init(pfc);
1146                 if (ret < 0)
1147                         return ret;
1148
1149                 /* .init() may have overridden pfc->info */
1150                 info = pfc->info;
1151         }
1152
1153         ret = sh_pfc_suspend_init(pfc);
1154         if (ret)
1155                 return ret;
1156
1157         /* Enable dummy states for those platforms without pinctrl support */
1158         if (!of_have_populated_dt())
1159                 pinctrl_provide_dummies();
1160
1161         ret = sh_pfc_init_ranges(pfc);
1162         if (ret < 0)
1163                 return ret;
1164
1165         /*
1166          * Initialize pinctrl bindings first
1167          */
1168         ret = sh_pfc_register_pinctrl(pfc);
1169         if (unlikely(ret != 0))
1170                 return ret;
1171
1172 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
1173         /*
1174          * Then the GPIO chip
1175          */
1176         ret = sh_pfc_register_gpiochip(pfc);
1177         if (unlikely(ret != 0)) {
1178                 /*
1179                  * If the GPIO chip fails to come up we still leave the
1180                  * PFC state as it is, given that there are already
1181                  * extant users of it that have succeeded by this point.
1182                  */
1183                 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
1184         }
1185 #endif
1186
1187         platform_set_drvdata(pdev, pfc);
1188
1189         dev_info(pfc->dev, "%s support registered\n", info->name);
1190
1191         return 0;
1192 }
1193
1194 static const struct platform_device_id sh_pfc_id_table[] = {
1195 #ifdef CONFIG_PINCTRL_PFC_SH7203
1196         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
1197 #endif
1198 #ifdef CONFIG_PINCTRL_PFC_SH7264
1199         { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
1200 #endif
1201 #ifdef CONFIG_PINCTRL_PFC_SH7269
1202         { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
1203 #endif
1204 #ifdef CONFIG_PINCTRL_PFC_SH7720
1205         { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
1206 #endif
1207 #ifdef CONFIG_PINCTRL_PFC_SH7722
1208         { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
1209 #endif
1210 #ifdef CONFIG_PINCTRL_PFC_SH7723
1211         { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
1212 #endif
1213 #ifdef CONFIG_PINCTRL_PFC_SH7724
1214         { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
1215 #endif
1216 #ifdef CONFIG_PINCTRL_PFC_SH7734
1217         { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
1218 #endif
1219 #ifdef CONFIG_PINCTRL_PFC_SH7757
1220         { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
1221 #endif
1222 #ifdef CONFIG_PINCTRL_PFC_SH7785
1223         { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
1224 #endif
1225 #ifdef CONFIG_PINCTRL_PFC_SH7786
1226         { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
1227 #endif
1228 #ifdef CONFIG_PINCTRL_PFC_SHX3
1229         { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
1230 #endif
1231         { },
1232 };
1233
1234 static struct platform_driver sh_pfc_driver = {
1235         .probe          = sh_pfc_probe,
1236         .id_table       = sh_pfc_id_table,
1237         .driver         = {
1238                 .name   = DRV_NAME,
1239                 .of_match_table = of_match_ptr(sh_pfc_of_table),
1240                 .pm     = DEV_PM_OPS,
1241         },
1242 };
1243
1244 static int __init sh_pfc_init(void)
1245 {
1246         sh_pfc_check_driver(&sh_pfc_driver);
1247         return platform_driver_register(&sh_pfc_driver);
1248 }
1249 postcore_initcall(sh_pfc_init);