drivers/pinctrl/renesas/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pin Control and GPIO driver for SuperH Pin Function Controller.
   4  *
   5  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   6  *
   7  * Copyright (C) 2008 Magnus Damm
   8  * Copyright (C) 2009 - 2012 Paul Mundt
   9  */
  10
  11 #define DRV_NAME "sh-pfc"
  12
  13 #include <linux/bitops.h>
  14 #include <linux/err.h>
  15 #include <linux/errno.h>
  16 #include <linux/io.h>
  17 #include <linux/ioport.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/pinctrl/machine.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/psci.h>
  25 #include <linux/slab.h>
  26 #include <linux/sys_soc.h>
  27
  28 #include "core.h"
  29
  30 static int sh_pfc_map_resources(struct sh_pfc *pfc,
  31                                 struct platform_device *pdev)
  32 {
  33         struct sh_pfc_window *windows;
  34         unsigned int *irqs = NULL;
  35         unsigned int num_windows;
  36         struct resource *res;
  37         unsigned int i;
  38         int num_irqs;
  39
  40         /* Count the MEM and IRQ resources. */
  41         for (num_windows = 0;; num_windows++) {
  42                 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
  43                 if (!res)
  44                         break;
  45         }
  46         if (num_windows == 0)
  47                 return -EINVAL;
  48
  49         num_irqs = platform_irq_count(pdev);
  50         if (num_irqs < 0)
  51                 return num_irqs;
  52
  53         /* Allocate memory windows and IRQs arrays. */
  54         windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
  55                                GFP_KERNEL);
  56         if (windows == NULL)
  57                 return -ENOMEM;
  58
  59         pfc->num_windows = num_windows;
  60         pfc->windows = windows;
  61
  62         if (num_irqs) {
  63                 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
  64                                     GFP_KERNEL);
  65                 if (irqs == NULL)
  66                         return -ENOMEM;
  67
  68                 pfc->num_irqs = num_irqs;
  69                 pfc->irqs = irqs;
  70         }
  71
  72         /* Fill them. */
  73         for (i = 0; i < num_windows; i++) {
  74                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
  75                 windows->phys = res->start;
  76                 windows->size = resource_size(res);
  77                 windows->virt = devm_ioremap_resource(pfc->dev, res);
  78                 if (IS_ERR(windows->virt))
  79                         return -ENOMEM;
  80                 windows++;
  81         }
  82         for (i = 0; i < num_irqs; i++)
  83                 *irqs++ = platform_get_irq(pdev, i);
  84
  85         return 0;
  86 }
  87
  88 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
  89 {
  90         struct sh_pfc_window *window;
  91         phys_addr_t address = reg;
  92         unsigned int i;
  93
  94         /* scan through physical windows and convert address */
  95         for (i = 0; i < pfc->num_windows; i++) {
  96                 window = pfc->windows + i;
  97
  98                 if (address < window->phys)
  99                         continue;
 100
 101                 if (address >= (window->phys + window->size))
 102                         continue;
 103
 104                 return window->virt + (address - window->phys);
 105         }
 106
 107         BUG();
 108         return NULL;
 109 }
 110
 111 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
 112 {
 113         unsigned int offset;
 114         unsigned int i;
 115
 116         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
 117                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
 118
 119                 if (pin <= range->end)
 120                         return pin >= range->start
 121                              ? offset + pin - range->start : -1;
 122
 123                 offset += range->end - range->start + 1;
 124         }
 125
 126         return -EINVAL;
 127 }
 128
 129 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
 130 {
 131         if (enum_id < r->begin)
 132                 return 0;
 133
 134         if (enum_id > r->end)
 135                 return 0;
 136
 137         return 1;
 138 }
 139
 140 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
 141 {
 142         switch (reg_width) {
 143         case 8:
 144                 return ioread8(mapped_reg);
 145         case 16:
 146                 return ioread16(mapped_reg);
 147         case 32:
 148                 return ioread32(mapped_reg);
 149         }
 150
 151         BUG();
 152         return 0;
 153 }
 154
 155 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 156                           u32 data)
 157 {
 158         switch (reg_width) {
 159         case 8:
 160                 iowrite8(data, mapped_reg);
 161                 return;
 162         case 16:
 163                 iowrite16(data, mapped_reg);
 164                 return;
 165         case 32:
 166                 iowrite32(data, mapped_reg);
 167                 return;
 168         }
 169
 170         BUG();
 171 }
 172
 173 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
 174 {
 175         return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
 176 }
 177
 178 static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
 179 {
 180         u32 unlock;
 181
 182         if (!pfc->info->unlock_reg)
 183                 return;
 184
 185         if (pfc->info->unlock_reg >= 0x80000000UL)
 186                 unlock = pfc->info->unlock_reg;
 187         else
 188                 /* unlock_reg is a mask */
 189                 unlock = reg & ~pfc->info->unlock_reg;
 190
 191         sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data);
 192 }
 193
 194 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
 195 {
 196         sh_pfc_unlock_reg(pfc, reg, data);
 197         sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
 198 }
 199
 200 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 201                                      const struct pinmux_cfg_reg *crp,
 202                                      unsigned int in_pos,
 203                                      void __iomem **mapped_regp, u32 *maskp,
 204                                      unsigned int *posp)
 205 {
 206         unsigned int k;
 207
 208         *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
 209
 210         if (crp->field_width) {
 211                 *maskp = (1 << crp->field_width) - 1;
 212                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 213         } else {
 214                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 215                 *posp = crp->reg_width;
 216                 for (k = 0; k <= in_pos; k++)
 217                         *posp -= crp->var_field_width[k];
 218         }
 219 }
 220
 221 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 222                                     const struct pinmux_cfg_reg *crp,
 223                                     unsigned int field, u32 value)
 224 {
 225         void __iomem *mapped_reg;
 226         unsigned int pos;
 227         u32 mask, data;
 228
 229         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 230
 231         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 232                 "r_width = %u, f_width = %u\n",
 233                 crp->reg, value, field, crp->reg_width, hweight32(mask));
 234
 235         mask = ~(mask << pos);
 236         value = value << pos;
 237
 238         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 239         data &= mask;
 240         data |= value;
 241
 242         sh_pfc_unlock_reg(pfc, crp->reg, data);
 243         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 244 }
 245
 246 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 247                                  const struct pinmux_cfg_reg **crp,
 248                                  unsigned int *fieldp, u32 *valuep)
 249 {
 250         unsigned int k = 0;
 251
 252         while (1) {
 253                 const struct pinmux_cfg_reg *config_reg =
 254                         pfc->info->cfg_regs + k;
 255                 unsigned int r_width = config_reg->reg_width;
 256                 unsigned int f_width = config_reg->field_width;
 257                 unsigned int curr_width;
 258                 unsigned int bit_pos;
 259                 unsigned int pos = 0;
 260                 unsigned int m = 0;
 261
 262                 if (!r_width)
 263                         break;
 264
 265                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 266                         u32 ncomb;
 267                         u32 n;
 268
 269                         if (f_width)
 270                                 curr_width = f_width;
 271                         else
 272                                 curr_width = config_reg->var_field_width[m];
 273
 274                         ncomb = 1 << curr_width;
 275                         for (n = 0; n < ncomb; n++) {
 276                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 277                                         *crp = config_reg;
 278                                         *fieldp = m;
 279                                         *valuep = n;
 280                                         return 0;
 281                                 }
 282                         }
 283                         pos += ncomb;
 284                         m++;
 285                 }
 286                 k++;
 287         }
 288
 289         return -EINVAL;
 290 }
 291
 292 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 293                               u16 *enum_idp)
 294 {
 295         const u16 *data = pfc->info->pinmux_data;
 296         unsigned int k;
 297
 298         if (pos) {
 299                 *enum_idp = data[pos + 1];
 300                 return pos + 1;
 301         }
 302
 303         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 304                 if (data[k] == mark) {
 305                         *enum_idp = data[k + 1];
 306                         return k + 1;
 307                 }
 308         }
 309
 310         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 311                 mark);
 312         return -EINVAL;
 313 }
 314
 315 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 316 {
 317         const struct pinmux_range *range;
 318         int pos = 0;
 319
 320         switch (pinmux_type) {
 321         case PINMUX_TYPE_GPIO:
 322         case PINMUX_TYPE_FUNCTION:
 323                 range = NULL;
 324                 break;
 325
 326 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
 327         case PINMUX_TYPE_OUTPUT:
 328                 range = &pfc->info->output;
 329                 break;
 330
 331         case PINMUX_TYPE_INPUT:
 332                 range = &pfc->info->input;
 333                 break;
 334 #endif /* CONFIG_PINCTRL_SH_PFC_GPIO */
 335
 336         default:
 337                 return -EINVAL;
 338         }
 339
 340         /* Iterate over all the configuration fields we need to update. */
 341         while (1) {
 342                 const struct pinmux_cfg_reg *cr;
 343                 unsigned int field;
 344                 u16 enum_id;
 345                 u32 value;
 346                 int in_range;
 347                 int ret;
 348
 349                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 350                 if (pos < 0)
 351                         return pos;
 352
 353                 if (!enum_id)
 354                         break;
 355
 356                 /* Check if the configuration field selects a function. If it
 357                  * doesn't, skip the field if it's not applicable to the
 358                  * requested pinmux type.
 359                  */
 360                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 361                 if (!in_range) {
 362                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 363                                 /* Functions are allowed to modify all
 364                                  * fields.
 365                                  */
 366                                 in_range = 1;
 367                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 368                                 /* Input/output types can only modify fields
 369                                  * that correspond to their respective ranges.
 370                                  */
 371                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 372
 373                                 /*
 374                                  * special case pass through for fixed
 375                                  * input-only or output-only pins without
 376                                  * function enum register association.
 377                                  */
 378                                 if (in_range && enum_id == range->force)
 379                                         continue;
 380                         }
 381                         /* GPIOs are only allowed to modify function fields. */
 382                 }
 383
 384                 if (!in_range)
 385                         continue;
 386
 387                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 388                 if (ret < 0)
 389                         return ret;
 390
 391                 sh_pfc_write_config_reg(pfc, cr, field, value);
 392         }
 393
 394         return 0;
 395 }
 396
 397 const struct pinmux_bias_reg *
 398 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
 399                        unsigned int *bit)
 400 {
 401         unsigned int i, j;
 402
 403         for (i = 0; pfc->info->bias_regs[i].puen; i++) {
 404                 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
 405                         if (pfc->info->bias_regs[i].pins[j] == pin) {
 406                                 *bit = j;
 407                                 return &pfc->info->bias_regs[i];
 408                         }
 409                 }
 410         }
 411
 412         WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
 413
 414         return NULL;
 415 }
 416
 417 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 418 {
 419         struct sh_pfc_pin_range *range;
 420         unsigned int nr_ranges;
 421         unsigned int i;
 422
 423         if (pfc->info->pins[0].pin == (u16)-1) {
 424                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 425                  * in its pin arrays yet. Consider the pin numbers range as
 426                  * continuous and allocate a single range.
 427                  */
 428                 pfc->nr_ranges = 1;
 429                 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
 430                                            GFP_KERNEL);
 431                 if (pfc->ranges == NULL)
 432                         return -ENOMEM;
 433
 434                 pfc->ranges->start = 0;
 435                 pfc->ranges->end = pfc->info->nr_pins - 1;
 436                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 437
 438                 return 0;
 439         }
 440
 441         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 442          * be sorted by pin numbers, and pins without a GPIO port must come
 443          * last.
 444          */
 445         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 446                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 447                         nr_ranges++;
 448         }
 449
 450         pfc->nr_ranges = nr_ranges;
 451         pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
 452                                    GFP_KERNEL);
 453         if (pfc->ranges == NULL)
 454                 return -ENOMEM;
 455
 456         range = pfc->ranges;
 457         range->start = pfc->info->pins[0].pin;
 458
 459         for (i = 1; i < pfc->info->nr_pins; ++i) {
 460                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 461                         continue;
 462
 463                 range->end = pfc->info->pins[i-1].pin;
 464                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 465                         pfc->nr_gpio_pins = range->end + 1;
 466
 467                 range++;
 468                 range->start = pfc->info->pins[i].pin;
 469         }
 470
 471         range->end = pfc->info->pins[i-1].pin;
 472         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 473                 pfc->nr_gpio_pins = range->end + 1;
 474
 475         return 0;
 476 }
 477
 478 #ifdef CONFIG_OF
 479 static const struct of_device_id sh_pfc_of_table[] = {
 480 #ifdef CONFIG_PINCTRL_PFC_EMEV2
 481         {
 482                 .compatible = "renesas,pfc-emev2",
 483                 .data = &emev2_pinmux_info,
 484         },
 485 #endif
 486 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
 487         {
 488                 .compatible = "renesas,pfc-r8a73a4",
 489                 .data = &r8a73a4_pinmux_info,
 490         },
 491 #endif
 492 #ifdef CONFIG_PINCTRL_PFC_R8A7740
 493         {
 494                 .compatible = "renesas,pfc-r8a7740",
 495                 .data = &r8a7740_pinmux_info,
 496         },
 497 #endif
 498 #ifdef CONFIG_PINCTRL_PFC_R8A7742
 499         {
 500                 .compatible = "renesas,pfc-r8a7742",
 501                 .data = &r8a7742_pinmux_info,
 502         },
 503 #endif
 504 #ifdef CONFIG_PINCTRL_PFC_R8A7743
 505         {
 506                 .compatible = "renesas,pfc-r8a7743",
 507                 .data = &r8a7743_pinmux_info,
 508         },
 509 #endif
 510 #ifdef CONFIG_PINCTRL_PFC_R8A7744
 511         {
 512                 .compatible = "renesas,pfc-r8a7744",
 513                 .data = &r8a7744_pinmux_info,
 514         },
 515 #endif
 516 #ifdef CONFIG_PINCTRL_PFC_R8A7745
 517         {
 518                 .compatible = "renesas,pfc-r8a7745",
 519                 .data = &r8a7745_pinmux_info,
 520         },
 521 #endif
 522 #ifdef CONFIG_PINCTRL_PFC_R8A77470
 523         {
 524                 .compatible = "renesas,pfc-r8a77470",
 525                 .data = &r8a77470_pinmux_info,
 526         },
 527 #endif
 528 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
 529         {
 530                 .compatible = "renesas,pfc-r8a774a1",
 531                 .data = &r8a774a1_pinmux_info,
 532         },
 533 #endif
 534 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
 535         {
 536                 .compatible = "renesas,pfc-r8a774b1",
 537                 .data = &r8a774b1_pinmux_info,
 538         },
 539 #endif
 540 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
 541         {
 542                 .compatible = "renesas,pfc-r8a774c0",
 543                 .data = &r8a774c0_pinmux_info,
 544         },
 545 #endif
 546 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
 547         {
 548                 .compatible = "renesas,pfc-r8a774e1",
 549                 .data = &r8a774e1_pinmux_info,
 550         },
 551 #endif
 552 #ifdef CONFIG_PINCTRL_PFC_R8A7778
 553         {
 554                 .compatible = "renesas,pfc-r8a7778",
 555                 .data = &r8a7778_pinmux_info,
 556         },
 557 #endif
 558 #ifdef CONFIG_PINCTRL_PFC_R8A7779
 559         {
 560                 .compatible = "renesas,pfc-r8a7779",
 561                 .data = &r8a7779_pinmux_info,
 562         },
 563 #endif
 564 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 565         {
 566                 .compatible = "renesas,pfc-r8a7790",
 567                 .data = &r8a7790_pinmux_info,
 568         },
 569 #endif
 570 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 571         {
 572                 .compatible = "renesas,pfc-r8a7791",
 573                 .data = &r8a7791_pinmux_info,
 574         },
 575 #endif
 576 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 577         {
 578                 .compatible = "renesas,pfc-r8a7792",
 579                 .data = &r8a7792_pinmux_info,
 580         },
 581 #endif
 582 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 583         {
 584                 .compatible = "renesas,pfc-r8a7793",
 585                 .data = &r8a7793_pinmux_info,
 586         },
 587 #endif
 588 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 589         {
 590                 .compatible = "renesas,pfc-r8a7794",
 591                 .data = &r8a7794_pinmux_info,
 592         },
 593 #endif
 594 /* Both r8a7795 entries must be present to make sanity checks work */
 595 #ifdef CONFIG_PINCTRL_PFC_R8A77950
 596         {
 597                 .compatible = "renesas,pfc-r8a7795",
 598                 .data = &r8a77950_pinmux_info,
 599         },
 600 #endif
 601 #ifdef CONFIG_PINCTRL_PFC_R8A77951
 602         {
 603                 .compatible = "renesas,pfc-r8a7795",
 604                 .data = &r8a77951_pinmux_info,
 605         },
 606 #endif
 607 #ifdef CONFIG_PINCTRL_PFC_R8A77960
 608         {
 609                 .compatible = "renesas,pfc-r8a7796",
 610                 .data = &r8a77960_pinmux_info,
 611         },
 612 #endif
 613 #ifdef CONFIG_PINCTRL_PFC_R8A77961
 614         {
 615                 .compatible = "renesas,pfc-r8a77961",
 616                 .data = &r8a77961_pinmux_info,
 617         },
 618 #endif
 619 #ifdef CONFIG_PINCTRL_PFC_R8A77965
 620         {
 621                 .compatible = "renesas,pfc-r8a77965",
 622                 .data = &r8a77965_pinmux_info,
 623         },
 624 #endif
 625 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 626         {
 627                 .compatible = "renesas,pfc-r8a77970",
 628                 .data = &r8a77970_pinmux_info,
 629         },
 630 #endif
 631 #ifdef CONFIG_PINCTRL_PFC_R8A77980
 632         {
 633                 .compatible = "renesas,pfc-r8a77980",
 634                 .data = &r8a77980_pinmux_info,
 635         },
 636 #endif
 637 #ifdef CONFIG_PINCTRL_PFC_R8A77990
 638         {
 639                 .compatible = "renesas,pfc-r8a77990",
 640                 .data = &r8a77990_pinmux_info,
 641         },
 642 #endif
 643 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 644         {
 645                 .compatible = "renesas,pfc-r8a77995",
 646                 .data = &r8a77995_pinmux_info,
 647         },
 648 #endif
 649 #ifdef CONFIG_PINCTRL_PFC_R8A779A0
 650         {
 651                 .compatible = "renesas,pfc-r8a779a0",
 652                 .data = &r8a779a0_pinmux_info,
 653         },
 654 #endif
 655 #ifdef CONFIG_PINCTRL_PFC_SH73A0
 656         {
 657                 .compatible = "renesas,pfc-sh73a0",
 658                 .data = &sh73a0_pinmux_info,
 659         },
 660 #endif
 661         { },
 662 };
 663 #endif
 664
 665 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
 666 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 667 {
 668 }
 669
 670 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 671 {
 672         pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
 673 }
 674
 675 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
 676 {
 677         sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
 678 }
 679
 680 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
 681         void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
 682 {
 683         unsigned int i, n = 0;
 684
 685         if (pfc->info->cfg_regs)
 686                 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
 687                         do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
 688
 689         if (pfc->info->drive_regs)
 690                 for (i = 0; pfc->info->drive_regs[i].reg; i++)
 691                         do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
 692
 693         if (pfc->info->bias_regs)
 694                 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
 695                         do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
 696                         if (pfc->info->bias_regs[i].pud)
 697                                 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
 698                 }
 699
 700         if (pfc->info->ioctrl_regs)
 701                 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
 702                         do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
 703
 704         return n;
 705 }
 706
 707 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
 708 {
 709         unsigned int n;
 710
 711         /* This is the best we can do to check for the presence of PSCI */
 712         if (!psci_ops.cpu_suspend)
 713                 return 0;
 714
 715         n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
 716         if (!n)
 717                 return 0;
 718
 719         pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
 720                                              sizeof(*pfc->saved_regs),
 721                                              GFP_KERNEL);
 722         if (!pfc->saved_regs)
 723                 return -ENOMEM;
 724
 725         dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
 726         return 0;
 727 }
 728
 729 static int sh_pfc_suspend_noirq(struct device *dev)
 730 {
 731         struct sh_pfc *pfc = dev_get_drvdata(dev);
 732
 733         if (pfc->saved_regs)
 734                 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
 735         return 0;
 736 }
 737
 738 static int sh_pfc_resume_noirq(struct device *dev)
 739 {
 740         struct sh_pfc *pfc = dev_get_drvdata(dev);
 741
 742         if (pfc->saved_regs)
 743                 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
 744         return 0;
 745 }
 746
 747 static const struct dev_pm_ops sh_pfc_pm  = {
 748         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
 749 };
 750 #define DEV_PM_OPS      &sh_pfc_pm
 751 #else
 752 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
 753 #define DEV_PM_OPS      NULL
 754 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
 755
 756 #ifdef DEBUG
 757 #define SH_PFC_MAX_REGS         300
 758 #define SH_PFC_MAX_ENUMS        3000
 759
 760 static unsigned int sh_pfc_errors __initdata = 0;
 761 static unsigned int sh_pfc_warnings __initdata = 0;
 762 static u32 *sh_pfc_regs __initdata = NULL;
 763 static u32 sh_pfc_num_regs __initdata = 0;
 764 static u16 *sh_pfc_enums __initdata = NULL;
 765 static u32 sh_pfc_num_enums __initdata = 0;
 766
 767 #define sh_pfc_err(fmt, ...)                                    \
 768         do {                                                    \
 769                 pr_err("%s: " fmt, drvname, ##__VA_ARGS__);     \
 770                 sh_pfc_errors++;                                \
 771         } while (0)
 772 #define sh_pfc_warn(fmt, ...)                                   \
 773         do {                                                    \
 774                 pr_warn("%s: " fmt, drvname, ##__VA_ARGS__);    \
 775                 sh_pfc_warnings++;                              \
 776         } while (0)
 777
 778 static bool __init is0s(const u16 *enum_ids, unsigned int n)
 779 {
 780         unsigned int i;
 781
 782         for (i = 0; i < n; i++)
 783                 if (enum_ids[i])
 784                         return false;
 785
 786         return true;
 787 }
 788
 789 static bool __init same_name(const char *a, const char *b)
 790 {
 791         if (!a || !b)
 792                 return false;
 793
 794         return !strcmp(a, b);
 795 }
 796
 797 static void __init sh_pfc_check_reg(const char *drvname, u32 reg)
 798 {
 799         unsigned int i;
 800
 801         for (i = 0; i < sh_pfc_num_regs; i++)
 802                 if (reg == sh_pfc_regs[i]) {
 803                         sh_pfc_err("reg 0x%x conflict\n", reg);
 804                         return;
 805                 }
 806
 807         if (sh_pfc_num_regs == SH_PFC_MAX_REGS) {
 808                 pr_warn_once("%s: Please increase SH_PFC_MAX_REGS\n", drvname);
 809                 return;
 810         }
 811
 812         sh_pfc_regs[sh_pfc_num_regs++] = reg;
 813 }
 814
 815 static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id)
 816 {
 817         unsigned int i;
 818
 819         for (i = 0; i < sh_pfc_num_enums; i++) {
 820                 if (enum_id == sh_pfc_enums[i])
 821                         return -EINVAL;
 822         }
 823
 824         if (sh_pfc_num_enums == SH_PFC_MAX_ENUMS) {
 825                 pr_warn_once("%s: Please increase SH_PFC_MAX_ENUMS\n", drvname);
 826                 return 0;
 827         }
 828
 829         sh_pfc_enums[sh_pfc_num_enums++] = enum_id;
 830         return 0;
 831 }
 832
 833 static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg,
 834                                           const u16 *enums, unsigned int n)
 835 {
 836         unsigned int i;
 837
 838         for (i = 0; i < n; i++) {
 839                 if (enums[i] && sh_pfc_check_enum(drvname, enums[i]))
 840                         sh_pfc_err("reg 0x%x enum_id %u conflict\n", reg,
 841                                    enums[i]);
 842         }
 843 }
 844
 845 static void __init sh_pfc_check_pin(const struct sh_pfc_soc_info *info,
 846                                     u32 reg, unsigned int pin)
 847 {
 848         const char *drvname = info->name;
 849         unsigned int i;
 850
 851         if (pin == SH_PFC_PIN_NONE)
 852                 return;
 853
 854         for (i = 0; i < info->nr_pins; i++) {
 855                 if (pin == info->pins[i].pin)
 856                         return;
 857         }
 858
 859         sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);
 860 }
 861
 862 static void __init sh_pfc_check_cfg_reg(const char *drvname,
 863                                         const struct pinmux_cfg_reg *cfg_reg)
 864 {
 865         unsigned int i, n, rw, fw;
 866
 867         sh_pfc_check_reg(drvname, cfg_reg->reg);
 868
 869         if (cfg_reg->field_width) {
 870                 n = cfg_reg->reg_width / cfg_reg->field_width;
 871                 /* Skip field checks (done at build time) */
 872                 goto check_enum_ids;
 873         }
 874
 875         for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
 876                 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw))
 877                         sh_pfc_warn("reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
 878                                     cfg_reg->reg, rw, rw + fw - 1);
 879                 n += 1 << fw;
 880                 rw += fw;
 881         }
 882
 883         if (rw != cfg_reg->reg_width)
 884                 sh_pfc_err("reg 0x%x: var_field_width declares %u instead of %u bits\n",
 885                            cfg_reg->reg, rw, cfg_reg->reg_width);
 886
 887         if (n != cfg_reg->nr_enum_ids)
 888                 sh_pfc_err("reg 0x%x: enum_ids[] has %u instead of %u values\n",
 889                            cfg_reg->reg, cfg_reg->nr_enum_ids, n);
 890
 891 check_enum_ids:
 892         sh_pfc_check_reg_enums(drvname, cfg_reg->reg, cfg_reg->enum_ids, n);
 893 }
 894
 895 static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
 896                                           const struct pinmux_drive_reg *drive)
 897 {
 898         const char *drvname = info->name;
 899         unsigned long seen = 0, mask;
 900         unsigned int i;
 901
 902         sh_pfc_check_reg(info->name, drive->reg);
 903         for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
 904                 const struct pinmux_drive_reg_field *field = &drive->fields[i];
 905
 906                 if (!field->pin && !field->offset && !field->size)
 907                         continue;
 908
 909                 mask = GENMASK(field->offset + field->size, field->offset);
 910                 if (mask & seen)
 911                         sh_pfc_err("drive_reg 0x%x: field %u overlap\n",
 912                                    drive->reg, i);
 913                 seen |= mask;
 914
 915                 sh_pfc_check_pin(info, drive->reg, field->pin);
 916         }
 917 }
 918
 919 static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
 920                                          const struct pinmux_bias_reg *bias)
 921 {
 922         unsigned int i;
 923
 924         sh_pfc_check_reg(info->name, bias->puen);
 925         if (bias->pud)
 926                 sh_pfc_check_reg(info->name, bias->pud);
 927         for (i = 0; i < ARRAY_SIZE(bias->pins); i++)
 928                 sh_pfc_check_pin(info, bias->puen, bias->pins[i]);
 929 }
 930
 931 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
 932 {
 933         const char *drvname = info->name;
 934         unsigned int *refcnts;
 935         unsigned int i, j, k;
 936
 937         pr_info("Checking %s\n", drvname);
 938         sh_pfc_num_regs = 0;
 939         sh_pfc_num_enums = 0;
 940
 941         /* Check pins */
 942         for (i = 0; i < info->nr_pins; i++) {
 943                 const struct sh_pfc_pin *pin = &info->pins[i];
 944
 945                 if (!pin->name) {
 946                         sh_pfc_err("empty pin %u\n", i);
 947                         continue;
 948                 }
 949                 for (j = 0; j < i; j++) {
 950                         const struct sh_pfc_pin *pin2 = &info->pins[j];
 951
 952                         if (same_name(pin->name, pin2->name))
 953                                 sh_pfc_err("pin %s: name conflict\n",
 954                                            pin->name);
 955
 956                         if (pin->pin != (u16)-1 && pin->pin == pin2->pin)
 957                                 sh_pfc_err("pin %s/%s: pin %u conflict\n",
 958                                            pin->name, pin2->name, pin->pin);
 959
 960                         if (pin->enum_id && pin->enum_id == pin2->enum_id)
 961                                 sh_pfc_err("pin %s/%s: enum_id %u conflict\n",
 962                                            pin->name, pin2->name,
 963                                            pin->enum_id);
 964                 }
 965         }
 966
 967         /* Check groups and functions */
 968         refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
 969         if (!refcnts)
 970                 return;
 971
 972         for (i = 0; i < info->nr_functions; i++) {
 973                 const struct sh_pfc_function *func = &info->functions[i];
 974
 975                 if (!func->name) {
 976                         sh_pfc_err("empty function %u\n", i);
 977                         continue;
 978                 }
 979                 for (j = 0; j < i; j++) {
 980                         if (same_name(func->name, info->functions[j].name))
 981                                 sh_pfc_err("function %s: name conflict\n",
 982                                            func->name);
 983                 }
 984                 for (j = 0; j < func->nr_groups; j++) {
 985                         for (k = 0; k < info->nr_groups; k++) {
 986                                 if (same_name(func->groups[j],
 987                                               info->groups[k].name)) {
 988                                         refcnts[k]++;
 989                                         break;
 990                                 }
 991                         }
 992
 993                         if (k == info->nr_groups)
 994                                 sh_pfc_err("function %s: group %s not found\n",
 995                                            func->name, func->groups[j]);
 996                 }
 997         }
 998
 999         for (i = 0; i < info->nr_groups; i++) {
1000                 const struct sh_pfc_pin_group *group = &info->groups[i];
1001
1002                 if (!group->name) {
1003                         sh_pfc_err("empty group %u\n", i);
1004                         continue;
1005                 }
1006                 for (j = 0; j < i; j++) {
1007                         if (same_name(group->name, info->groups[j].name))
1008                                 sh_pfc_err("group %s: name conflict\n",
1009                                            group->name);
1010                 }
1011                 if (!refcnts[i])
1012                         sh_pfc_err("orphan group %s\n", group->name);
1013                 else if (refcnts[i] > 1)
1014                         sh_pfc_warn("group %s referenced by %u functions\n",
1015                                     group->name, refcnts[i]);
1016         }
1017
1018         kfree(refcnts);
1019
1020         /* Check config register descriptions */
1021         for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
1022                 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
1023
1024         /* Check drive strength registers */
1025         for (i = 0; info->drive_regs && info->drive_regs[i].reg; i++)
1026                 sh_pfc_check_drive_reg(info, &info->drive_regs[i]);
1027
1028         /* Check bias registers */
1029         for (i = 0; info->bias_regs && info->bias_regs[i].puen; i++)
1030                 sh_pfc_check_bias_reg(info, &info->bias_regs[i]);
1031
1032         /* Check ioctrl registers */
1033         for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
1034                 sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg);
1035
1036         /* Check data registers */
1037         for (i = 0; info->data_regs && info->data_regs[i].reg; i++) {
1038                 sh_pfc_check_reg(drvname, info->data_regs[i].reg);
1039                 sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg,
1040                                        info->data_regs[i].enum_ids,
1041                                        info->data_regs[i].reg_width);
1042         }
1043
1044 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
1045         /* Check function GPIOs */
1046         for (i = 0; i < info->nr_func_gpios; i++) {
1047                 const struct pinmux_func *func = &info->func_gpios[i];
1048
1049                 if (!func->name) {
1050                         sh_pfc_err("empty function gpio %u\n", i);
1051                         continue;
1052                 }
1053                 for (j = 0; j < i; j++) {
1054                         if (same_name(func->name, info->func_gpios[j].name))
1055                                 sh_pfc_err("func_gpio %s: name conflict\n",
1056                                            func->name);
1057                 }
1058                 if (sh_pfc_check_enum(drvname, func->enum_id))
1059                         sh_pfc_err("%s enum_id %u conflict\n", func->name,
1060                                    func->enum_id);
1061         }
1062 #endif
1063 }
1064
1065 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
1066 {
1067         unsigned int i;
1068
1069         if (!IS_ENABLED(CONFIG_SUPERH) &&
1070             !of_find_matching_node(NULL, pdrv->driver.of_match_table))
1071                 return;
1072
1073         sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs),
1074                               GFP_KERNEL);
1075         if (!sh_pfc_regs)
1076                 return;
1077
1078         sh_pfc_enums = kcalloc(SH_PFC_MAX_ENUMS, sizeof(*sh_pfc_enums),
1079                               GFP_KERNEL);
1080         if (!sh_pfc_enums)
1081                 goto free_regs;
1082
1083         pr_warn("Checking builtin pinmux tables\n");
1084
1085         for (i = 0; pdrv->id_table[i].name[0]; i++)
1086                 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
1087
1088 #ifdef CONFIG_OF
1089         for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
1090                 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
1091 #endif
1092
1093         pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
1094                 sh_pfc_warnings);
1095
1096         kfree(sh_pfc_enums);
1097 free_regs:
1098         kfree(sh_pfc_regs);
1099 }
1100
1101 #else /* !DEBUG */
1102 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
1103 #endif /* !DEBUG */
1104
1105 #ifdef CONFIG_OF
1106 static const void *sh_pfc_quirk_match(void)
1107 {
1108 #if defined(CONFIG_PINCTRL_PFC_R8A77950) || \
1109     defined(CONFIG_PINCTRL_PFC_R8A77951)
1110         const struct soc_device_attribute *match;
1111         static const struct soc_device_attribute quirks[] = {
1112                 {
1113                         .soc_id = "r8a7795", .revision = "ES1.*",
1114                         .data = &r8a77950_pinmux_info,
1115                 },
1116                 {
1117                         .soc_id = "r8a7795",
1118                         .data = &r8a77951_pinmux_info,
1119                 },
1120
1121                 { /* sentinel */ }
1122         };
1123
1124         match = soc_device_match(quirks);
1125         if (match)
1126                 return match->data ?: ERR_PTR(-ENODEV);
1127 #endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */
1128
1129         return NULL;
1130 }
1131 #endif /* CONFIG_OF */
1132
1133 static int sh_pfc_probe(struct platform_device *pdev)
1134 {
1135         const struct sh_pfc_soc_info *info;
1136         struct sh_pfc *pfc;
1137         int ret;
1138
1139 #ifdef CONFIG_OF
1140         if (pdev->dev.of_node) {
1141                 info = sh_pfc_quirk_match();
1142                 if (IS_ERR(info))
1143                         return PTR_ERR(info);
1144
1145                 if (!info)
1146                         info = of_device_get_match_data(&pdev->dev);
1147         } else
1148 #endif
1149                 info = (const void *)platform_get_device_id(pdev)->driver_data;
1150
1151         pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
1152         if (pfc == NULL)
1153                 return -ENOMEM;
1154
1155         pfc->info = info;
1156         pfc->dev = &pdev->dev;
1157
1158         ret = sh_pfc_map_resources(pfc, pdev);
1159         if (unlikely(ret < 0))
1160                 return ret;
1161
1162         spin_lock_init(&pfc->lock);
1163
1164         if (info->ops && info->ops->init) {
1165                 ret = info->ops->init(pfc);
1166                 if (ret < 0)
1167                         return ret;
1168
1169                 /* .init() may have overridden pfc->info */
1170                 info = pfc->info;
1171         }
1172
1173         ret = sh_pfc_suspend_init(pfc);
1174         if (ret)
1175                 return ret;
1176
1177         /* Enable dummy states for those platforms without pinctrl support */
1178         if (!of_have_populated_dt())
1179                 pinctrl_provide_dummies();
1180
1181         ret = sh_pfc_init_ranges(pfc);
1182         if (ret < 0)
1183                 return ret;
1184
1185         /*
1186          * Initialize pinctrl bindings first
1187          */
1188         ret = sh_pfc_register_pinctrl(pfc);
1189         if (unlikely(ret != 0))
1190                 return ret;
1191
1192 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
1193         /*
1194          * Then the GPIO chip
1195          */
1196         ret = sh_pfc_register_gpiochip(pfc);
1197         if (unlikely(ret != 0)) {
1198                 /*
1199                  * If the GPIO chip fails to come up we still leave the
1200                  * PFC state as it is, given that there are already
1201                  * extant users of it that have succeeded by this point.
1202                  */
1203                 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
1204         }
1205 #endif
1206
1207         platform_set_drvdata(pdev, pfc);
1208
1209         dev_info(pfc->dev, "%s support registered\n", info->name);
1210
1211         return 0;
1212 }
1213
1214 static const struct platform_device_id sh_pfc_id_table[] = {
1215 #ifdef CONFIG_PINCTRL_PFC_SH7203
1216         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
1217 #endif
1218 #ifdef CONFIG_PINCTRL_PFC_SH7264
1219         { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
1220 #endif
1221 #ifdef CONFIG_PINCTRL_PFC_SH7269
1222         { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
1223 #endif
1224 #ifdef CONFIG_PINCTRL_PFC_SH7720
1225         { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
1226 #endif
1227 #ifdef CONFIG_PINCTRL_PFC_SH7722
1228         { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
1229 #endif
1230 #ifdef CONFIG_PINCTRL_PFC_SH7723
1231         { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
1232 #endif
1233 #ifdef CONFIG_PINCTRL_PFC_SH7724
1234         { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
1235 #endif
1236 #ifdef CONFIG_PINCTRL_PFC_SH7734
1237         { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
1238 #endif
1239 #ifdef CONFIG_PINCTRL_PFC_SH7757
1240         { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
1241 #endif
1242 #ifdef CONFIG_PINCTRL_PFC_SH7785
1243         { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
1244 #endif
1245 #ifdef CONFIG_PINCTRL_PFC_SH7786
1246         { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
1247 #endif
1248 #ifdef CONFIG_PINCTRL_PFC_SHX3
1249         { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
1250 #endif
1251         { },
1252 };
1253
1254 static struct platform_driver sh_pfc_driver = {
1255         .probe          = sh_pfc_probe,
1256         .id_table       = sh_pfc_id_table,
1257         .driver         = {
1258                 .name   = DRV_NAME,
1259                 .of_match_table = of_match_ptr(sh_pfc_of_table),
1260                 .pm     = DEV_PM_OPS,
1261         },
1262 };
1263
1264 static int __init sh_pfc_init(void)
1265 {
1266         sh_pfc_check_driver(&sh_pfc_driver);
1267         return platform_driver_register(&sh_pfc_driver);
1268 }
1269 postcore_initcall(sh_pfc_init);