1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2013, Sony Mobile Communications AB.
5 #ifndef __PINCTRL_MSM_H__
6 #define __PINCTRL_MSM_H__
9 #include <linux/types.h>
11 #include <linux/pinctrl/pinctrl.h>
13 struct platform_device;
15 struct pinctrl_pin_desc;
17 #define APQ_PIN_FUNCTION(fname) \
18 [APQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \
20 ARRAY_SIZE(fname##_groups))
22 #define IPQ_PIN_FUNCTION(fname) \
23 [IPQ_MUX_##fname] = PINCTRL_PINFUNCTION(#fname, \
25 ARRAY_SIZE(fname##_groups))
27 #define MSM_PIN_FUNCTION(fname) \
28 [msm_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \
30 ARRAY_SIZE(fname##_groups))
32 #define QCA_PIN_FUNCTION(fname) \
33 [qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \
35 ARRAY_SIZE(fname##_groups))
38 * struct msm_pingroup - Qualcomm pingroup definition
39 * @grp: Generic data of the pin group (name and pins)
40 * @funcs: A list of pinmux functions that can be selected for
41 * this group. The index of the selected function is used
42 * for programming the function selector.
43 * Entries should be indices into the groups list of the
44 * struct msm_pinctrl_soc_data.
45 * @ctl_reg: Offset of the register holding control bits for this group.
46 * @io_reg: Offset of the register holding input/output bits for this group.
47 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
48 * @intr_status_reg: Offset of the register holding the status bits for this group.
49 * @intr_target_reg: Offset of the register specifying routing of the interrupts
51 * @mux_bit: Offset in @ctl_reg for the pinmux function selection.
52 * @pull_bit: Offset in @ctl_reg for the bias configuration.
53 * @drv_bit: Offset in @ctl_reg for the drive strength configuration.
54 * @od_bit: Offset in @ctl_reg for controlling open drain.
55 * @oe_bit: Offset in @ctl_reg for controlling output enable.
56 * @in_bit: Offset in @io_reg for the input bit value.
57 * @out_bit: Offset in @io_reg for the output bit value.
58 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
59 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
61 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
62 * @intr_target_width: Number of bits used for specifying interrupt routing target.
63 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
64 * this gpio should get routed to the KPSS processor.
65 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
66 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
67 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
68 * @intr_detection_width: Number of bits used for specifying interrupt type,
69 * Should be 2 for SoCs that can detect both edges in hardware,
90 unsigned i2c_pull_bit:5;
93 unsigned egpio_enable:5;
94 unsigned egpio_present:5;
99 unsigned intr_enable_bit:5;
100 unsigned intr_status_bit:5;
101 unsigned intr_ack_high:1;
103 unsigned intr_target_bit:5;
104 unsigned intr_target_width:5;
105 unsigned intr_target_kpss_val:5;
106 unsigned intr_raw_status_bit:5;
107 unsigned intr_polarity_bit:5;
108 unsigned intr_detection_bit:5;
109 unsigned intr_detection_width:5;
113 * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
114 * @gpio: The GPIOs that are wakeup capable
115 * @wakeirq: The interrupt at the always-on interrupt controller
117 struct msm_gpio_wakeirq_map {
119 unsigned int wakeirq;
123 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
124 * @pins: An array describing all pins the pin controller affects.
125 * @npins: The number of entries in @pins.
126 * @functions: An array describing all mux functions the SoC supports.
127 * @nfunctions: The number of entries in @functions.
128 * @groups: An array describing all pin groups the pin SoC supports.
129 * @ngroups: The numbmer of entries in @groups.
130 * @ngpio: The number of pingroups the driver should expose as GPIOs.
131 * @pull_no_keeper: The SoC does not support keeper bias.
132 * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM
133 * @nwakeirq_map: The number of entries in @wakeirq_map
134 * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need
135 * to be aware that their parent can't handle dual
137 * @gpio_func: Which function number is GPIO (usually 0).
138 * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in
139 * hardware this is a mux 1-level above the TLMM, we'll treat
140 * it as if this is just another mux state of the TLMM. Since
141 * it doesn't really map to hardware, we'll allocate a virtual
142 * function number for eGPIO and any time we see that function
143 * number used we'll treat it as a request to mux away from
144 * our TLMM towards another owner.
146 struct msm_pinctrl_soc_data {
147 const struct pinctrl_pin_desc *pins;
149 const struct pinfunction *functions;
151 const struct msm_pingroup *groups;
155 const char *const *tiles;
157 const int *reserved_gpios;
158 const struct msm_gpio_wakeirq_map *wakeirq_map;
159 unsigned int nwakeirq_map;
160 bool wakeirq_dual_edge_errata;
161 unsigned int gpio_func;
162 unsigned int egpio_func;
165 extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
167 int msm_pinctrl_probe(struct platform_device *pdev,
168 const struct msm_pinctrl_soc_data *soc_data);
169 void msm_pinctrl_remove(struct platform_device *pdev);