1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013, Sony Mobile Communications AB.
4 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
10 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pinctrl/machine.h>
14 #include <linux/pinctrl/pinctrl.h>
15 #include <linux/pinctrl/pinmux.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/slab.h>
19 #include <linux/gpio/driver.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/reboot.h>
24 #include <linux/log2.h>
25 #include <linux/qcom_scm.h>
28 #include <linux/soc/qcom/irq.h>
31 #include "../pinconf.h"
32 #include "pinctrl-msm.h"
33 #include "../pinctrl-utils.h"
35 #define MAX_NR_GPIO 300
36 #define MAX_NR_TILES 4
37 #define PS_HOLD_OFFSET 0x820
40 * struct msm_pinctrl - state for a pinctrl-msm device
41 * @dev: device handle.
42 * @pctrl: pinctrl handle.
43 * @chip: gpiochip handle.
44 * @restart_nb: restart notifier block.
45 * @irq: parent irq for the TLMM irq_chip.
46 * @lock: Spinlock to protect register resources as well
47 * as msm_pinctrl data structures.
48 * @enabled_irqs: Bitmap of currently enabled irqs.
49 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
51 * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller
52 * @soc; Reference to soc_data of platform specific data.
53 * @regs: Base addresses for the TLMM tiles.
57 struct pinctrl_dev *pctrl;
58 struct gpio_chip chip;
59 struct pinctrl_desc desc;
60 struct notifier_block restart_nb;
62 struct irq_chip irq_chip;
65 bool intr_target_use_scm;
69 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
70 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
71 DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);
73 const struct msm_pinctrl_soc_data *soc;
74 void __iomem *regs[MAX_NR_TILES];
75 u32 phys_base[MAX_NR_TILES];
78 #define MSM_ACCESSOR(name) \
79 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
80 const struct msm_pingroup *g) \
82 return readl(pctrl->regs[g->tile] + g->name##_reg); \
84 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
85 const struct msm_pingroup *g) \
87 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
92 MSM_ACCESSOR(intr_cfg)
93 MSM_ACCESSOR(intr_status)
94 MSM_ACCESSOR(intr_target)
96 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
98 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
100 return pctrl->soc->ngroups;
103 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
106 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
108 return pctrl->soc->groups[group].name;
111 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
113 const unsigned **pins,
116 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
118 *pins = pctrl->soc->groups[group].pins;
119 *num_pins = pctrl->soc->groups[group].npins;
123 static const struct pinctrl_ops msm_pinctrl_ops = {
124 .get_groups_count = msm_get_groups_count,
125 .get_group_name = msm_get_group_name,
126 .get_group_pins = msm_get_group_pins,
127 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
128 .dt_free_map = pinctrl_utils_free_map,
131 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
133 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
134 struct gpio_chip *chip = &pctrl->chip;
136 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
139 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
141 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
143 return pctrl->soc->nfunctions;
146 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
149 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
151 return pctrl->soc->functions[function].name;
154 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
156 const char * const **groups,
157 unsigned * const num_groups)
159 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
161 *groups = pctrl->soc->functions[function].groups;
162 *num_groups = pctrl->soc->functions[function].ngroups;
166 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
170 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
171 const struct msm_pingroup *g;
176 g = &pctrl->soc->groups[group];
177 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
179 for (i = 0; i < g->nfuncs; i++) {
180 if (g->funcs[i] == function)
184 if (WARN_ON(i == g->nfuncs))
187 raw_spin_lock_irqsave(&pctrl->lock, flags);
189 val = msm_readl_ctl(pctrl, g);
191 val |= i << g->mux_bit;
192 msm_writel_ctl(val, pctrl, g);
194 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
199 static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
200 struct pinctrl_gpio_range *range,
203 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
204 const struct msm_pingroup *g = &pctrl->soc->groups[offset];
206 /* No funcs? Probably ACPI so can't do anything here */
210 /* For now assume function 0 is GPIO because it always is */
211 return msm_pinmux_set_mux(pctldev, g->funcs[0], offset);
214 static const struct pinmux_ops msm_pinmux_ops = {
215 .request = msm_pinmux_request,
216 .get_functions_count = msm_get_functions_count,
217 .get_function_name = msm_get_function_name,
218 .get_function_groups = msm_get_function_groups,
219 .gpio_request_enable = msm_pinmux_request_gpio,
220 .set_mux = msm_pinmux_set_mux,
223 static int msm_config_reg(struct msm_pinctrl *pctrl,
224 const struct msm_pingroup *g,
230 case PIN_CONFIG_BIAS_DISABLE:
231 case PIN_CONFIG_BIAS_PULL_DOWN:
232 case PIN_CONFIG_BIAS_BUS_HOLD:
233 case PIN_CONFIG_BIAS_PULL_UP:
237 case PIN_CONFIG_DRIVE_STRENGTH:
241 case PIN_CONFIG_OUTPUT:
242 case PIN_CONFIG_INPUT_ENABLE:
253 #define MSM_NO_PULL 0
254 #define MSM_PULL_DOWN 1
256 #define MSM_PULL_UP_NO_KEEPER 2
257 #define MSM_PULL_UP 3
259 static unsigned msm_regval_to_drive(u32 val)
261 return (val + 1) * 2;
264 static int msm_config_group_get(struct pinctrl_dev *pctldev,
266 unsigned long *config)
268 const struct msm_pingroup *g;
269 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
270 unsigned param = pinconf_to_config_param(*config);
277 g = &pctrl->soc->groups[group];
279 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
283 val = msm_readl_ctl(pctrl, g);
284 arg = (val >> bit) & mask;
286 /* Convert register value to pinconf value */
288 case PIN_CONFIG_BIAS_DISABLE:
289 if (arg != MSM_NO_PULL)
293 case PIN_CONFIG_BIAS_PULL_DOWN:
294 if (arg != MSM_PULL_DOWN)
298 case PIN_CONFIG_BIAS_BUS_HOLD:
299 if (pctrl->soc->pull_no_keeper)
302 if (arg != MSM_KEEPER)
306 case PIN_CONFIG_BIAS_PULL_UP:
307 if (pctrl->soc->pull_no_keeper)
308 arg = arg == MSM_PULL_UP_NO_KEEPER;
310 arg = arg == MSM_PULL_UP;
314 case PIN_CONFIG_DRIVE_STRENGTH:
315 arg = msm_regval_to_drive(arg);
317 case PIN_CONFIG_OUTPUT:
318 /* Pin is not output */
322 val = msm_readl_io(pctrl, g);
323 arg = !!(val & BIT(g->in_bit));
325 case PIN_CONFIG_INPUT_ENABLE:
335 *config = pinconf_to_config_packed(param, arg);
340 static int msm_config_group_set(struct pinctrl_dev *pctldev,
342 unsigned long *configs,
343 unsigned num_configs)
345 const struct msm_pingroup *g;
346 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
356 g = &pctrl->soc->groups[group];
358 for (i = 0; i < num_configs; i++) {
359 param = pinconf_to_config_param(configs[i]);
360 arg = pinconf_to_config_argument(configs[i]);
362 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
366 /* Convert pinconf values to register values */
368 case PIN_CONFIG_BIAS_DISABLE:
371 case PIN_CONFIG_BIAS_PULL_DOWN:
374 case PIN_CONFIG_BIAS_BUS_HOLD:
375 if (pctrl->soc->pull_no_keeper)
380 case PIN_CONFIG_BIAS_PULL_UP:
381 if (pctrl->soc->pull_no_keeper)
382 arg = MSM_PULL_UP_NO_KEEPER;
386 case PIN_CONFIG_DRIVE_STRENGTH:
387 /* Check for invalid values */
388 if (arg > 16 || arg < 2 || (arg % 2) != 0)
393 case PIN_CONFIG_OUTPUT:
394 /* set output value */
395 raw_spin_lock_irqsave(&pctrl->lock, flags);
396 val = msm_readl_io(pctrl, g);
398 val |= BIT(g->out_bit);
400 val &= ~BIT(g->out_bit);
401 msm_writel_io(val, pctrl, g);
402 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
407 case PIN_CONFIG_INPUT_ENABLE:
412 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
417 /* Range-check user-supplied value */
419 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
423 raw_spin_lock_irqsave(&pctrl->lock, flags);
424 val = msm_readl_ctl(pctrl, g);
425 val &= ~(mask << bit);
427 msm_writel_ctl(val, pctrl, g);
428 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
434 static const struct pinconf_ops msm_pinconf_ops = {
436 .pin_config_group_get = msm_config_group_get,
437 .pin_config_group_set = msm_config_group_set,
440 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
442 const struct msm_pingroup *g;
443 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
447 g = &pctrl->soc->groups[offset];
449 raw_spin_lock_irqsave(&pctrl->lock, flags);
451 val = msm_readl_ctl(pctrl, g);
452 val &= ~BIT(g->oe_bit);
453 msm_writel_ctl(val, pctrl, g);
455 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
460 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
462 const struct msm_pingroup *g;
463 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
467 g = &pctrl->soc->groups[offset];
469 raw_spin_lock_irqsave(&pctrl->lock, flags);
471 val = msm_readl_io(pctrl, g);
473 val |= BIT(g->out_bit);
475 val &= ~BIT(g->out_bit);
476 msm_writel_io(val, pctrl, g);
478 val = msm_readl_ctl(pctrl, g);
479 val |= BIT(g->oe_bit);
480 msm_writel_ctl(val, pctrl, g);
482 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
487 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
489 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
490 const struct msm_pingroup *g;
493 g = &pctrl->soc->groups[offset];
495 val = msm_readl_ctl(pctrl, g);
497 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :
498 GPIO_LINE_DIRECTION_IN;
501 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
503 const struct msm_pingroup *g;
504 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
507 g = &pctrl->soc->groups[offset];
509 val = msm_readl_io(pctrl, g);
510 return !!(val & BIT(g->in_bit));
513 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
515 const struct msm_pingroup *g;
516 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
520 g = &pctrl->soc->groups[offset];
522 raw_spin_lock_irqsave(&pctrl->lock, flags);
524 val = msm_readl_io(pctrl, g);
526 val |= BIT(g->out_bit);
528 val &= ~BIT(g->out_bit);
529 msm_writel_io(val, pctrl, g);
531 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
534 #ifdef CONFIG_DEBUG_FS
535 #include <linux/seq_file.h>
537 static void msm_gpio_dbg_show_one(struct seq_file *s,
538 struct pinctrl_dev *pctldev,
539 struct gpio_chip *chip,
543 const struct msm_pingroup *g;
544 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
552 static const char * const pulls_keeper[] = {
559 static const char * const pulls_no_keeper[] = {
565 if (!gpiochip_line_is_valid(chip, offset))
568 g = &pctrl->soc->groups[offset];
569 ctl_reg = msm_readl_ctl(pctrl, g);
570 io_reg = msm_readl_io(pctrl, g);
572 is_out = !!(ctl_reg & BIT(g->oe_bit));
573 func = (ctl_reg >> g->mux_bit) & 7;
574 drive = (ctl_reg >> g->drv_bit) & 7;
575 pull = (ctl_reg >> g->pull_bit) & 3;
578 val = !!(io_reg & BIT(g->out_bit));
580 val = !!(io_reg & BIT(g->in_bit));
582 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
583 seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
584 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
585 if (pctrl->soc->pull_no_keeper)
586 seq_printf(s, " %s", pulls_no_keeper[pull]);
588 seq_printf(s, " %s", pulls_keeper[pull]);
592 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
594 unsigned gpio = chip->base;
597 for (i = 0; i < chip->ngpio; i++, gpio++)
598 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
602 #define msm_gpio_dbg_show NULL
605 static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
606 unsigned long *valid_mask,
609 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
612 const int *reserved = pctrl->soc->reserved_gpios;
615 /* Driver provided reserved list overrides DT and ACPI */
617 bitmap_fill(valid_mask, ngpios);
618 for (i = 0; reserved[i] >= 0; i++) {
619 if (i >= ngpios || reserved[i] >= ngpios) {
620 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
623 clear_bit(reserved[i], valid_mask);
629 /* The number of GPIOs in the ACPI tables */
630 len = ret = device_property_count_u16(pctrl->dev, "gpios");
637 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
641 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
643 dev_err(pctrl->dev, "could not read list of GPIOs\n");
647 bitmap_zero(valid_mask, ngpios);
648 for (i = 0; i < len; i++)
649 set_bit(tmp[i], valid_mask);
656 static const struct gpio_chip msm_gpio_template = {
657 .direction_input = msm_gpio_direction_input,
658 .direction_output = msm_gpio_direction_output,
659 .get_direction = msm_gpio_get_direction,
662 .request = gpiochip_generic_request,
663 .free = gpiochip_generic_free,
664 .dbg_show = msm_gpio_dbg_show,
667 /* For dual-edge interrupts in software, since some hardware has no
670 * At appropriate moments, this function may be called to flip the polarity
671 * settings of both-edge irq lines to try and catch the next edge.
673 * The attempt is considered successful if:
674 * - the status bit goes high, indicating that an edge was caught, or
675 * - the input value of the gpio doesn't change during the attempt.
676 * If the value changes twice during the process, that would cause the first
677 * test to fail but would force the second, as two opposite
678 * transitions would cause a detection no matter the polarity setting.
680 * The do-loop tries to sledge-hammer closed the timing hole between
681 * the initial value-read and the polarity-write - if the line value changes
682 * during that window, an interrupt is lost, the new polarity setting is
683 * incorrect, and the first success test will fail, causing a retry.
685 * Algorithm comes from Google's msmgpio driver.
687 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
688 const struct msm_pingroup *g,
691 int loop_limit = 100;
692 unsigned val, val2, intstat;
696 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
698 pol = msm_readl_intr_cfg(pctrl, g);
699 pol ^= BIT(g->intr_polarity_bit);
700 msm_writel_intr_cfg(pol, pctrl, g);
702 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
703 intstat = msm_readl_intr_status(pctrl, g);
704 if (intstat || (val == val2))
706 } while (loop_limit-- > 0);
707 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
711 static void msm_gpio_irq_mask(struct irq_data *d)
713 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
714 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
715 const struct msm_pingroup *g;
720 irq_chip_mask_parent(d);
722 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
725 g = &pctrl->soc->groups[d->hwirq];
727 raw_spin_lock_irqsave(&pctrl->lock, flags);
729 val = msm_readl_intr_cfg(pctrl, g);
731 * There are two bits that control interrupt forwarding to the CPU. The
732 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be
733 * latched into the interrupt status register when the hardware detects
734 * an irq that it's configured for (either edge for edge type or level
735 * for level type irq). The 'non-raw' status enable bit causes the
736 * hardware to assert the summary interrupt to the CPU if the latched
737 * status bit is set. There's a bug though, the edge detection logic
738 * seems to have a problem where toggling the RAW_STATUS_EN bit may
739 * cause the status bit to latch spuriously when there isn't any edge
740 * so we can't touch that bit for edge type irqs and we have to keep
741 * the bit set anyway so that edges are latched while the line is masked.
743 * To make matters more complicated, leaving the RAW_STATUS_EN bit
744 * enabled all the time causes level interrupts to re-latch into the
745 * status register because the level is still present on the line after
746 * we ack it. We clear the raw status enable bit during mask here and
747 * set the bit on unmask so the interrupt can't latch into the hardware
750 if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
751 val &= ~BIT(g->intr_raw_status_bit);
753 val &= ~BIT(g->intr_enable_bit);
754 msm_writel_intr_cfg(val, pctrl, g);
756 clear_bit(d->hwirq, pctrl->enabled_irqs);
758 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
761 static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear)
763 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
764 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
765 const struct msm_pingroup *g;
770 irq_chip_unmask_parent(d);
772 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
775 g = &pctrl->soc->groups[d->hwirq];
777 raw_spin_lock_irqsave(&pctrl->lock, flags);
781 * clear the interrupt status bit before unmask to avoid
782 * any erroneous interrupts that would have got latched
783 * when the interrupt is not in use.
785 val = msm_readl_intr_status(pctrl, g);
786 val &= ~BIT(g->intr_status_bit);
787 msm_writel_intr_status(val, pctrl, g);
790 val = msm_readl_intr_cfg(pctrl, g);
791 val |= BIT(g->intr_raw_status_bit);
792 val |= BIT(g->intr_enable_bit);
793 msm_writel_intr_cfg(val, pctrl, g);
795 set_bit(d->hwirq, pctrl->enabled_irqs);
797 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
800 static void msm_gpio_irq_enable(struct irq_data *d)
803 * Clear the interrupt that may be pending before we enable
805 * This is especially a problem with the GPIOs routed to the
806 * PDC. These GPIOs are direct-connect interrupts to the GIC.
807 * Disabling the interrupt line at the PDC does not prevent
808 * the interrupt from being latched at the GIC. The state at
809 * GIC needs to be cleared before enabling.
811 if (d->parent_data) {
812 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, 0);
813 irq_chip_enable_parent(d);
816 msm_gpio_irq_clear_unmask(d, true);
819 static void msm_gpio_irq_disable(struct irq_data *d)
821 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
822 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
825 irq_chip_disable_parent(d);
827 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
828 msm_gpio_irq_mask(d);
831 static void msm_gpio_irq_unmask(struct irq_data *d)
833 msm_gpio_irq_clear_unmask(d, false);
836 static void msm_gpio_irq_ack(struct irq_data *d)
838 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
839 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
840 const struct msm_pingroup *g;
844 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
847 g = &pctrl->soc->groups[d->hwirq];
849 raw_spin_lock_irqsave(&pctrl->lock, flags);
851 val = msm_readl_intr_status(pctrl, g);
852 if (g->intr_ack_high)
853 val |= BIT(g->intr_status_bit);
855 val &= ~BIT(g->intr_status_bit);
856 msm_writel_intr_status(val, pctrl, g);
858 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
859 msm_gpio_update_dual_edge_pos(pctrl, g, d);
861 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
864 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
866 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
867 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
868 const struct msm_pingroup *g;
873 irq_chip_set_type_parent(d, type);
875 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
878 g = &pctrl->soc->groups[d->hwirq];
880 raw_spin_lock_irqsave(&pctrl->lock, flags);
883 * For hw without possibility of detecting both edges
885 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
886 set_bit(d->hwirq, pctrl->dual_edge_irqs);
888 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
890 /* Route interrupts to application cpu.
891 * With intr_target_use_scm interrupts are routed to
892 * application cpu using scm calls.
894 if (pctrl->intr_target_use_scm) {
895 u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
898 qcom_scm_io_readl(addr, &val);
900 val &= ~(7 << g->intr_target_bit);
901 val |= g->intr_target_kpss_val << g->intr_target_bit;
903 ret = qcom_scm_io_writel(addr, val);
906 "Failed routing %lu interrupt to Apps proc",
909 val = msm_readl_intr_target(pctrl, g);
910 val &= ~(7 << g->intr_target_bit);
911 val |= g->intr_target_kpss_val << g->intr_target_bit;
912 msm_writel_intr_target(val, pctrl, g);
915 /* Update configuration for gpio.
916 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
917 * internal circuitry of TLMM, toggling the RAW_STATUS
918 * could cause the INTR_STATUS to be set for EDGE interrupts.
920 val = msm_readl_intr_cfg(pctrl, g);
921 val |= BIT(g->intr_raw_status_bit);
922 if (g->intr_detection_width == 2) {
923 val &= ~(3 << g->intr_detection_bit);
924 val &= ~(1 << g->intr_polarity_bit);
926 case IRQ_TYPE_EDGE_RISING:
927 val |= 1 << g->intr_detection_bit;
928 val |= BIT(g->intr_polarity_bit);
930 case IRQ_TYPE_EDGE_FALLING:
931 val |= 2 << g->intr_detection_bit;
932 val |= BIT(g->intr_polarity_bit);
934 case IRQ_TYPE_EDGE_BOTH:
935 val |= 3 << g->intr_detection_bit;
936 val |= BIT(g->intr_polarity_bit);
938 case IRQ_TYPE_LEVEL_LOW:
940 case IRQ_TYPE_LEVEL_HIGH:
941 val |= BIT(g->intr_polarity_bit);
944 } else if (g->intr_detection_width == 1) {
945 val &= ~(1 << g->intr_detection_bit);
946 val &= ~(1 << g->intr_polarity_bit);
948 case IRQ_TYPE_EDGE_RISING:
949 val |= BIT(g->intr_detection_bit);
950 val |= BIT(g->intr_polarity_bit);
952 case IRQ_TYPE_EDGE_FALLING:
953 val |= BIT(g->intr_detection_bit);
955 case IRQ_TYPE_EDGE_BOTH:
956 val |= BIT(g->intr_detection_bit);
957 val |= BIT(g->intr_polarity_bit);
959 case IRQ_TYPE_LEVEL_LOW:
961 case IRQ_TYPE_LEVEL_HIGH:
962 val |= BIT(g->intr_polarity_bit);
968 msm_writel_intr_cfg(val, pctrl, g);
970 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
971 msm_gpio_update_dual_edge_pos(pctrl, g, d);
973 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
975 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
976 irq_set_handler_locked(d, handle_level_irq);
977 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
978 irq_set_handler_locked(d, handle_edge_irq);
983 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
985 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
986 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
989 * While they may not wake up when the TLMM is powered off,
990 * some GPIOs would like to wakeup the system from suspend
991 * when TLMM is powered on. To allow that, enable the GPIO
992 * summary line to be wakeup capable at GIC.
995 irq_chip_set_wake_parent(d, on);
997 irq_set_irq_wake(pctrl->irq, on);
1002 static int msm_gpio_irq_reqres(struct irq_data *d)
1004 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1005 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1008 if (!try_module_get(gc->owner))
1011 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
1014 msm_gpio_direction_input(gc, d->hwirq);
1016 if (gpiochip_lock_as_irq(gc, d->hwirq)) {
1018 "unable to lock HW IRQ %lu for IRQ\n",
1025 module_put(gc->owner);
1029 static void msm_gpio_irq_relres(struct irq_data *d)
1031 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1033 gpiochip_unlock_as_irq(gc, d->hwirq);
1034 module_put(gc->owner);
1037 static int msm_gpio_irq_set_affinity(struct irq_data *d,
1038 const struct cpumask *dest, bool force)
1040 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1041 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1043 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1044 return irq_chip_set_affinity_parent(d, dest, force);
1049 static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1051 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1052 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1054 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1055 return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
1060 static void msm_gpio_irq_handler(struct irq_desc *desc)
1062 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1063 const struct msm_pingroup *g;
1064 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1065 struct irq_chip *chip = irq_desc_get_chip(desc);
1071 chained_irq_enter(chip, desc);
1074 * Each pin has it's own IRQ status register, so use
1075 * enabled_irq bitmap to limit the number of reads.
1077 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
1078 g = &pctrl->soc->groups[i];
1079 val = msm_readl_intr_status(pctrl, g);
1080 if (val & BIT(g->intr_status_bit)) {
1081 irq_pin = irq_find_mapping(gc->irq.domain, i);
1082 generic_handle_irq(irq_pin);
1087 /* No interrupts were flagged */
1089 handle_bad_irq(desc);
1091 chained_irq_exit(chip, desc);
1094 static int msm_gpio_wakeirq(struct gpio_chip *gc,
1096 unsigned int child_type,
1097 unsigned int *parent,
1098 unsigned int *parent_type)
1100 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1101 const struct msm_gpio_wakeirq_map *map;
1104 *parent = GPIO_NO_WAKE_IRQ;
1105 *parent_type = IRQ_TYPE_EDGE_RISING;
1107 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
1108 map = &pctrl->soc->wakeirq_map[i];
1109 if (map->gpio == child) {
1110 *parent = map->wakeirq;
1118 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
1120 if (pctrl->soc->reserved_gpios)
1123 return device_property_count_u16(pctrl->dev, "gpios") > 0;
1126 static int msm_gpio_init(struct msm_pinctrl *pctrl)
1128 struct gpio_chip *chip;
1129 struct gpio_irq_chip *girq;
1131 unsigned gpio, ngpio = pctrl->soc->ngpios;
1132 struct device_node *np;
1135 if (WARN_ON(ngpio > MAX_NR_GPIO))
1138 chip = &pctrl->chip;
1140 chip->ngpio = ngpio;
1141 chip->label = dev_name(pctrl->dev);
1142 chip->parent = pctrl->dev;
1143 chip->owner = THIS_MODULE;
1144 chip->of_node = pctrl->dev->of_node;
1145 if (msm_gpio_needs_valid_mask(pctrl))
1146 chip->init_valid_mask = msm_gpio_init_valid_mask;
1148 pctrl->irq_chip.name = "msmgpio";
1149 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
1150 pctrl->irq_chip.irq_disable = msm_gpio_irq_disable;
1151 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
1152 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
1153 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
1154 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
1155 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
1156 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
1157 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
1158 pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity;
1159 pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity;
1161 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
1163 chip->irq.parent_domain = irq_find_matching_host(np,
1166 if (!chip->irq.parent_domain)
1167 return -EPROBE_DEFER;
1168 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
1169 pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent;
1171 * Let's skip handling the GPIOs, if the parent irqchip
1172 * is handling the direct connect IRQ of the GPIO.
1174 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain);
1175 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
1176 gpio = pctrl->soc->wakeirq_map[i].gpio;
1177 set_bit(gpio, pctrl->skip_wake_irqs);
1182 girq->chip = &pctrl->irq_chip;
1183 girq->parent_handler = msm_gpio_irq_handler;
1184 girq->fwnode = pctrl->dev->fwnode;
1185 girq->num_parents = 1;
1186 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
1190 girq->default_type = IRQ_TYPE_NONE;
1191 girq->handler = handle_bad_irq;
1192 girq->parents[0] = pctrl->irq;
1194 ret = gpiochip_add_data(&pctrl->chip, pctrl);
1196 dev_err(pctrl->dev, "Failed register gpiochip\n");
1201 * For DeviceTree-supported systems, the gpio core checks the
1202 * pinctrl's device node for the "gpio-ranges" property.
1203 * If it is present, it takes care of adding the pin ranges
1204 * for the driver. In this case the driver can skip ahead.
1206 * In order to remain compatible with older, existing DeviceTree
1207 * files which don't set the "gpio-ranges" property or systems that
1208 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1210 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1211 ret = gpiochip_add_pin_range(&pctrl->chip,
1212 dev_name(pctrl->dev), 0, 0, chip->ngpio);
1214 dev_err(pctrl->dev, "Failed to add pin range\n");
1215 gpiochip_remove(&pctrl->chip);
1223 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
1226 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1228 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1233 static struct msm_pinctrl *poweroff_pctrl;
1235 static void msm_ps_hold_poweroff(void)
1237 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
1240 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1243 const struct msm_function *func = pctrl->soc->functions;
1245 for (i = 0; i < pctrl->soc->nfunctions; i++)
1246 if (!strcmp(func[i].name, "ps_hold")) {
1247 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1248 pctrl->restart_nb.priority = 128;
1249 if (register_restart_handler(&pctrl->restart_nb))
1251 "failed to setup restart handler.\n");
1252 poweroff_pctrl = pctrl;
1253 pm_power_off = msm_ps_hold_poweroff;
1258 static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
1260 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1262 return pinctrl_force_sleep(pctrl->pctrl);
1265 static __maybe_unused int msm_pinctrl_resume(struct device *dev)
1267 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1269 return pinctrl_force_default(pctrl->pctrl);
1272 SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1273 msm_pinctrl_resume);
1275 EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1277 int msm_pinctrl_probe(struct platform_device *pdev,
1278 const struct msm_pinctrl_soc_data *soc_data)
1280 struct msm_pinctrl *pctrl;
1281 struct resource *res;
1285 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1289 pctrl->dev = &pdev->dev;
1290 pctrl->soc = soc_data;
1291 pctrl->chip = msm_gpio_template;
1292 pctrl->intr_target_use_scm = of_device_is_compatible(
1293 pctrl->dev->of_node,
1294 "qcom,ipq8064-pinctrl");
1296 raw_spin_lock_init(&pctrl->lock);
1298 if (soc_data->tiles) {
1299 for (i = 0; i < soc_data->ntiles; i++) {
1300 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1301 soc_data->tiles[i]);
1302 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1303 if (IS_ERR(pctrl->regs[i]))
1304 return PTR_ERR(pctrl->regs[i]);
1307 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1308 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
1309 if (IS_ERR(pctrl->regs[0]))
1310 return PTR_ERR(pctrl->regs[0]);
1312 pctrl->phys_base[0] = res->start;
1315 msm_pinctrl_setup_pm_reset(pctrl);
1317 pctrl->irq = platform_get_irq(pdev, 0);
1321 pctrl->desc.owner = THIS_MODULE;
1322 pctrl->desc.pctlops = &msm_pinctrl_ops;
1323 pctrl->desc.pmxops = &msm_pinmux_ops;
1324 pctrl->desc.confops = &msm_pinconf_ops;
1325 pctrl->desc.name = dev_name(&pdev->dev);
1326 pctrl->desc.pins = pctrl->soc->pins;
1327 pctrl->desc.npins = pctrl->soc->npins;
1329 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1330 if (IS_ERR(pctrl->pctrl)) {
1331 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1332 return PTR_ERR(pctrl->pctrl);
1335 ret = msm_gpio_init(pctrl);
1339 platform_set_drvdata(pdev, pctrl);
1341 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1345 EXPORT_SYMBOL(msm_pinctrl_probe);
1347 int msm_pinctrl_remove(struct platform_device *pdev)
1349 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1351 gpiochip_remove(&pctrl->chip);
1353 unregister_restart_handler(&pctrl->restart_nb);
1357 EXPORT_SYMBOL(msm_pinctrl_remove);