2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/delay.h>
16 #include <linux/err.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/slab.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
29 #include <linux/spinlock.h>
30 #include <linux/reboot.h>
32 #include <linux/log2.h>
35 #include "../pinconf.h"
36 #include "pinctrl-msm.h"
37 #include "../pinctrl-utils.h"
39 #define MAX_NR_GPIO 300
40 #define PS_HOLD_OFFSET 0x820
43 * struct msm_pinctrl - state for a pinctrl-msm device
44 * @dev: device handle.
45 * @pctrl: pinctrl handle.
46 * @chip: gpiochip handle.
47 * @restart_nb: restart notifier block.
48 * @irq: parent irq for the TLMM irq_chip.
49 * @lock: Spinlock to protect register resources as well
50 * as msm_pinctrl data structures.
51 * @enabled_irqs: Bitmap of currently enabled irqs.
52 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
54 * @soc; Reference to soc_data of platform specific data.
55 * @regs: Base address for the TLMM register map.
59 struct pinctrl_dev *pctrl;
60 struct gpio_chip chip;
61 struct pinctrl_desc desc;
62 struct notifier_block restart_nb;
64 struct irq_chip irq_chip;
69 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
70 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
72 const struct msm_pinctrl_soc_data *soc;
76 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
78 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
80 return pctrl->soc->ngroups;
83 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
86 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
88 return pctrl->soc->groups[group].name;
91 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
93 const unsigned **pins,
96 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
98 *pins = pctrl->soc->groups[group].pins;
99 *num_pins = pctrl->soc->groups[group].npins;
103 static const struct pinctrl_ops msm_pinctrl_ops = {
104 .get_groups_count = msm_get_groups_count,
105 .get_group_name = msm_get_group_name,
106 .get_group_pins = msm_get_group_pins,
107 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
108 .dt_free_map = pinctrl_utils_free_map,
111 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
113 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
114 struct gpio_chip *chip = &pctrl->chip;
116 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
119 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
121 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
123 return pctrl->soc->nfunctions;
126 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
129 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
131 return pctrl->soc->functions[function].name;
134 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
136 const char * const **groups,
137 unsigned * const num_groups)
139 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
141 *groups = pctrl->soc->functions[function].groups;
142 *num_groups = pctrl->soc->functions[function].ngroups;
146 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
150 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
151 const struct msm_pingroup *g;
156 g = &pctrl->soc->groups[group];
157 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
159 for (i = 0; i < g->nfuncs; i++) {
160 if (g->funcs[i] == function)
164 if (WARN_ON(i == g->nfuncs))
167 raw_spin_lock_irqsave(&pctrl->lock, flags);
169 val = readl(pctrl->regs + g->ctl_reg);
171 val |= i << g->mux_bit;
172 writel(val, pctrl->regs + g->ctl_reg);
174 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
179 static const struct pinmux_ops msm_pinmux_ops = {
180 .request = msm_pinmux_request,
181 .get_functions_count = msm_get_functions_count,
182 .get_function_name = msm_get_function_name,
183 .get_function_groups = msm_get_function_groups,
184 .set_mux = msm_pinmux_set_mux,
187 static int msm_config_reg(struct msm_pinctrl *pctrl,
188 const struct msm_pingroup *g,
194 case PIN_CONFIG_BIAS_DISABLE:
195 case PIN_CONFIG_BIAS_PULL_DOWN:
196 case PIN_CONFIG_BIAS_BUS_HOLD:
197 case PIN_CONFIG_BIAS_PULL_UP:
201 case PIN_CONFIG_DRIVE_STRENGTH:
205 case PIN_CONFIG_OUTPUT:
206 case PIN_CONFIG_INPUT_ENABLE:
217 #define MSM_NO_PULL 0
218 #define MSM_PULL_DOWN 1
220 #define MSM_PULL_UP_NO_KEEPER 2
221 #define MSM_PULL_UP 3
223 static unsigned msm_regval_to_drive(u32 val)
225 return (val + 1) * 2;
228 static int msm_config_group_get(struct pinctrl_dev *pctldev,
230 unsigned long *config)
232 const struct msm_pingroup *g;
233 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
234 unsigned param = pinconf_to_config_param(*config);
241 g = &pctrl->soc->groups[group];
243 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
247 val = readl(pctrl->regs + g->ctl_reg);
248 arg = (val >> bit) & mask;
250 /* Convert register value to pinconf value */
252 case PIN_CONFIG_BIAS_DISABLE:
253 if (arg != MSM_NO_PULL)
257 case PIN_CONFIG_BIAS_PULL_DOWN:
258 if (arg != MSM_PULL_DOWN)
262 case PIN_CONFIG_BIAS_BUS_HOLD:
263 if (pctrl->soc->pull_no_keeper)
266 if (arg != MSM_KEEPER)
270 case PIN_CONFIG_BIAS_PULL_UP:
271 if (pctrl->soc->pull_no_keeper)
272 arg = arg == MSM_PULL_UP_NO_KEEPER;
274 arg = arg == MSM_PULL_UP;
278 case PIN_CONFIG_DRIVE_STRENGTH:
279 arg = msm_regval_to_drive(arg);
281 case PIN_CONFIG_OUTPUT:
282 /* Pin is not output */
286 val = readl(pctrl->regs + g->io_reg);
287 arg = !!(val & BIT(g->in_bit));
289 case PIN_CONFIG_INPUT_ENABLE:
299 *config = pinconf_to_config_packed(param, arg);
304 static int msm_config_group_set(struct pinctrl_dev *pctldev,
306 unsigned long *configs,
307 unsigned num_configs)
309 const struct msm_pingroup *g;
310 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
320 g = &pctrl->soc->groups[group];
322 for (i = 0; i < num_configs; i++) {
323 param = pinconf_to_config_param(configs[i]);
324 arg = pinconf_to_config_argument(configs[i]);
326 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
330 /* Convert pinconf values to register values */
332 case PIN_CONFIG_BIAS_DISABLE:
335 case PIN_CONFIG_BIAS_PULL_DOWN:
338 case PIN_CONFIG_BIAS_BUS_HOLD:
339 if (pctrl->soc->pull_no_keeper)
344 case PIN_CONFIG_BIAS_PULL_UP:
345 if (pctrl->soc->pull_no_keeper)
346 arg = MSM_PULL_UP_NO_KEEPER;
350 case PIN_CONFIG_DRIVE_STRENGTH:
351 /* Check for invalid values */
352 if (arg > 16 || arg < 2 || (arg % 2) != 0)
357 case PIN_CONFIG_OUTPUT:
358 /* set output value */
359 raw_spin_lock_irqsave(&pctrl->lock, flags);
360 val = readl(pctrl->regs + g->io_reg);
362 val |= BIT(g->out_bit);
364 val &= ~BIT(g->out_bit);
365 writel(val, pctrl->regs + g->io_reg);
366 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
371 case PIN_CONFIG_INPUT_ENABLE:
376 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
381 /* Range-check user-supplied value */
383 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
387 raw_spin_lock_irqsave(&pctrl->lock, flags);
388 val = readl(pctrl->regs + g->ctl_reg);
389 val &= ~(mask << bit);
391 writel(val, pctrl->regs + g->ctl_reg);
392 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
398 static const struct pinconf_ops msm_pinconf_ops = {
400 .pin_config_group_get = msm_config_group_get,
401 .pin_config_group_set = msm_config_group_set,
404 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
406 const struct msm_pingroup *g;
407 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
411 g = &pctrl->soc->groups[offset];
413 raw_spin_lock_irqsave(&pctrl->lock, flags);
415 val = readl(pctrl->regs + g->ctl_reg);
416 val &= ~BIT(g->oe_bit);
417 writel(val, pctrl->regs + g->ctl_reg);
419 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
424 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
426 const struct msm_pingroup *g;
427 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
431 g = &pctrl->soc->groups[offset];
433 raw_spin_lock_irqsave(&pctrl->lock, flags);
435 val = readl(pctrl->regs + g->io_reg);
437 val |= BIT(g->out_bit);
439 val &= ~BIT(g->out_bit);
440 writel(val, pctrl->regs + g->io_reg);
442 val = readl(pctrl->regs + g->ctl_reg);
443 val |= BIT(g->oe_bit);
444 writel(val, pctrl->regs + g->ctl_reg);
446 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
451 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
453 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
454 const struct msm_pingroup *g;
457 g = &pctrl->soc->groups[offset];
459 val = readl(pctrl->regs + g->ctl_reg);
461 /* 0 = output, 1 = input */
462 return val & BIT(g->oe_bit) ? 0 : 1;
465 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
467 const struct msm_pingroup *g;
468 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
471 g = &pctrl->soc->groups[offset];
473 val = readl(pctrl->regs + g->io_reg);
474 return !!(val & BIT(g->in_bit));
477 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
479 const struct msm_pingroup *g;
480 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
484 g = &pctrl->soc->groups[offset];
486 raw_spin_lock_irqsave(&pctrl->lock, flags);
488 val = readl(pctrl->regs + g->io_reg);
490 val |= BIT(g->out_bit);
492 val &= ~BIT(g->out_bit);
493 writel(val, pctrl->regs + g->io_reg);
495 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
498 #ifdef CONFIG_DEBUG_FS
499 #include <linux/seq_file.h>
501 static void msm_gpio_dbg_show_one(struct seq_file *s,
502 struct pinctrl_dev *pctldev,
503 struct gpio_chip *chip,
507 const struct msm_pingroup *g;
508 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
516 static const char * const pulls_keeper[] = {
523 static const char * const pulls_no_keeper[] = {
529 if (!gpiochip_line_is_valid(chip, offset))
532 g = &pctrl->soc->groups[offset];
533 ctl_reg = readl(pctrl->regs + g->ctl_reg);
534 io_reg = readl(pctrl->regs + g->io_reg);
536 is_out = !!(ctl_reg & BIT(g->oe_bit));
537 func = (ctl_reg >> g->mux_bit) & 7;
538 drive = (ctl_reg >> g->drv_bit) & 7;
539 pull = (ctl_reg >> g->pull_bit) & 3;
542 val = !!(io_reg & BIT(g->out_bit));
544 val = !!(io_reg & BIT(g->in_bit));
546 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
547 seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
548 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
549 if (pctrl->soc->pull_no_keeper)
550 seq_printf(s, " %s", pulls_no_keeper[pull]);
552 seq_printf(s, " %s", pulls_keeper[pull]);
556 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
558 unsigned gpio = chip->base;
561 for (i = 0; i < chip->ngpio; i++, gpio++)
562 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
566 #define msm_gpio_dbg_show NULL
569 static const struct gpio_chip msm_gpio_template = {
570 .direction_input = msm_gpio_direction_input,
571 .direction_output = msm_gpio_direction_output,
572 .get_direction = msm_gpio_get_direction,
575 .request = gpiochip_generic_request,
576 .free = gpiochip_generic_free,
577 .dbg_show = msm_gpio_dbg_show,
580 /* For dual-edge interrupts in software, since some hardware has no
583 * At appropriate moments, this function may be called to flip the polarity
584 * settings of both-edge irq lines to try and catch the next edge.
586 * The attempt is considered successful if:
587 * - the status bit goes high, indicating that an edge was caught, or
588 * - the input value of the gpio doesn't change during the attempt.
589 * If the value changes twice during the process, that would cause the first
590 * test to fail but would force the second, as two opposite
591 * transitions would cause a detection no matter the polarity setting.
593 * The do-loop tries to sledge-hammer closed the timing hole between
594 * the initial value-read and the polarity-write - if the line value changes
595 * during that window, an interrupt is lost, the new polarity setting is
596 * incorrect, and the first success test will fail, causing a retry.
598 * Algorithm comes from Google's msmgpio driver.
600 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
601 const struct msm_pingroup *g,
604 int loop_limit = 100;
605 unsigned val, val2, intstat;
609 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
611 pol = readl(pctrl->regs + g->intr_cfg_reg);
612 pol ^= BIT(g->intr_polarity_bit);
613 writel(pol, pctrl->regs + g->intr_cfg_reg);
615 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
616 intstat = readl(pctrl->regs + g->intr_status_reg);
617 if (intstat || (val == val2))
619 } while (loop_limit-- > 0);
620 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
624 static void msm_gpio_irq_mask(struct irq_data *d)
626 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
627 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
628 const struct msm_pingroup *g;
632 g = &pctrl->soc->groups[d->hwirq];
634 raw_spin_lock_irqsave(&pctrl->lock, flags);
636 val = readl(pctrl->regs + g->intr_cfg_reg);
637 val &= ~BIT(g->intr_enable_bit);
638 writel(val, pctrl->regs + g->intr_cfg_reg);
640 clear_bit(d->hwirq, pctrl->enabled_irqs);
642 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
645 static void msm_gpio_irq_unmask(struct irq_data *d)
647 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
648 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
649 const struct msm_pingroup *g;
653 g = &pctrl->soc->groups[d->hwirq];
655 raw_spin_lock_irqsave(&pctrl->lock, flags);
657 val = readl(pctrl->regs + g->intr_cfg_reg);
658 val |= BIT(g->intr_enable_bit);
659 writel(val, pctrl->regs + g->intr_cfg_reg);
661 set_bit(d->hwirq, pctrl->enabled_irqs);
663 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
666 static void msm_gpio_irq_ack(struct irq_data *d)
668 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
669 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
670 const struct msm_pingroup *g;
674 g = &pctrl->soc->groups[d->hwirq];
676 raw_spin_lock_irqsave(&pctrl->lock, flags);
678 val = readl(pctrl->regs + g->intr_status_reg);
679 if (g->intr_ack_high)
680 val |= BIT(g->intr_status_bit);
682 val &= ~BIT(g->intr_status_bit);
683 writel(val, pctrl->regs + g->intr_status_reg);
685 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
686 msm_gpio_update_dual_edge_pos(pctrl, g, d);
688 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
691 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
693 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
694 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
695 const struct msm_pingroup *g;
699 g = &pctrl->soc->groups[d->hwirq];
701 raw_spin_lock_irqsave(&pctrl->lock, flags);
704 * For hw without possibility of detecting both edges
706 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
707 set_bit(d->hwirq, pctrl->dual_edge_irqs);
709 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
711 /* Route interrupts to application cpu */
712 val = readl(pctrl->regs + g->intr_target_reg);
713 val &= ~(7 << g->intr_target_bit);
714 val |= g->intr_target_kpss_val << g->intr_target_bit;
715 writel(val, pctrl->regs + g->intr_target_reg);
717 /* Update configuration for gpio.
718 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
719 * internal circuitry of TLMM, toggling the RAW_STATUS
720 * could cause the INTR_STATUS to be set for EDGE interrupts.
722 val = readl(pctrl->regs + g->intr_cfg_reg);
723 val |= BIT(g->intr_raw_status_bit);
724 if (g->intr_detection_width == 2) {
725 val &= ~(3 << g->intr_detection_bit);
726 val &= ~(1 << g->intr_polarity_bit);
728 case IRQ_TYPE_EDGE_RISING:
729 val |= 1 << g->intr_detection_bit;
730 val |= BIT(g->intr_polarity_bit);
732 case IRQ_TYPE_EDGE_FALLING:
733 val |= 2 << g->intr_detection_bit;
734 val |= BIT(g->intr_polarity_bit);
736 case IRQ_TYPE_EDGE_BOTH:
737 val |= 3 << g->intr_detection_bit;
738 val |= BIT(g->intr_polarity_bit);
740 case IRQ_TYPE_LEVEL_LOW:
742 case IRQ_TYPE_LEVEL_HIGH:
743 val |= BIT(g->intr_polarity_bit);
746 } else if (g->intr_detection_width == 1) {
747 val &= ~(1 << g->intr_detection_bit);
748 val &= ~(1 << g->intr_polarity_bit);
750 case IRQ_TYPE_EDGE_RISING:
751 val |= BIT(g->intr_detection_bit);
752 val |= BIT(g->intr_polarity_bit);
754 case IRQ_TYPE_EDGE_FALLING:
755 val |= BIT(g->intr_detection_bit);
757 case IRQ_TYPE_EDGE_BOTH:
758 val |= BIT(g->intr_detection_bit);
759 val |= BIT(g->intr_polarity_bit);
761 case IRQ_TYPE_LEVEL_LOW:
763 case IRQ_TYPE_LEVEL_HIGH:
764 val |= BIT(g->intr_polarity_bit);
770 writel(val, pctrl->regs + g->intr_cfg_reg);
772 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
773 msm_gpio_update_dual_edge_pos(pctrl, g, d);
775 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
777 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
778 irq_set_handler_locked(d, handle_level_irq);
779 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
780 irq_set_handler_locked(d, handle_edge_irq);
785 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
787 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
788 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
791 raw_spin_lock_irqsave(&pctrl->lock, flags);
793 irq_set_irq_wake(pctrl->irq, on);
795 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
800 static void msm_gpio_irq_handler(struct irq_desc *desc)
802 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
803 const struct msm_pingroup *g;
804 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
805 struct irq_chip *chip = irq_desc_get_chip(desc);
811 chained_irq_enter(chip, desc);
814 * Each pin has it's own IRQ status register, so use
815 * enabled_irq bitmap to limit the number of reads.
817 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
818 g = &pctrl->soc->groups[i];
819 val = readl(pctrl->regs + g->intr_status_reg);
820 if (val & BIT(g->intr_status_bit)) {
821 irq_pin = irq_find_mapping(gc->irq.domain, i);
822 generic_handle_irq(irq_pin);
827 /* No interrupts were flagged */
829 handle_bad_irq(desc);
831 chained_irq_exit(chip, desc);
834 static int msm_gpio_init_valid_mask(struct gpio_chip *chip,
835 struct msm_pinctrl *pctrl)
839 unsigned int max_gpios = pctrl->soc->ngpios;
842 /* The number of GPIOs in the ACPI tables */
843 len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0);
850 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
854 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
856 dev_err(pctrl->dev, "could not read list of GPIOs\n");
860 bitmap_zero(chip->valid_mask, max_gpios);
861 for (i = 0; i < len; i++)
862 set_bit(tmp[i], chip->valid_mask);
869 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
871 return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0;
874 static int msm_gpio_init(struct msm_pinctrl *pctrl)
876 struct gpio_chip *chip;
878 unsigned ngpio = pctrl->soc->ngpios;
880 if (WARN_ON(ngpio > MAX_NR_GPIO))
886 chip->label = dev_name(pctrl->dev);
887 chip->parent = pctrl->dev;
888 chip->owner = THIS_MODULE;
889 chip->of_node = pctrl->dev->of_node;
890 chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl);
892 pctrl->irq_chip.name = "msmgpio";
893 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
894 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
895 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
896 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
897 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
899 ret = gpiochip_add_data(&pctrl->chip, pctrl);
901 dev_err(pctrl->dev, "Failed register gpiochip\n");
905 ret = msm_gpio_init_valid_mask(chip, pctrl);
907 dev_err(pctrl->dev, "Failed to setup irq valid bits\n");
908 gpiochip_remove(&pctrl->chip);
913 * For DeviceTree-supported systems, the gpio core checks the
914 * pinctrl's device node for the "gpio-ranges" property.
915 * If it is present, it takes care of adding the pin ranges
916 * for the driver. In this case the driver can skip ahead.
918 * In order to remain compatible with older, existing DeviceTree
919 * files which don't set the "gpio-ranges" property or systems that
920 * utilize ACPI the driver has to call gpiochip_add_pin_range().
922 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
923 ret = gpiochip_add_pin_range(&pctrl->chip,
924 dev_name(pctrl->dev), 0, 0, chip->ngpio);
926 dev_err(pctrl->dev, "Failed to add pin range\n");
927 gpiochip_remove(&pctrl->chip);
932 ret = gpiochip_irqchip_add(chip,
938 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
939 gpiochip_remove(&pctrl->chip);
943 gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq,
944 msm_gpio_irq_handler);
949 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
952 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
954 writel(0, pctrl->regs + PS_HOLD_OFFSET);
959 static struct msm_pinctrl *poweroff_pctrl;
961 static void msm_ps_hold_poweroff(void)
963 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
966 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
969 const struct msm_function *func = pctrl->soc->functions;
971 for (i = 0; i < pctrl->soc->nfunctions; i++)
972 if (!strcmp(func[i].name, "ps_hold")) {
973 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
974 pctrl->restart_nb.priority = 128;
975 if (register_restart_handler(&pctrl->restart_nb))
977 "failed to setup restart handler.\n");
978 poweroff_pctrl = pctrl;
979 pm_power_off = msm_ps_hold_poweroff;
984 int msm_pinctrl_probe(struct platform_device *pdev,
985 const struct msm_pinctrl_soc_data *soc_data)
987 struct msm_pinctrl *pctrl;
988 struct resource *res;
991 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
995 pctrl->dev = &pdev->dev;
996 pctrl->soc = soc_data;
997 pctrl->chip = msm_gpio_template;
999 raw_spin_lock_init(&pctrl->lock);
1001 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1002 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1003 if (IS_ERR(pctrl->regs))
1004 return PTR_ERR(pctrl->regs);
1006 msm_pinctrl_setup_pm_reset(pctrl);
1008 pctrl->irq = platform_get_irq(pdev, 0);
1009 if (pctrl->irq < 0) {
1010 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
1014 pctrl->desc.owner = THIS_MODULE;
1015 pctrl->desc.pctlops = &msm_pinctrl_ops;
1016 pctrl->desc.pmxops = &msm_pinmux_ops;
1017 pctrl->desc.confops = &msm_pinconf_ops;
1018 pctrl->desc.name = dev_name(&pdev->dev);
1019 pctrl->desc.pins = pctrl->soc->pins;
1020 pctrl->desc.npins = pctrl->soc->npins;
1022 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1023 if (IS_ERR(pctrl->pctrl)) {
1024 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1025 return PTR_ERR(pctrl->pctrl);
1028 ret = msm_gpio_init(pctrl);
1032 platform_set_drvdata(pdev, pctrl);
1034 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1038 EXPORT_SYMBOL(msm_pinctrl_probe);
1040 int msm_pinctrl_remove(struct platform_device *pdev)
1042 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1044 gpiochip_remove(&pctrl->chip);
1046 unregister_restart_handler(&pctrl->restart_nb);
1050 EXPORT_SYMBOL(msm_pinctrl_remove);