drivers/pinctrl/pinctrl-xway.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  linux/drivers/pinctrl/pinmux-xway.c
   4  *  based on linux/drivers/pinctrl/pinmux-pxa910.c
   5  *
   6  *  Copyright (C) 2012 John Crispin <john@phrozen.org>
   7  *  Copyright (C) 2015 Martin Schiller <mschiller@tdt.de>
   8  */
   9
  10 #include <linux/err.h>
  11 #include <linux/slab.h>
  12 #include <linux/module.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_gpio.h>
  16 #include <linux/ioport.h>
  17 #include <linux/io.h>
  18 #include <linux/device.h>
  19 #include <linux/platform_device.h>
  20
  21 #include "pinctrl-lantiq.h"
  22
  23 #include <lantiq_soc.h>
  24
  25 /* we have up to 4 banks of 16 bit each */
  26 #define PINS                    16
  27 #define PORT3                   3
  28 #define PORT(x)                 (x / PINS)
  29 #define PORT_PIN(x)             (x % PINS)
  30
  31 /* we have 2 mux bits that can be set for each pin */
  32 #define MUX_ALT0        0x1
  33 #define MUX_ALT1        0x2
  34
  35 /*
  36  * each bank has this offset apart from the 4th bank that is mixed into the
  37  * other 3 ranges
  38  */
  39 #define REG_OFF                 0x30
  40
  41 /* these are the offsets to our registers */
  42 #define GPIO_BASE(p)            (REG_OFF * PORT(p))
  43 #define GPIO_OUT(p)             GPIO_BASE(p)
  44 #define GPIO_IN(p)              (GPIO_BASE(p) + 0x04)
  45 #define GPIO_DIR(p)             (GPIO_BASE(p) + 0x08)
  46 #define GPIO_ALT0(p)            (GPIO_BASE(p) + 0x0C)
  47 #define GPIO_ALT1(p)            (GPIO_BASE(p) + 0x10)
  48 #define GPIO_OD(p)              (GPIO_BASE(p) + 0x14)
  49 #define GPIO_PUDSEL(p)          (GPIO_BASE(p) + 0x1c)
  50 #define GPIO_PUDEN(p)           (GPIO_BASE(p) + 0x20)
  51
  52 /* the 4th port needs special offsets for some registers */
  53 #define GPIO3_OD                (GPIO_BASE(0) + 0x24)
  54 #define GPIO3_PUDSEL            (GPIO_BASE(0) + 0x28)
  55 #define GPIO3_PUDEN             (GPIO_BASE(0) + 0x2C)
  56 #define GPIO3_ALT1              (GPIO_BASE(PINS) + 0x24)
  57
  58 /* macros to help us access the registers */
  59 #define gpio_getbit(m, r, p)    (!!(ltq_r32(m + r) & BIT(p)))
  60 #define gpio_setbit(m, r, p)    ltq_w32_mask(0, BIT(p), m + r)
  61 #define gpio_clearbit(m, r, p)  ltq_w32_mask(BIT(p), 0, m + r)
  62
  63 #define MFP_XWAY(a, f0, f1, f2, f3)     \
  64         {                               \
  65                 .name = #a,             \
  66                 .pin = a,               \
  67                 .func = {               \
  68                         XWAY_MUX_##f0,  \
  69                         XWAY_MUX_##f1,  \
  70                         XWAY_MUX_##f2,  \
  71                         XWAY_MUX_##f3,  \
  72                 },                      \
  73         }
  74
  75 #define GRP_MUX(a, m, p)                \
  76         { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }
  77
  78 #define FUNC_MUX(f, m)          \
  79         { .func = f, .mux = XWAY_MUX_##m, }
  80
  81 enum xway_mux {
  82         XWAY_MUX_GPIO = 0,
  83         XWAY_MUX_SPI,
  84         XWAY_MUX_ASC,
  85         XWAY_MUX_USIF,
  86         XWAY_MUX_PCI,
  87         XWAY_MUX_CBUS,
  88         XWAY_MUX_CGU,
  89         XWAY_MUX_EBU,
  90         XWAY_MUX_EBU2,
  91         XWAY_MUX_JTAG,
  92         XWAY_MUX_MCD,
  93         XWAY_MUX_EXIN,
  94         XWAY_MUX_TDM,
  95         XWAY_MUX_STP,
  96         XWAY_MUX_SIN,
  97         XWAY_MUX_GPT,
  98         XWAY_MUX_NMI,
  99         XWAY_MUX_MDIO,
 100         XWAY_MUX_MII,
 101         XWAY_MUX_EPHY,
 102         XWAY_MUX_DFE,
 103         XWAY_MUX_SDIO,
 104         XWAY_MUX_GPHY,
 105         XWAY_MUX_SSI,
 106         XWAY_MUX_WIFI,
 107         XWAY_MUX_NONE = 0xffff,
 108 };
 109
 110 /* ---------  DEPRECATED: xr9 related code --------- */
 111 /* ----------  use xrx100/xrx200 instead  ---------- */
 112 #define XR9_MAX_PIN             56
 113
 114 static const struct ltq_mfp_pin xway_mfp[] = {
 115         /*       pin    f0      f1      f2      f3   */
 116         MFP_XWAY(GPIO0, GPIO,   EXIN,   NONE,   TDM),
 117         MFP_XWAY(GPIO1, GPIO,   EXIN,   NONE,   NONE),
 118         MFP_XWAY(GPIO2, GPIO,   CGU,    EXIN,   GPHY),
 119         MFP_XWAY(GPIO3, GPIO,   CGU,    NONE,   PCI),
 120         MFP_XWAY(GPIO4, GPIO,   STP,    NONE,   ASC),
 121         MFP_XWAY(GPIO5, GPIO,   STP,    GPHY,   NONE),
 122         MFP_XWAY(GPIO6, GPIO,   STP,    GPT,    ASC),
 123         MFP_XWAY(GPIO7, GPIO,   CGU,    PCI,    GPHY),
 124         MFP_XWAY(GPIO8, GPIO,   CGU,    NMI,    NONE),
 125         MFP_XWAY(GPIO9, GPIO,   ASC,    SPI,    EXIN),
 126         MFP_XWAY(GPIO10, GPIO,  ASC,    SPI,    NONE),
 127         MFP_XWAY(GPIO11, GPIO,  ASC,    PCI,    SPI),
 128         MFP_XWAY(GPIO12, GPIO,  ASC,    NONE,   NONE),
 129         MFP_XWAY(GPIO13, GPIO,  EBU,    SPI,    NONE),
 130         MFP_XWAY(GPIO14, GPIO,  CGU,    PCI,    NONE),
 131         MFP_XWAY(GPIO15, GPIO,  SPI,    JTAG,   NONE),
 132         MFP_XWAY(GPIO16, GPIO,  SPI,    NONE,   JTAG),
 133         MFP_XWAY(GPIO17, GPIO,  SPI,    NONE,   JTAG),
 134         MFP_XWAY(GPIO18, GPIO,  SPI,    NONE,   JTAG),
 135         MFP_XWAY(GPIO19, GPIO,  PCI,    NONE,   NONE),
 136         MFP_XWAY(GPIO20, GPIO,  JTAG,   NONE,   NONE),
 137         MFP_XWAY(GPIO21, GPIO,  PCI,    EBU,    GPT),
 138         MFP_XWAY(GPIO22, GPIO,  SPI,    NONE,   NONE),
 139         MFP_XWAY(GPIO23, GPIO,  EBU,    PCI,    STP),
 140         MFP_XWAY(GPIO24, GPIO,  EBU,    TDM,    PCI),
 141         MFP_XWAY(GPIO25, GPIO,  TDM,    NONE,   ASC),
 142         MFP_XWAY(GPIO26, GPIO,  EBU,    NONE,   TDM),
 143         MFP_XWAY(GPIO27, GPIO,  TDM,    NONE,   ASC),
 144         MFP_XWAY(GPIO28, GPIO,  GPT,    NONE,   NONE),
 145         MFP_XWAY(GPIO29, GPIO,  PCI,    NONE,   NONE),
 146         MFP_XWAY(GPIO30, GPIO,  PCI,    NONE,   NONE),
 147         MFP_XWAY(GPIO31, GPIO,  EBU,    PCI,    NONE),
 148         MFP_XWAY(GPIO32, GPIO,  NONE,   NONE,   EBU),
 149         MFP_XWAY(GPIO33, GPIO,  NONE,   NONE,   EBU),
 150         MFP_XWAY(GPIO34, GPIO,  NONE,   NONE,   EBU),
 151         MFP_XWAY(GPIO35, GPIO,  NONE,   NONE,   EBU),
 152         MFP_XWAY(GPIO36, GPIO,  SIN,    NONE,   EBU),
 153         MFP_XWAY(GPIO37, GPIO,  PCI,    NONE,   NONE),
 154         MFP_XWAY(GPIO38, GPIO,  PCI,    NONE,   NONE),
 155         MFP_XWAY(GPIO39, GPIO,  EXIN,   NONE,   NONE),
 156         MFP_XWAY(GPIO40, GPIO,  NONE,   NONE,   NONE),
 157         MFP_XWAY(GPIO41, GPIO,  NONE,   NONE,   NONE),
 158         MFP_XWAY(GPIO42, GPIO,  MDIO,   NONE,   NONE),
 159         MFP_XWAY(GPIO43, GPIO,  MDIO,   NONE,   NONE),
 160         MFP_XWAY(GPIO44, GPIO,  MII,    SIN,    GPHY),
 161         MFP_XWAY(GPIO45, GPIO,  NONE,   GPHY,   SIN),
 162         MFP_XWAY(GPIO46, GPIO,  NONE,   NONE,   EXIN),
 163         MFP_XWAY(GPIO47, GPIO,  MII,    GPHY,   SIN),
 164         MFP_XWAY(GPIO48, GPIO,  EBU,    NONE,   NONE),
 165         MFP_XWAY(GPIO49, GPIO,  EBU,    NONE,   NONE),
 166         MFP_XWAY(GPIO50, GPIO,  NONE,   NONE,   NONE),
 167         MFP_XWAY(GPIO51, GPIO,  NONE,   NONE,   NONE),
 168         MFP_XWAY(GPIO52, GPIO,  NONE,   NONE,   NONE),
 169         MFP_XWAY(GPIO53, GPIO,  NONE,   NONE,   NONE),
 170         MFP_XWAY(GPIO54, GPIO,  NONE,   NONE,   NONE),
 171         MFP_XWAY(GPIO55, GPIO,  NONE,   NONE,   NONE),
 172 };
 173
 174 static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35};
 175 static const unsigned pins_asc0[] = {GPIO11, GPIO12};
 176 static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10};
 177 static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6};
 178 static const unsigned pins_nmi[] = {GPIO8};
 179 static const unsigned pins_mdio[] = {GPIO42, GPIO43};
 180
 181 static const unsigned pins_gphy0_led0[] = {GPIO5};
 182 static const unsigned pins_gphy0_led1[] = {GPIO7};
 183 static const unsigned pins_gphy0_led2[] = {GPIO2};
 184 static const unsigned pins_gphy1_led0[] = {GPIO44};
 185 static const unsigned pins_gphy1_led1[] = {GPIO45};
 186 static const unsigned pins_gphy1_led2[] = {GPIO47};
 187
 188 static const unsigned pins_ebu_a24[] = {GPIO13};
 189 static const unsigned pins_ebu_clk[] = {GPIO21};
 190 static const unsigned pins_ebu_cs1[] = {GPIO23};
 191 static const unsigned pins_ebu_a23[] = {GPIO24};
 192 static const unsigned pins_ebu_wait[] = {GPIO26};
 193 static const unsigned pins_ebu_a25[] = {GPIO31};
 194 static const unsigned pins_ebu_rdy[] = {GPIO48};
 195 static const unsigned pins_ebu_rd[] = {GPIO49};
 196
 197 static const unsigned pins_nand_ale[] = {GPIO13};
 198 static const unsigned pins_nand_cs1[] = {GPIO23};
 199 static const unsigned pins_nand_cle[] = {GPIO24};
 200 static const unsigned pins_nand_rdy[] = {GPIO48};
 201 static const unsigned pins_nand_rd[] = {GPIO49};
 202
 203 static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9};
 204
 205 static const unsigned pins_exin0[] = {GPIO0};
 206 static const unsigned pins_exin1[] = {GPIO1};
 207 static const unsigned pins_exin2[] = {GPIO2};
 208 static const unsigned pins_exin3[] = {GPIO39};
 209 static const unsigned pins_exin4[] = {GPIO46};
 210 static const unsigned pins_exin5[] = {GPIO9};
 211
 212 static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18};
 213 static const unsigned pins_spi_cs1[] = {GPIO15};
 214 static const unsigned pins_spi_cs2[] = {GPIO22};
 215 static const unsigned pins_spi_cs3[] = {GPIO13};
 216 static const unsigned pins_spi_cs4[] = {GPIO10};
 217 static const unsigned pins_spi_cs5[] = {GPIO9};
 218 static const unsigned pins_spi_cs6[] = {GPIO11};
 219
 220 static const unsigned pins_gpt1[] = {GPIO28};
 221 static const unsigned pins_gpt2[] = {GPIO21};
 222 static const unsigned pins_gpt3[] = {GPIO6};
 223
 224 static const unsigned pins_clkout0[] = {GPIO8};
 225 static const unsigned pins_clkout1[] = {GPIO7};
 226 static const unsigned pins_clkout2[] = {GPIO3};
 227 static const unsigned pins_clkout3[] = {GPIO2};
 228
 229 static const unsigned pins_pci_gnt1[] = {GPIO30};
 230 static const unsigned pins_pci_gnt2[] = {GPIO23};
 231 static const unsigned pins_pci_gnt3[] = {GPIO19};
 232 static const unsigned pins_pci_gnt4[] = {GPIO38};
 233 static const unsigned pins_pci_req1[] = {GPIO29};
 234 static const unsigned pins_pci_req2[] = {GPIO31};
 235 static const unsigned pins_pci_req3[] = {GPIO3};
 236 static const unsigned pins_pci_req4[] = {GPIO37};
 237
 238 static const struct ltq_pin_group xway_grps[] = {
 239         GRP_MUX("exin0", EXIN, pins_exin0),
 240         GRP_MUX("exin1", EXIN, pins_exin1),
 241         GRP_MUX("exin2", EXIN, pins_exin2),
 242         GRP_MUX("jtag", JTAG, pins_jtag),
 243         GRP_MUX("ebu a23", EBU, pins_ebu_a23),
 244         GRP_MUX("ebu a24", EBU, pins_ebu_a24),
 245         GRP_MUX("ebu a25", EBU, pins_ebu_a25),
 246         GRP_MUX("ebu clk", EBU, pins_ebu_clk),
 247         GRP_MUX("ebu cs1", EBU, pins_ebu_cs1),
 248         GRP_MUX("ebu wait", EBU, pins_ebu_wait),
 249         GRP_MUX("nand ale", EBU, pins_nand_ale),
 250         GRP_MUX("nand cs1", EBU, pins_nand_cs1),
 251         GRP_MUX("nand cle", EBU, pins_nand_cle),
 252         GRP_MUX("spi", SPI, pins_spi),
 253         GRP_MUX("spi_cs1", SPI, pins_spi_cs1),
 254         GRP_MUX("spi_cs2", SPI, pins_spi_cs2),
 255         GRP_MUX("spi_cs3", SPI, pins_spi_cs3),
 256         GRP_MUX("spi_cs4", SPI, pins_spi_cs4),
 257         GRP_MUX("spi_cs5", SPI, pins_spi_cs5),
 258         GRP_MUX("spi_cs6", SPI, pins_spi_cs6),
 259         GRP_MUX("asc0", ASC, pins_asc0),
 260         GRP_MUX("asc0 cts rts", ASC, pins_asc0_cts_rts),
 261         GRP_MUX("stp", STP, pins_stp),
 262         GRP_MUX("nmi", NMI, pins_nmi),
 263         GRP_MUX("gpt1", GPT, pins_gpt1),
 264         GRP_MUX("gpt2", GPT, pins_gpt2),
 265         GRP_MUX("gpt3", GPT, pins_gpt3),
 266         GRP_MUX("clkout0", CGU, pins_clkout0),
 267         GRP_MUX("clkout1", CGU, pins_clkout1),
 268         GRP_MUX("clkout2", CGU, pins_clkout2),
 269         GRP_MUX("clkout3", CGU, pins_clkout3),
 270         GRP_MUX("gnt1", PCI, pins_pci_gnt1),
 271         GRP_MUX("gnt2", PCI, pins_pci_gnt2),
 272         GRP_MUX("gnt3", PCI, pins_pci_gnt3),
 273         GRP_MUX("req1", PCI, pins_pci_req1),
 274         GRP_MUX("req2", PCI, pins_pci_req2),
 275         GRP_MUX("req3", PCI, pins_pci_req3),
 276 /* xrx only */
 277         GRP_MUX("nand rdy", EBU, pins_nand_rdy),
 278         GRP_MUX("nand rd", EBU, pins_nand_rd),
 279         GRP_MUX("exin3", EXIN, pins_exin3),
 280         GRP_MUX("exin4", EXIN, pins_exin4),
 281         GRP_MUX("exin5", EXIN, pins_exin5),
 282         GRP_MUX("gnt4", PCI, pins_pci_gnt4),
 283         GRP_MUX("req4", PCI, pins_pci_gnt4),
 284         GRP_MUX("mdio", MDIO, pins_mdio),
 285         GRP_MUX("gphy0 led0", GPHY, pins_gphy0_led0),
 286         GRP_MUX("gphy0 led1", GPHY, pins_gphy0_led1),
 287         GRP_MUX("gphy0 led2", GPHY, pins_gphy0_led2),
 288         GRP_MUX("gphy1 led0", GPHY, pins_gphy1_led0),
 289         GRP_MUX("gphy1 led1", GPHY, pins_gphy1_led1),
 290         GRP_MUX("gphy1 led2", GPHY, pins_gphy1_led2),
 291 };
 292
 293 static const char * const xway_pci_grps[] = {"gnt1", "gnt2",
 294                                                 "gnt3", "req1",
 295                                                 "req2", "req3"};
 296 static const char * const xway_spi_grps[] = {"spi", "spi_cs1",
 297                                                 "spi_cs2", "spi_cs3",
 298                                                 "spi_cs4", "spi_cs5",
 299                                                 "spi_cs6"};
 300 static const char * const xway_cgu_grps[] = {"clkout0", "clkout1",
 301                                                 "clkout2", "clkout3"};
 302 static const char * const xway_ebu_grps[] = {"ebu a23", "ebu a24",
 303                                                 "ebu a25", "ebu cs1",
 304                                                 "ebu wait", "ebu clk",
 305                                                 "nand ale", "nand cs1",
 306                                                 "nand cle"};
 307 static const char * const xway_exin_grps[] = {"exin0", "exin1", "exin2"};
 308 static const char * const xway_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
 309 static const char * const xway_asc_grps[] = {"asc0", "asc0 cts rts"};
 310 static const char * const xway_jtag_grps[] = {"jtag"};
 311 static const char * const xway_stp_grps[] = {"stp"};
 312 static const char * const xway_nmi_grps[] = {"nmi"};
 313
 314 /* ar9/vr9/gr9 */
 315 static const char * const xrx_mdio_grps[] = {"mdio"};
 316 static const char * const xrx_gphy_grps[] = {"gphy0 led0", "gphy0 led1",
 317                                                 "gphy0 led2", "gphy1 led0",
 318                                                 "gphy1 led1", "gphy1 led2"};
 319 static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24",
 320                                                 "ebu a25", "ebu cs1",
 321                                                 "ebu wait", "ebu clk",
 322                                                 "nand ale", "nand cs1",
 323                                                 "nand cle", "nand rdy",
 324                                                 "nand rd"};
 325 static const char * const xrx_exin_grps[] = {"exin0", "exin1", "exin2",
 326                                                 "exin3", "exin4", "exin5"};
 327 static const char * const xrx_pci_grps[] = {"gnt1", "gnt2",
 328                                                 "gnt3", "gnt4",
 329                                                 "req1", "req2",
 330                                                 "req3", "req4"};
 331
 332 static const struct ltq_pmx_func xrx_funcs[] = {
 333         {"spi",         ARRAY_AND_SIZE(xway_spi_grps)},
 334         {"asc",         ARRAY_AND_SIZE(xway_asc_grps)},
 335         {"cgu",         ARRAY_AND_SIZE(xway_cgu_grps)},
 336         {"jtag",        ARRAY_AND_SIZE(xway_jtag_grps)},
 337         {"exin",        ARRAY_AND_SIZE(xrx_exin_grps)},
 338         {"stp",         ARRAY_AND_SIZE(xway_stp_grps)},
 339         {"gpt",         ARRAY_AND_SIZE(xway_gpt_grps)},
 340         {"nmi",         ARRAY_AND_SIZE(xway_nmi_grps)},
 341         {"pci",         ARRAY_AND_SIZE(xrx_pci_grps)},
 342         {"ebu",         ARRAY_AND_SIZE(xrx_ebu_grps)},
 343         {"mdio",        ARRAY_AND_SIZE(xrx_mdio_grps)},
 344         {"gphy",        ARRAY_AND_SIZE(xrx_gphy_grps)},
 345 };
 346
 347 /* ---------  ase related code --------- */
 348 #define ASE_MAX_PIN             32
 349
 350 static const struct ltq_mfp_pin ase_mfp[] = {
 351         /*       pin    f0      f1      f2      f3   */
 352         MFP_XWAY(GPIO0, GPIO,   EXIN,   MII,    TDM),
 353         MFP_XWAY(GPIO1, GPIO,   STP,    DFE,    EBU),
 354         MFP_XWAY(GPIO2, GPIO,   STP,    DFE,    EPHY),
 355         MFP_XWAY(GPIO3, GPIO,   STP,    EPHY,   EBU),
 356         MFP_XWAY(GPIO4, GPIO,   GPT,    EPHY,   MII),
 357         MFP_XWAY(GPIO5, GPIO,   MII,    ASC,    GPT),
 358         MFP_XWAY(GPIO6, GPIO,   MII,    ASC,    EXIN),
 359         MFP_XWAY(GPIO7, GPIO,   SPI,    MII,    JTAG),
 360         MFP_XWAY(GPIO8, GPIO,   SPI,    MII,    JTAG),
 361         MFP_XWAY(GPIO9, GPIO,   SPI,    MII,    JTAG),
 362         MFP_XWAY(GPIO10, GPIO,  SPI,    MII,    JTAG),
 363         MFP_XWAY(GPIO11, GPIO,  EBU,    CGU,    JTAG),
 364         MFP_XWAY(GPIO12, GPIO,  EBU,    MII,    SDIO),
 365         MFP_XWAY(GPIO13, GPIO,  EBU,    MII,    CGU),
 366         MFP_XWAY(GPIO14, GPIO,  EBU,    SPI,    CGU),
 367         MFP_XWAY(GPIO15, GPIO,  EBU,    SPI,    SDIO),
 368         MFP_XWAY(GPIO16, GPIO,  NONE,   NONE,   NONE),
 369         MFP_XWAY(GPIO17, GPIO,  NONE,   NONE,   NONE),
 370         MFP_XWAY(GPIO18, GPIO,  NONE,   NONE,   NONE),
 371         MFP_XWAY(GPIO19, GPIO,  EBU,    MII,    SDIO),
 372         MFP_XWAY(GPIO20, GPIO,  EBU,    MII,    SDIO),
 373         MFP_XWAY(GPIO21, GPIO,  EBU,    MII,    EBU2),
 374         MFP_XWAY(GPIO22, GPIO,  EBU,    MII,    CGU),
 375         MFP_XWAY(GPIO23, GPIO,  EBU,    MII,    CGU),
 376         MFP_XWAY(GPIO24, GPIO,  EBU,    EBU2,   MDIO),
 377         MFP_XWAY(GPIO25, GPIO,  EBU,    MII,    GPT),
 378         MFP_XWAY(GPIO26, GPIO,  EBU,    MII,    SDIO),
 379         MFP_XWAY(GPIO27, GPIO,  EBU,    NONE,   MDIO),
 380         MFP_XWAY(GPIO28, GPIO,  MII,    EBU,    SDIO),
 381         MFP_XWAY(GPIO29, GPIO,  EBU,    MII,    EXIN),
 382         MFP_XWAY(GPIO30, GPIO,  NONE,   NONE,   NONE),
 383         MFP_XWAY(GPIO31, GPIO,  NONE,   NONE,   NONE),
 384 };
 385
 386 static const unsigned ase_exin_pin_map[] = {GPIO6, GPIO29, GPIO0};
 387
 388 static const unsigned ase_pins_exin0[] = {GPIO6};
 389 static const unsigned ase_pins_exin1[] = {GPIO29};
 390 static const unsigned ase_pins_exin2[] = {GPIO0};
 391
 392 static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};
 393 static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};
 394 static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};
 395 static const unsigned ase_pins_mdio[] = {GPIO24, GPIO27};
 396 static const unsigned ase_pins_ephy_led0[] = {GPIO2};
 397 static const unsigned ase_pins_ephy_led1[] = {GPIO3};
 398 static const unsigned ase_pins_ephy_led2[] = {GPIO4};
 399 static const unsigned ase_pins_dfe_led0[] = {GPIO1};
 400 static const unsigned ase_pins_dfe_led1[] = {GPIO2};
 401
 402 static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; /* DEPRECATED */
 403 static const unsigned ase_pins_spi_di[] = {GPIO8};
 404 static const unsigned ase_pins_spi_do[] = {GPIO9};
 405 static const unsigned ase_pins_spi_clk[] = {GPIO10};
 406 static const unsigned ase_pins_spi_cs1[] = {GPIO7};
 407 static const unsigned ase_pins_spi_cs2[] = {GPIO15};
 408 static const unsigned ase_pins_spi_cs3[] = {GPIO14};
 409
 410 static const unsigned ase_pins_gpt1[] = {GPIO5};
 411 static const unsigned ase_pins_gpt2[] = {GPIO4};
 412 static const unsigned ase_pins_gpt3[] = {GPIO25};
 413
 414 static const unsigned ase_pins_clkout0[] = {GPIO23};
 415 static const unsigned ase_pins_clkout1[] = {GPIO22};
 416 static const unsigned ase_pins_clkout2[] = {GPIO14};
 417
 418 static const struct ltq_pin_group ase_grps[] = {
 419         GRP_MUX("exin0", EXIN, ase_pins_exin0),
 420         GRP_MUX("exin1", EXIN, ase_pins_exin1),
 421         GRP_MUX("exin2", EXIN, ase_pins_exin2),
 422         GRP_MUX("jtag", JTAG, ase_pins_jtag),
 423         GRP_MUX("spi", SPI, ase_pins_spi), /* DEPRECATED */
 424         GRP_MUX("spi_di", SPI, ase_pins_spi_di),
 425         GRP_MUX("spi_do", SPI, ase_pins_spi_do),
 426         GRP_MUX("spi_clk", SPI, ase_pins_spi_clk),
 427         GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
 428         GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
 429         GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
 430         GRP_MUX("asc", ASC, ase_pins_asc),
 431         GRP_MUX("stp", STP, ase_pins_stp),
 432         GRP_MUX("gpt1", GPT, ase_pins_gpt1),
 433         GRP_MUX("gpt2", GPT, ase_pins_gpt2),
 434         GRP_MUX("gpt3", GPT, ase_pins_gpt3),
 435         GRP_MUX("clkout0", CGU, ase_pins_clkout0),
 436         GRP_MUX("clkout1", CGU, ase_pins_clkout1),
 437         GRP_MUX("clkout2", CGU, ase_pins_clkout2),
 438         GRP_MUX("mdio", MDIO, ase_pins_mdio),
 439         GRP_MUX("dfe led0", DFE, ase_pins_dfe_led0),
 440         GRP_MUX("dfe led1", DFE, ase_pins_dfe_led1),
 441         GRP_MUX("ephy led0", EPHY, ase_pins_ephy_led0),
 442         GRP_MUX("ephy led1", EPHY, ase_pins_ephy_led1),
 443         GRP_MUX("ephy led2", EPHY, ase_pins_ephy_led2),
 444 };
 445
 446 static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"};
 447 static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
 448 static const char * const ase_cgu_grps[] = {"clkout0", "clkout1",
 449                                                 "clkout2"};
 450 static const char * const ase_mdio_grps[] = {"mdio"};
 451 static const char * const ase_dfe_grps[] = {"dfe led0", "dfe led1"};
 452 static const char * const ase_ephy_grps[] = {"ephy led0", "ephy led1",
 453                                                 "ephy led2"};
 454 static const char * const ase_asc_grps[] = {"asc"};
 455 static const char * const ase_jtag_grps[] = {"jtag"};
 456 static const char * const ase_stp_grps[] = {"stp"};
 457 static const char * const ase_spi_grps[] = {"spi",  /* DEPRECATED */
 458                                                 "spi_di", "spi_do",
 459                                                 "spi_clk", "spi_cs1",
 460                                                 "spi_cs2", "spi_cs3"};
 461
 462 static const struct ltq_pmx_func ase_funcs[] = {
 463         {"spi",         ARRAY_AND_SIZE(ase_spi_grps)},
 464         {"asc",         ARRAY_AND_SIZE(ase_asc_grps)},
 465         {"cgu",         ARRAY_AND_SIZE(ase_cgu_grps)},
 466         {"jtag",        ARRAY_AND_SIZE(ase_jtag_grps)},
 467         {"exin",        ARRAY_AND_SIZE(ase_exin_grps)},
 468         {"stp",         ARRAY_AND_SIZE(ase_stp_grps)},
 469         {"gpt",         ARRAY_AND_SIZE(ase_gpt_grps)},
 470         {"mdio",        ARRAY_AND_SIZE(ase_mdio_grps)},
 471         {"ephy",        ARRAY_AND_SIZE(ase_ephy_grps)},
 472         {"dfe",         ARRAY_AND_SIZE(ase_dfe_grps)},
 473 };
 474
 475 /* ---------  danube related code --------- */
 476 #define DANUBE_MAX_PIN          32
 477
 478 static const struct ltq_mfp_pin danube_mfp[] = {
 479         /*       pin    f0      f1      f2      f3   */
 480         MFP_XWAY(GPIO0, GPIO,   EXIN,   SDIO,   TDM),
 481         MFP_XWAY(GPIO1, GPIO,   EXIN,   CBUS,   MII),
 482         MFP_XWAY(GPIO2, GPIO,   CGU,    EXIN,   MII),
 483         MFP_XWAY(GPIO3, GPIO,   CGU,    SDIO,   PCI),
 484         MFP_XWAY(GPIO4, GPIO,   STP,    DFE,    ASC),
 485         MFP_XWAY(GPIO5, GPIO,   STP,    MII,    DFE),
 486         MFP_XWAY(GPIO6, GPIO,   STP,    GPT,    ASC),
 487         MFP_XWAY(GPIO7, GPIO,   CGU,    CBUS,   MII),
 488         MFP_XWAY(GPIO8, GPIO,   CGU,    NMI,    MII),
 489         MFP_XWAY(GPIO9, GPIO,   ASC,    SPI,    MII),
 490         MFP_XWAY(GPIO10, GPIO,  ASC,    SPI,    MII),
 491         MFP_XWAY(GPIO11, GPIO,  ASC,    CBUS,   SPI),
 492         MFP_XWAY(GPIO12, GPIO,  ASC,    CBUS,   MCD),
 493         MFP_XWAY(GPIO13, GPIO,  EBU,    SPI,    MII),
 494         MFP_XWAY(GPIO14, GPIO,  CGU,    CBUS,   MII),
 495         MFP_XWAY(GPIO15, GPIO,  SPI,    SDIO,   JTAG),
 496         MFP_XWAY(GPIO16, GPIO,  SPI,    SDIO,   JTAG),
 497         MFP_XWAY(GPIO17, GPIO,  SPI,    SDIO,   JTAG),
 498         MFP_XWAY(GPIO18, GPIO,  SPI,    SDIO,   JTAG),
 499         MFP_XWAY(GPIO19, GPIO,  PCI,    SDIO,   MII),
 500         MFP_XWAY(GPIO20, GPIO,  JTAG,   SDIO,   MII),
 501         MFP_XWAY(GPIO21, GPIO,  PCI,    EBU,    GPT),
 502         MFP_XWAY(GPIO22, GPIO,  SPI,    MCD,    MII),
 503         MFP_XWAY(GPIO23, GPIO,  EBU,    PCI,    STP),
 504         MFP_XWAY(GPIO24, GPIO,  EBU,    TDM,    PCI),
 505         MFP_XWAY(GPIO25, GPIO,  TDM,    SDIO,   ASC),
 506         MFP_XWAY(GPIO26, GPIO,  EBU,    TDM,    SDIO),
 507         MFP_XWAY(GPIO27, GPIO,  TDM,    SDIO,   ASC),
 508         MFP_XWAY(GPIO28, GPIO,  GPT,    MII,    SDIO),
 509         MFP_XWAY(GPIO29, GPIO,  PCI,    CBUS,   MII),
 510         MFP_XWAY(GPIO30, GPIO,  PCI,    CBUS,   MII),
 511         MFP_XWAY(GPIO31, GPIO,  EBU,    PCI,    MII),
 512 };
 513
 514 static const unsigned danube_exin_pin_map[] = {GPIO0, GPIO1, GPIO2};
 515
 516 static const unsigned danube_pins_exin0[] = {GPIO0};
 517 static const unsigned danube_pins_exin1[] = {GPIO1};
 518 static const unsigned danube_pins_exin2[] = {GPIO2};
 519
 520 static const unsigned danube_pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO18, GPIO20};
 521 static const unsigned danube_pins_asc0[] = {GPIO11, GPIO12};
 522 static const unsigned danube_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
 523 static const unsigned danube_pins_stp[] = {GPIO4, GPIO5, GPIO6};
 524 static const unsigned danube_pins_nmi[] = {GPIO8};
 525
 526 static const unsigned danube_pins_dfe_led0[] = {GPIO4};
 527 static const unsigned danube_pins_dfe_led1[] = {GPIO5};
 528
 529 static const unsigned danube_pins_ebu_a24[] = {GPIO13};
 530 static const unsigned danube_pins_ebu_clk[] = {GPIO21};
 531 static const unsigned danube_pins_ebu_cs1[] = {GPIO23};
 532 static const unsigned danube_pins_ebu_a23[] = {GPIO24};
 533 static const unsigned danube_pins_ebu_wait[] = {GPIO26};
 534 static const unsigned danube_pins_ebu_a25[] = {GPIO31};
 535
 536 static const unsigned danube_pins_nand_ale[] = {GPIO13};
 537 static const unsigned danube_pins_nand_cs1[] = {GPIO23};
 538 static const unsigned danube_pins_nand_cle[] = {GPIO24};
 539
 540 static const unsigned danube_pins_spi[] = {GPIO16, GPIO17, GPIO18}; /* DEPRECATED */
 541 static const unsigned danube_pins_spi_di[] = {GPIO16};
 542 static const unsigned danube_pins_spi_do[] = {GPIO17};
 543 static const unsigned danube_pins_spi_clk[] = {GPIO18};
 544 static const unsigned danube_pins_spi_cs1[] = {GPIO15};
 545 static const unsigned danube_pins_spi_cs2[] = {GPIO21};
 546 static const unsigned danube_pins_spi_cs3[] = {GPIO13};
 547 static const unsigned danube_pins_spi_cs4[] = {GPIO10};
 548 static const unsigned danube_pins_spi_cs5[] = {GPIO9};
 549 static const unsigned danube_pins_spi_cs6[] = {GPIO11};
 550
 551 static const unsigned danube_pins_gpt1[] = {GPIO28};
 552 static const unsigned danube_pins_gpt2[] = {GPIO21};
 553 static const unsigned danube_pins_gpt3[] = {GPIO6};
 554
 555 static const unsigned danube_pins_clkout0[] = {GPIO8};
 556 static const unsigned danube_pins_clkout1[] = {GPIO7};
 557 static const unsigned danube_pins_clkout2[] = {GPIO3};
 558 static const unsigned danube_pins_clkout3[] = {GPIO2};
 559
 560 static const unsigned danube_pins_pci_gnt1[] = {GPIO30};
 561 static const unsigned danube_pins_pci_gnt2[] = {GPIO23};
 562 static const unsigned danube_pins_pci_gnt3[] = {GPIO19};
 563 static const unsigned danube_pins_pci_req1[] = {GPIO29};
 564 static const unsigned danube_pins_pci_req2[] = {GPIO31};
 565 static const unsigned danube_pins_pci_req3[] = {GPIO3};
 566
 567 static const struct ltq_pin_group danube_grps[] = {
 568         GRP_MUX("exin0", EXIN, danube_pins_exin0),
 569         GRP_MUX("exin1", EXIN, danube_pins_exin1),
 570         GRP_MUX("exin2", EXIN, danube_pins_exin2),
 571         GRP_MUX("jtag", JTAG, danube_pins_jtag),
 572         GRP_MUX("ebu a23", EBU, danube_pins_ebu_a23),
 573         GRP_MUX("ebu a24", EBU, danube_pins_ebu_a24),
 574         GRP_MUX("ebu a25", EBU, danube_pins_ebu_a25),
 575         GRP_MUX("ebu clk", EBU, danube_pins_ebu_clk),
 576         GRP_MUX("ebu cs1", EBU, danube_pins_ebu_cs1),
 577         GRP_MUX("ebu wait", EBU, danube_pins_ebu_wait),
 578         GRP_MUX("nand ale", EBU, danube_pins_nand_ale),
 579         GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1),
 580         GRP_MUX("nand cle", EBU, danube_pins_nand_cle),
 581         GRP_MUX("spi", SPI, danube_pins_spi), /* DEPRECATED */
 582         GRP_MUX("spi_di", SPI, danube_pins_spi_di),
 583         GRP_MUX("spi_do", SPI, danube_pins_spi_do),
 584         GRP_MUX("spi_clk", SPI, danube_pins_spi_clk),
 585         GRP_MUX("spi_cs1", SPI, danube_pins_spi_cs1),
 586         GRP_MUX("spi_cs2", SPI, danube_pins_spi_cs2),
 587         GRP_MUX("spi_cs3", SPI, danube_pins_spi_cs3),
 588         GRP_MUX("spi_cs4", SPI, danube_pins_spi_cs4),
 589         GRP_MUX("spi_cs5", SPI, danube_pins_spi_cs5),
 590         GRP_MUX("spi_cs6", SPI, danube_pins_spi_cs6),
 591         GRP_MUX("asc0", ASC, danube_pins_asc0),
 592         GRP_MUX("asc0 cts rts", ASC, danube_pins_asc0_cts_rts),
 593         GRP_MUX("stp", STP, danube_pins_stp),
 594         GRP_MUX("nmi", NMI, danube_pins_nmi),
 595         GRP_MUX("gpt1", GPT, danube_pins_gpt1),
 596         GRP_MUX("gpt2", GPT, danube_pins_gpt2),
 597         GRP_MUX("gpt3", GPT, danube_pins_gpt3),
 598         GRP_MUX("clkout0", CGU, danube_pins_clkout0),
 599         GRP_MUX("clkout1", CGU, danube_pins_clkout1),
 600         GRP_MUX("clkout2", CGU, danube_pins_clkout2),
 601         GRP_MUX("clkout3", CGU, danube_pins_clkout3),
 602         GRP_MUX("gnt1", PCI, danube_pins_pci_gnt1),
 603         GRP_MUX("gnt2", PCI, danube_pins_pci_gnt2),
 604         GRP_MUX("gnt3", PCI, danube_pins_pci_gnt3),
 605         GRP_MUX("req1", PCI, danube_pins_pci_req1),
 606         GRP_MUX("req2", PCI, danube_pins_pci_req2),
 607         GRP_MUX("req3", PCI, danube_pins_pci_req3),
 608         GRP_MUX("dfe led0", DFE, danube_pins_dfe_led0),
 609         GRP_MUX("dfe led1", DFE, danube_pins_dfe_led1),
 610 };
 611
 612 static const char * const danube_pci_grps[] = {"gnt1", "gnt2",
 613                                                 "gnt3", "req1",
 614                                                 "req2", "req3"};
 615 static const char * const danube_spi_grps[] = {"spi", /* DEPRECATED */
 616                                                 "spi_di", "spi_do",
 617                                                 "spi_clk", "spi_cs1",
 618                                                 "spi_cs2", "spi_cs3",
 619                                                 "spi_cs4", "spi_cs5",
 620                                                 "spi_cs6"};
 621 static const char * const danube_cgu_grps[] = {"clkout0", "clkout1",
 622                                                 "clkout2", "clkout3"};
 623 static const char * const danube_ebu_grps[] = {"ebu a23", "ebu a24",
 624                                                 "ebu a25", "ebu cs1",
 625                                                 "ebu wait", "ebu clk",
 626                                                 "nand ale", "nand cs1",
 627                                                 "nand cle"};
 628 static const char * const danube_dfe_grps[] = {"dfe led0", "dfe led1"};
 629 static const char * const danube_exin_grps[] = {"exin0", "exin1", "exin2"};
 630 static const char * const danube_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
 631 static const char * const danube_asc_grps[] = {"asc0", "asc0 cts rts"};
 632 static const char * const danube_jtag_grps[] = {"jtag"};
 633 static const char * const danube_stp_grps[] = {"stp"};
 634 static const char * const danube_nmi_grps[] = {"nmi"};
 635
 636 static const struct ltq_pmx_func danube_funcs[] = {
 637         {"spi",         ARRAY_AND_SIZE(danube_spi_grps)},
 638         {"asc",         ARRAY_AND_SIZE(danube_asc_grps)},
 639         {"cgu",         ARRAY_AND_SIZE(danube_cgu_grps)},
 640         {"jtag",        ARRAY_AND_SIZE(danube_jtag_grps)},
 641         {"exin",        ARRAY_AND_SIZE(danube_exin_grps)},
 642         {"stp",         ARRAY_AND_SIZE(danube_stp_grps)},
 643         {"gpt",         ARRAY_AND_SIZE(danube_gpt_grps)},
 644         {"nmi",         ARRAY_AND_SIZE(danube_nmi_grps)},
 645         {"pci",         ARRAY_AND_SIZE(danube_pci_grps)},
 646         {"ebu",         ARRAY_AND_SIZE(danube_ebu_grps)},
 647         {"dfe",         ARRAY_AND_SIZE(danube_dfe_grps)},
 648 };
 649
 650 /* ---------  xrx100 related code --------- */
 651 #define XRX100_MAX_PIN          56
 652
 653 static const struct ltq_mfp_pin xrx100_mfp[] = {
 654         /*       pin    f0      f1      f2      f3   */
 655         MFP_XWAY(GPIO0, GPIO,   EXIN,   SDIO,   TDM),
 656         MFP_XWAY(GPIO1, GPIO,   EXIN,   CBUS,   SIN),
 657         MFP_XWAY(GPIO2, GPIO,   CGU,    EXIN,   NONE),
 658         MFP_XWAY(GPIO3, GPIO,   CGU,    SDIO,   PCI),
 659         MFP_XWAY(GPIO4, GPIO,   STP,    DFE,    ASC),
 660         MFP_XWAY(GPIO5, GPIO,   STP,    NONE,   DFE),
 661         MFP_XWAY(GPIO6, GPIO,   STP,    GPT,    ASC),
 662         MFP_XWAY(GPIO7, GPIO,   CGU,    CBUS,   NONE),
 663         MFP_XWAY(GPIO8, GPIO,   CGU,    NMI,    NONE),
 664         MFP_XWAY(GPIO9, GPIO,   ASC,    SPI,    EXIN),
 665         MFP_XWAY(GPIO10, GPIO,  ASC,    SPI,    EXIN),
 666         MFP_XWAY(GPIO11, GPIO,  ASC,    CBUS,   SPI),
 667         MFP_XWAY(GPIO12, GPIO,  ASC,    CBUS,   MCD),
 668         MFP_XWAY(GPIO13, GPIO,  EBU,    SPI,    NONE),
 669         MFP_XWAY(GPIO14, GPIO,  CGU,    NONE,   NONE),
 670         MFP_XWAY(GPIO15, GPIO,  SPI,    SDIO,   MCD),
 671         MFP_XWAY(GPIO16, GPIO,  SPI,    SDIO,   NONE),
 672         MFP_XWAY(GPIO17, GPIO,  SPI,    SDIO,   NONE),
 673         MFP_XWAY(GPIO18, GPIO,  SPI,    SDIO,   NONE),
 674         MFP_XWAY(GPIO19, GPIO,  PCI,    SDIO,   CGU),
 675         MFP_XWAY(GPIO20, GPIO,  NONE,   SDIO,   EBU),
 676         MFP_XWAY(GPIO21, GPIO,  PCI,    EBU,    GPT),
 677         MFP_XWAY(GPIO22, GPIO,  SPI,    NONE,   EBU),
 678         MFP_XWAY(GPIO23, GPIO,  EBU,    PCI,    STP),
 679         MFP_XWAY(GPIO24, GPIO,  EBU,    TDM,    PCI),
 680         MFP_XWAY(GPIO25, GPIO,  TDM,    SDIO,   ASC),
 681         MFP_XWAY(GPIO26, GPIO,  EBU,    TDM,    SDIO),
 682         MFP_XWAY(GPIO27, GPIO,  TDM,    SDIO,   ASC),
 683         MFP_XWAY(GPIO28, GPIO,  GPT,    NONE,   SDIO),
 684         MFP_XWAY(GPIO29, GPIO,  PCI,    CBUS,   NONE),
 685         MFP_XWAY(GPIO30, GPIO,  PCI,    CBUS,   NONE),
 686         MFP_XWAY(GPIO31, GPIO,  EBU,    PCI,    NONE),
 687         MFP_XWAY(GPIO32, GPIO,  MII,    NONE,   EBU),
 688         MFP_XWAY(GPIO33, GPIO,  MII,    NONE,   EBU),
 689         MFP_XWAY(GPIO34, GPIO,  SIN,    SSI,    NONE),
 690         MFP_XWAY(GPIO35, GPIO,  SIN,    SSI,    NONE),
 691         MFP_XWAY(GPIO36, GPIO,  SIN,    SSI,    NONE),
 692         MFP_XWAY(GPIO37, GPIO,  PCI,    NONE,   NONE),
 693         MFP_XWAY(GPIO38, GPIO,  PCI,    NONE,   NONE),
 694         MFP_XWAY(GPIO39, GPIO,  NONE,   EXIN,   NONE),
 695         MFP_XWAY(GPIO40, GPIO,  MII,    TDM,    NONE),
 696         MFP_XWAY(GPIO41, GPIO,  MII,    TDM,    NONE),
 697         MFP_XWAY(GPIO42, GPIO,  MDIO,   NONE,   NONE),
 698         MFP_XWAY(GPIO43, GPIO,  MDIO,   NONE,   NONE),
 699         MFP_XWAY(GPIO44, GPIO,  MII,    SIN,    NONE),
 700         MFP_XWAY(GPIO45, GPIO,  MII,    NONE,   SIN),
 701         MFP_XWAY(GPIO46, GPIO,  MII,    NONE,   EXIN),
 702         MFP_XWAY(GPIO47, GPIO,  MII,    NONE,   SIN),
 703         MFP_XWAY(GPIO48, GPIO,  EBU,    NONE,   NONE),
 704         MFP_XWAY(GPIO49, GPIO,  EBU,    NONE,   NONE),
 705         MFP_XWAY(GPIO50, GPIO,  NONE,   NONE,   NONE),
 706         MFP_XWAY(GPIO51, GPIO,  NONE,   NONE,   NONE),
 707         MFP_XWAY(GPIO52, GPIO,  NONE,   NONE,   NONE),
 708         MFP_XWAY(GPIO53, GPIO,  NONE,   NONE,   NONE),
 709         MFP_XWAY(GPIO54, GPIO,  NONE,   NONE,   NONE),
 710         MFP_XWAY(GPIO55, GPIO,  NONE,   NONE,   NONE),
 711 };
 712
 713 static const unsigned xrx100_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
 714
 715 static const unsigned xrx100_pins_exin0[] = {GPIO0};
 716 static const unsigned xrx100_pins_exin1[] = {GPIO1};
 717 static const unsigned xrx100_pins_exin2[] = {GPIO2};
 718 static const unsigned xrx100_pins_exin3[] = {GPIO39};
 719 static const unsigned xrx100_pins_exin4[] = {GPIO10};
 720 static const unsigned xrx100_pins_exin5[] = {GPIO9};
 721
 722 static const unsigned xrx100_pins_asc0[] = {GPIO11, GPIO12};
 723 static const unsigned xrx100_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
 724 static const unsigned xrx100_pins_stp[] = {GPIO4, GPIO5, GPIO6};
 725 static const unsigned xrx100_pins_nmi[] = {GPIO8};
 726 static const unsigned xrx100_pins_mdio[] = {GPIO42, GPIO43};
 727
 728 static const unsigned xrx100_pins_dfe_led0[] = {GPIO4};
 729 static const unsigned xrx100_pins_dfe_led1[] = {GPIO5};
 730
 731 static const unsigned xrx100_pins_ebu_a24[] = {GPIO13};
 732 static const unsigned xrx100_pins_ebu_clk[] = {GPIO21};
 733 static const unsigned xrx100_pins_ebu_cs1[] = {GPIO23};
 734 static const unsigned xrx100_pins_ebu_a23[] = {GPIO24};
 735 static const unsigned xrx100_pins_ebu_wait[] = {GPIO26};
 736 static const unsigned xrx100_pins_ebu_a25[] = {GPIO31};
 737
 738 static const unsigned xrx100_pins_nand_ale[] = {GPIO13};
 739 static const unsigned xrx100_pins_nand_cs1[] = {GPIO23};
 740 static const unsigned xrx100_pins_nand_cle[] = {GPIO24};
 741 static const unsigned xrx100_pins_nand_rdy[] = {GPIO48};
 742 static const unsigned xrx100_pins_nand_rd[] = {GPIO49};
 743
 744 static const unsigned xrx100_pins_spi_di[] = {GPIO16};
 745 static const unsigned xrx100_pins_spi_do[] = {GPIO17};
 746 static const unsigned xrx100_pins_spi_clk[] = {GPIO18};
 747 static const unsigned xrx100_pins_spi_cs1[] = {GPIO15};
 748 static const unsigned xrx100_pins_spi_cs2[] = {GPIO22};
 749 static const unsigned xrx100_pins_spi_cs3[] = {GPIO13};
 750 static const unsigned xrx100_pins_spi_cs4[] = {GPIO10};
 751 static const unsigned xrx100_pins_spi_cs5[] = {GPIO9};
 752 static const unsigned xrx100_pins_spi_cs6[] = {GPIO11};
 753
 754 static const unsigned xrx100_pins_gpt1[] = {GPIO28};
 755 static const unsigned xrx100_pins_gpt2[] = {GPIO21};
 756 static const unsigned xrx100_pins_gpt3[] = {GPIO6};
 757
 758 static const unsigned xrx100_pins_clkout0[] = {GPIO8};
 759 static const unsigned xrx100_pins_clkout1[] = {GPIO7};
 760 static const unsigned xrx100_pins_clkout2[] = {GPIO3};
 761 static const unsigned xrx100_pins_clkout3[] = {GPIO2};
 762
 763 static const unsigned xrx100_pins_pci_gnt1[] = {GPIO30};
 764 static const unsigned xrx100_pins_pci_gnt2[] = {GPIO23};
 765 static const unsigned xrx100_pins_pci_gnt3[] = {GPIO19};
 766 static const unsigned xrx100_pins_pci_gnt4[] = {GPIO38};
 767 static const unsigned xrx100_pins_pci_req1[] = {GPIO29};
 768 static const unsigned xrx100_pins_pci_req2[] = {GPIO31};
 769 static const unsigned xrx100_pins_pci_req3[] = {GPIO3};
 770 static const unsigned xrx100_pins_pci_req4[] = {GPIO37};
 771
 772 static const struct ltq_pin_group xrx100_grps[] = {
 773         GRP_MUX("exin0", EXIN, xrx100_pins_exin0),
 774         GRP_MUX("exin1", EXIN, xrx100_pins_exin1),
 775         GRP_MUX("exin2", EXIN, xrx100_pins_exin2),
 776         GRP_MUX("exin3", EXIN, xrx100_pins_exin3),
 777         GRP_MUX("exin4", EXIN, xrx100_pins_exin4),
 778         GRP_MUX("exin5", EXIN, xrx100_pins_exin5),
 779         GRP_MUX("ebu a23", EBU, xrx100_pins_ebu_a23),
 780         GRP_MUX("ebu a24", EBU, xrx100_pins_ebu_a24),
 781         GRP_MUX("ebu a25", EBU, xrx100_pins_ebu_a25),
 782         GRP_MUX("ebu clk", EBU, xrx100_pins_ebu_clk),
 783         GRP_MUX("ebu cs1", EBU, xrx100_pins_ebu_cs1),
 784         GRP_MUX("ebu wait", EBU, xrx100_pins_ebu_wait),
 785         GRP_MUX("nand ale", EBU, xrx100_pins_nand_ale),
 786         GRP_MUX("nand cs1", EBU, xrx100_pins_nand_cs1),
 787         GRP_MUX("nand cle", EBU, xrx100_pins_nand_cle),
 788         GRP_MUX("nand rdy", EBU, xrx100_pins_nand_rdy),
 789         GRP_MUX("nand rd", EBU, xrx100_pins_nand_rd),
 790         GRP_MUX("spi_di", SPI, xrx100_pins_spi_di),
 791         GRP_MUX("spi_do", SPI, xrx100_pins_spi_do),
 792         GRP_MUX("spi_clk", SPI, xrx100_pins_spi_clk),
 793         GRP_MUX("spi_cs1", SPI, xrx100_pins_spi_cs1),
 794         GRP_MUX("spi_cs2", SPI, xrx100_pins_spi_cs2),
 795         GRP_MUX("spi_cs3", SPI, xrx100_pins_spi_cs3),
 796         GRP_MUX("spi_cs4", SPI, xrx100_pins_spi_cs4),
 797         GRP_MUX("spi_cs5", SPI, xrx100_pins_spi_cs5),
 798         GRP_MUX("spi_cs6", SPI, xrx100_pins_spi_cs6),
 799         GRP_MUX("asc0", ASC, xrx100_pins_asc0),
 800         GRP_MUX("asc0 cts rts", ASC, xrx100_pins_asc0_cts_rts),
 801         GRP_MUX("stp", STP, xrx100_pins_stp),
 802         GRP_MUX("nmi", NMI, xrx100_pins_nmi),
 803         GRP_MUX("gpt1", GPT, xrx100_pins_gpt1),
 804         GRP_MUX("gpt2", GPT, xrx100_pins_gpt2),
 805         GRP_MUX("gpt3", GPT, xrx100_pins_gpt3),
 806         GRP_MUX("clkout0", CGU, xrx100_pins_clkout0),
 807         GRP_MUX("clkout1", CGU, xrx100_pins_clkout1),
 808         GRP_MUX("clkout2", CGU, xrx100_pins_clkout2),
 809         GRP_MUX("clkout3", CGU, xrx100_pins_clkout3),
 810         GRP_MUX("gnt1", PCI, xrx100_pins_pci_gnt1),
 811         GRP_MUX("gnt2", PCI, xrx100_pins_pci_gnt2),
 812         GRP_MUX("gnt3", PCI, xrx100_pins_pci_gnt3),
 813         GRP_MUX("gnt4", PCI, xrx100_pins_pci_gnt4),
 814         GRP_MUX("req1", PCI, xrx100_pins_pci_req1),
 815         GRP_MUX("req2", PCI, xrx100_pins_pci_req2),
 816         GRP_MUX("req3", PCI, xrx100_pins_pci_req3),
 817         GRP_MUX("req4", PCI, xrx100_pins_pci_req4),
 818         GRP_MUX("mdio", MDIO, xrx100_pins_mdio),
 819         GRP_MUX("dfe led0", DFE, xrx100_pins_dfe_led0),
 820         GRP_MUX("dfe led1", DFE, xrx100_pins_dfe_led1),
 821 };
 822
 823 static const char * const xrx100_pci_grps[] = {"gnt1", "gnt2",
 824                                                 "gnt3", "gnt4",
 825                                                 "req1", "req2",
 826                                                 "req3", "req4"};
 827 static const char * const xrx100_spi_grps[] = {"spi_di", "spi_do",
 828                                                 "spi_clk", "spi_cs1",
 829                                                 "spi_cs2", "spi_cs3",
 830                                                 "spi_cs4", "spi_cs5",
 831                                                 "spi_cs6"};
 832 static const char * const xrx100_cgu_grps[] = {"clkout0", "clkout1",
 833                                                 "clkout2", "clkout3"};
 834 static const char * const xrx100_ebu_grps[] = {"ebu a23", "ebu a24",
 835                                                 "ebu a25", "ebu cs1",
 836                                                 "ebu wait", "ebu clk",
 837                                                 "nand ale", "nand cs1",
 838                                                 "nand cle", "nand rdy",
 839                                                 "nand rd"};
 840 static const char * const xrx100_exin_grps[] = {"exin0", "exin1", "exin2",
 841                                                 "exin3", "exin4", "exin5"};
 842 static const char * const xrx100_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
 843 static const char * const xrx100_asc_grps[] = {"asc0", "asc0 cts rts"};
 844 static const char * const xrx100_stp_grps[] = {"stp"};
 845 static const char * const xrx100_nmi_grps[] = {"nmi"};
 846 static const char * const xrx100_mdio_grps[] = {"mdio"};
 847 static const char * const xrx100_dfe_grps[] = {"dfe led0", "dfe led1"};
 848
 849 static const struct ltq_pmx_func xrx100_funcs[] = {
 850         {"spi",         ARRAY_AND_SIZE(xrx100_spi_grps)},
 851         {"asc",         ARRAY_AND_SIZE(xrx100_asc_grps)},
 852         {"cgu",         ARRAY_AND_SIZE(xrx100_cgu_grps)},
 853         {"exin",        ARRAY_AND_SIZE(xrx100_exin_grps)},
 854         {"stp",         ARRAY_AND_SIZE(xrx100_stp_grps)},
 855         {"gpt",         ARRAY_AND_SIZE(xrx100_gpt_grps)},
 856         {"nmi",         ARRAY_AND_SIZE(xrx100_nmi_grps)},
 857         {"pci",         ARRAY_AND_SIZE(xrx100_pci_grps)},
 858         {"ebu",         ARRAY_AND_SIZE(xrx100_ebu_grps)},
 859         {"mdio",        ARRAY_AND_SIZE(xrx100_mdio_grps)},
 860         {"dfe",         ARRAY_AND_SIZE(xrx100_dfe_grps)},
 861 };
 862
 863 /* ---------  xrx200 related code --------- */
 864 #define XRX200_MAX_PIN          50
 865
 866 static const struct ltq_mfp_pin xrx200_mfp[] = {
 867         /*       pin    f0      f1      f2      f3   */
 868         MFP_XWAY(GPIO0, GPIO,   EXIN,   SDIO,   TDM),
 869         MFP_XWAY(GPIO1, GPIO,   EXIN,   CBUS,   SIN),
 870         MFP_XWAY(GPIO2, GPIO,   CGU,    EXIN,   GPHY),
 871         MFP_XWAY(GPIO3, GPIO,   CGU,    SDIO,   PCI),
 872         MFP_XWAY(GPIO4, GPIO,   STP,    DFE,    USIF),
 873         MFP_XWAY(GPIO5, GPIO,   STP,    GPHY,   DFE),
 874         MFP_XWAY(GPIO6, GPIO,   STP,    GPT,    USIF),
 875         MFP_XWAY(GPIO7, GPIO,   CGU,    CBUS,   GPHY),
 876         MFP_XWAY(GPIO8, GPIO,   CGU,    NMI,    NONE),
 877         MFP_XWAY(GPIO9, GPIO,   USIF,   SPI,    EXIN),
 878         MFP_XWAY(GPIO10, GPIO,  USIF,   SPI,    EXIN),
 879         MFP_XWAY(GPIO11, GPIO,  USIF,   CBUS,   SPI),
 880         MFP_XWAY(GPIO12, GPIO,  USIF,   CBUS,   MCD),
 881         MFP_XWAY(GPIO13, GPIO,  EBU,    SPI,    NONE),
 882         MFP_XWAY(GPIO14, GPIO,  CGU,    CBUS,   USIF),
 883         MFP_XWAY(GPIO15, GPIO,  SPI,    SDIO,   MCD),
 884         MFP_XWAY(GPIO16, GPIO,  SPI,    SDIO,   NONE),
 885         MFP_XWAY(GPIO17, GPIO,  SPI,    SDIO,   NONE),
 886         MFP_XWAY(GPIO18, GPIO,  SPI,    SDIO,   NONE),
 887         MFP_XWAY(GPIO19, GPIO,  PCI,    SDIO,   CGU),
 888         MFP_XWAY(GPIO20, GPIO,  NONE,   SDIO,   EBU),
 889         MFP_XWAY(GPIO21, GPIO,  PCI,    EBU,    GPT),
 890         MFP_XWAY(GPIO22, GPIO,  SPI,    CGU,    EBU),
 891         MFP_XWAY(GPIO23, GPIO,  EBU,    PCI,    STP),
 892         MFP_XWAY(GPIO24, GPIO,  EBU,    TDM,    PCI),
 893         MFP_XWAY(GPIO25, GPIO,  TDM,    SDIO,   USIF),
 894         MFP_XWAY(GPIO26, GPIO,  EBU,    TDM,    SDIO),
 895         MFP_XWAY(GPIO27, GPIO,  TDM,    SDIO,   USIF),
 896         MFP_XWAY(GPIO28, GPIO,  GPT,    PCI,    SDIO),
 897         MFP_XWAY(GPIO29, GPIO,  PCI,    CBUS,   EXIN),
 898         MFP_XWAY(GPIO30, GPIO,  PCI,    CBUS,   NONE),
 899         MFP_XWAY(GPIO31, GPIO,  EBU,    PCI,    NONE),
 900         MFP_XWAY(GPIO32, GPIO,  MII,    NONE,   EBU),
 901         MFP_XWAY(GPIO33, GPIO,  MII,    NONE,   EBU),
 902         MFP_XWAY(GPIO34, GPIO,  SIN,    SSI,    NONE),
 903         MFP_XWAY(GPIO35, GPIO,  SIN,    SSI,    NONE),
 904         MFP_XWAY(GPIO36, GPIO,  SIN,    SSI,    EXIN),
 905         MFP_XWAY(GPIO37, GPIO,  USIF,   NONE,   PCI),
 906         MFP_XWAY(GPIO38, GPIO,  PCI,    USIF,   NONE),
 907         MFP_XWAY(GPIO39, GPIO,  USIF,   EXIN,   NONE),
 908         MFP_XWAY(GPIO40, GPIO,  MII,    TDM,    NONE),
 909         MFP_XWAY(GPIO41, GPIO,  MII,    TDM,    NONE),
 910         MFP_XWAY(GPIO42, GPIO,  MDIO,   NONE,   NONE),
 911         MFP_XWAY(GPIO43, GPIO,  MDIO,   NONE,   NONE),
 912         MFP_XWAY(GPIO44, GPIO,  MII,    SIN,    GPHY),
 913         MFP_XWAY(GPIO45, GPIO,  MII,    GPHY,   SIN),
 914         MFP_XWAY(GPIO46, GPIO,  MII,    NONE,   EXIN),
 915         MFP_XWAY(GPIO47, GPIO,  MII,    GPHY,   SIN),
 916         MFP_XWAY(GPIO48, GPIO,  EBU,    NONE,   NONE),
 917         MFP_XWAY(GPIO49, GPIO,  EBU,    NONE,   NONE),
 918 };
 919
 920 static const unsigned xrx200_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
 921
 922 static const unsigned xrx200_pins_exin0[] = {GPIO0};
 923 static const unsigned xrx200_pins_exin1[] = {GPIO1};
 924 static const unsigned xrx200_pins_exin2[] = {GPIO2};
 925 static const unsigned xrx200_pins_exin3[] = {GPIO39};
 926 static const unsigned xrx200_pins_exin4[] = {GPIO10};
 927 static const unsigned xrx200_pins_exin5[] = {GPIO9};
 928
 929 static const unsigned xrx200_pins_usif_uart_rx[] = {GPIO11};
 930 static const unsigned xrx200_pins_usif_uart_tx[] = {GPIO12};
 931 static const unsigned xrx200_pins_usif_uart_rts[] = {GPIO9};
 932 static const unsigned xrx200_pins_usif_uart_cts[] = {GPIO10};
 933 static const unsigned xrx200_pins_usif_uart_dtr[] = {GPIO4};
 934 static const unsigned xrx200_pins_usif_uart_dsr[] = {GPIO6};
 935 static const unsigned xrx200_pins_usif_uart_dcd[] = {GPIO25};
 936 static const unsigned xrx200_pins_usif_uart_ri[] = {GPIO27};
 937
 938 static const unsigned xrx200_pins_usif_spi_di[] = {GPIO11};
 939 static const unsigned xrx200_pins_usif_spi_do[] = {GPIO12};
 940 static const unsigned xrx200_pins_usif_spi_clk[] = {GPIO38};
 941 static const unsigned xrx200_pins_usif_spi_cs0[] = {GPIO37};
 942 static const unsigned xrx200_pins_usif_spi_cs1[] = {GPIO39};
 943 static const unsigned xrx200_pins_usif_spi_cs2[] = {GPIO14};
 944
 945 static const unsigned xrx200_pins_stp[] = {GPIO4, GPIO5, GPIO6};
 946 static const unsigned xrx200_pins_nmi[] = {GPIO8};
 947 static const unsigned xrx200_pins_mdio[] = {GPIO42, GPIO43};
 948
 949 static const unsigned xrx200_pins_dfe_led0[] = {GPIO4};
 950 static const unsigned xrx200_pins_dfe_led1[] = {GPIO5};
 951
 952 static const unsigned xrx200_pins_gphy0_led0[] = {GPIO5};
 953 static const unsigned xrx200_pins_gphy0_led1[] = {GPIO7};
 954 static const unsigned xrx200_pins_gphy0_led2[] = {GPIO2};
 955 static const unsigned xrx200_pins_gphy1_led0[] = {GPIO44};
 956 static const unsigned xrx200_pins_gphy1_led1[] = {GPIO45};
 957 static const unsigned xrx200_pins_gphy1_led2[] = {GPIO47};
 958
 959 static const unsigned xrx200_pins_ebu_a24[] = {GPIO13};
 960 static const unsigned xrx200_pins_ebu_clk[] = {GPIO21};
 961 static const unsigned xrx200_pins_ebu_cs1[] = {GPIO23};
 962 static const unsigned xrx200_pins_ebu_a23[] = {GPIO24};
 963 static const unsigned xrx200_pins_ebu_wait[] = {GPIO26};
 964 static const unsigned xrx200_pins_ebu_a25[] = {GPIO31};
 965
 966 static const unsigned xrx200_pins_nand_ale[] = {GPIO13};
 967 static const unsigned xrx200_pins_nand_cs1[] = {GPIO23};
 968 static const unsigned xrx200_pins_nand_cle[] = {GPIO24};
 969 static const unsigned xrx200_pins_nand_rdy[] = {GPIO48};
 970 static const unsigned xrx200_pins_nand_rd[] = {GPIO49};
 971
 972 static const unsigned xrx200_pins_spi_di[] = {GPIO16};
 973 static const unsigned xrx200_pins_spi_do[] = {GPIO17};
 974 static const unsigned xrx200_pins_spi_clk[] = {GPIO18};
 975 static const unsigned xrx200_pins_spi_cs1[] = {GPIO15};
 976 static const unsigned xrx200_pins_spi_cs2[] = {GPIO22};
 977 static const unsigned xrx200_pins_spi_cs3[] = {GPIO13};
 978 static const unsigned xrx200_pins_spi_cs4[] = {GPIO10};
 979 static const unsigned xrx200_pins_spi_cs5[] = {GPIO9};
 980 static const unsigned xrx200_pins_spi_cs6[] = {GPIO11};
 981
 982 static const unsigned xrx200_pins_gpt1[] = {GPIO28};
 983 static const unsigned xrx200_pins_gpt2[] = {GPIO21};
 984 static const unsigned xrx200_pins_gpt3[] = {GPIO6};
 985
 986 static const unsigned xrx200_pins_clkout0[] = {GPIO8};
 987 static const unsigned xrx200_pins_clkout1[] = {GPIO7};
 988 static const unsigned xrx200_pins_clkout2[] = {GPIO3};
 989 static const unsigned xrx200_pins_clkout3[] = {GPIO2};
 990
 991 static const unsigned xrx200_pins_pci_gnt1[] = {GPIO28};
 992 static const unsigned xrx200_pins_pci_gnt2[] = {GPIO23};
 993 static const unsigned xrx200_pins_pci_gnt3[] = {GPIO19};
 994 static const unsigned xrx200_pins_pci_gnt4[] = {GPIO38};
 995 static const unsigned xrx200_pins_pci_req1[] = {GPIO29};
 996 static const unsigned xrx200_pins_pci_req2[] = {GPIO31};
 997 static const unsigned xrx200_pins_pci_req3[] = {GPIO3};
 998 static const unsigned xrx200_pins_pci_req4[] = {GPIO37};
 999
1000 static const struct ltq_pin_group xrx200_grps[] = {
1001         GRP_MUX("exin0", EXIN, xrx200_pins_exin0),
1002         GRP_MUX("exin1", EXIN, xrx200_pins_exin1),
1003         GRP_MUX("exin2", EXIN, xrx200_pins_exin2),
1004         GRP_MUX("exin3", EXIN, xrx200_pins_exin3),
1005         GRP_MUX("exin4", EXIN, xrx200_pins_exin4),
1006         GRP_MUX("exin5", EXIN, xrx200_pins_exin5),
1007         GRP_MUX("ebu a23", EBU, xrx200_pins_ebu_a23),
1008         GRP_MUX("ebu a24", EBU, xrx200_pins_ebu_a24),
1009         GRP_MUX("ebu a25", EBU, xrx200_pins_ebu_a25),
1010         GRP_MUX("ebu clk", EBU, xrx200_pins_ebu_clk),
1011         GRP_MUX("ebu cs1", EBU, xrx200_pins_ebu_cs1),
1012         GRP_MUX("ebu wait", EBU, xrx200_pins_ebu_wait),
1013         GRP_MUX("nand ale", EBU, xrx200_pins_nand_ale),
1014         GRP_MUX("nand cs1", EBU, xrx200_pins_nand_cs1),
1015         GRP_MUX("nand cle", EBU, xrx200_pins_nand_cle),
1016         GRP_MUX("nand rdy", EBU, xrx200_pins_nand_rdy),
1017         GRP_MUX("nand rd", EBU, xrx200_pins_nand_rd),
1018         GRP_MUX("spi_di", SPI, xrx200_pins_spi_di),
1019         GRP_MUX("spi_do", SPI, xrx200_pins_spi_do),
1020         GRP_MUX("spi_clk", SPI, xrx200_pins_spi_clk),
1021         GRP_MUX("spi_cs1", SPI, xrx200_pins_spi_cs1),
1022         GRP_MUX("spi_cs2", SPI, xrx200_pins_spi_cs2),
1023         GRP_MUX("spi_cs3", SPI, xrx200_pins_spi_cs3),
1024         GRP_MUX("spi_cs4", SPI, xrx200_pins_spi_cs4),
1025         GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5),
1026         GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6),
1027         GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_rx),
1028         GRP_MUX("usif uart_tx", USIF, xrx200_pins_usif_uart_tx),
1029         GRP_MUX("usif uart_rts", USIF, xrx200_pins_usif_uart_rts),
1030         GRP_MUX("usif uart_cts", USIF, xrx200_pins_usif_uart_cts),
1031         GRP_MUX("usif uart_dtr", USIF, xrx200_pins_usif_uart_dtr),
1032         GRP_MUX("usif uart_dsr", USIF, xrx200_pins_usif_uart_dsr),
1033         GRP_MUX("usif uart_dcd", USIF, xrx200_pins_usif_uart_dcd),
1034         GRP_MUX("usif uart_ri", USIF, xrx200_pins_usif_uart_ri),
1035         GRP_MUX("usif spi_di", USIF, xrx200_pins_usif_spi_di),
1036         GRP_MUX("usif spi_do", USIF, xrx200_pins_usif_spi_do),
1037         GRP_MUX("usif spi_clk", USIF, xrx200_pins_usif_spi_clk),
1038         GRP_MUX("usif spi_cs0", USIF, xrx200_pins_usif_spi_cs0),
1039         GRP_MUX("usif spi_cs1", USIF, xrx200_pins_usif_spi_cs1),
1040         GRP_MUX("usif spi_cs2", USIF, xrx200_pins_usif_spi_cs2),
1041         GRP_MUX("stp", STP, xrx200_pins_stp),
1042         GRP_MUX("nmi", NMI, xrx200_pins_nmi),
1043         GRP_MUX("gpt1", GPT, xrx200_pins_gpt1),
1044         GRP_MUX("gpt2", GPT, xrx200_pins_gpt2),
1045         GRP_MUX("gpt3", GPT, xrx200_pins_gpt3),
1046         GRP_MUX("clkout0", CGU, xrx200_pins_clkout0),
1047         GRP_MUX("clkout1", CGU, xrx200_pins_clkout1),
1048         GRP_MUX("clkout2", CGU, xrx200_pins_clkout2),
1049         GRP_MUX("clkout3", CGU, xrx200_pins_clkout3),
1050         GRP_MUX("gnt1", PCI, xrx200_pins_pci_gnt1),
1051         GRP_MUX("gnt2", PCI, xrx200_pins_pci_gnt2),
1052         GRP_MUX("gnt3", PCI, xrx200_pins_pci_gnt3),
1053         GRP_MUX("gnt4", PCI, xrx200_pins_pci_gnt4),
1054         GRP_MUX("req1", PCI, xrx200_pins_pci_req1),
1055         GRP_MUX("req2", PCI, xrx200_pins_pci_req2),
1056         GRP_MUX("req3", PCI, xrx200_pins_pci_req3),
1057         GRP_MUX("req4", PCI, xrx200_pins_pci_req4),
1058         GRP_MUX("mdio", MDIO, xrx200_pins_mdio),
1059         GRP_MUX("dfe led0", DFE, xrx200_pins_dfe_led0),
1060         GRP_MUX("dfe led1", DFE, xrx200_pins_dfe_led1),
1061         GRP_MUX("gphy0 led0", GPHY, xrx200_pins_gphy0_led0),
1062         GRP_MUX("gphy0 led1", GPHY, xrx200_pins_gphy0_led1),
1063         GRP_MUX("gphy0 led2", GPHY, xrx200_pins_gphy0_led2),
1064         GRP_MUX("gphy1 led0", GPHY, xrx200_pins_gphy1_led0),
1065         GRP_MUX("gphy1 led1", GPHY, xrx200_pins_gphy1_led1),
1066         GRP_MUX("gphy1 led2", GPHY, xrx200_pins_gphy1_led2),
1067 };
1068
1069 static const char * const xrx200_pci_grps[] = {"gnt1", "gnt2",
1070                                                 "gnt3", "gnt4",
1071                                                 "req1", "req2",
1072                                                 "req3", "req4"};
1073 static const char * const xrx200_spi_grps[] = {"spi_di", "spi_do",
1074                                                 "spi_clk", "spi_cs1",
1075                                                 "spi_cs2", "spi_cs3",
1076                                                 "spi_cs4", "spi_cs5",
1077                                                 "spi_cs6"};
1078 static const char * const xrx200_cgu_grps[] = {"clkout0", "clkout1",
1079                                                 "clkout2", "clkout3"};
1080 static const char * const xrx200_ebu_grps[] = {"ebu a23", "ebu a24",
1081                                                 "ebu a25", "ebu cs1",
1082                                                 "ebu wait", "ebu clk",
1083                                                 "nand ale", "nand cs1",
1084                                                 "nand cle", "nand rdy",
1085                                                 "nand rd"};
1086 static const char * const xrx200_exin_grps[] = {"exin0", "exin1", "exin2",
1087                                                 "exin3", "exin4", "exin5"};
1088 static const char * const xrx200_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
1089 static const char * const xrx200_usif_grps[] = {"usif uart_rx", "usif uart_tx",
1090                                                 "usif uart_rts", "usif uart_cts",
1091                                                 "usif uart_dtr", "usif uart_dsr",
1092                                                 "usif uart_dcd", "usif uart_ri",
1093                                                 "usif spi_di", "usif spi_do",
1094                                                 "usif spi_clk", "usif spi_cs0",
1095                                                 "usif spi_cs1", "usif spi_cs2"};
1096 static const char * const xrx200_stp_grps[] = {"stp"};
1097 static const char * const xrx200_nmi_grps[] = {"nmi"};
1098 static const char * const xrx200_mdio_grps[] = {"mdio"};
1099 static const char * const xrx200_dfe_grps[] = {"dfe led0", "dfe led1"};
1100 static const char * const xrx200_gphy_grps[] = {"gphy0 led0", "gphy0 led1",
1101                                                 "gphy0 led2", "gphy1 led0",
1102                                                 "gphy1 led1", "gphy1 led2"};
1103
1104 static const struct ltq_pmx_func xrx200_funcs[] = {
1105         {"spi",         ARRAY_AND_SIZE(xrx200_spi_grps)},
1106         {"usif",        ARRAY_AND_SIZE(xrx200_usif_grps)},
1107         {"cgu",         ARRAY_AND_SIZE(xrx200_cgu_grps)},
1108         {"exin",        ARRAY_AND_SIZE(xrx200_exin_grps)},
1109         {"stp",         ARRAY_AND_SIZE(xrx200_stp_grps)},
1110         {"gpt",         ARRAY_AND_SIZE(xrx200_gpt_grps)},
1111         {"nmi",         ARRAY_AND_SIZE(xrx200_nmi_grps)},
1112         {"pci",         ARRAY_AND_SIZE(xrx200_pci_grps)},
1113         {"ebu",         ARRAY_AND_SIZE(xrx200_ebu_grps)},
1114         {"mdio",        ARRAY_AND_SIZE(xrx200_mdio_grps)},
1115         {"dfe",         ARRAY_AND_SIZE(xrx200_dfe_grps)},
1116         {"gphy",        ARRAY_AND_SIZE(xrx200_gphy_grps)},
1117 };
1118
1119 /* ---------  xrx300 related code --------- */
1120 #define XRX300_MAX_PIN          64
1121
1122 static const struct ltq_mfp_pin xrx300_mfp[] = {
1123         /*       pin    f0      f1      f2      f3   */
1124         MFP_XWAY(GPIO0, GPIO,   EXIN,   EPHY,   NONE),
1125         MFP_XWAY(GPIO1, GPIO,   NONE,   EXIN,   NONE),
1126         MFP_XWAY(GPIO2, NONE,   NONE,   NONE,   NONE),
1127         MFP_XWAY(GPIO3, GPIO,   CGU,    NONE,   NONE),
1128         MFP_XWAY(GPIO4, GPIO,   STP,    DFE,    NONE),
1129         MFP_XWAY(GPIO5, GPIO,   STP,    EPHY,   DFE),
1130         MFP_XWAY(GPIO6, GPIO,   STP,    NONE,   NONE),
1131         MFP_XWAY(GPIO7, NONE,   NONE,   NONE,   NONE),
1132         MFP_XWAY(GPIO8, GPIO,   CGU,    GPHY,   EPHY),
1133         MFP_XWAY(GPIO9, GPIO,   WIFI,   NONE,   EXIN),
1134         MFP_XWAY(GPIO10, GPIO,  USIF,   SPI,    EXIN),
1135         MFP_XWAY(GPIO11, GPIO,  USIF,   WIFI,   SPI),
1136         MFP_XWAY(GPIO12, NONE,  NONE,   NONE,   NONE),
1137         MFP_XWAY(GPIO13, GPIO,  EBU,    NONE,   NONE),
1138         MFP_XWAY(GPIO14, GPIO,  CGU,    USIF,   EPHY),
1139         MFP_XWAY(GPIO15, GPIO,  SPI,    NONE,   MCD),
1140         MFP_XWAY(GPIO16, GPIO,  SPI,    EXIN,   NONE),
1141         MFP_XWAY(GPIO17, GPIO,  SPI,    NONE,   NONE),
1142         MFP_XWAY(GPIO18, GPIO,  SPI,    NONE,   NONE),
1143         MFP_XWAY(GPIO19, GPIO,  USIF,   NONE,   EPHY),
1144         MFP_XWAY(GPIO20, NONE,  NONE,   NONE,   NONE),
1145         MFP_XWAY(GPIO21, NONE,  NONE,   NONE,   NONE),
1146         MFP_XWAY(GPIO22, NONE,  NONE,   NONE,   NONE),
1147         MFP_XWAY(GPIO23, GPIO,  EBU,    NONE,   NONE),
1148         MFP_XWAY(GPIO24, GPIO,  EBU,    NONE,   NONE),
1149         MFP_XWAY(GPIO25, GPIO,  TDM,    NONE,   NONE),
1150         MFP_XWAY(GPIO26, GPIO,  TDM,    NONE,   NONE),
1151         MFP_XWAY(GPIO27, GPIO,  TDM,    NONE,   NONE),
1152         MFP_XWAY(GPIO28, NONE,  NONE,   NONE,   NONE),
1153         MFP_XWAY(GPIO29, NONE,  NONE,   NONE,   NONE),
1154         MFP_XWAY(GPIO30, NONE,  NONE,   NONE,   NONE),
1155         MFP_XWAY(GPIO31, NONE,  NONE,   NONE,   NONE),
1156         MFP_XWAY(GPIO32, NONE,  NONE,   NONE,   NONE),
1157         MFP_XWAY(GPIO33, NONE,  NONE,   NONE,   NONE),
1158         MFP_XWAY(GPIO34, GPIO,  NONE,   SSI,    NONE),
1159         MFP_XWAY(GPIO35, GPIO,  NONE,   SSI,    NONE),
1160         MFP_XWAY(GPIO36, GPIO,  NONE,   SSI,    NONE),
1161         MFP_XWAY(GPIO37, NONE,  NONE,   NONE,   NONE),
1162         MFP_XWAY(GPIO38, NONE,  NONE,   NONE,   NONE),
1163         MFP_XWAY(GPIO39, NONE,  NONE,   NONE,   NONE),
1164         MFP_XWAY(GPIO40, NONE,  NONE,   NONE,   NONE),
1165         MFP_XWAY(GPIO41, NONE,  NONE,   NONE,   NONE),
1166         MFP_XWAY(GPIO42, GPIO,  MDIO,   NONE,   NONE),
1167         MFP_XWAY(GPIO43, GPIO,  MDIO,   NONE,   NONE),
1168         MFP_XWAY(GPIO44, NONE,  NONE,   NONE,   NONE),
1169         MFP_XWAY(GPIO45, NONE,  NONE,   NONE,   NONE),
1170         MFP_XWAY(GPIO46, NONE,  NONE,   NONE,   NONE),
1171         MFP_XWAY(GPIO47, NONE,  NONE,   NONE,   NONE),
1172         MFP_XWAY(GPIO48, GPIO,  EBU,    NONE,   NONE),
1173         MFP_XWAY(GPIO49, GPIO,  EBU,    NONE,   NONE),
1174         MFP_XWAY(GPIO50, GPIO,  EBU,    NONE,   NONE),
1175         MFP_XWAY(GPIO51, GPIO,  EBU,    NONE,   NONE),
1176         MFP_XWAY(GPIO52, GPIO,  EBU,    NONE,   NONE),
1177         MFP_XWAY(GPIO53, GPIO,  EBU,    NONE,   NONE),
1178         MFP_XWAY(GPIO54, GPIO,  EBU,    NONE,   NONE),
1179         MFP_XWAY(GPIO55, GPIO,  EBU,    NONE,   NONE),
1180         MFP_XWAY(GPIO56, GPIO,  EBU,    NONE,   NONE),
1181         MFP_XWAY(GPIO57, GPIO,  EBU,    NONE,   NONE),
1182         MFP_XWAY(GPIO58, GPIO,  EBU,    TDM,    NONE),
1183         MFP_XWAY(GPIO59, GPIO,  EBU,    NONE,   NONE),
1184         MFP_XWAY(GPIO60, GPIO,  EBU,    NONE,   NONE),
1185         MFP_XWAY(GPIO61, GPIO,  EBU,    NONE,   NONE),
1186         MFP_XWAY(GPIO62, NONE,  NONE,   NONE,   NONE),
1187         MFP_XWAY(GPIO63, NONE,  NONE,   NONE,   NONE),
1188 };
1189
1190 static const unsigned xrx300_exin_pin_map[] = {GPIO0, GPIO1, GPIO16, GPIO10, GPIO9};
1191
1192 static const unsigned xrx300_pins_exin0[] = {GPIO0};
1193 static const unsigned xrx300_pins_exin1[] = {GPIO1};
1194 static const unsigned xrx300_pins_exin2[] = {GPIO16};
1195 /* EXIN3 is not available on xrX300 */
1196 static const unsigned xrx300_pins_exin4[] = {GPIO10};
1197 static const unsigned xrx300_pins_exin5[] = {GPIO9};
1198
1199 static const unsigned xrx300_pins_usif_uart_rx[] = {GPIO11};
1200 static const unsigned xrx300_pins_usif_uart_tx[] = {GPIO10};
1201
1202 static const unsigned xrx300_pins_usif_spi_di[] = {GPIO11};
1203 static const unsigned xrx300_pins_usif_spi_do[] = {GPIO10};
1204 static const unsigned xrx300_pins_usif_spi_clk[] = {GPIO19};
1205 static const unsigned xrx300_pins_usif_spi_cs0[] = {GPIO14};
1206
1207 static const unsigned xrx300_pins_stp[] = {GPIO4, GPIO5, GPIO6};
1208 static const unsigned xrx300_pins_mdio[] = {GPIO42, GPIO43};
1209
1210 static const unsigned xrx300_pins_dfe_led0[] = {GPIO4};
1211 static const unsigned xrx300_pins_dfe_led1[] = {GPIO5};
1212
1213 static const unsigned xrx300_pins_ephy0_led0[] = {GPIO5};
1214 static const unsigned xrx300_pins_ephy0_led1[] = {GPIO8};
1215 static const unsigned xrx300_pins_ephy1_led0[] = {GPIO14};
1216 static const unsigned xrx300_pins_ephy1_led1[] = {GPIO19};
1217
1218 static const unsigned xrx300_pins_nand_ale[] = {GPIO13};
1219 static const unsigned xrx300_pins_nand_cs1[] = {GPIO23};
1220 static const unsigned xrx300_pins_nand_cle[] = {GPIO24};
1221 static const unsigned xrx300_pins_nand_rdy[] = {GPIO48};
1222 static const unsigned xrx300_pins_nand_rd[] = {GPIO49};
1223 static const unsigned xrx300_pins_nand_d1[] = {GPIO50};
1224 static const unsigned xrx300_pins_nand_d0[] = {GPIO51};
1225 static const unsigned xrx300_pins_nand_d2[] = {GPIO52};
1226 static const unsigned xrx300_pins_nand_d7[] = {GPIO53};
1227 static const unsigned xrx300_pins_nand_d6[] = {GPIO54};
1228 static const unsigned xrx300_pins_nand_d5[] = {GPIO55};
1229 static const unsigned xrx300_pins_nand_d4[] = {GPIO56};
1230 static const unsigned xrx300_pins_nand_d3[] = {GPIO57};
1231 static const unsigned xrx300_pins_nand_cs0[] = {GPIO58};
1232 static const unsigned xrx300_pins_nand_wr[] = {GPIO59};
1233 static const unsigned xrx300_pins_nand_wp[] = {GPIO60};
1234 static const unsigned xrx300_pins_nand_se[] = {GPIO61};
1235
1236 static const unsigned xrx300_pins_spi_di[] = {GPIO16};
1237 static const unsigned xrx300_pins_spi_do[] = {GPIO17};
1238 static const unsigned xrx300_pins_spi_clk[] = {GPIO18};
1239 static const unsigned xrx300_pins_spi_cs1[] = {GPIO15};
1240 /* SPI_CS2 is not available on xrX300 */
1241 /* SPI_CS3 is not available on xrX300 */
1242 static const unsigned xrx300_pins_spi_cs4[] = {GPIO10};
1243 /* SPI_CS5 is not available on xrX300 */
1244 static const unsigned xrx300_pins_spi_cs6[] = {GPIO11};
1245
1246 /* CLKOUT0 is not available on xrX300 */
1247 /* CLKOUT1 is not available on xrX300 */
1248 static const unsigned xrx300_pins_clkout2[] = {GPIO3};
1249
1250 static const struct ltq_pin_group xrx300_grps[] = {
1251         GRP_MUX("exin0", EXIN, xrx300_pins_exin0),
1252         GRP_MUX("exin1", EXIN, xrx300_pins_exin1),
1253         GRP_MUX("exin2", EXIN, xrx300_pins_exin2),
1254         GRP_MUX("exin4", EXIN, xrx300_pins_exin4),
1255         GRP_MUX("exin5", EXIN, xrx300_pins_exin5),
1256         GRP_MUX("nand ale", EBU, xrx300_pins_nand_ale),
1257         GRP_MUX("nand cs1", EBU, xrx300_pins_nand_cs1),
1258         GRP_MUX("nand cle", EBU, xrx300_pins_nand_cle),
1259         GRP_MUX("nand rdy", EBU, xrx300_pins_nand_rdy),
1260         GRP_MUX("nand rd", EBU, xrx300_pins_nand_rd),
1261         GRP_MUX("nand d1", EBU, xrx300_pins_nand_d1),
1262         GRP_MUX("nand d0", EBU, xrx300_pins_nand_d0),
1263         GRP_MUX("nand d2", EBU, xrx300_pins_nand_d2),
1264         GRP_MUX("nand d7", EBU, xrx300_pins_nand_d7),
1265         GRP_MUX("nand d6", EBU, xrx300_pins_nand_d6),
1266         GRP_MUX("nand d5", EBU, xrx300_pins_nand_d5),
1267         GRP_MUX("nand d4", EBU, xrx300_pins_nand_d4),
1268         GRP_MUX("nand d3", EBU, xrx300_pins_nand_d3),
1269         GRP_MUX("nand cs0", EBU, xrx300_pins_nand_cs0),
1270         GRP_MUX("nand wr", EBU, xrx300_pins_nand_wr),
1271         GRP_MUX("nand wp", EBU, xrx300_pins_nand_wp),
1272         GRP_MUX("nand se", EBU, xrx300_pins_nand_se),
1273         GRP_MUX("spi_di", SPI, xrx300_pins_spi_di),
1274         GRP_MUX("spi_do", SPI, xrx300_pins_spi_do),
1275         GRP_MUX("spi_clk", SPI, xrx300_pins_spi_clk),
1276         GRP_MUX("spi_cs1", SPI, xrx300_pins_spi_cs1),
1277         GRP_MUX("spi_cs4", SPI, xrx300_pins_spi_cs4),
1278         GRP_MUX("spi_cs6", SPI, xrx300_pins_spi_cs6),
1279         GRP_MUX("usif uart_rx", USIF, xrx300_pins_usif_uart_rx),
1280         GRP_MUX("usif uart_tx", USIF, xrx300_pins_usif_uart_tx),
1281         GRP_MUX("usif spi_di", USIF, xrx300_pins_usif_spi_di),
1282         GRP_MUX("usif spi_do", USIF, xrx300_pins_usif_spi_do),
1283         GRP_MUX("usif spi_clk", USIF, xrx300_pins_usif_spi_clk),
1284         GRP_MUX("usif spi_cs0", USIF, xrx300_pins_usif_spi_cs0),
1285         GRP_MUX("stp", STP, xrx300_pins_stp),
1286         GRP_MUX("clkout2", CGU, xrx300_pins_clkout2),
1287         GRP_MUX("mdio", MDIO, xrx300_pins_mdio),
1288         GRP_MUX("dfe led0", DFE, xrx300_pins_dfe_led0),
1289         GRP_MUX("dfe led1", DFE, xrx300_pins_dfe_led1),
1290         GRP_MUX("ephy0 led0", GPHY, xrx300_pins_ephy0_led0),
1291         GRP_MUX("ephy0 led1", GPHY, xrx300_pins_ephy0_led1),
1292         GRP_MUX("ephy1 led0", GPHY, xrx300_pins_ephy1_led0),
1293         GRP_MUX("ephy1 led1", GPHY, xrx300_pins_ephy1_led1),
1294 };
1295
1296 static const char * const xrx300_spi_grps[] = {"spi_di", "spi_do",
1297                                                 "spi_clk", "spi_cs1",
1298                                                 "spi_cs4", "spi_cs6"};
1299 static const char * const xrx300_cgu_grps[] = {"clkout2"};
1300 static const char * const xrx300_ebu_grps[] = {"nand ale", "nand cs1",
1301                                                 "nand cle", "nand rdy",
1302                                                 "nand rd", "nand d1",
1303                                                 "nand d0", "nand d2",
1304                                                 "nand d7", "nand d6",
1305                                                 "nand d5", "nand d4",
1306                                                 "nand d3", "nand cs0",
1307                                                 "nand wr", "nand wp",
1308                                                 "nand se"};
1309 static const char * const xrx300_exin_grps[] = {"exin0", "exin1", "exin2",
1310                                                 "exin4", "exin5"};
1311 static const char * const xrx300_usif_grps[] = {"usif uart_rx", "usif uart_tx",
1312                                                 "usif spi_di", "usif spi_do",
1313                                                 "usif spi_clk", "usif spi_cs0"};
1314 static const char * const xrx300_stp_grps[] = {"stp"};
1315 static const char * const xrx300_mdio_grps[] = {"mdio"};
1316 static const char * const xrx300_dfe_grps[] = {"dfe led0", "dfe led1"};
1317 static const char * const xrx300_gphy_grps[] = {"ephy0 led0", "ephy0 led1",
1318                                                 "ephy1 led0", "ephy1 led1"};
1319
1320 static const struct ltq_pmx_func xrx300_funcs[] = {
1321         {"spi",         ARRAY_AND_SIZE(xrx300_spi_grps)},
1322         {"usif",        ARRAY_AND_SIZE(xrx300_usif_grps)},
1323         {"cgu",         ARRAY_AND_SIZE(xrx300_cgu_grps)},
1324         {"exin",        ARRAY_AND_SIZE(xrx300_exin_grps)},
1325         {"stp",         ARRAY_AND_SIZE(xrx300_stp_grps)},
1326         {"ebu",         ARRAY_AND_SIZE(xrx300_ebu_grps)},
1327         {"mdio",        ARRAY_AND_SIZE(xrx300_mdio_grps)},
1328         {"dfe",         ARRAY_AND_SIZE(xrx300_dfe_grps)},
1329         {"ephy",        ARRAY_AND_SIZE(xrx300_gphy_grps)},
1330 };
1331
1332 /* ---------  pinconf related code --------- */
1333 static int xway_pinconf_get(struct pinctrl_dev *pctldev,
1334                                 unsigned pin,
1335                                 unsigned long *config)
1336 {
1337         struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
1338         enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
1339         int port = PORT(pin);
1340         u32 reg;
1341
1342         switch (param) {
1343         case LTQ_PINCONF_PARAM_OPEN_DRAIN:
1344                 if (port == PORT3)
1345                         reg = GPIO3_OD;
1346                 else
1347                         reg = GPIO_OD(pin);
1348                 *config = LTQ_PINCONF_PACK(param,
1349                         !gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
1350                 break;
1351
1352         case LTQ_PINCONF_PARAM_PULL:
1353                 if (port == PORT3)
1354                         reg = GPIO3_PUDEN;
1355                 else
1356                         reg = GPIO_PUDEN(pin);
1357                 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) {
1358                         *config = LTQ_PINCONF_PACK(param, 0);
1359                         break;
1360                 }
1361
1362                 if (port == PORT3)
1363                         reg = GPIO3_PUDSEL;
1364                 else
1365                         reg = GPIO_PUDSEL(pin);
1366                 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)))
1367                         *config = LTQ_PINCONF_PACK(param, 2);
1368                 else
1369                         *config = LTQ_PINCONF_PACK(param, 1);
1370                 break;
1371
1372         case LTQ_PINCONF_PARAM_OUTPUT:
1373                 reg = GPIO_DIR(pin);
1374                 *config = LTQ_PINCONF_PACK(param,
1375                         gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
1376                 break;
1377         default:
1378                 dev_err(pctldev->dev, "Invalid config param %04x\n", param);
1379                 return -ENOTSUPP;
1380         }
1381         return 0;
1382 }
1383
1384 static int xway_pinconf_set(struct pinctrl_dev *pctldev,
1385                                 unsigned pin,
1386                                 unsigned long *configs,
1387                                 unsigned num_configs)
1388 {
1389         struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
1390         enum ltq_pinconf_param param;
1391         int arg;
1392         int port = PORT(pin);
1393         u32 reg;
1394         int i;
1395
1396         for (i = 0; i < num_configs; i++) {
1397                 param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
1398                 arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
1399
1400                 switch (param) {
1401                 case LTQ_PINCONF_PARAM_OPEN_DRAIN:
1402                         if (port == PORT3)
1403                                 reg = GPIO3_OD;
1404                         else
1405                                 reg = GPIO_OD(pin);
1406                         if (arg == 0)
1407                                 gpio_setbit(info->membase[0],
1408                                         reg,
1409                                         PORT_PIN(pin));
1410                         else
1411                                 gpio_clearbit(info->membase[0],
1412                                         reg,
1413                                         PORT_PIN(pin));
1414                         break;
1415
1416                 case LTQ_PINCONF_PARAM_PULL:
1417                         if (port == PORT3)
1418                                 reg = GPIO3_PUDEN;
1419                         else
1420                                 reg = GPIO_PUDEN(pin);
1421                         if (arg == 0) {
1422                                 gpio_clearbit(info->membase[0],
1423                                         reg,
1424                                         PORT_PIN(pin));
1425                                 break;
1426                         }
1427                         gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
1428
1429                         if (port == PORT3)
1430                                 reg = GPIO3_PUDSEL;
1431                         else
1432                                 reg = GPIO_PUDSEL(pin);
1433                         if (arg == 1)
1434                                 gpio_clearbit(info->membase[0],
1435                                         reg,
1436                                         PORT_PIN(pin));
1437                         else if (arg == 2)
1438                                 gpio_setbit(info->membase[0],
1439                                         reg,
1440                                         PORT_PIN(pin));
1441                         else
1442                                 dev_err(pctldev->dev,
1443                                         "Invalid pull value %d\n", arg);
1444                         break;
1445
1446                 case LTQ_PINCONF_PARAM_OUTPUT:
1447                         reg = GPIO_DIR(pin);
1448                         if (arg == 0)
1449                                 gpio_clearbit(info->membase[0],
1450                                         reg,
1451                                         PORT_PIN(pin));
1452                         else
1453                                 gpio_setbit(info->membase[0],
1454                                         reg,
1455                                         PORT_PIN(pin));
1456                         break;
1457
1458                 default:
1459                         dev_err(pctldev->dev,
1460                                 "Invalid config param %04x\n", param);
1461                         return -ENOTSUPP;
1462                 }
1463         } /* for each config */
1464
1465         return 0;
1466 }
1467
1468 int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
1469                         unsigned selector,
1470                         unsigned long *configs,
1471                         unsigned num_configs)
1472 {
1473         struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
1474         int i, ret = 0;
1475
1476         for (i = 0; i < info->grps[selector].npins && !ret; i++)
1477                 ret = xway_pinconf_set(pctldev,
1478                                 info->grps[selector].pins[i],
1479                                 configs,
1480                                 num_configs);
1481
1482         return ret;
1483 }
1484
1485 static const struct pinconf_ops xway_pinconf_ops = {
1486         .pin_config_get = xway_pinconf_get,
1487         .pin_config_set = xway_pinconf_set,
1488         .pin_config_group_set = xway_pinconf_group_set,
1489 };
1490
1491 static struct pinctrl_desc xway_pctrl_desc = {
1492         .owner          = THIS_MODULE,
1493         .confops        = &xway_pinconf_ops,
1494 };
1495
1496 static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
1497                                 int pin, int mux)
1498 {
1499         struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
1500         int port = PORT(pin);
1501         u32 alt1_reg = GPIO_ALT1(pin);
1502
1503         if (port == PORT3)
1504                 alt1_reg = GPIO3_ALT1;
1505
1506         if (mux & MUX_ALT0)
1507                 gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
1508         else
1509                 gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
1510
1511         if (mux & MUX_ALT1)
1512                 gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin));
1513         else
1514                 gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin));
1515
1516         return 0;
1517 }
1518
1519 static const struct ltq_cfg_param xway_cfg_params[] = {
1520         {"lantiq,pull",         LTQ_PINCONF_PARAM_PULL},
1521         {"lantiq,open-drain",   LTQ_PINCONF_PARAM_OPEN_DRAIN},
1522         {"lantiq,output",       LTQ_PINCONF_PARAM_OUTPUT},
1523 };
1524
1525 static struct ltq_pinmux_info xway_info = {
1526         .desc           = &xway_pctrl_desc,
1527         .apply_mux      = xway_mux_apply,
1528         .params         = xway_cfg_params,
1529         .num_params     = ARRAY_SIZE(xway_cfg_params),
1530 };
1531
1532 /* ---------  gpio_chip related code --------- */
1533 static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
1534 {
1535         struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1536
1537         if (val)
1538                 gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
1539         else
1540                 gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
1541 }
1542
1543 static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin)
1544 {
1545         struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1546
1547         return !!gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin));
1548 }
1549
1550 static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
1551 {
1552         struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1553
1554         gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
1555
1556         return 0;
1557 }
1558
1559 static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val)
1560 {
1561         struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1562
1563         if (PORT(pin) == PORT3)
1564                 gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin));
1565         else
1566                 gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin));
1567         gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
1568         xway_gpio_set(chip, pin, val);
1569
1570         return 0;
1571 }
1572
1573 /*
1574  * gpiolib gpiod_to_irq callback function.
1575  * Returns the mapped IRQ (external interrupt) number for a given GPIO pin.
1576  */
1577 static int xway_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1578 {
1579         struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
1580         int i;
1581
1582         for (i = 0; i < info->num_exin; i++)
1583                 if (info->exin[i] == offset)
1584                         return ltq_eiu_get_irq(i);
1585
1586         return -1;
1587 }
1588
1589 static struct gpio_chip xway_chip = {
1590         .label = "gpio-xway",
1591         .direction_input = xway_gpio_dir_in,
1592         .direction_output = xway_gpio_dir_out,
1593         .get = xway_gpio_get,
1594         .set = xway_gpio_set,
1595         .request = gpiochip_generic_request,
1596         .free = gpiochip_generic_free,
1597         .to_irq = xway_gpio_to_irq,
1598         .base = -1,
1599 };
1600
1601
1602 /* --------- register the pinctrl layer --------- */
1603 struct pinctrl_xway_soc {
1604         int pin_count;
1605         const struct ltq_mfp_pin *mfp;
1606         const struct ltq_pin_group *grps;
1607         unsigned int num_grps;
1608         const struct ltq_pmx_func *funcs;
1609         unsigned int num_funcs;
1610         const unsigned *exin;
1611         unsigned int num_exin;
1612 };
1613
1614 /* xway xr9 series (DEPRECATED: Use XWAY xRX100/xRX200 Family) */
1615 static struct pinctrl_xway_soc xr9_pinctrl = {
1616         .pin_count = XR9_MAX_PIN,
1617         .mfp = xway_mfp,
1618         .grps = xway_grps,
1619         .num_grps = ARRAY_SIZE(xway_grps),
1620         .funcs = xrx_funcs,
1621         .num_funcs = ARRAY_SIZE(xrx_funcs),
1622         .exin = xway_exin_pin_map,
1623         .num_exin = 6
1624 };
1625
1626 /* XWAY AMAZON Family */
1627 static struct pinctrl_xway_soc ase_pinctrl = {
1628         .pin_count = ASE_MAX_PIN,
1629         .mfp = ase_mfp,
1630         .grps = ase_grps,
1631         .num_grps = ARRAY_SIZE(ase_grps),
1632         .funcs = ase_funcs,
1633         .num_funcs = ARRAY_SIZE(ase_funcs),
1634         .exin = ase_exin_pin_map,
1635         .num_exin = 3
1636 };
1637
1638 /* XWAY DANUBE Family */
1639 static struct pinctrl_xway_soc danube_pinctrl = {
1640         .pin_count = DANUBE_MAX_PIN,
1641         .mfp = danube_mfp,
1642         .grps = danube_grps,
1643         .num_grps = ARRAY_SIZE(danube_grps),
1644         .funcs = danube_funcs,
1645         .num_funcs = ARRAY_SIZE(danube_funcs),
1646         .exin = danube_exin_pin_map,
1647         .num_exin = 3
1648 };
1649
1650 /* XWAY xRX100 Family */
1651 static struct pinctrl_xway_soc xrx100_pinctrl = {
1652         .pin_count = XRX100_MAX_PIN,
1653         .mfp = xrx100_mfp,
1654         .grps = xrx100_grps,
1655         .num_grps = ARRAY_SIZE(xrx100_grps),
1656         .funcs = xrx100_funcs,
1657         .num_funcs = ARRAY_SIZE(xrx100_funcs),
1658         .exin = xrx100_exin_pin_map,
1659         .num_exin = 6
1660 };
1661
1662 /* XWAY xRX200 Family */
1663 static struct pinctrl_xway_soc xrx200_pinctrl = {
1664         .pin_count = XRX200_MAX_PIN,
1665         .mfp = xrx200_mfp,
1666         .grps = xrx200_grps,
1667         .num_grps = ARRAY_SIZE(xrx200_grps),
1668         .funcs = xrx200_funcs,
1669         .num_funcs = ARRAY_SIZE(xrx200_funcs),
1670         .exin = xrx200_exin_pin_map,
1671         .num_exin = 6
1672 };
1673
1674 /* XWAY xRX300 Family */
1675 static struct pinctrl_xway_soc xrx300_pinctrl = {
1676         .pin_count = XRX300_MAX_PIN,
1677         .mfp = xrx300_mfp,
1678         .grps = xrx300_grps,
1679         .num_grps = ARRAY_SIZE(xrx300_grps),
1680         .funcs = xrx300_funcs,
1681         .num_funcs = ARRAY_SIZE(xrx300_funcs),
1682         .exin = xrx300_exin_pin_map,
1683         .num_exin = 5
1684 };
1685
1686 static struct pinctrl_gpio_range xway_gpio_range = {
1687         .name   = "XWAY GPIO",
1688         .gc     = &xway_chip,
1689 };
1690
1691 static const struct of_device_id xway_match[] = {
1692         { .compatible = "lantiq,pinctrl-xway", .data = &danube_pinctrl}, /*DEPRECATED*/
1693         { .compatible = "lantiq,pinctrl-xr9", .data = &xr9_pinctrl}, /*DEPRECATED*/
1694         { .compatible = "lantiq,pinctrl-ase", .data = &ase_pinctrl}, /*DEPRECATED*/
1695         { .compatible = "lantiq,ase-pinctrl", .data = &ase_pinctrl},
1696         { .compatible = "lantiq,danube-pinctrl", .data = &danube_pinctrl},
1697         { .compatible = "lantiq,xrx100-pinctrl", .data = &xrx100_pinctrl},
1698         { .compatible = "lantiq,xrx200-pinctrl", .data = &xrx200_pinctrl},
1699         { .compatible = "lantiq,xrx300-pinctrl", .data = &xrx300_pinctrl},
1700         {},
1701 };
1702 MODULE_DEVICE_TABLE(of, xway_match);
1703
1704 static int pinmux_xway_probe(struct platform_device *pdev)
1705 {
1706         const struct of_device_id *match;
1707         const struct pinctrl_xway_soc *xway_soc;
1708         int ret, i;
1709
1710         /* get and remap our register range */
1711         xway_info.membase[0] = devm_platform_ioremap_resource(pdev, 0);
1712         if (IS_ERR(xway_info.membase[0]))
1713                 return PTR_ERR(xway_info.membase[0]);
1714
1715         match = of_match_device(xway_match, &pdev->dev);
1716         if (match)
1717                 xway_soc = (const struct pinctrl_xway_soc *) match->data;
1718         else
1719                 xway_soc = &danube_pinctrl;
1720
1721         /* find out how many pads we have */
1722         xway_chip.ngpio = xway_soc->pin_count;
1723
1724         /* load our pad descriptors */
1725         xway_info.pads = devm_kcalloc(&pdev->dev,
1726                         xway_chip.ngpio, sizeof(struct pinctrl_pin_desc),
1727                         GFP_KERNEL);
1728         if (!xway_info.pads)
1729                 return -ENOMEM;
1730
1731         for (i = 0; i < xway_chip.ngpio; i++) {
1732                 char *name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "io%d", i);
1733
1734                 if (!name)
1735                         return -ENOMEM;
1736
1737                 xway_info.pads[i].number = GPIO0 + i;
1738                 xway_info.pads[i].name = name;
1739         }
1740         xway_pctrl_desc.pins = xway_info.pads;
1741
1742         /* setup the data needed by pinctrl */
1743         xway_pctrl_desc.name    = dev_name(&pdev->dev);
1744         xway_pctrl_desc.npins   = xway_chip.ngpio;
1745
1746         xway_info.num_pads      = xway_chip.ngpio;
1747         xway_info.num_mfp       = xway_chip.ngpio;
1748         xway_info.mfp           = xway_soc->mfp;
1749         xway_info.grps          = xway_soc->grps;
1750         xway_info.num_grps      = xway_soc->num_grps;
1751         xway_info.funcs         = xway_soc->funcs;
1752         xway_info.num_funcs     = xway_soc->num_funcs;
1753         xway_info.exin          = xway_soc->exin;
1754         xway_info.num_exin      = xway_soc->num_exin;
1755
1756         /* register with the generic lantiq layer */
1757         ret = ltq_pinctrl_register(pdev, &xway_info);
1758         if (ret) {
1759                 dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
1760                 return ret;
1761         }
1762
1763         /* register the gpio chip */
1764         xway_chip.parent = &pdev->dev;
1765         xway_chip.owner = THIS_MODULE;
1766         ret = devm_gpiochip_add_data(&pdev->dev, &xway_chip, NULL);
1767         if (ret) {
1768                 dev_err(&pdev->dev, "Failed to register gpio chip\n");
1769                 return ret;
1770         }
1771
1772         /*
1773          * For DeviceTree-supported systems, the gpio core checks the
1774          * pinctrl's device node for the "gpio-ranges" property.
1775          * If it is present, it takes care of adding the pin ranges
1776          * for the driver. In this case the driver can skip ahead.
1777          *
1778          * In order to remain compatible with older, existing DeviceTree
1779          * files which don't set the "gpio-ranges" property or systems that
1780          * utilize ACPI the driver has to call gpiochip_add_pin_range().
1781          */
1782         if (!of_property_read_bool(pdev->dev.of_node, "gpio-ranges")) {
1783                 /* finish with registering the gpio range in pinctrl */
1784                 xway_gpio_range.npins = xway_chip.ngpio;
1785                 xway_gpio_range.base = xway_chip.base;
1786                 pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range);
1787         }
1788
1789         dev_info(&pdev->dev, "Init done\n");
1790         return 0;
1791 }
1792
1793 static struct platform_driver pinmux_xway_driver = {
1794         .probe  = pinmux_xway_probe,
1795         .driver = {
1796                 .name   = "pinctrl-xway",
1797                 .of_match_table = xway_match,
1798         },
1799 };
1800
1801 static int __init pinmux_xway_init(void)
1802 {
1803         return platform_driver_register(&pinmux_xway_driver);
1804 }
1805
1806 core_initcall_sync(pinmux_xway_init);