drivers/pinctrl/pinctrl-tegra124.c

   1 /*
   2  * Pinctrl data for the NVIDIA Tegra124 pinmux
   3  *
   4  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21
  22 #include "pinctrl-tegra.h"
  23
  24 /*
  25  * Most pins affected by the pinmux can also be GPIOs. Define these first.
  26  * These must match how the GPIO driver names/numbers its pins.
  27  */
  28 #define _GPIO(offset)                           (offset)
  29
  30 #define TEGRA_PIN_CLK_32K_OUT_PA0               _GPIO(0)
  31 #define TEGRA_PIN_UART3_CTS_N_PA1               _GPIO(1)
  32 #define TEGRA_PIN_DAP2_FS_PA2                   _GPIO(2)
  33 #define TEGRA_PIN_DAP2_SCLK_PA3                 _GPIO(3)
  34 #define TEGRA_PIN_DAP2_DIN_PA4                  _GPIO(4)
  35 #define TEGRA_PIN_DAP2_DOUT_PA5                 _GPIO(5)
  36 #define TEGRA_PIN_SDMMC3_CLK_PA6                _GPIO(6)
  37 #define TEGRA_PIN_SDMMC3_CMD_PA7                _GPIO(7)
  38 #define TEGRA_PIN_PB0                           _GPIO(8)
  39 #define TEGRA_PIN_PB1                           _GPIO(9)
  40 #define TEGRA_PIN_SDMMC3_DAT3_PB4               _GPIO(12)
  41 #define TEGRA_PIN_SDMMC3_DAT2_PB5               _GPIO(13)
  42 #define TEGRA_PIN_SDMMC3_DAT1_PB6               _GPIO(14)
  43 #define TEGRA_PIN_SDMMC3_DAT0_PB7               _GPIO(15)
  44 #define TEGRA_PIN_UART3_RTS_N_PC0               _GPIO(16)
  45 #define TEGRA_PIN_UART2_TXD_PC2                 _GPIO(18)
  46 #define TEGRA_PIN_UART2_RXD_PC3                 _GPIO(19)
  47 #define TEGRA_PIN_GEN1_I2C_SCL_PC4              _GPIO(20)
  48 #define TEGRA_PIN_GEN1_I2C_SDA_PC5              _GPIO(21)
  49 #define TEGRA_PIN_PC7                           _GPIO(23)
  50 #define TEGRA_PIN_PG0                           _GPIO(48)
  51 #define TEGRA_PIN_PG1                           _GPIO(49)
  52 #define TEGRA_PIN_PG2                           _GPIO(50)
  53 #define TEGRA_PIN_PG3                           _GPIO(51)
  54 #define TEGRA_PIN_PG4                           _GPIO(52)
  55 #define TEGRA_PIN_PG5                           _GPIO(53)
  56 #define TEGRA_PIN_PG6                           _GPIO(54)
  57 #define TEGRA_PIN_PG7                           _GPIO(55)
  58 #define TEGRA_PIN_PH0                           _GPIO(56)
  59 #define TEGRA_PIN_PH1                           _GPIO(57)
  60 #define TEGRA_PIN_PH2                           _GPIO(58)
  61 #define TEGRA_PIN_PH3                           _GPIO(59)
  62 #define TEGRA_PIN_PH4                           _GPIO(60)
  63 #define TEGRA_PIN_PH5                           _GPIO(61)
  64 #define TEGRA_PIN_PH6                           _GPIO(62)
  65 #define TEGRA_PIN_PH7                           _GPIO(63)
  66 #define TEGRA_PIN_PI0                           _GPIO(64)
  67 #define TEGRA_PIN_PI1                           _GPIO(65)
  68 #define TEGRA_PIN_PI2                           _GPIO(66)
  69 #define TEGRA_PIN_PI3                           _GPIO(67)
  70 #define TEGRA_PIN_PI4                           _GPIO(68)
  71 #define TEGRA_PIN_PI5                           _GPIO(69)
  72 #define TEGRA_PIN_PI6                           _GPIO(70)
  73 #define TEGRA_PIN_PI7                           _GPIO(71)
  74 #define TEGRA_PIN_PJ0                           _GPIO(72)
  75 #define TEGRA_PIN_PJ2                           _GPIO(74)
  76 #define TEGRA_PIN_UART2_CTS_N_PJ5               _GPIO(77)
  77 #define TEGRA_PIN_UART2_RTS_N_PJ6               _GPIO(78)
  78 #define TEGRA_PIN_PJ7                           _GPIO(79)
  79 #define TEGRA_PIN_PK0                           _GPIO(80)
  80 #define TEGRA_PIN_PK1                           _GPIO(81)
  81 #define TEGRA_PIN_PK2                           _GPIO(82)
  82 #define TEGRA_PIN_PK3                           _GPIO(83)
  83 #define TEGRA_PIN_PK4                           _GPIO(84)
  84 #define TEGRA_PIN_SPDIF_OUT_PK5                 _GPIO(85)
  85 #define TEGRA_PIN_SPDIF_IN_PK6                  _GPIO(86)
  86 #define TEGRA_PIN_PK7                           _GPIO(87)
  87 #define TEGRA_PIN_DAP1_FS_PN0                   _GPIO(104)
  88 #define TEGRA_PIN_DAP1_DIN_PN1                  _GPIO(105)
  89 #define TEGRA_PIN_DAP1_DOUT_PN2                 _GPIO(106)
  90 #define TEGRA_PIN_DAP1_SCLK_PN3                 _GPIO(107)
  91 #define TEGRA_PIN_USB_VBUS_EN0_PN4              _GPIO(108)
  92 #define TEGRA_PIN_USB_VBUS_EN1_PN5              _GPIO(109)
  93 #define TEGRA_PIN_HDMI_INT_PN7                  _GPIO(111)
  94 #define TEGRA_PIN_ULPI_DATA7_PO0                _GPIO(112)
  95 #define TEGRA_PIN_ULPI_DATA0_PO1                _GPIO(113)
  96 #define TEGRA_PIN_ULPI_DATA1_PO2                _GPIO(114)
  97 #define TEGRA_PIN_ULPI_DATA2_PO3                _GPIO(115)
  98 #define TEGRA_PIN_ULPI_DATA3_PO4                _GPIO(116)
  99 #define TEGRA_PIN_ULPI_DATA4_PO5                _GPIO(117)
 100 #define TEGRA_PIN_ULPI_DATA5_PO6                _GPIO(118)
 101 #define TEGRA_PIN_ULPI_DATA6_PO7                _GPIO(119)
 102 #define TEGRA_PIN_DAP3_FS_PP0                   _GPIO(120)
 103 #define TEGRA_PIN_DAP3_DIN_PP1                  _GPIO(121)
 104 #define TEGRA_PIN_DAP3_DOUT_PP2                 _GPIO(122)
 105 #define TEGRA_PIN_DAP3_SCLK_PP3                 _GPIO(123)
 106 #define TEGRA_PIN_DAP4_FS_PP4                   _GPIO(124)
 107 #define TEGRA_PIN_DAP4_DIN_PP5                  _GPIO(125)
 108 #define TEGRA_PIN_DAP4_DOUT_PP6                 _GPIO(126)
 109 #define TEGRA_PIN_DAP4_SCLK_PP7                 _GPIO(127)
 110 #define TEGRA_PIN_KB_COL0_PQ0                   _GPIO(128)
 111 #define TEGRA_PIN_KB_COL1_PQ1                   _GPIO(129)
 112 #define TEGRA_PIN_KB_COL2_PQ2                   _GPIO(130)
 113 #define TEGRA_PIN_KB_COL3_PQ3                   _GPIO(131)
 114 #define TEGRA_PIN_KB_COL4_PQ4                   _GPIO(132)
 115 #define TEGRA_PIN_KB_COL5_PQ5                   _GPIO(133)
 116 #define TEGRA_PIN_KB_COL6_PQ6                   _GPIO(134)
 117 #define TEGRA_PIN_KB_COL7_PQ7                   _GPIO(135)
 118 #define TEGRA_PIN_KB_ROW0_PR0                   _GPIO(136)
 119 #define TEGRA_PIN_KB_ROW1_PR1                   _GPIO(137)
 120 #define TEGRA_PIN_KB_ROW2_PR2                   _GPIO(138)
 121 #define TEGRA_PIN_KB_ROW3_PR3                   _GPIO(139)
 122 #define TEGRA_PIN_KB_ROW4_PR4                   _GPIO(140)
 123 #define TEGRA_PIN_KB_ROW5_PR5                   _GPIO(141)
 124 #define TEGRA_PIN_KB_ROW6_PR6                   _GPIO(142)
 125 #define TEGRA_PIN_KB_ROW7_PR7                   _GPIO(143)
 126 #define TEGRA_PIN_KB_ROW8_PS0                   _GPIO(144)
 127 #define TEGRA_PIN_KB_ROW9_PS1                   _GPIO(145)
 128 #define TEGRA_PIN_KB_ROW10_PS2                  _GPIO(146)
 129 #define TEGRA_PIN_KB_ROW11_PS3                  _GPIO(147)
 130 #define TEGRA_PIN_KB_ROW12_PS4                  _GPIO(148)
 131 #define TEGRA_PIN_KB_ROW13_PS5                  _GPIO(149)
 132 #define TEGRA_PIN_KB_ROW14_PS6                  _GPIO(150)
 133 #define TEGRA_PIN_KB_ROW15_PS7                  _GPIO(151)
 134 #define TEGRA_PIN_KB_ROW16_PT0                  _GPIO(152)
 135 #define TEGRA_PIN_KB_ROW17_PT1                  _GPIO(153)
 136 #define TEGRA_PIN_GEN2_I2C_SCL_PT5              _GPIO(157)
 137 #define TEGRA_PIN_GEN2_I2C_SDA_PT6              _GPIO(158)
 138 #define TEGRA_PIN_SDMMC4_CMD_PT7                _GPIO(159)
 139 #define TEGRA_PIN_PU0                           _GPIO(160)
 140 #define TEGRA_PIN_PU1                           _GPIO(161)
 141 #define TEGRA_PIN_PU2                           _GPIO(162)
 142 #define TEGRA_PIN_PU3                           _GPIO(163)
 143 #define TEGRA_PIN_PU4                           _GPIO(164)
 144 #define TEGRA_PIN_PU5                           _GPIO(165)
 145 #define TEGRA_PIN_PU6                           _GPIO(166)
 146 #define TEGRA_PIN_PV0                           _GPIO(168)
 147 #define TEGRA_PIN_PV1                           _GPIO(169)
 148 #define TEGRA_PIN_SDMMC3_CD_N_PV2               _GPIO(170)
 149 #define TEGRA_PIN_SDMMC1_WP_N_PV3               _GPIO(171)
 150 #define TEGRA_PIN_DDC_SCL_PV4                   _GPIO(172)
 151 #define TEGRA_PIN_DDC_SDA_PV5                   _GPIO(173)
 152 #define TEGRA_PIN_GPIO_W2_AUD_PW2               _GPIO(178)
 153 #define TEGRA_PIN_GPIO_W3_AUD_PW3               _GPIO(179)
 154 #define TEGRA_PIN_DAP_MCLK1_PW4                 _GPIO(180)
 155 #define TEGRA_PIN_CLK2_OUT_PW5                  _GPIO(181)
 156 #define TEGRA_PIN_UART3_TXD_PW6                 _GPIO(182)
 157 #define TEGRA_PIN_UART3_RXD_PW7                 _GPIO(183)
 158 #define TEGRA_PIN_DVFS_PWM_PX0                  _GPIO(184)
 159 #define TEGRA_PIN_GPIO_X1_AUD_PX1               _GPIO(185)
 160 #define TEGRA_PIN_DVFS_CLK_PX2                  _GPIO(186)
 161 #define TEGRA_PIN_GPIO_X3_AUD_PX3               _GPIO(187)
 162 #define TEGRA_PIN_GPIO_X4_AUD_PX4               _GPIO(188)
 163 #define TEGRA_PIN_GPIO_X5_AUD_PX5               _GPIO(189)
 164 #define TEGRA_PIN_GPIO_X6_AUD_PX6               _GPIO(190)
 165 #define TEGRA_PIN_GPIO_X7_AUD_PX7               _GPIO(191)
 166 #define TEGRA_PIN_ULPI_CLK_PY0                  _GPIO(192)
 167 #define TEGRA_PIN_ULPI_DIR_PY1                  _GPIO(193)
 168 #define TEGRA_PIN_ULPI_NXT_PY2                  _GPIO(194)
 169 #define TEGRA_PIN_ULPI_STP_PY3                  _GPIO(195)
 170 #define TEGRA_PIN_SDMMC1_DAT3_PY4               _GPIO(196)
 171 #define TEGRA_PIN_SDMMC1_DAT2_PY5               _GPIO(197)
 172 #define TEGRA_PIN_SDMMC1_DAT1_PY6               _GPIO(198)
 173 #define TEGRA_PIN_SDMMC1_DAT0_PY7               _GPIO(199)
 174 #define TEGRA_PIN_SDMMC1_CLK_PZ0                _GPIO(200)
 175 #define TEGRA_PIN_SDMMC1_CMD_PZ1                _GPIO(201)
 176 #define TEGRA_PIN_PWR_I2C_SCL_PZ6               _GPIO(206)
 177 #define TEGRA_PIN_PWR_I2C_SDA_PZ7               _GPIO(207)
 178 #define TEGRA_PIN_SDMMC4_DAT0_PAA0              _GPIO(208)
 179 #define TEGRA_PIN_SDMMC4_DAT1_PAA1              _GPIO(209)
 180 #define TEGRA_PIN_SDMMC4_DAT2_PAA2              _GPIO(210)
 181 #define TEGRA_PIN_SDMMC4_DAT3_PAA3              _GPIO(211)
 182 #define TEGRA_PIN_SDMMC4_DAT4_PAA4              _GPIO(212)
 183 #define TEGRA_PIN_SDMMC4_DAT5_PAA5              _GPIO(213)
 184 #define TEGRA_PIN_SDMMC4_DAT6_PAA6              _GPIO(214)
 185 #define TEGRA_PIN_SDMMC4_DAT7_PAA7              _GPIO(215)
 186 #define TEGRA_PIN_PBB0                          _GPIO(216)
 187 #define TEGRA_PIN_CAM_I2C_SCL_PBB1              _GPIO(217)
 188 #define TEGRA_PIN_CAM_I2C_SDA_PBB2              _GPIO(218)
 189 #define TEGRA_PIN_PBB3                          _GPIO(219)
 190 #define TEGRA_PIN_PBB4                          _GPIO(220)
 191 #define TEGRA_PIN_PBB5                          _GPIO(221)
 192 #define TEGRA_PIN_PBB6                          _GPIO(222)
 193 #define TEGRA_PIN_PBB7                          _GPIO(223)
 194 #define TEGRA_PIN_CAM_MCLK_PCC0                 _GPIO(224)
 195 #define TEGRA_PIN_PCC1                          _GPIO(225)
 196 #define TEGRA_PIN_PCC2                          _GPIO(226)
 197 #define TEGRA_PIN_SDMMC4_CLK_PCC4               _GPIO(228)
 198 #define TEGRA_PIN_CLK2_REQ_PCC5                 _GPIO(229)
 199 #define TEGRA_PIN_PEX_L0_RST_N_PDD1             _GPIO(233)
 200 #define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2          _GPIO(234)
 201 #define TEGRA_PIN_PEX_WAKE_N_PDD3               _GPIO(235)
 202 #define TEGRA_PIN_PEX_L1_RST_N_PDD5             _GPIO(237)
 203 #define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6          _GPIO(238)
 204 #define TEGRA_PIN_CLK3_OUT_PEE0                 _GPIO(240)
 205 #define TEGRA_PIN_CLK3_REQ_PEE1                 _GPIO(241)
 206 #define TEGRA_PIN_DAP_MCLK1_REQ_PEE2            _GPIO(242)
 207 #define TEGRA_PIN_HDMI_CEC_PEE3                 _GPIO(243)
 208 #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4        _GPIO(244)
 209 #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5         _GPIO(245)
 210 #define TEGRA_PIN_DP_HPD_PFF0                   _GPIO(248)
 211 #define TEGRA_PIN_USB_VBUS_EN2_PFF1             _GPIO(249)
 212 #define TEGRA_PIN_PFF2                          _GPIO(250)
 213
 214 /* All non-GPIO pins follow */
 215 #define NUM_GPIOS                               (TEGRA_PIN_PFF2 + 1)
 216 #define _PIN(offset)                            (NUM_GPIOS + (offset))
 217
 218 /* Non-GPIO pins */
 219 #define TEGRA_PIN_CORE_PWR_REQ                  _PIN(0)
 220 #define TEGRA_PIN_CPU_PWR_REQ                   _PIN(1)
 221 #define TEGRA_PIN_PWR_INT_N                     _PIN(2)
 222 #define TEGRA_PIN_GMI_CLK_LB                    _PIN(3)
 223 #define TEGRA_PIN_RESET_OUT_N                   _PIN(4)
 224 #define TEGRA_PIN_OWR                           _PIN(5)
 225 #define TEGRA_PIN_CLK_32K_IN                    _PIN(6)
 226 #define TEGRA_PIN_JTAG_RTCK                     _PIN(7)
 227
 228 static const struct pinctrl_pin_desc tegra124_pins[] = {
 229         PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
 230         PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
 231         PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
 232         PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
 233         PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
 234         PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
 235         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
 236         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
 237         PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"),
 238         PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"),
 239         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
 240         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
 241         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
 242         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
 243         PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
 244         PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
 245         PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
 246         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
 247         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
 248         PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"),
 249         PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"),
 250         PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"),
 251         PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"),
 252         PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"),
 253         PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"),
 254         PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"),
 255         PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"),
 256         PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"),
 257         PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"),
 258         PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"),
 259         PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"),
 260         PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"),
 261         PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"),
 262         PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"),
 263         PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
 264         PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"),
 265         PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"),
 266         PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"),
 267         PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"),
 268         PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"),
 269         PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"),
 270         PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"),
 271         PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"),
 272         PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"),
 273         PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"),
 274         PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"),
 275         PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
 276         PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
 277         PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"),
 278         PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
 279         PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
 280         PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
 281         PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
 282         PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
 283         PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
 284         PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
 285         PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
 286         PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
 287         PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
 288         PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
 289         PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
 290         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
 291         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
 292         PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
 293         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
 294         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
 295         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
 296         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
 297         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
 298         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
 299         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
 300         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
 301         PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
 302         PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
 303         PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
 304         PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
 305         PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
 306         PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
 307         PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
 308         PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
 309         PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
 310         PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
 311         PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
 312         PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
 313         PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
 314         PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
 315         PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
 316         PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
 317         PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
 318         PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
 319         PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
 320         PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
 321         PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
 322         PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
 323         PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
 324         PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
 325         PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
 326         PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
 327         PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
 328         PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
 329         PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
 330         PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
 331         PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
 332         PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
 333         PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW16 PT0"),
 334         PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW17 PT1"),
 335         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
 336         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
 337         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
 338         PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
 339         PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
 340         PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
 341         PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
 342         PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
 343         PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
 344         PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
 345         PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
 346         PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
 347         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
 348         PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
 349         PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
 350         PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
 351         PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
 352         PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
 353         PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
 354         PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
 355         PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
 356         PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
 357         PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
 358         PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
 359         PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
 360         PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
 361         PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
 362         PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
 363         PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
 364         PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
 365         PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
 366         PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
 367         PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
 368         PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
 369         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
 370         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
 371         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
 372         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
 373         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
 374         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
 375         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
 376         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
 377         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
 378         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
 379         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
 380         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
 381         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
 382         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
 383         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
 384         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
 385         PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
 386         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
 387         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
 388         PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
 389         PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
 390         PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
 391         PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
 392         PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
 393         PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
 394         PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
 395         PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
 396         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
 397         PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
 398         PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
 399         PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
 400         PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
 401         PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
 402         PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
 403         PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
 404         PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
 405         PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"),
 406         PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
 407         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
 408         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
 409         PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
 410         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
 411         PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
 412         PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
 413         PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
 414         PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
 415         PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
 416         PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
 417         PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
 418         PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
 419         PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
 420 };
 421
 422 static const unsigned clk_32k_out_pa0_pins[] = {
 423         TEGRA_PIN_CLK_32K_OUT_PA0,
 424 };
 425
 426 static const unsigned uart3_cts_n_pa1_pins[] = {
 427         TEGRA_PIN_UART3_CTS_N_PA1,
 428 };
 429
 430 static const unsigned dap2_fs_pa2_pins[] = {
 431         TEGRA_PIN_DAP2_FS_PA2,
 432 };
 433
 434 static const unsigned dap2_sclk_pa3_pins[] = {
 435         TEGRA_PIN_DAP2_SCLK_PA3,
 436 };
 437
 438 static const unsigned dap2_din_pa4_pins[] = {
 439         TEGRA_PIN_DAP2_DIN_PA4,
 440 };
 441
 442 static const unsigned dap2_dout_pa5_pins[] = {
 443         TEGRA_PIN_DAP2_DOUT_PA5,
 444 };
 445
 446 static const unsigned sdmmc3_clk_pa6_pins[] = {
 447         TEGRA_PIN_SDMMC3_CLK_PA6,
 448 };
 449
 450 static const unsigned sdmmc3_cmd_pa7_pins[] = {
 451         TEGRA_PIN_SDMMC3_CMD_PA7,
 452 };
 453
 454 static const unsigned pb0_pins[] = {
 455         TEGRA_PIN_PB0,
 456 };
 457
 458 static const unsigned pb1_pins[] = {
 459         TEGRA_PIN_PB1,
 460 };
 461
 462 static const unsigned sdmmc3_dat3_pb4_pins[] = {
 463         TEGRA_PIN_SDMMC3_DAT3_PB4,
 464 };
 465
 466 static const unsigned sdmmc3_dat2_pb5_pins[] = {
 467         TEGRA_PIN_SDMMC3_DAT2_PB5,
 468 };
 469
 470 static const unsigned sdmmc3_dat1_pb6_pins[] = {
 471         TEGRA_PIN_SDMMC3_DAT1_PB6,
 472 };
 473
 474 static const unsigned sdmmc3_dat0_pb7_pins[] = {
 475         TEGRA_PIN_SDMMC3_DAT0_PB7,
 476 };
 477
 478 static const unsigned uart3_rts_n_pc0_pins[] = {
 479         TEGRA_PIN_UART3_RTS_N_PC0,
 480 };
 481
 482 static const unsigned uart2_txd_pc2_pins[] = {
 483         TEGRA_PIN_UART2_TXD_PC2,
 484 };
 485
 486 static const unsigned uart2_rxd_pc3_pins[] = {
 487         TEGRA_PIN_UART2_RXD_PC3,
 488 };
 489
 490 static const unsigned gen1_i2c_scl_pc4_pins[] = {
 491         TEGRA_PIN_GEN1_I2C_SCL_PC4,
 492 };
 493
 494 static const unsigned gen1_i2c_sda_pc5_pins[] = {
 495         TEGRA_PIN_GEN1_I2C_SDA_PC5,
 496 };
 497
 498 static const unsigned pc7_pins[] = {
 499         TEGRA_PIN_PC7,
 500 };
 501
 502 static const unsigned pg0_pins[] = {
 503         TEGRA_PIN_PG0,
 504 };
 505
 506 static const unsigned pg1_pins[] = {
 507         TEGRA_PIN_PG1,
 508 };
 509
 510 static const unsigned pg2_pins[] = {
 511         TEGRA_PIN_PG2,
 512 };
 513
 514 static const unsigned pg3_pins[] = {
 515         TEGRA_PIN_PG3,
 516 };
 517
 518 static const unsigned pg4_pins[] = {
 519         TEGRA_PIN_PG4,
 520 };
 521
 522 static const unsigned pg5_pins[] = {
 523         TEGRA_PIN_PG5,
 524 };
 525
 526 static const unsigned pg6_pins[] = {
 527         TEGRA_PIN_PG6,
 528 };
 529
 530 static const unsigned pg7_pins[] = {
 531         TEGRA_PIN_PG7,
 532 };
 533
 534 static const unsigned ph0_pins[] = {
 535         TEGRA_PIN_PH0,
 536 };
 537
 538 static const unsigned ph1_pins[] = {
 539         TEGRA_PIN_PH1,
 540 };
 541
 542 static const unsigned ph2_pins[] = {
 543         TEGRA_PIN_PH2,
 544 };
 545
 546 static const unsigned ph3_pins[] = {
 547         TEGRA_PIN_PH3,
 548 };
 549
 550 static const unsigned ph4_pins[] = {
 551         TEGRA_PIN_PH4,
 552 };
 553
 554 static const unsigned ph5_pins[] = {
 555         TEGRA_PIN_PH5,
 556 };
 557
 558 static const unsigned ph6_pins[] = {
 559         TEGRA_PIN_PH6,
 560 };
 561
 562 static const unsigned ph7_pins[] = {
 563         TEGRA_PIN_PH7,
 564 };
 565
 566 static const unsigned pi0_pins[] = {
 567         TEGRA_PIN_PI0,
 568 };
 569
 570 static const unsigned pi1_pins[] = {
 571         TEGRA_PIN_PI1,
 572 };
 573
 574 static const unsigned pi2_pins[] = {
 575         TEGRA_PIN_PI2,
 576 };
 577
 578 static const unsigned pi3_pins[] = {
 579         TEGRA_PIN_PI3,
 580 };
 581
 582 static const unsigned pi4_pins[] = {
 583         TEGRA_PIN_PI4,
 584 };
 585
 586 static const unsigned pi5_pins[] = {
 587         TEGRA_PIN_PI5,
 588 };
 589
 590 static const unsigned pi6_pins[] = {
 591         TEGRA_PIN_PI6,
 592 };
 593
 594 static const unsigned pi7_pins[] = {
 595         TEGRA_PIN_PI7,
 596 };
 597
 598 static const unsigned pj0_pins[] = {
 599         TEGRA_PIN_PJ0,
 600 };
 601
 602 static const unsigned pj2_pins[] = {
 603         TEGRA_PIN_PJ2,
 604 };
 605
 606 static const unsigned uart2_cts_n_pj5_pins[] = {
 607         TEGRA_PIN_UART2_CTS_N_PJ5,
 608 };
 609
 610 static const unsigned uart2_rts_n_pj6_pins[] = {
 611         TEGRA_PIN_UART2_RTS_N_PJ6,
 612 };
 613
 614 static const unsigned pj7_pins[] = {
 615         TEGRA_PIN_PJ7,
 616 };
 617
 618 static const unsigned pk0_pins[] = {
 619         TEGRA_PIN_PK0,
 620 };
 621
 622 static const unsigned pk1_pins[] = {
 623         TEGRA_PIN_PK1,
 624 };
 625
 626 static const unsigned pk2_pins[] = {
 627         TEGRA_PIN_PK2,
 628 };
 629
 630 static const unsigned pk3_pins[] = {
 631         TEGRA_PIN_PK3,
 632 };
 633
 634 static const unsigned pk4_pins[] = {
 635         TEGRA_PIN_PK4,
 636 };
 637
 638 static const unsigned spdif_out_pk5_pins[] = {
 639         TEGRA_PIN_SPDIF_OUT_PK5,
 640 };
 641
 642 static const unsigned spdif_in_pk6_pins[] = {
 643         TEGRA_PIN_SPDIF_IN_PK6,
 644 };
 645
 646 static const unsigned pk7_pins[] = {
 647         TEGRA_PIN_PK7,
 648 };
 649
 650 static const unsigned dap1_fs_pn0_pins[] = {
 651         TEGRA_PIN_DAP1_FS_PN0,
 652 };
 653
 654 static const unsigned dap1_din_pn1_pins[] = {
 655         TEGRA_PIN_DAP1_DIN_PN1,
 656 };
 657
 658 static const unsigned dap1_dout_pn2_pins[] = {
 659         TEGRA_PIN_DAP1_DOUT_PN2,
 660 };
 661
 662 static const unsigned dap1_sclk_pn3_pins[] = {
 663         TEGRA_PIN_DAP1_SCLK_PN3,
 664 };
 665
 666 static const unsigned usb_vbus_en0_pn4_pins[] = {
 667         TEGRA_PIN_USB_VBUS_EN0_PN4,
 668 };
 669
 670 static const unsigned usb_vbus_en1_pn5_pins[] = {
 671         TEGRA_PIN_USB_VBUS_EN1_PN5,
 672 };
 673
 674 static const unsigned hdmi_int_pn7_pins[] = {
 675         TEGRA_PIN_HDMI_INT_PN7,
 676 };
 677
 678 static const unsigned ulpi_data7_po0_pins[] = {
 679         TEGRA_PIN_ULPI_DATA7_PO0,
 680 };
 681
 682 static const unsigned ulpi_data0_po1_pins[] = {
 683         TEGRA_PIN_ULPI_DATA0_PO1,
 684 };
 685
 686 static const unsigned ulpi_data1_po2_pins[] = {
 687         TEGRA_PIN_ULPI_DATA1_PO2,
 688 };
 689
 690 static const unsigned ulpi_data2_po3_pins[] = {
 691         TEGRA_PIN_ULPI_DATA2_PO3,
 692 };
 693
 694 static const unsigned ulpi_data3_po4_pins[] = {
 695         TEGRA_PIN_ULPI_DATA3_PO4,
 696 };
 697
 698 static const unsigned ulpi_data4_po5_pins[] = {
 699         TEGRA_PIN_ULPI_DATA4_PO5,
 700 };
 701
 702 static const unsigned ulpi_data5_po6_pins[] = {
 703         TEGRA_PIN_ULPI_DATA5_PO6,
 704 };
 705
 706 static const unsigned ulpi_data6_po7_pins[] = {
 707         TEGRA_PIN_ULPI_DATA6_PO7,
 708 };
 709
 710 static const unsigned dap3_fs_pp0_pins[] = {
 711         TEGRA_PIN_DAP3_FS_PP0,
 712 };
 713
 714 static const unsigned dap3_din_pp1_pins[] = {
 715         TEGRA_PIN_DAP3_DIN_PP1,
 716 };
 717
 718 static const unsigned dap3_dout_pp2_pins[] = {
 719         TEGRA_PIN_DAP3_DOUT_PP2,
 720 };
 721
 722 static const unsigned dap3_sclk_pp3_pins[] = {
 723         TEGRA_PIN_DAP3_SCLK_PP3,
 724 };
 725
 726 static const unsigned dap4_fs_pp4_pins[] = {
 727         TEGRA_PIN_DAP4_FS_PP4,
 728 };
 729
 730 static const unsigned dap4_din_pp5_pins[] = {
 731         TEGRA_PIN_DAP4_DIN_PP5,
 732 };
 733
 734 static const unsigned dap4_dout_pp6_pins[] = {
 735         TEGRA_PIN_DAP4_DOUT_PP6,
 736 };
 737
 738 static const unsigned dap4_sclk_pp7_pins[] = {
 739         TEGRA_PIN_DAP4_SCLK_PP7,
 740 };
 741
 742 static const unsigned kb_col0_pq0_pins[] = {
 743         TEGRA_PIN_KB_COL0_PQ0,
 744 };
 745
 746 static const unsigned kb_col1_pq1_pins[] = {
 747         TEGRA_PIN_KB_COL1_PQ1,
 748 };
 749
 750 static const unsigned kb_col2_pq2_pins[] = {
 751         TEGRA_PIN_KB_COL2_PQ2,
 752 };
 753
 754 static const unsigned kb_col3_pq3_pins[] = {
 755         TEGRA_PIN_KB_COL3_PQ3,
 756 };
 757
 758 static const unsigned kb_col4_pq4_pins[] = {
 759         TEGRA_PIN_KB_COL4_PQ4,
 760 };
 761
 762 static const unsigned kb_col5_pq5_pins[] = {
 763         TEGRA_PIN_KB_COL5_PQ5,
 764 };
 765
 766 static const unsigned kb_col6_pq6_pins[] = {
 767         TEGRA_PIN_KB_COL6_PQ6,
 768 };
 769
 770 static const unsigned kb_col7_pq7_pins[] = {
 771         TEGRA_PIN_KB_COL7_PQ7,
 772 };
 773
 774 static const unsigned kb_row0_pr0_pins[] = {
 775         TEGRA_PIN_KB_ROW0_PR0,
 776 };
 777
 778 static const unsigned kb_row1_pr1_pins[] = {
 779         TEGRA_PIN_KB_ROW1_PR1,
 780 };
 781
 782 static const unsigned kb_row2_pr2_pins[] = {
 783         TEGRA_PIN_KB_ROW2_PR2,
 784 };
 785
 786 static const unsigned kb_row3_pr3_pins[] = {
 787         TEGRA_PIN_KB_ROW3_PR3,
 788 };
 789
 790 static const unsigned kb_row4_pr4_pins[] = {
 791         TEGRA_PIN_KB_ROW4_PR4,
 792 };
 793
 794 static const unsigned kb_row5_pr5_pins[] = {
 795         TEGRA_PIN_KB_ROW5_PR5,
 796 };
 797
 798 static const unsigned kb_row6_pr6_pins[] = {
 799         TEGRA_PIN_KB_ROW6_PR6,
 800 };
 801
 802 static const unsigned kb_row7_pr7_pins[] = {
 803         TEGRA_PIN_KB_ROW7_PR7,
 804 };
 805
 806 static const unsigned kb_row8_ps0_pins[] = {
 807         TEGRA_PIN_KB_ROW8_PS0,
 808 };
 809
 810 static const unsigned kb_row9_ps1_pins[] = {
 811         TEGRA_PIN_KB_ROW9_PS1,
 812 };
 813
 814 static const unsigned kb_row10_ps2_pins[] = {
 815         TEGRA_PIN_KB_ROW10_PS2,
 816 };
 817
 818 static const unsigned kb_row11_ps3_pins[] = {
 819         TEGRA_PIN_KB_ROW11_PS3,
 820 };
 821
 822 static const unsigned kb_row12_ps4_pins[] = {
 823         TEGRA_PIN_KB_ROW12_PS4,
 824 };
 825
 826 static const unsigned kb_row13_ps5_pins[] = {
 827         TEGRA_PIN_KB_ROW13_PS5,
 828 };
 829
 830 static const unsigned kb_row14_ps6_pins[] = {
 831         TEGRA_PIN_KB_ROW14_PS6,
 832 };
 833
 834 static const unsigned kb_row15_ps7_pins[] = {
 835         TEGRA_PIN_KB_ROW15_PS7,
 836 };
 837
 838 static const unsigned kb_row16_pt0_pins[] = {
 839         TEGRA_PIN_KB_ROW16_PT0,
 840 };
 841
 842 static const unsigned kb_row17_pt1_pins[] = {
 843         TEGRA_PIN_KB_ROW17_PT1,
 844 };
 845
 846 static const unsigned gen2_i2c_scl_pt5_pins[] = {
 847         TEGRA_PIN_GEN2_I2C_SCL_PT5,
 848 };
 849
 850 static const unsigned gen2_i2c_sda_pt6_pins[] = {
 851         TEGRA_PIN_GEN2_I2C_SDA_PT6,
 852 };
 853
 854 static const unsigned sdmmc4_cmd_pt7_pins[] = {
 855         TEGRA_PIN_SDMMC4_CMD_PT7,
 856 };
 857
 858 static const unsigned pu0_pins[] = {
 859         TEGRA_PIN_PU0,
 860 };
 861
 862 static const unsigned pu1_pins[] = {
 863         TEGRA_PIN_PU1,
 864 };
 865
 866 static const unsigned pu2_pins[] = {
 867         TEGRA_PIN_PU2,
 868 };
 869
 870 static const unsigned pu3_pins[] = {
 871         TEGRA_PIN_PU3,
 872 };
 873
 874 static const unsigned pu4_pins[] = {
 875         TEGRA_PIN_PU4,
 876 };
 877
 878 static const unsigned pu5_pins[] = {
 879         TEGRA_PIN_PU5,
 880 };
 881
 882 static const unsigned pu6_pins[] = {
 883         TEGRA_PIN_PU6,
 884 };
 885
 886 static const unsigned pv0_pins[] = {
 887         TEGRA_PIN_PV0,
 888 };
 889
 890 static const unsigned pv1_pins[] = {
 891         TEGRA_PIN_PV1,
 892 };
 893
 894 static const unsigned sdmmc3_cd_n_pv2_pins[] = {
 895         TEGRA_PIN_SDMMC3_CD_N_PV2,
 896 };
 897
 898 static const unsigned sdmmc1_wp_n_pv3_pins[] = {
 899         TEGRA_PIN_SDMMC1_WP_N_PV3,
 900 };
 901
 902 static const unsigned ddc_scl_pv4_pins[] = {
 903         TEGRA_PIN_DDC_SCL_PV4,
 904 };
 905
 906 static const unsigned ddc_sda_pv5_pins[] = {
 907         TEGRA_PIN_DDC_SDA_PV5,
 908 };
 909
 910 static const unsigned gpio_w2_aud_pw2_pins[] = {
 911         TEGRA_PIN_GPIO_W2_AUD_PW2,
 912 };
 913
 914 static const unsigned gpio_w3_aud_pw3_pins[] = {
 915         TEGRA_PIN_GPIO_W3_AUD_PW3,
 916 };
 917
 918 static const unsigned dap_mclk1_pw4_pins[] = {
 919         TEGRA_PIN_DAP_MCLK1_PW4,
 920 };
 921
 922 static const unsigned clk2_out_pw5_pins[] = {
 923         TEGRA_PIN_CLK2_OUT_PW5,
 924 };
 925
 926 static const unsigned uart3_txd_pw6_pins[] = {
 927         TEGRA_PIN_UART3_TXD_PW6,
 928 };
 929
 930 static const unsigned uart3_rxd_pw7_pins[] = {
 931         TEGRA_PIN_UART3_RXD_PW7,
 932 };
 933
 934 static const unsigned dvfs_pwm_px0_pins[] = {
 935         TEGRA_PIN_DVFS_PWM_PX0,
 936 };
 937
 938 static const unsigned gpio_x1_aud_px1_pins[] = {
 939         TEGRA_PIN_GPIO_X1_AUD_PX1,
 940 };
 941
 942 static const unsigned dvfs_clk_px2_pins[] = {
 943         TEGRA_PIN_DVFS_CLK_PX2,
 944 };
 945
 946 static const unsigned gpio_x3_aud_px3_pins[] = {
 947         TEGRA_PIN_GPIO_X3_AUD_PX3,
 948 };
 949
 950 static const unsigned gpio_x4_aud_px4_pins[] = {
 951         TEGRA_PIN_GPIO_X4_AUD_PX4,
 952 };
 953
 954 static const unsigned gpio_x5_aud_px5_pins[] = {
 955         TEGRA_PIN_GPIO_X5_AUD_PX5,
 956 };
 957
 958 static const unsigned gpio_x6_aud_px6_pins[] = {
 959         TEGRA_PIN_GPIO_X6_AUD_PX6,
 960 };
 961
 962 static const unsigned gpio_x7_aud_px7_pins[] = {
 963         TEGRA_PIN_GPIO_X7_AUD_PX7,
 964 };
 965
 966 static const unsigned ulpi_clk_py0_pins[] = {
 967         TEGRA_PIN_ULPI_CLK_PY0,
 968 };
 969
 970 static const unsigned ulpi_dir_py1_pins[] = {
 971         TEGRA_PIN_ULPI_DIR_PY1,
 972 };
 973
 974 static const unsigned ulpi_nxt_py2_pins[] = {
 975         TEGRA_PIN_ULPI_NXT_PY2,
 976 };
 977
 978 static const unsigned ulpi_stp_py3_pins[] = {
 979         TEGRA_PIN_ULPI_STP_PY3,
 980 };
 981
 982 static const unsigned sdmmc1_dat3_py4_pins[] = {
 983         TEGRA_PIN_SDMMC1_DAT3_PY4,
 984 };
 985
 986 static const unsigned sdmmc1_dat2_py5_pins[] = {
 987         TEGRA_PIN_SDMMC1_DAT2_PY5,
 988 };
 989
 990 static const unsigned sdmmc1_dat1_py6_pins[] = {
 991         TEGRA_PIN_SDMMC1_DAT1_PY6,
 992 };
 993
 994 static const unsigned sdmmc1_dat0_py7_pins[] = {
 995         TEGRA_PIN_SDMMC1_DAT0_PY7,
 996 };
 997
 998 static const unsigned sdmmc1_clk_pz0_pins[] = {
 999         TEGRA_PIN_SDMMC1_CLK_PZ0,
1000 };
1001
1002 static const unsigned sdmmc1_cmd_pz1_pins[] = {
1003         TEGRA_PIN_SDMMC1_CMD_PZ1,
1004 };
1005
1006 static const unsigned pwr_i2c_scl_pz6_pins[] = {
1007         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1008 };
1009
1010 static const unsigned pwr_i2c_sda_pz7_pins[] = {
1011         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1012 };
1013
1014 static const unsigned sdmmc4_dat0_paa0_pins[] = {
1015         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1016 };
1017
1018 static const unsigned sdmmc4_dat1_paa1_pins[] = {
1019         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1020 };
1021
1022 static const unsigned sdmmc4_dat2_paa2_pins[] = {
1023         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1024 };
1025
1026 static const unsigned sdmmc4_dat3_paa3_pins[] = {
1027         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1028 };
1029
1030 static const unsigned sdmmc4_dat4_paa4_pins[] = {
1031         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1032 };
1033
1034 static const unsigned sdmmc4_dat5_paa5_pins[] = {
1035         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1036 };
1037
1038 static const unsigned sdmmc4_dat6_paa6_pins[] = {
1039         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1040 };
1041
1042 static const unsigned sdmmc4_dat7_paa7_pins[] = {
1043         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1044 };
1045
1046 static const unsigned pbb0_pins[] = {
1047         TEGRA_PIN_PBB0,
1048 };
1049
1050 static const unsigned cam_i2c_scl_pbb1_pins[] = {
1051         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1052 };
1053
1054 static const unsigned cam_i2c_sda_pbb2_pins[] = {
1055         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1056 };
1057
1058 static const unsigned pbb3_pins[] = {
1059         TEGRA_PIN_PBB3,
1060 };
1061
1062 static const unsigned pbb4_pins[] = {
1063         TEGRA_PIN_PBB4,
1064 };
1065
1066 static const unsigned pbb5_pins[] = {
1067         TEGRA_PIN_PBB5,
1068 };
1069
1070 static const unsigned pbb6_pins[] = {
1071         TEGRA_PIN_PBB6,
1072 };
1073
1074 static const unsigned pbb7_pins[] = {
1075         TEGRA_PIN_PBB7,
1076 };
1077
1078 static const unsigned cam_mclk_pcc0_pins[] = {
1079         TEGRA_PIN_CAM_MCLK_PCC0,
1080 };
1081
1082 static const unsigned pcc1_pins[] = {
1083         TEGRA_PIN_PCC1,
1084 };
1085
1086 static const unsigned pcc2_pins[] = {
1087         TEGRA_PIN_PCC2,
1088 };
1089
1090 static const unsigned sdmmc4_clk_pcc4_pins[] = {
1091         TEGRA_PIN_SDMMC4_CLK_PCC4,
1092 };
1093
1094 static const unsigned clk2_req_pcc5_pins[] = {
1095         TEGRA_PIN_CLK2_REQ_PCC5,
1096 };
1097
1098 static const unsigned pex_l0_rst_n_pdd1_pins[] = {
1099         TEGRA_PIN_PEX_L0_RST_N_PDD1,
1100 };
1101
1102 static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
1103         TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1104 };
1105
1106 static const unsigned pex_wake_n_pdd3_pins[] = {
1107         TEGRA_PIN_PEX_WAKE_N_PDD3,
1108 };
1109
1110 static const unsigned pex_l1_rst_n_pdd5_pins[] = {
1111         TEGRA_PIN_PEX_L1_RST_N_PDD5,
1112 };
1113
1114 static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
1115         TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1116 };
1117
1118 static const unsigned clk3_out_pee0_pins[] = {
1119         TEGRA_PIN_CLK3_OUT_PEE0,
1120 };
1121
1122 static const unsigned clk3_req_pee1_pins[] = {
1123         TEGRA_PIN_CLK3_REQ_PEE1,
1124 };
1125
1126 static const unsigned dap_mclk1_req_pee2_pins[] = {
1127         TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1128 };
1129
1130 static const unsigned hdmi_cec_pee3_pins[] = {
1131         TEGRA_PIN_HDMI_CEC_PEE3,
1132 };
1133
1134 static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1135         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1136 };
1137
1138 static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1139         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1140 };
1141
1142 static const unsigned dp_hpd_pff0_pins[] = {
1143         TEGRA_PIN_DP_HPD_PFF0,
1144 };
1145
1146 static const unsigned usb_vbus_en2_pff1_pins[] = {
1147         TEGRA_PIN_USB_VBUS_EN2_PFF1,
1148 };
1149
1150 static const unsigned pff2_pins[] = {
1151         TEGRA_PIN_PFF2,
1152 };
1153
1154 static const unsigned core_pwr_req_pins[] = {
1155         TEGRA_PIN_CORE_PWR_REQ,
1156 };
1157
1158 static const unsigned cpu_pwr_req_pins[] = {
1159         TEGRA_PIN_CPU_PWR_REQ,
1160 };
1161
1162 static const unsigned pwr_int_n_pins[] = {
1163         TEGRA_PIN_PWR_INT_N,
1164 };
1165
1166 static const unsigned gmi_clk_lb_pins[] = {
1167         TEGRA_PIN_GMI_CLK_LB,
1168 };
1169
1170 static const unsigned reset_out_n_pins[] = {
1171         TEGRA_PIN_RESET_OUT_N,
1172 };
1173
1174 static const unsigned owr_pins[] = {
1175         TEGRA_PIN_OWR,
1176 };
1177
1178 static const unsigned clk_32k_in_pins[] = {
1179         TEGRA_PIN_CLK_32K_IN,
1180 };
1181
1182 static const unsigned jtag_rtck_pins[] = {
1183         TEGRA_PIN_JTAG_RTCK,
1184 };
1185
1186 static const unsigned drive_ao1_pins[] = {
1187         TEGRA_PIN_KB_ROW0_PR0,
1188         TEGRA_PIN_KB_ROW1_PR1,
1189         TEGRA_PIN_KB_ROW2_PR2,
1190         TEGRA_PIN_KB_ROW3_PR3,
1191         TEGRA_PIN_KB_ROW4_PR4,
1192         TEGRA_PIN_KB_ROW5_PR5,
1193         TEGRA_PIN_KB_ROW6_PR6,
1194         TEGRA_PIN_KB_ROW7_PR7,
1195         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1196         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1197 };
1198
1199 static const unsigned drive_ao2_pins[] = {
1200         TEGRA_PIN_CLK_32K_OUT_PA0,
1201         TEGRA_PIN_CLK_32K_IN,
1202         TEGRA_PIN_KB_COL0_PQ0,
1203         TEGRA_PIN_KB_COL1_PQ1,
1204         TEGRA_PIN_KB_COL2_PQ2,
1205         TEGRA_PIN_KB_COL3_PQ3,
1206         TEGRA_PIN_KB_COL4_PQ4,
1207         TEGRA_PIN_KB_COL5_PQ5,
1208         TEGRA_PIN_KB_COL6_PQ6,
1209         TEGRA_PIN_KB_COL7_PQ7,
1210         TEGRA_PIN_KB_ROW8_PS0,
1211         TEGRA_PIN_KB_ROW9_PS1,
1212         TEGRA_PIN_KB_ROW10_PS2,
1213         TEGRA_PIN_KB_ROW11_PS3,
1214         TEGRA_PIN_KB_ROW12_PS4,
1215         TEGRA_PIN_KB_ROW13_PS5,
1216         TEGRA_PIN_KB_ROW14_PS6,
1217         TEGRA_PIN_KB_ROW15_PS7,
1218         TEGRA_PIN_KB_ROW16_PT0,
1219         TEGRA_PIN_KB_ROW17_PT1,
1220         TEGRA_PIN_SDMMC3_CD_N_PV2,
1221         TEGRA_PIN_CORE_PWR_REQ,
1222         TEGRA_PIN_CPU_PWR_REQ,
1223         TEGRA_PIN_PWR_INT_N,
1224 };
1225
1226 static const unsigned drive_at1_pins[] = {
1227         TEGRA_PIN_PH0,
1228         TEGRA_PIN_PH1,
1229         TEGRA_PIN_PH2,
1230         TEGRA_PIN_PH3,
1231 };
1232
1233 static const unsigned drive_at2_pins[] = {
1234         TEGRA_PIN_PG0,
1235         TEGRA_PIN_PG1,
1236         TEGRA_PIN_PG2,
1237         TEGRA_PIN_PG3,
1238         TEGRA_PIN_PG4,
1239         TEGRA_PIN_PG5,
1240         TEGRA_PIN_PG6,
1241         TEGRA_PIN_PG7,
1242         TEGRA_PIN_PI0,
1243         TEGRA_PIN_PI1,
1244         TEGRA_PIN_PI3,
1245         TEGRA_PIN_PI4,
1246         TEGRA_PIN_PI7,
1247         TEGRA_PIN_PK0,
1248         TEGRA_PIN_PK2,
1249 };
1250
1251 static const unsigned drive_at3_pins[] = {
1252         TEGRA_PIN_PC7,
1253         TEGRA_PIN_PJ0,
1254 };
1255
1256 static const unsigned drive_at4_pins[] = {
1257         TEGRA_PIN_PB0,
1258         TEGRA_PIN_PB1,
1259         TEGRA_PIN_PJ0,
1260         TEGRA_PIN_PJ7,
1261         TEGRA_PIN_PK7,
1262 };
1263
1264 static const unsigned drive_at5_pins[] = {
1265         TEGRA_PIN_GEN2_I2C_SCL_PT5,
1266         TEGRA_PIN_GEN2_I2C_SDA_PT6,
1267 };
1268
1269 static const unsigned drive_cdev1_pins[] = {
1270         TEGRA_PIN_DAP_MCLK1_PW4,
1271         TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1272 };
1273
1274 static const unsigned drive_cdev2_pins[] = {
1275         TEGRA_PIN_CLK2_OUT_PW5,
1276         TEGRA_PIN_CLK2_REQ_PCC5,
1277 };
1278
1279 static const unsigned drive_dap1_pins[] = {
1280         TEGRA_PIN_DAP1_FS_PN0,
1281         TEGRA_PIN_DAP1_DIN_PN1,
1282         TEGRA_PIN_DAP1_DOUT_PN2,
1283         TEGRA_PIN_DAP1_SCLK_PN3,
1284 };
1285
1286 static const unsigned drive_dap2_pins[] = {
1287         TEGRA_PIN_DAP2_FS_PA2,
1288         TEGRA_PIN_DAP2_SCLK_PA3,
1289         TEGRA_PIN_DAP2_DIN_PA4,
1290         TEGRA_PIN_DAP2_DOUT_PA5,
1291 };
1292
1293 static const unsigned drive_dap3_pins[] = {
1294         TEGRA_PIN_DAP3_FS_PP0,
1295         TEGRA_PIN_DAP3_DIN_PP1,
1296         TEGRA_PIN_DAP3_DOUT_PP2,
1297         TEGRA_PIN_DAP3_SCLK_PP3,
1298 };
1299
1300 static const unsigned drive_dap4_pins[] = {
1301         TEGRA_PIN_DAP4_FS_PP4,
1302         TEGRA_PIN_DAP4_DIN_PP5,
1303         TEGRA_PIN_DAP4_DOUT_PP6,
1304         TEGRA_PIN_DAP4_SCLK_PP7,
1305 };
1306
1307 static const unsigned drive_dbg_pins[] = {
1308         TEGRA_PIN_GEN1_I2C_SCL_PC4,
1309         TEGRA_PIN_GEN1_I2C_SDA_PC5,
1310         TEGRA_PIN_PU0,
1311         TEGRA_PIN_PU1,
1312         TEGRA_PIN_PU2,
1313         TEGRA_PIN_PU3,
1314         TEGRA_PIN_PU4,
1315         TEGRA_PIN_PU5,
1316         TEGRA_PIN_PU6,
1317 };
1318
1319 static const unsigned drive_sdio3_pins[] = {
1320         TEGRA_PIN_SDMMC3_CLK_PA6,
1321         TEGRA_PIN_SDMMC3_CMD_PA7,
1322         TEGRA_PIN_SDMMC3_DAT3_PB4,
1323         TEGRA_PIN_SDMMC3_DAT2_PB5,
1324         TEGRA_PIN_SDMMC3_DAT1_PB6,
1325         TEGRA_PIN_SDMMC3_DAT0_PB7,
1326         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1327         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1328 };
1329
1330 static const unsigned drive_spi_pins[] = {
1331         TEGRA_PIN_DVFS_PWM_PX0,
1332         TEGRA_PIN_GPIO_X1_AUD_PX1,
1333         TEGRA_PIN_DVFS_CLK_PX2,
1334         TEGRA_PIN_GPIO_X3_AUD_PX3,
1335         TEGRA_PIN_GPIO_X4_AUD_PX4,
1336         TEGRA_PIN_GPIO_X5_AUD_PX5,
1337         TEGRA_PIN_GPIO_X6_AUD_PX6,
1338         TEGRA_PIN_GPIO_X7_AUD_PX7,
1339         TEGRA_PIN_GPIO_W2_AUD_PW2,
1340         TEGRA_PIN_GPIO_W3_AUD_PW3,
1341 };
1342
1343 static const unsigned drive_uaa_pins[] = {
1344         TEGRA_PIN_ULPI_DATA0_PO1,
1345         TEGRA_PIN_ULPI_DATA1_PO2,
1346         TEGRA_PIN_ULPI_DATA2_PO3,
1347         TEGRA_PIN_ULPI_DATA3_PO4,
1348 };
1349
1350 static const unsigned drive_uab_pins[] = {
1351         TEGRA_PIN_ULPI_DATA7_PO0,
1352         TEGRA_PIN_ULPI_DATA4_PO5,
1353         TEGRA_PIN_ULPI_DATA5_PO6,
1354         TEGRA_PIN_ULPI_DATA6_PO7,
1355         TEGRA_PIN_PV0,
1356         TEGRA_PIN_PV1,
1357 };
1358
1359 static const unsigned drive_uart2_pins[] = {
1360         TEGRA_PIN_UART2_TXD_PC2,
1361         TEGRA_PIN_UART2_RXD_PC3,
1362         TEGRA_PIN_UART2_CTS_N_PJ5,
1363         TEGRA_PIN_UART2_RTS_N_PJ6,
1364 };
1365
1366 static const unsigned drive_uart3_pins[] = {
1367         TEGRA_PIN_UART3_CTS_N_PA1,
1368         TEGRA_PIN_UART3_RTS_N_PC0,
1369         TEGRA_PIN_UART3_TXD_PW6,
1370         TEGRA_PIN_UART3_RXD_PW7,
1371 };
1372
1373 static const unsigned drive_sdio1_pins[] = {
1374         TEGRA_PIN_SDMMC1_DAT3_PY4,
1375         TEGRA_PIN_SDMMC1_DAT2_PY5,
1376         TEGRA_PIN_SDMMC1_DAT1_PY6,
1377         TEGRA_PIN_SDMMC1_DAT0_PY7,
1378         TEGRA_PIN_SDMMC1_CLK_PZ0,
1379         TEGRA_PIN_SDMMC1_CMD_PZ1,
1380 };
1381
1382 static const unsigned drive_ddc_pins[] = {
1383         TEGRA_PIN_DDC_SCL_PV4,
1384         TEGRA_PIN_DDC_SDA_PV5,
1385 };
1386
1387 static const unsigned drive_gma_pins[] = {
1388         TEGRA_PIN_SDMMC4_CLK_PCC4,
1389         TEGRA_PIN_SDMMC4_CMD_PT7,
1390         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1391         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1392         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1393         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1394         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1395         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1396         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1397         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1398 };
1399
1400 static const unsigned drive_gme_pins[] = {
1401         TEGRA_PIN_PBB0,
1402         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1403         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1404         TEGRA_PIN_PBB3,
1405         TEGRA_PIN_PCC2,
1406 };
1407
1408 static const unsigned drive_gmf_pins[] = {
1409         TEGRA_PIN_PBB4,
1410         TEGRA_PIN_PBB5,
1411         TEGRA_PIN_PBB6,
1412         TEGRA_PIN_PBB7,
1413 };
1414
1415 static const unsigned drive_gmg_pins[] = {
1416         TEGRA_PIN_CAM_MCLK_PCC0,
1417 };
1418
1419 static const unsigned drive_gmh_pins[] = {
1420         TEGRA_PIN_PCC1,
1421 };
1422
1423 static const unsigned drive_owr_pins[] = {
1424         TEGRA_PIN_SDMMC3_CD_N_PV2,
1425         TEGRA_PIN_OWR,
1426 };
1427
1428 static const unsigned drive_uda_pins[] = {
1429         TEGRA_PIN_ULPI_CLK_PY0,
1430         TEGRA_PIN_ULPI_DIR_PY1,
1431         TEGRA_PIN_ULPI_NXT_PY2,
1432         TEGRA_PIN_ULPI_STP_PY3,
1433 };
1434
1435 static const unsigned drive_gpv_pins[] = {
1436         TEGRA_PIN_PEX_L0_RST_N_PDD1,
1437         TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1438         TEGRA_PIN_PEX_WAKE_N_PDD3,
1439         TEGRA_PIN_PEX_L1_RST_N_PDD5,
1440         TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1441         TEGRA_PIN_USB_VBUS_EN2_PFF1,
1442         TEGRA_PIN_PFF2,
1443 };
1444
1445 static const unsigned drive_dev3_pins[] = {
1446         TEGRA_PIN_CLK3_OUT_PEE0,
1447         TEGRA_PIN_CLK3_REQ_PEE1,
1448 };
1449
1450 static const unsigned drive_cec_pins[] = {
1451         TEGRA_PIN_HDMI_CEC_PEE3,
1452 };
1453
1454 static const unsigned drive_at6_pins[] = {
1455         TEGRA_PIN_PK1,
1456         TEGRA_PIN_PK3,
1457         TEGRA_PIN_PK4,
1458         TEGRA_PIN_PI2,
1459         TEGRA_PIN_PI5,
1460         TEGRA_PIN_PI6,
1461         TEGRA_PIN_PH4,
1462         TEGRA_PIN_PH5,
1463         TEGRA_PIN_PH6,
1464         TEGRA_PIN_PH7,
1465 };
1466
1467 static const unsigned drive_dap5_pins[] = {
1468         TEGRA_PIN_SPDIF_IN_PK6,
1469         TEGRA_PIN_SPDIF_OUT_PK5,
1470         TEGRA_PIN_DP_HPD_PFF0,
1471 };
1472
1473 static const unsigned drive_usb_vbus_en_pins[] = {
1474         TEGRA_PIN_USB_VBUS_EN0_PN4,
1475         TEGRA_PIN_USB_VBUS_EN1_PN5,
1476 };
1477
1478 static const unsigned drive_ao3_pins[] = {
1479         TEGRA_PIN_RESET_OUT_N,
1480 };
1481
1482 static const unsigned drive_ao0_pins[] = {
1483         TEGRA_PIN_JTAG_RTCK,
1484 };
1485
1486 static const unsigned drive_hv0_pins[] = {
1487         TEGRA_PIN_HDMI_INT_PN7,
1488 };
1489
1490 static const unsigned drive_sdio4_pins[] = {
1491         TEGRA_PIN_SDMMC1_WP_N_PV3,
1492 };
1493
1494 static const unsigned drive_ao4_pins[] = {
1495         TEGRA_PIN_JTAG_RTCK,
1496 };
1497
1498 enum tegra_mux {
1499         TEGRA_MUX_BLINK,
1500         TEGRA_MUX_CCLA,
1501         TEGRA_MUX_CEC,
1502         TEGRA_MUX_CLDVFS,
1503         TEGRA_MUX_CLK,
1504         TEGRA_MUX_CLK12,
1505         TEGRA_MUX_CPU,
1506         TEGRA_MUX_DAP,
1507         TEGRA_MUX_DAP1,
1508         TEGRA_MUX_DAP2,
1509         TEGRA_MUX_DEV3,
1510         TEGRA_MUX_DISPLAYA,
1511         TEGRA_MUX_DISPLAYA_ALT,
1512         TEGRA_MUX_DISPLAYB,
1513         TEGRA_MUX_DP,
1514         TEGRA_MUX_DTV,
1515         TEGRA_MUX_EXTPERIPH1,
1516         TEGRA_MUX_EXTPERIPH2,
1517         TEGRA_MUX_EXTPERIPH3,
1518         TEGRA_MUX_GMI,
1519         TEGRA_MUX_GMI_ALT,
1520         TEGRA_MUX_HDA,
1521         TEGRA_MUX_HSI,
1522         TEGRA_MUX_I2C1,
1523         TEGRA_MUX_I2C2,
1524         TEGRA_MUX_I2C3,
1525         TEGRA_MUX_I2C4,
1526         TEGRA_MUX_I2CPWR,
1527         TEGRA_MUX_I2S0,
1528         TEGRA_MUX_I2S1,
1529         TEGRA_MUX_I2S2,
1530         TEGRA_MUX_I2S3,
1531         TEGRA_MUX_I2S4,
1532         TEGRA_MUX_IRDA,
1533         TEGRA_MUX_KBC,
1534         TEGRA_MUX_OWR,
1535         TEGRA_MUX_PE,
1536         TEGRA_MUX_PE0,
1537         TEGRA_MUX_PE1,
1538         TEGRA_MUX_PMI,
1539         TEGRA_MUX_PWM0,
1540         TEGRA_MUX_PWM1,
1541         TEGRA_MUX_PWM2,
1542         TEGRA_MUX_PWM3,
1543         TEGRA_MUX_PWRON,
1544         TEGRA_MUX_RESET_OUT_N,
1545         TEGRA_MUX_RSVD1,
1546         TEGRA_MUX_RSVD2,
1547         TEGRA_MUX_RSVD3,
1548         TEGRA_MUX_RSVD4,
1549         TEGRA_MUX_RTCK,
1550         TEGRA_MUX_SATA,
1551         TEGRA_MUX_SDMMC1,
1552         TEGRA_MUX_SDMMC2,
1553         TEGRA_MUX_SDMMC3,
1554         TEGRA_MUX_SDMMC4,
1555         TEGRA_MUX_SOC,
1556         TEGRA_MUX_SPDIF,
1557         TEGRA_MUX_SPI1,
1558         TEGRA_MUX_SPI2,
1559         TEGRA_MUX_SPI3,
1560         TEGRA_MUX_SPI4,
1561         TEGRA_MUX_SPI5,
1562         TEGRA_MUX_SPI6,
1563         TEGRA_MUX_SYS,
1564         TEGRA_MUX_TMDS,
1565         TEGRA_MUX_TRACE,
1566         TEGRA_MUX_UARTA,
1567         TEGRA_MUX_UARTB,
1568         TEGRA_MUX_UARTC,
1569         TEGRA_MUX_UARTD,
1570         TEGRA_MUX_ULPI,
1571         TEGRA_MUX_USB,
1572         TEGRA_MUX_VGP1,
1573         TEGRA_MUX_VGP2,
1574         TEGRA_MUX_VGP3,
1575         TEGRA_MUX_VGP4,
1576         TEGRA_MUX_VGP5,
1577         TEGRA_MUX_VGP6,
1578         TEGRA_MUX_VI,
1579         TEGRA_MUX_VI_ALT1,
1580         TEGRA_MUX_VI_ALT3,
1581         TEGRA_MUX_VIMCLK2,
1582         TEGRA_MUX_VIMCLK2_ALT,
1583 };
1584
1585 #define FUNCTION(fname)                                 \
1586         {                                               \
1587                 .name = #fname,                         \
1588         }
1589
1590 static struct tegra_function tegra124_functions[] = {
1591         FUNCTION(blink),
1592         FUNCTION(ccla),
1593         FUNCTION(cec),
1594         FUNCTION(cldvfs),
1595         FUNCTION(clk),
1596         FUNCTION(clk12),
1597         FUNCTION(cpu),
1598         FUNCTION(dap),
1599         FUNCTION(dap1),
1600         FUNCTION(dap2),
1601         FUNCTION(dev3),
1602         FUNCTION(displaya),
1603         FUNCTION(displaya_alt),
1604         FUNCTION(displayb),
1605         FUNCTION(dp),
1606         FUNCTION(dtv),
1607         FUNCTION(extperiph1),
1608         FUNCTION(extperiph2),
1609         FUNCTION(extperiph3),
1610         FUNCTION(gmi),
1611         FUNCTION(gmi_alt),
1612         FUNCTION(hda),
1613         FUNCTION(hsi),
1614         FUNCTION(i2c1),
1615         FUNCTION(i2c2),
1616         FUNCTION(i2c3),
1617         FUNCTION(i2c4),
1618         FUNCTION(i2cpwr),
1619         FUNCTION(i2s0),
1620         FUNCTION(i2s1),
1621         FUNCTION(i2s2),
1622         FUNCTION(i2s3),
1623         FUNCTION(i2s4),
1624         FUNCTION(irda),
1625         FUNCTION(kbc),
1626         FUNCTION(owr),
1627         FUNCTION(pe),
1628         FUNCTION(pe0),
1629         FUNCTION(pe1),
1630         FUNCTION(pmi),
1631         FUNCTION(pwm0),
1632         FUNCTION(pwm1),
1633         FUNCTION(pwm2),
1634         FUNCTION(pwm3),
1635         FUNCTION(pwron),
1636         FUNCTION(reset_out_n),
1637         FUNCTION(rsvd1),
1638         FUNCTION(rsvd2),
1639         FUNCTION(rsvd3),
1640         FUNCTION(rsvd4),
1641         FUNCTION(rtck),
1642         FUNCTION(sata),
1643         FUNCTION(sdmmc1),
1644         FUNCTION(sdmmc2),
1645         FUNCTION(sdmmc3),
1646         FUNCTION(sdmmc4),
1647         FUNCTION(soc),
1648         FUNCTION(spdif),
1649         FUNCTION(spi1),
1650         FUNCTION(spi2),
1651         FUNCTION(spi3),
1652         FUNCTION(spi4),
1653         FUNCTION(spi5),
1654         FUNCTION(spi6),
1655         FUNCTION(sys),
1656         FUNCTION(tmds),
1657         FUNCTION(trace),
1658         FUNCTION(uarta),
1659         FUNCTION(uartb),
1660         FUNCTION(uartc),
1661         FUNCTION(uartd),
1662         FUNCTION(ulpi),
1663         FUNCTION(usb),
1664         FUNCTION(vgp1),
1665         FUNCTION(vgp2),
1666         FUNCTION(vgp3),
1667         FUNCTION(vgp4),
1668         FUNCTION(vgp5),
1669         FUNCTION(vgp6),
1670         FUNCTION(vi),
1671         FUNCTION(vi_alt1),
1672         FUNCTION(vi_alt3),
1673         FUNCTION(vimclk2),
1674         FUNCTION(vimclk2_alt),
1675 };
1676
1677 #define DRV_PINGROUP_REG_A              0x868   /* bank 0 */
1678 #define PINGROUP_REG_A                  0x3000  /* bank 1 */
1679
1680 #define PINGROUP_REG_Y(r)               ((r) - PINGROUP_REG_A)
1681 #define PINGROUP_REG_N(r)               -1
1682
1683 #define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel)  \
1684         {                                                               \
1685                 .name = #pg_name,                                       \
1686                 .pins = pg_name##_pins,                                 \
1687                 .npins = ARRAY_SIZE(pg_name##_pins),                    \
1688                 .funcs = {                                              \
1689                         TEGRA_MUX_##f0,                                 \
1690                         TEGRA_MUX_##f1,                                 \
1691                         TEGRA_MUX_##f2,                                 \
1692                         TEGRA_MUX_##f3,                                 \
1693                 },                                                      \
1694                 .func_safe = TEGRA_MUX_##f_safe,                        \
1695                 .mux_reg = PINGROUP_REG_Y(r),                           \
1696                 .mux_bank = 1,                                          \
1697                 .mux_bit = 0,                                           \
1698                 .pupd_reg = PINGROUP_REG_Y(r),                          \
1699                 .pupd_bank = 1,                                         \
1700                 .pupd_bit = 2,                                          \
1701                 .tri_reg = PINGROUP_REG_Y(r),                           \
1702                 .tri_bank = 1,                                          \
1703                 .tri_bit = 4,                                           \
1704                 .einput_reg = PINGROUP_REG_Y(r),                        \
1705                 .einput_bank = 1,                                       \
1706                 .einput_bit = 5,                                        \
1707                 .odrain_reg = PINGROUP_REG_##od(r),                     \
1708                 .odrain_bank = 1,                                       \
1709                 .odrain_bit = 6,                                        \
1710                 .lock_reg = PINGROUP_REG_Y(r),                          \
1711                 .lock_bank = 1,                                         \
1712                 .lock_bit = 7,                                          \
1713                 .ioreset_reg = PINGROUP_REG_##ior(r),                   \
1714                 .ioreset_bank = 1,                                      \
1715                 .ioreset_bit = 8,                                       \
1716                 .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r),               \
1717                 .rcv_sel_bank = 1,                                      \
1718                 .rcv_sel_bit = 9,                                       \
1719                 .drv_reg = -1,                                          \
1720                 .drvtype_reg = -1,                                      \
1721         }
1722
1723 #define DRV_PINGROUP_REG_Y(r)           ((r) - DRV_PINGROUP_REG_A)
1724 #define DRV_PINGROUP_REG_N(r)           -1
1725
1726
1727 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b,              \
1728                      drvdn_b, drvdn_w, drvup_b, drvup_w,                \
1729                      slwr_b, slwr_w, slwf_b, slwf_w,                    \
1730                      drvtype)                                           \
1731         {                                                               \
1732                 .name = "drive_" #pg_name,                              \
1733                 .pins = drive_##pg_name##_pins,                         \
1734                 .npins = ARRAY_SIZE(drive_##pg_name##_pins),            \
1735                 .mux_reg = -1,                                          \
1736                 .pupd_reg = -1,                                         \
1737                 .tri_reg = -1,                                          \
1738                 .einput_reg = -1,                                       \
1739                 .odrain_reg = -1,                                       \
1740                 .lock_reg = -1,                                         \
1741                 .ioreset_reg = -1,                                      \
1742                 .rcv_sel_reg = -1,                                      \
1743                 .drv_reg = DRV_PINGROUP_REG_Y(r),                       \
1744                 .drv_bank = 0,                                          \
1745                 .hsm_bit = hsm_b,                                       \
1746                 .schmitt_bit = schmitt_b,                               \
1747                 .lpmd_bit = lpmd_b,                                     \
1748                 .drvdn_bit = drvdn_b,                                   \
1749                 .drvdn_width = drvdn_w,                                 \
1750                 .drvup_bit = drvup_b,                                   \
1751                 .drvup_width = drvup_w,                                 \
1752                 .slwr_bit = slwr_b,                                     \
1753                 .slwr_width = slwr_w,                                   \
1754                 .slwf_bit = slwf_b,                                     \
1755                 .slwf_width = slwf_w,                                   \
1756                 .drvtype_reg = DRV_PINGROUP_REG_##drvtype(r),           \
1757                 .drvtype_bank = 0,                                      \
1758                 .drvtype_bit = 6,                                       \
1759         }
1760
1761 static const struct tegra_pingroup tegra124_groups[] = {
1762        /*       pg_name,                f0,         f1,         f2,           f3,          safe,       r,      od, ior, rcv_sel */
1763        PINGROUP(ulpi_data0_po1,         SPI3,       HSI,        UARTA,        ULPI,        SPI3,       0x3000,  N,  N,  N),
1764        PINGROUP(ulpi_data1_po2,         SPI3,       HSI,        UARTA,        ULPI,        SPI3,       0x3004,  N,  N,  N),
1765        PINGROUP(ulpi_data2_po3,         SPI3,       HSI,        UARTA,        ULPI,        SPI3,       0x3008,  N,  N,  N),
1766        PINGROUP(ulpi_data3_po4,         SPI3,       HSI,        UARTA,        ULPI,        SPI3,       0x300c,  N,  N,  N),
1767        PINGROUP(ulpi_data4_po5,         SPI2,       HSI,        UARTA,        ULPI,        SPI2,       0x3010,  N,  N,  N),
1768        PINGROUP(ulpi_data5_po6,         SPI2,       HSI,        UARTA,        ULPI,        SPI2,       0x3014,  N,  N,  N),
1769        PINGROUP(ulpi_data6_po7,         SPI2,       HSI,        UARTA,        ULPI,        SPI2,       0x3018,  N,  N,  N),
1770        PINGROUP(ulpi_data7_po0,         SPI2,       HSI,        UARTA,        ULPI,        SPI2,       0x301c,  N,  N,  N),
1771        PINGROUP(ulpi_clk_py0,           SPI1,       SPI5,       UARTD,        ULPI,        SPI1,       0x3020,  N,  N,  N),
1772        PINGROUP(ulpi_dir_py1,           SPI1,       SPI5,       UARTD,        ULPI,        SPI1,       0x3024,  N,  N,  N),
1773        PINGROUP(ulpi_nxt_py2,           SPI1,       SPI5,       UARTD,        ULPI,        SPI1,       0x3028,  N,  N,  N),
1774        PINGROUP(ulpi_stp_py3,           SPI1,       SPI5,       UARTD,        ULPI,        SPI1,       0x302c,  N,  N,  N),
1775        PINGROUP(dap3_fs_pp0,            I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    I2S2,       0x3030,  N,  N,  N),
1776        PINGROUP(dap3_din_pp1,           I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    I2S2,       0x3034,  N,  N,  N),
1777        PINGROUP(dap3_dout_pp2,          I2S2,       SPI5,       DISPLAYA,     RSVD4,       I2S2,       0x3038,  N,  N,  N),
1778        PINGROUP(dap3_sclk_pp3,          I2S2,       SPI5,       RSVD3,        DISPLAYB,    I2S2,       0x303c,  N,  N,  N),
1779        PINGROUP(pv0,                    RSVD1,      RSVD2,      RSVD3,        RSVD4,       RSVD1,      0x3040,  N,  N,  N),
1780        PINGROUP(pv1,                    RSVD1,      RSVD2,      RSVD3,        RSVD4,       RSVD1,      0x3044,  N,  N,  N),
1781        PINGROUP(sdmmc1_clk_pz0,         SDMMC1,     CLK12,      RSVD3,        RSVD4,       RSVD3,      0x3048,  N,  N,  N),
1782        PINGROUP(sdmmc1_cmd_pz1,         SDMMC1,     SPDIF,      SPI4,         UARTA,       SDMMC1,     0x304c,  N,  N,  N),
1783        PINGROUP(sdmmc1_dat3_py4,        SDMMC1,     SPDIF,      SPI4,         UARTA,       SDMMC1,     0x3050,  N,  N,  N),
1784        PINGROUP(sdmmc1_dat2_py5,        SDMMC1,     PWM0,       SPI4,         UARTA,       SDMMC1,     0x3054,  N,  N,  N),
1785        PINGROUP(sdmmc1_dat1_py6,        SDMMC1,     PWM1,       SPI4,         UARTA,       SDMMC1,     0x3058,  N,  N,  N),
1786        PINGROUP(sdmmc1_dat0_py7,        SDMMC1,     RSVD2,      SPI4,         UARTA,       SDMMC1,     0x305c,  N,  N,  N),
1787        PINGROUP(clk2_out_pw5,           EXTPERIPH2, RSVD2,      RSVD3,        RSVD4,       EXTPERIPH2, 0x3068,  N,  N,  N),
1788        PINGROUP(clk2_req_pcc5,          DAP,        RSVD2,      RSVD3,        RSVD4,       DAP,        0x306c,  N,  N,  N),
1789        PINGROUP(hdmi_int_pn7,           RSVD1,      RSVD2,      RSVD3,        RSVD4,       RSVD1,      0x3110,  N,  N,  Y),
1790        PINGROUP(ddc_scl_pv4,            I2C4,       RSVD2,      RSVD3,        RSVD4,       I2C4,       0x3114,  N,  N,  Y),
1791        PINGROUP(ddc_sda_pv5,            I2C4,       RSVD2,      RSVD3,        RSVD4,       I2C4,       0x3118,  N,  N,  Y),
1792        PINGROUP(uart2_rxd_pc3,          IRDA,       SPDIF,      UARTA,        SPI4,        IRDA,       0x3164,  N,  N,  N),
1793        PINGROUP(uart2_txd_pc2,          IRDA,       SPDIF,      UARTA,        SPI4,        IRDA,       0x3168,  N,  N,  N),
1794        PINGROUP(uart2_rts_n_pj6,        UARTA,      UARTB,      GMI,          SPI4,        UARTA,      0x316c,  N,  N,  N),
1795        PINGROUP(uart2_cts_n_pj5,        UARTA,      UARTB,      GMI,          SPI4,        UARTA,      0x3170,  N,  N,  N),
1796        PINGROUP(uart3_txd_pw6,          UARTC,      RSVD2,      GMI,          SPI4,        UARTC,      0x3174,  N,  N,  N),
1797        PINGROUP(uart3_rxd_pw7,          UARTC,      RSVD2,      GMI,          SPI4,        UARTC,      0x3178,  N,  N,  N),
1798        PINGROUP(uart3_cts_n_pa1,        UARTC,      SDMMC1,     DTV,          GMI,         UARTC,      0x317c,  N,  N,  N),
1799        PINGROUP(uart3_rts_n_pc0,        UARTC,      PWM0,       DTV,          GMI,         UARTC,      0x3180,  N,  N,  N),
1800        PINGROUP(pu0,                    OWR,        UARTA,      GMI,          RSVD4,       RSVD4,      0x3184,  N,  N,  N),
1801        PINGROUP(pu1,                    RSVD1,      UARTA,      GMI,          RSVD4,       RSVD4,      0x3188,  N,  N,  N),
1802        PINGROUP(pu2,                    RSVD1,      UARTA,      GMI,          RSVD4,       RSVD4,      0x318c,  N,  N,  N),
1803        PINGROUP(pu3,                    PWM0,       UARTA,      GMI,          DISPLAYB,    PWM0,       0x3190,  N,  N,  N),
1804        PINGROUP(pu4,                    PWM1,       UARTA,      GMI,          DISPLAYB,    PWM1,       0x3194,  N,  N,  N),
1805        PINGROUP(pu5,                    PWM2,       UARTA,      GMI,          DISPLAYB,    PWM2,       0x3198,  N,  N,  N),
1806        PINGROUP(pu6,                    PWM3,       UARTA,      RSVD3,        GMI,         RSVD3,      0x319c,  N,  N,  N),
1807        PINGROUP(gen1_i2c_sda_pc5,       I2C1,       RSVD2,      RSVD3,        RSVD4,       I2C1,       0x31a0,  Y,  N,  N),
1808        PINGROUP(gen1_i2c_scl_pc4,       I2C1,       RSVD2,      RSVD3,        RSVD4,       I2C1,       0x31a4,  Y,  N,  N),
1809        PINGROUP(dap4_fs_pp4,            I2S3,       GMI,        DTV,          RSVD4,       I2S3,       0x31a8,  N,  N,  N),
1810        PINGROUP(dap4_din_pp5,           I2S3,       GMI,        RSVD3,        RSVD4,       I2S3,       0x31ac,  N,  N,  N),
1811        PINGROUP(dap4_dout_pp6,          I2S3,       GMI,        DTV,          RSVD4,       I2S3,       0x31b0,  N,  N,  N),
1812        PINGROUP(dap4_sclk_pp7,          I2S3,       GMI,        RSVD3,        RSVD4,       I2S3,       0x31b4,  N,  N,  N),
1813        PINGROUP(clk3_out_pee0,          EXTPERIPH3, RSVD2,      RSVD3,        RSVD4,       RSVD3,      0x31b8,  N,  N,  N),
1814        PINGROUP(clk3_req_pee1,          DEV3,       RSVD2,      RSVD3,        RSVD4,       RSVD4,      0x31bc,  N,  N,  N),
1815        PINGROUP(pc7,                    RSVD1,      RSVD2,      GMI,          GMI_ALT,     RSVD1,      0x31c0,  N,  N,  N),
1816        PINGROUP(pi5,                    SDMMC2,     RSVD2,      GMI,          RSVD4,       GMI,        0x31c4,  N,  N,  N),
1817        PINGROUP(pi7,                    RSVD1,      TRACE,      GMI,          DTV,         RSVD1,      0x31c8,  N,  N,  N),
1818        PINGROUP(pk0,                    RSVD1,      SDMMC3,     GMI,          SOC,         RSVD1,      0x31cc,  N,  N,  N),
1819        PINGROUP(pk1,                    SDMMC2,     TRACE,      GMI,          RSVD4,       GMI,        0x31d0,  N,  N,  N),
1820        PINGROUP(pj0,                    RSVD1,      RSVD2,      GMI,          USB,         RSVD1,      0x31d4,  N,  N,  N),
1821        PINGROUP(pj2,                    RSVD1,      RSVD2,      GMI,          SOC,         RSVD1,      0x31d8,  N,  N,  N),
1822        PINGROUP(pk3,                    SDMMC2,     TRACE,      GMI,          CCLA,        GMI,        0x31dc,  N,  N,  N),
1823        PINGROUP(pk4,                    SDMMC2,     RSVD2,      GMI,          GMI_ALT,     GMI,        0x31e0,  N,  N,  N),
1824        PINGROUP(pk2,                    RSVD1,      RSVD2,      GMI,          RSVD4,       RSVD4,      0x31e4,  N,  N,  N),
1825        PINGROUP(pi3,                    RSVD1,      RSVD2,      GMI,          SPI4,        RSVD1,      0x31e8,  N,  N,  N),
1826        PINGROUP(pi6,                    RSVD1,      RSVD2,      GMI,          SDMMC2,      RSVD1,      0x31ec,  N,  N,  N),
1827        PINGROUP(pg0,                    RSVD1,      RSVD2,      GMI,          RSVD4,       RSVD4,      0x31f0,  N,  N,  N),
1828        PINGROUP(pg1,                    RSVD1,      RSVD2,      GMI,          RSVD4,       RSVD4,      0x31f4,  N,  N,  N),
1829        PINGROUP(pg2,                    RSVD1,      TRACE,      GMI,          RSVD4,       RSVD4,      0x31f8,  N,  N,  N),
1830        PINGROUP(pg3,                    RSVD1,      TRACE,      GMI,          RSVD4,       RSVD4,      0x31fc,  N,  N,  N),
1831        PINGROUP(pg4,                    RSVD1,      TMDS,       GMI,          SPI4,        RSVD1,      0x3200,  N,  N,  N),
1832        PINGROUP(pg5,                    RSVD1,      RSVD2,      GMI,          SPI4,        RSVD1,      0x3204,  N,  N,  N),
1833        PINGROUP(pg6,                    RSVD1,      RSVD2,      GMI,          SPI4,        RSVD1,      0x3208,  N,  N,  N),
1834        PINGROUP(pg7,                    RSVD1,      RSVD2,      GMI,          SPI4,        RSVD1,      0x320c,  N,  N,  N),
1835        PINGROUP(ph0,                    PWM0,       TRACE,      GMI,          DTV,         GMI,        0x3210,  N,  N,  N),
1836        PINGROUP(ph1,                    PWM1,       TMDS,       GMI,          DISPLAYA,    GMI,        0x3214,  N,  N,  N),
1837        PINGROUP(ph2,                    PWM2,       TMDS,       GMI,          CLDVFS,      GMI,        0x3218,  N,  N,  N),
1838        PINGROUP(ph3,                    PWM3,       SPI4,       GMI,          CLDVFS,      GMI,        0x321c,  N,  N,  N),
1839        PINGROUP(ph4,                    SDMMC2,     RSVD2,      GMI,          RSVD4,       GMI,        0x3220,  N,  N,  N),
1840        PINGROUP(ph5,                    SDMMC2,     RSVD2,      GMI,          RSVD4,       GMI,        0x3224,  N,  N,  N),
1841        PINGROUP(ph6,                    SDMMC2,     TRACE,      GMI,          DTV,         GMI,        0x3228,  N,  N,  N),
1842        PINGROUP(ph7,                    SDMMC2,     TRACE,      GMI,          DTV,         GMI,        0x322c,  N,  N,  N),
1843        PINGROUP(pj7,                    UARTD,      RSVD2,      GMI,          GMI_ALT,     RSVD2,      0x3230,  N,  N,  N),
1844        PINGROUP(pb0,                    UARTD,      RSVD2,      GMI,          RSVD4,       RSVD2,      0x3234,  N,  N,  N),
1845        PINGROUP(pb1,                    UARTD,      RSVD2,      GMI,          RSVD4,       RSVD2,      0x3238,  N,  N,  N),
1846        PINGROUP(pk7,                    UARTD,      RSVD2,      GMI,          RSVD4,       RSVD2,      0x323c,  N,  N,  N),
1847        PINGROUP(pi0,                    RSVD1,      RSVD2,      GMI,          RSVD4,       RSVD4,      0x3240,  N,  N,  N),
1848        PINGROUP(pi1,                    RSVD1,      RSVD2,      GMI,          RSVD4,       RSVD1,      0x3244,  N,  N,  N),
1849        PINGROUP(pi2,                    SDMMC2,     TRACE,      GMI,          RSVD4,       GMI,        0x3248,  N,  N,  N),
1850        PINGROUP(pi4,                    SPI4,       TRACE,      GMI,          DISPLAYA,    GMI,        0x324c,  N,  N,  N),
1851        PINGROUP(gen2_i2c_scl_pt5,       I2C2,       RSVD2,      GMI,          RSVD4,       RSVD2,      0x3250,  Y,  N,  N),
1852        PINGROUP(gen2_i2c_sda_pt6,       I2C2,       RSVD2,      GMI,          RSVD4,       RSVD2,      0x3254,  Y,  N,  N),
1853        PINGROUP(sdmmc4_clk_pcc4,        SDMMC4,     RSVD2,      GMI,          RSVD4,       RSVD2,      0x3258,  N,  Y,  N),
1854        PINGROUP(sdmmc4_cmd_pt7,         SDMMC4,     RSVD2,      GMI,          RSVD4,       RSVD2,      0x325c,  N,  Y,  N),
1855        PINGROUP(sdmmc4_dat0_paa0,       SDMMC4,     SPI3,       GMI,          RSVD4,       SDMMC4,     0x3260,  N,  Y,  N),
1856        PINGROUP(sdmmc4_dat1_paa1,       SDMMC4,     SPI3,       GMI,          RSVD4,       SDMMC4,     0x3264,  N,  Y,  N),
1857        PINGROUP(sdmmc4_dat2_paa2,       SDMMC4,     SPI3,       GMI,          RSVD4,       SDMMC4,     0x3268,  N,  Y,  N),
1858        PINGROUP(sdmmc4_dat3_paa3,       SDMMC4,     SPI3,       GMI,          RSVD4,       SDMMC4,     0x326c,  N,  Y,  N),
1859        PINGROUP(sdmmc4_dat4_paa4,       SDMMC4,     SPI3,       GMI,          RSVD4,       SDMMC4,     0x3270,  N,  Y,  N),
1860        PINGROUP(sdmmc4_dat5_paa5,       SDMMC4,     SPI3,       RSVD3,        RSVD4,       SDMMC4,     0x3274,  N,  Y,  N),
1861        PINGROUP(sdmmc4_dat6_paa6,       SDMMC4,     SPI3,       GMI,          RSVD4,       SDMMC4,     0x3278,  N,  Y,  N),
1862        PINGROUP(sdmmc4_dat7_paa7,       SDMMC4,     RSVD2,      GMI,          RSVD4,       SDMMC4,     0x327c,  N,  Y,  N),
1863        PINGROUP(cam_mclk_pcc0,          VI,         VI_ALT1,    VI_ALT3,      SDMMC2,      VI,         0x3284,  N,  N,  N),
1864        PINGROUP(pcc1,                   I2S4,       RSVD2,      RSVD3,        SDMMC2,      I2S4,       0x3288,  N,  N,  N),
1865        PINGROUP(pbb0,                   VGP6,       VIMCLK2,    SDMMC2,       VIMCLK2_ALT, VGP6,       0x328c,  N,  N,  N),
1866        PINGROUP(cam_i2c_scl_pbb1,       VGP1,       I2C3,       RSVD3,        SDMMC2,      VGP1,       0x3290,  Y,  N,  N),
1867        PINGROUP(cam_i2c_sda_pbb2,       VGP2,       I2C3,       RSVD3,        SDMMC2,      VGP2,       0x3294,  Y,  N,  N),
1868        PINGROUP(pbb3,                   VGP3,       DISPLAYA,   DISPLAYB,     SDMMC2,      VGP3,       0x3298,  N,  N,  N),
1869        PINGROUP(pbb4,                   VGP4,       DISPLAYA,   DISPLAYB,     SDMMC2,      VGP4,       0x329c,  N,  N,  N),
1870        PINGROUP(pbb5,                   VGP5,       DISPLAYA,   RSVD3,        SDMMC2,      VGP5,       0x32a0,  N,  N,  N),
1871        PINGROUP(pbb6,                   I2S4,       RSVD2,      DISPLAYB,     SDMMC2,      I2S4,       0x32a4,  N,  N,  N),
1872        PINGROUP(pbb7,                   I2S4,       RSVD2,      RSVD3,        SDMMC2,      I2S4,       0x32a8,  N,  N,  N),
1873        PINGROUP(pcc2,                   I2S4,       RSVD2,      SDMMC3,       SDMMC2,      I2S4,       0x32ac,  N,  N,  N),
1874        PINGROUP(jtag_rtck,              RTCK,       RSVD2,      RSVD3,        RSVD4,       RTCK,       0x32b0,  N,  N,  N),
1875        PINGROUP(pwr_i2c_scl_pz6,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x32b4,  Y,  N,  N),
1876        PINGROUP(pwr_i2c_sda_pz7,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x32b8,  Y,  N,  N),
1877        PINGROUP(kb_row0_pr0,            KBC,        RSVD2,      RSVD3,        RSVD4,       RSVD4,      0x32bc,  N,  N,  N),
1878        PINGROUP(kb_row1_pr1,            KBC,        RSVD2,      RSVD3,        RSVD4,       RSVD4,      0x32c0,  N,  N,  N),
1879        PINGROUP(kb_row2_pr2,            KBC,        RSVD2,      RSVD3,        RSVD4,       RSVD4,      0x32c4,  N,  N,  N),
1880        PINGROUP(kb_row3_pr3,            KBC,        DISPLAYA,   SYS,          DISPLAYB,    KBC,        0x32c8,  N,  N,  N),
1881        PINGROUP(kb_row4_pr4,            KBC,        DISPLAYA,   RSVD3,        DISPLAYB,    RSVD3,      0x32cc,  N,  N,  N),
1882        PINGROUP(kb_row5_pr5,            KBC,        DISPLAYA,   RSVD3,        DISPLAYB,    RSVD3,      0x32d0,  N,  N,  N),
1883        PINGROUP(kb_row6_pr6,            KBC,        DISPLAYA,   DISPLAYA_ALT, DISPLAYB,    KBC,        0x32d4,  N,  N,  N),
1884        PINGROUP(kb_row7_pr7,            KBC,        RSVD2,      CLDVFS,       UARTA,       RSVD2,      0x32d8,  N,  N,  N),
1885        PINGROUP(kb_row8_ps0,            KBC,        RSVD2,      CLDVFS,       UARTA,       RSVD2,      0x32dc,  N,  N,  N),
1886        PINGROUP(kb_row9_ps1,            KBC,        RSVD2,      RSVD3,        UARTA,       KBC,        0x32e0,  N,  N,  N),
1887        PINGROUP(kb_row10_ps2,           KBC,        RSVD2,      RSVD3,        UARTA,       KBC,        0x32e4,  N,  N,  N),
1888        PINGROUP(kb_row11_ps3,           KBC,        RSVD2,      RSVD3,        IRDA,        RSVD3,      0x32e8,  N,  N,  N),
1889        PINGROUP(kb_row12_ps4,           KBC,        RSVD2,      RSVD3,        IRDA,        RSVD3,      0x32ec,  N,  N,  N),
1890        PINGROUP(kb_row13_ps5,           KBC,        RSVD2,      SPI2,         RSVD4,       RSVD4,      0x32f0,  N,  N,  N),
1891        PINGROUP(kb_row14_ps6,           KBC,        RSVD2,      SPI2,         RSVD4,       RSVD4,      0x32f4,  N,  N,  N),
1892        PINGROUP(kb_row15_ps7,           KBC,        SOC,        RSVD3,        RSVD4,       KBC,        0x32f8,  N,  N,  N),
1893        PINGROUP(kb_col0_pq0,            KBC,        RSVD2,      SPI2,         RSVD4,       RSVD4,      0x32fc,  N,  N,  N),
1894        PINGROUP(kb_col1_pq1,            KBC,        RSVD2,      SPI2,         RSVD4,       RSVD4,      0x3300,  N,  N,  N),
1895        PINGROUP(kb_col2_pq2,            KBC,        RSVD2,      SPI2,         RSVD4,       RSVD4,      0x3304,  N,  N,  N),
1896        PINGROUP(kb_col3_pq3,            KBC,        DISPLAYA,   PWM2,         UARTA,       KBC,        0x3308,  N,  N,  N),
1897        PINGROUP(kb_col4_pq4,            KBC,        OWR,        SDMMC3,       UARTA,       KBC,        0x330c,  N,  N,  N),
1898        PINGROUP(kb_col5_pq5,            KBC,        RSVD2,      SDMMC3,       RSVD4,       RSVD4,      0x3310,  N,  N,  N),
1899        PINGROUP(kb_col6_pq6,            KBC,        RSVD2,      SPI2,         UARTD,       RSVD2,      0x3314,  N,  N,  N),
1900        PINGROUP(kb_col7_pq7,            KBC,        RSVD2,      SPI2,         UARTD,       RSVD2,      0x3318,  N,  N,  N),
1901        PINGROUP(clk_32k_out_pa0,        BLINK,      SOC,        RSVD3,        RSVD4,       RSVD3,      0x331c,  N,  N,  N),
1902        PINGROUP(core_pwr_req,           PWRON,      RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x3324,  N,  N,  N),
1903        PINGROUP(cpu_pwr_req,            CPU,        RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x3328,  N,  N,  N),
1904        PINGROUP(pwr_int_n,              PMI,        RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x332c,  N,  N,  N),
1905        PINGROUP(clk_32k_in,             CLK,        RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x3330,  N,  N,  N),
1906        PINGROUP(owr,                    OWR,        RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x3334,  N,  N,  Y),
1907        PINGROUP(dap1_fs_pn0,            I2S0,       HDA,        GMI,          RSVD4,       RSVD4,      0x3338,  N,  N,  N),
1908        PINGROUP(dap1_din_pn1,           I2S0,       HDA,        GMI,          RSVD4,       RSVD4,      0x333c,  N,  N,  N),
1909        PINGROUP(dap1_dout_pn2,          I2S0,       HDA,        GMI,          SATA,        I2S0,       0x3340,  N,  N,  N),
1910        PINGROUP(dap1_sclk_pn3,          I2S0,       HDA,        GMI,          RSVD4,       I2S0,       0x3344,  N,  N,  N),
1911        PINGROUP(dap_mclk1_req_pee2,     DAP,        DAP1,       SATA,         RSVD4,       DAP,        0x3348,  N,  N,  N),
1912        PINGROUP(dap_mclk1_pw4,          EXTPERIPH1, DAP2,       RSVD3,        RSVD4,       RSVD3,      0x334c,  N,  N,  N),
1913        PINGROUP(spdif_in_pk6,           SPDIF,      RSVD2,      RSVD3,        I2C3,        RSVD3,      0x3350,  N,  N,  N),
1914        PINGROUP(spdif_out_pk5,          SPDIF,      RSVD2,      RSVD3,        I2C3,        RSVD3,      0x3354,  N,  N,  N),
1915        PINGROUP(dap2_fs_pa2,            I2S1,       HDA,        GMI,          RSVD4,       I2S1,       0x3358,  N,  N,  N),
1916        PINGROUP(dap2_din_pa4,           I2S1,       HDA,        GMI,          RSVD4,       I2S1,       0x335c,  N,  N,  N),
1917        PINGROUP(dap2_dout_pa5,          I2S1,       HDA,        GMI,          RSVD4,       I2S1,       0x3360,  N,  N,  N),
1918        PINGROUP(dap2_sclk_pa3,          I2S1,       HDA,        GMI,          RSVD4,       I2S1,       0x3364,  N,  N,  N),
1919        PINGROUP(dvfs_pwm_px0,           SPI6,       CLDVFS,     GMI,          RSVD4,       SPI6,       0x3368,  N,  N,  N),
1920        PINGROUP(gpio_x1_aud_px1,        SPI6,       RSVD2,      GMI,          RSVD4,       SPI6,       0x336c,  N,  N,  N),
1921        PINGROUP(gpio_x3_aud_px3,        SPI6,       SPI1,       GMI,          RSVD4,       SPI6,       0x3370,  N,  N,  N),
1922        PINGROUP(dvfs_clk_px2,           SPI6,       CLDVFS,     GMI,          RSVD4,       SPI6,       0x3374,  N,  N,  N),
1923        PINGROUP(gpio_x4_aud_px4,        GMI,        SPI1,       SPI2,         DAP2,        SPI1,       0x3378,  N,  N,  N),
1924        PINGROUP(gpio_x5_aud_px5,        GMI,        SPI1,       SPI2,         RSVD4,       SPI1,       0x337c,  N,  N,  N),
1925        PINGROUP(gpio_x6_aud_px6,        SPI6,       SPI1,       SPI2,         GMI,         SPI1,       0x3380,  N,  N,  N),
1926        PINGROUP(gpio_x7_aud_px7,        RSVD1,      SPI1,       SPI2,         RSVD4,       SPI1,       0x3384,  N,  N,  N),
1927        PINGROUP(sdmmc3_clk_pa6,         SDMMC3,     RSVD2,      RSVD3,        SPI3,        SDMMC3,     0x3390,  N,  N,  N),
1928        PINGROUP(sdmmc3_cmd_pa7,         SDMMC3,     PWM3,       UARTA,        SPI3,        SDMMC3,     0x3394,  N,  N,  N),
1929        PINGROUP(sdmmc3_dat0_pb7,        SDMMC3,     RSVD2,      RSVD3,        SPI3,        SDMMC3,     0x3398,  N,  N,  N),
1930        PINGROUP(sdmmc3_dat1_pb6,        SDMMC3,     PWM2,       UARTA,        SPI3,        SDMMC3,     0x339c,  N,  N,  N),
1931        PINGROUP(sdmmc3_dat2_pb5,        SDMMC3,     PWM1,       DISPLAYA,     SPI3,        SDMMC3,     0x33a0,  N,  N,  N),
1932        PINGROUP(sdmmc3_dat3_pb4,        SDMMC3,     PWM0,       DISPLAYB,     SPI3,        SDMMC3,     0x33a4,  N,  N,  N),
1933        PINGROUP(pex_l0_rst_n_pdd1,      PE0,        RSVD2,      RSVD3,        RSVD4,       PE0,        0x33bc,  N,  N,  N),
1934        PINGROUP(pex_l0_clkreq_n_pdd2,   PE0,        RSVD2,      RSVD3,        RSVD4,       PE0,        0x33c0,  N,  N,  N),
1935        PINGROUP(pex_wake_n_pdd3,        PE,         RSVD2,      RSVD3,        RSVD4,       PE,         0x33c4,  N,  N,  N),
1936        PINGROUP(pex_l1_rst_n_pdd5,      PE1,        RSVD2,      RSVD3,        RSVD4,       PE1,        0x33cc,  N,  N,  N),
1937        PINGROUP(pex_l1_clkreq_n_pdd6,   PE1,        RSVD2,      RSVD3,        RSVD4,       PE1,        0x33d0,  N,  N,  N),
1938        PINGROUP(hdmi_cec_pee3,          CEC,        RSVD2,      RSVD3,        RSVD4,       CEC,        0x33e0,  Y,  N,  N),
1939        PINGROUP(sdmmc1_wp_n_pv3,        SDMMC1,     CLK12,      SPI4,         UARTA,       SDMMC1,     0x33e4,  N,  N,  N),
1940        PINGROUP(sdmmc3_cd_n_pv2,        SDMMC3,     OWR,        RSVD3,        RSVD4,       SDMMC3,     0x33e8,  N,  N,  N),
1941        PINGROUP(gpio_w2_aud_pw2,        SPI6,       RSVD2,      SPI2,         I2C1,        RSVD2,      0x33ec,  N,  N,  N),
1942        PINGROUP(gpio_w3_aud_pw3,        SPI6,       SPI1,       SPI2,         I2C1,        SPI1,       0x33f0,  N,  N,  N),
1943        PINGROUP(usb_vbus_en0_pn4,       USB,        RSVD2,      RSVD3,        RSVD4,       USB,        0x33f4,  Y,  N,  N),
1944        PINGROUP(usb_vbus_en1_pn5,       USB,        RSVD2,      RSVD3,        RSVD4,       USB,        0x33f8,  Y,  N,  N),
1945        PINGROUP(sdmmc3_clk_lb_in_pee5,  SDMMC3,     RSVD2,      RSVD3,        RSVD4,       SDMMC3,     0x33fc,  N,  N,  N),
1946        PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3,     RSVD2,      RSVD3,        RSVD4,       SDMMC3,     0x3400,  N,  N,  N),
1947        PINGROUP(gmi_clk_lb,             SDMMC2,     RSVD2,      GMI,          RSVD4,       SDMMC2,     0x3404,  N,  N,  N),
1948        PINGROUP(reset_out_n,            RSVD1,      RSVD2,      RSVD3,        RESET_OUT_N, RSVD1,      0x3408,  N,  N,  N),
1949        PINGROUP(kb_row16_pt0,           KBC,        RSVD2,      RSVD3,        UARTC,       KBC,        0x340c,  N,  N,  N),
1950        PINGROUP(kb_row17_pt1,           KBC,        RSVD2,      RSVD3,        UARTC,       KBC,        0x3410,  N,  N,  N),
1951        PINGROUP(usb_vbus_en2_pff1,      USB,        RSVD2,      RSVD3,        RSVD4,       USB,        0x3414,  Y,  N,  N),
1952        PINGROUP(pff2,                   SATA,       RSVD2,      RSVD3,        RSVD4,       RSVD2,      0x3418,  Y,  N,  N),
1953        PINGROUP(dp_hpd_pff0,            DP,         RSVD2,      RSVD3,        RSVD4,       DP,         0x3430,  N,  N,  N),
1954
1955         /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
1956        DRV_PINGROUP(ao1,         0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1957        DRV_PINGROUP(ao2,         0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1958        DRV_PINGROUP(at1,         0x870,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1959        DRV_PINGROUP(at2,         0x874,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1960        DRV_PINGROUP(at3,         0x878,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1961        DRV_PINGROUP(at4,         0x87c,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1962        DRV_PINGROUP(at5,         0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1963        DRV_PINGROUP(cdev1,       0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1964        DRV_PINGROUP(cdev2,       0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1965        DRV_PINGROUP(dap1,        0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1966        DRV_PINGROUP(dap2,        0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1967        DRV_PINGROUP(dap3,        0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1968        DRV_PINGROUP(dap4,        0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1969        DRV_PINGROUP(dbg,         0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1970        DRV_PINGROUP(sdio3,       0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
1971        DRV_PINGROUP(spi,         0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1972        DRV_PINGROUP(uaa,         0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1973        DRV_PINGROUP(uab,         0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1974        DRV_PINGROUP(uart2,       0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1975        DRV_PINGROUP(uart3,       0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1976        DRV_PINGROUP(sdio1,       0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
1977        DRV_PINGROUP(ddc,         0x8fc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1978        DRV_PINGROUP(gma,         0x900,  2,  3,  4,  14,  5,  20,  5,  28,  2,  30,  2,  Y),
1979        DRV_PINGROUP(gme,         0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1980        DRV_PINGROUP(gmf,         0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1981        DRV_PINGROUP(gmg,         0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1982        DRV_PINGROUP(gmh,         0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1983        DRV_PINGROUP(owr,         0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1984        DRV_PINGROUP(uda,         0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1985        DRV_PINGROUP(gpv,         0x928,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1986        DRV_PINGROUP(dev3,        0x92c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1987        DRV_PINGROUP(cec,         0x938,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1988        DRV_PINGROUP(at6,         0x994,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1989        DRV_PINGROUP(dap5,        0x998,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1990        DRV_PINGROUP(usb_vbus_en, 0x99c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1991        DRV_PINGROUP(ao3,         0x9a8,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
1992        DRV_PINGROUP(ao0,         0x9b0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1993        DRV_PINGROUP(hv0,         0x9b4,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
1994        DRV_PINGROUP(sdio4,       0x9c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1995        DRV_PINGROUP(ao4,         0x9c8,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1996 };
1997
1998 static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
1999         .ngpios = NUM_GPIOS,
2000         .pins = tegra124_pins,
2001         .npins = ARRAY_SIZE(tegra124_pins),
2002         .functions = tegra124_functions,
2003         .nfunctions = ARRAY_SIZE(tegra124_functions),
2004         .groups = tegra124_groups,
2005         .ngroups = ARRAY_SIZE(tegra124_groups),
2006 };
2007
2008 static int tegra124_pinctrl_probe(struct platform_device *pdev)
2009 {
2010         return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
2011 }
2012
2013 static struct of_device_id tegra124_pinctrl_of_match[] = {
2014         { .compatible = "nvidia,tegra124-pinmux", },
2015         { },
2016 };
2017 MODULE_DEVICE_TABLE(of, tegra124_pinctrl_of_match);
2018
2019 static struct platform_driver tegra124_pinctrl_driver = {
2020         .driver = {
2021                 .name = "tegra124-pinctrl",
2022                 .owner = THIS_MODULE,
2023                 .of_match_table = tegra124_pinctrl_of_match,
2024         },
2025         .probe = tegra124_pinctrl_probe,
2026         .remove = tegra_pinctrl_remove,
2027 };
2028 module_platform_driver(tegra124_pinctrl_driver);
2029
2030 MODULE_AUTHOR("Ashwini Ghuge <aghuge@nvidia.com>");
2031 MODULE_DESCRIPTION("NVIDIA Tegra124 pinctrl driver");
2032 MODULE_LICENSE("GPL v2");