1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
6 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
8 * Driver for Semtech SX150X I2C GPIO Expanders
9 * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
11 * Author: Gregory Bean <gbean@codeaurora.org>
14 #include <linux/regmap.h>
15 #include <linux/i2c.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/mutex.h>
20 #include <linux/slab.h>
22 #include <linux/of_device.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 #include <linux/pinctrl/pinconf-generic.h>
31 #include "pinctrl-utils.h"
33 /* The chip models of sx150x */
40 SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
41 SX150X_MAX_REGISTER = 0xad,
42 SX150X_IRQ_TYPE_EDGE_RISING = 0x1,
43 SX150X_IRQ_TYPE_EDGE_FALLING = 0x2,
44 SX150X_789_RESET_KEY1 = 0x12,
45 SX150X_789_RESET_KEY2 = 0x34,
48 struct sx150x_123_pri {
58 struct sx150x_456_pri {
68 struct sx150x_789_pri {
77 struct sx150x_device_data {
88 struct sx150x_123_pri x123;
89 struct sx150x_456_pri x456;
90 struct sx150x_789_pri x789;
92 const struct pinctrl_pin_desc *pins;
96 struct sx150x_pinctrl {
98 struct i2c_client *client;
99 struct pinctrl_dev *pctldev;
100 struct pinctrl_desc pinctrl_desc;
101 struct gpio_chip gpio;
102 struct irq_chip irq_chip;
103 struct regmap *regmap;
109 const struct sx150x_device_data *data;
112 static const struct pinctrl_pin_desc sx150x_4_pins[] = {
113 PINCTRL_PIN(0, "gpio0"),
114 PINCTRL_PIN(1, "gpio1"),
115 PINCTRL_PIN(2, "gpio2"),
116 PINCTRL_PIN(3, "gpio3"),
117 PINCTRL_PIN(4, "oscio"),
120 static const struct pinctrl_pin_desc sx150x_8_pins[] = {
121 PINCTRL_PIN(0, "gpio0"),
122 PINCTRL_PIN(1, "gpio1"),
123 PINCTRL_PIN(2, "gpio2"),
124 PINCTRL_PIN(3, "gpio3"),
125 PINCTRL_PIN(4, "gpio4"),
126 PINCTRL_PIN(5, "gpio5"),
127 PINCTRL_PIN(6, "gpio6"),
128 PINCTRL_PIN(7, "gpio7"),
129 PINCTRL_PIN(8, "oscio"),
132 static const struct pinctrl_pin_desc sx150x_16_pins[] = {
133 PINCTRL_PIN(0, "gpio0"),
134 PINCTRL_PIN(1, "gpio1"),
135 PINCTRL_PIN(2, "gpio2"),
136 PINCTRL_PIN(3, "gpio3"),
137 PINCTRL_PIN(4, "gpio4"),
138 PINCTRL_PIN(5, "gpio5"),
139 PINCTRL_PIN(6, "gpio6"),
140 PINCTRL_PIN(7, "gpio7"),
141 PINCTRL_PIN(8, "gpio8"),
142 PINCTRL_PIN(9, "gpio9"),
143 PINCTRL_PIN(10, "gpio10"),
144 PINCTRL_PIN(11, "gpio11"),
145 PINCTRL_PIN(12, "gpio12"),
146 PINCTRL_PIN(13, "gpio13"),
147 PINCTRL_PIN(14, "gpio14"),
148 PINCTRL_PIN(15, "gpio15"),
149 PINCTRL_PIN(16, "oscio"),
152 static const struct sx150x_device_data sx1501q_device_data = {
158 .reg_irq_mask = 0x05,
162 .reg_pld_mode = 0x10,
163 .reg_pld_table0 = 0x11,
164 .reg_pld_table2 = 0x13,
165 .reg_advanced = 0xad,
168 .pins = sx150x_4_pins,
169 .npins = 4, /* oscio not available */
172 static const struct sx150x_device_data sx1502q_device_data = {
178 .reg_irq_mask = 0x05,
182 .reg_pld_mode = 0x10,
183 .reg_pld_table0 = 0x11,
184 .reg_pld_table1 = 0x12,
185 .reg_pld_table2 = 0x13,
186 .reg_pld_table3 = 0x14,
187 .reg_pld_table4 = 0x15,
188 .reg_advanced = 0xad,
191 .pins = sx150x_8_pins,
192 .npins = 8, /* oscio not available */
195 static const struct sx150x_device_data sx1503q_device_data = {
201 .reg_irq_mask = 0x08,
205 .reg_pld_mode = 0x20,
206 .reg_pld_table0 = 0x22,
207 .reg_pld_table1 = 0x24,
208 .reg_pld_table2 = 0x26,
209 .reg_pld_table3 = 0x28,
210 .reg_pld_table4 = 0x2a,
211 .reg_advanced = 0xad,
214 .pins = sx150x_16_pins,
215 .npins = 16, /* oscio not available */
218 static const struct sx150x_device_data sx1504q_device_data = {
224 .reg_irq_mask = 0x05,
228 .reg_pld_mode = 0x10,
229 .reg_pld_table0 = 0x11,
230 .reg_pld_table2 = 0x13,
233 .pins = sx150x_4_pins,
234 .npins = 4, /* oscio not available */
237 static const struct sx150x_device_data sx1505q_device_data = {
243 .reg_irq_mask = 0x05,
247 .reg_pld_mode = 0x10,
248 .reg_pld_table0 = 0x11,
249 .reg_pld_table1 = 0x12,
250 .reg_pld_table2 = 0x13,
251 .reg_pld_table3 = 0x14,
252 .reg_pld_table4 = 0x15,
255 .pins = sx150x_8_pins,
256 .npins = 8, /* oscio not available */
259 static const struct sx150x_device_data sx1506q_device_data = {
265 .reg_irq_mask = 0x08,
269 .reg_pld_mode = 0x20,
270 .reg_pld_table0 = 0x22,
271 .reg_pld_table1 = 0x24,
272 .reg_pld_table2 = 0x26,
273 .reg_pld_table3 = 0x28,
274 .reg_pld_table4 = 0x2a,
275 .reg_advanced = 0xad,
278 .pins = sx150x_16_pins,
279 .npins = 16, /* oscio not available */
282 static const struct sx150x_device_data sx1507q_device_data = {
288 .reg_irq_mask = 0x09,
293 .reg_polarity = 0x06,
299 .pins = sx150x_4_pins,
300 .npins = ARRAY_SIZE(sx150x_4_pins),
303 static const struct sx150x_device_data sx1508q_device_data = {
309 .reg_irq_mask = 0x09,
314 .reg_polarity = 0x06,
320 .pins = sx150x_8_pins,
321 .npins = ARRAY_SIZE(sx150x_8_pins),
324 static const struct sx150x_device_data sx1509q_device_data = {
330 .reg_irq_mask = 0x12,
335 .reg_polarity = 0x0c,
341 .pins = sx150x_16_pins,
342 .npins = ARRAY_SIZE(sx150x_16_pins),
345 static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
350 static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
356 static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
358 const unsigned int **pins,
359 unsigned int *num_pins)
364 static const struct pinctrl_ops sx150x_pinctrl_ops = {
365 .get_groups_count = sx150x_pinctrl_get_groups_count,
366 .get_group_name = sx150x_pinctrl_get_group_name,
367 .get_group_pins = sx150x_pinctrl_get_group_pins,
369 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
370 .dt_free_map = pinctrl_utils_free_map,
374 static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
376 if (pin >= pctl->data->npins)
379 /* OSCIO pin is only present in 789 devices */
380 if (pctl->data->model != SX150X_789)
383 return !strcmp(pctl->data->pins[pin].name, "oscio");
386 static int sx150x_gpio_get_direction(struct gpio_chip *chip,
389 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
393 if (sx150x_pin_is_oscio(pctl, offset))
394 return GPIO_LINE_DIRECTION_OUT;
396 ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
400 if (value & BIT(offset))
401 return GPIO_LINE_DIRECTION_IN;
403 return GPIO_LINE_DIRECTION_OUT;
406 static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
408 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
412 if (sx150x_pin_is_oscio(pctl, offset))
415 ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
419 return !!(value & BIT(offset));
422 static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
425 return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
426 BIT(offset), value ? BIT(offset) : 0);
429 static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
432 return regmap_write(pctl->regmap,
433 pctl->data->pri.x789.reg_clock,
434 (value ? 0x1f : 0x10));
437 static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
440 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
442 if (sx150x_pin_is_oscio(pctl, offset))
443 sx150x_gpio_oscio_set(pctl, value);
445 __sx150x_gpio_set(pctl, offset, value);
448 static void sx150x_gpio_set_multiple(struct gpio_chip *chip,
452 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
454 regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits);
457 static int sx150x_gpio_direction_input(struct gpio_chip *chip,
460 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
462 if (sx150x_pin_is_oscio(pctl, offset))
465 return regmap_write_bits(pctl->regmap,
467 BIT(offset), BIT(offset));
470 static int sx150x_gpio_direction_output(struct gpio_chip *chip,
471 unsigned int offset, int value)
473 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
476 if (sx150x_pin_is_oscio(pctl, offset))
477 return sx150x_gpio_oscio_set(pctl, value);
479 ret = __sx150x_gpio_set(pctl, offset, value);
483 return regmap_write_bits(pctl->regmap,
488 static void sx150x_irq_mask(struct irq_data *d)
490 struct sx150x_pinctrl *pctl =
491 gpiochip_get_data(irq_data_get_irq_chip_data(d));
492 unsigned int n = d->hwirq;
494 pctl->irq.masked |= BIT(n);
497 static void sx150x_irq_unmask(struct irq_data *d)
499 struct sx150x_pinctrl *pctl =
500 gpiochip_get_data(irq_data_get_irq_chip_data(d));
501 unsigned int n = d->hwirq;
503 pctl->irq.masked &= ~BIT(n);
506 static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl,
507 unsigned int line, unsigned int sense)
510 * Every interrupt line is represented by two bits shifted
511 * proportionally to the line number
513 const unsigned int n = line * 2;
514 const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING |
515 SX150X_IRQ_TYPE_EDGE_FALLING) << n);
517 pctl->irq.sense &= mask;
518 pctl->irq.sense |= sense << n;
521 static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
523 struct sx150x_pinctrl *pctl =
524 gpiochip_get_data(irq_data_get_irq_chip_data(d));
525 unsigned int n, val = 0;
527 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
532 if (flow_type & IRQ_TYPE_EDGE_RISING)
533 val |= SX150X_IRQ_TYPE_EDGE_RISING;
534 if (flow_type & IRQ_TYPE_EDGE_FALLING)
535 val |= SX150X_IRQ_TYPE_EDGE_FALLING;
537 sx150x_irq_set_sense(pctl, n, val);
541 static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
543 struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
544 unsigned long n, status;
548 err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
552 err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
557 for_each_set_bit(n, &status, pctl->data->ngpios)
558 handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n));
563 static void sx150x_irq_bus_lock(struct irq_data *d)
565 struct sx150x_pinctrl *pctl =
566 gpiochip_get_data(irq_data_get_irq_chip_data(d));
568 mutex_lock(&pctl->lock);
571 static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
573 struct sx150x_pinctrl *pctl =
574 gpiochip_get_data(irq_data_get_irq_chip_data(d));
576 regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
577 regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
578 mutex_unlock(&pctl->lock);
581 static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
582 unsigned long *config)
584 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
585 unsigned int param = pinconf_to_config_param(*config);
590 if (sx150x_pin_is_oscio(pctl, pin)) {
592 case PIN_CONFIG_DRIVE_PUSH_PULL:
593 case PIN_CONFIG_OUTPUT:
594 ret = regmap_read(pctl->regmap,
595 pctl->data->pri.x789.reg_clock,
600 if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
601 arg = (data & 0x1f) ? 1 : 0;
603 if ((data & 0x1f) == 0x1f)
605 else if ((data & 0x1f) == 0x10)
620 case PIN_CONFIG_BIAS_PULL_DOWN:
621 ret = regmap_read(pctl->regmap,
622 pctl->data->reg_pulldn,
635 case PIN_CONFIG_BIAS_PULL_UP:
636 ret = regmap_read(pctl->regmap,
637 pctl->data->reg_pullup,
650 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
651 if (pctl->data->model != SX150X_789)
654 ret = regmap_read(pctl->regmap,
655 pctl->data->pri.x789.reg_drain,
668 case PIN_CONFIG_DRIVE_PUSH_PULL:
669 if (pctl->data->model != SX150X_789)
672 ret = regmap_read(pctl->regmap,
673 pctl->data->pri.x789.reg_drain,
687 case PIN_CONFIG_OUTPUT:
688 ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
692 if (ret == GPIO_LINE_DIRECTION_IN)
695 ret = sx150x_gpio_get(&pctl->gpio, pin);
707 *config = pinconf_to_config_packed(param, arg);
712 static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
713 unsigned long *configs, unsigned int num_configs)
715 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
716 enum pin_config_param param;
721 for (i = 0; i < num_configs; i++) {
722 param = pinconf_to_config_param(configs[i]);
723 arg = pinconf_to_config_argument(configs[i]);
725 if (sx150x_pin_is_oscio(pctl, pin)) {
726 if (param == PIN_CONFIG_OUTPUT) {
727 ret = sx150x_gpio_direction_output(&pctl->gpio,
738 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
739 case PIN_CONFIG_BIAS_DISABLE:
740 ret = regmap_write_bits(pctl->regmap,
741 pctl->data->reg_pulldn,
746 ret = regmap_write_bits(pctl->regmap,
747 pctl->data->reg_pullup,
754 case PIN_CONFIG_BIAS_PULL_UP:
755 ret = regmap_write_bits(pctl->regmap,
756 pctl->data->reg_pullup,
763 case PIN_CONFIG_BIAS_PULL_DOWN:
764 ret = regmap_write_bits(pctl->regmap,
765 pctl->data->reg_pulldn,
772 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
773 if (pctl->data->model != SX150X_789 ||
774 sx150x_pin_is_oscio(pctl, pin))
777 ret = regmap_write_bits(pctl->regmap,
778 pctl->data->pri.x789.reg_drain,
785 case PIN_CONFIG_DRIVE_PUSH_PULL:
786 if (pctl->data->model != SX150X_789 ||
787 sx150x_pin_is_oscio(pctl, pin))
790 ret = regmap_write_bits(pctl->regmap,
791 pctl->data->pri.x789.reg_drain,
798 case PIN_CONFIG_OUTPUT:
799 ret = sx150x_gpio_direction_output(&pctl->gpio,
809 } /* for each config */
814 static const struct pinconf_ops sx150x_pinconf_ops = {
815 .pin_config_get = sx150x_pinconf_get,
816 .pin_config_set = sx150x_pinconf_set,
820 static const struct i2c_device_id sx150x_id[] = {
821 {"sx1501q", (kernel_ulong_t) &sx1501q_device_data },
822 {"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
823 {"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
824 {"sx1504q", (kernel_ulong_t) &sx1504q_device_data },
825 {"sx1505q", (kernel_ulong_t) &sx1505q_device_data },
826 {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
827 {"sx1507q", (kernel_ulong_t) &sx1507q_device_data },
828 {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
829 {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
833 static const struct of_device_id sx150x_of_match[] = {
834 { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data },
835 { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
836 { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
837 { .compatible = "semtech,sx1504q", .data = &sx1504q_device_data },
838 { .compatible = "semtech,sx1505q", .data = &sx1505q_device_data },
839 { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
840 { .compatible = "semtech,sx1507q", .data = &sx1507q_device_data },
841 { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
842 { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
846 static int sx150x_reset(struct sx150x_pinctrl *pctl)
850 err = i2c_smbus_write_byte_data(pctl->client,
851 pctl->data->pri.x789.reg_reset,
852 SX150X_789_RESET_KEY1);
856 err = i2c_smbus_write_byte_data(pctl->client,
857 pctl->data->pri.x789.reg_reset,
858 SX150X_789_RESET_KEY2);
862 static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
866 switch (pctl->data->model) {
868 reg = pctl->data->pri.x789.reg_misc;
869 value = SX150X_789_REG_MISC_AUTOCLEAR_OFF;
872 reg = pctl->data->pri.x456.reg_advanced;
876 * Only SX1506 has RegAdvanced, SX1504/5 are expected
877 * to initialize this offset to zero
883 reg = pctl->data->pri.x123.reg_advanced;
887 WARN(1, "Unknown chip model %d\n", pctl->data->model);
891 return regmap_write(pctl->regmap, reg, value);
894 static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
897 [SX150X_789] = pctl->data->pri.x789.reg_polarity,
898 [SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
899 [SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
903 if (pctl->data->model == SX150X_789 &&
904 of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
905 err = sx150x_reset(pctl);
910 err = sx150x_init_misc(pctl);
914 /* Set all pins to work in normal mode */
915 return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
918 static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
921 const struct sx150x_device_data *data = pctl->data;
923 if (reg == data->reg_sense) {
925 * RegSense packs two bits of configuration per GPIO,
926 * so we'd need to read twice as many bits as there
927 * are GPIO in our chip
929 return 2 * data->ngpios;
930 } else if ((data->model == SX150X_789 &&
931 (reg == data->pri.x789.reg_misc ||
932 reg == data->pri.x789.reg_clock ||
933 reg == data->pri.x789.reg_reset))
935 (data->model == SX150X_123 &&
936 reg == data->pri.x123.reg_advanced)
938 (data->model == SX150X_456 &&
939 data->pri.x456.reg_advanced &&
940 reg == data->pri.x456.reg_advanced)) {
947 static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
948 unsigned int reg, unsigned int val)
951 const struct sx150x_device_data *data = pctl->data;
954 * Whereas SX1509 presents RegSense in a simple layout as such:
955 * reg [ f f e e d d c c ]
956 * reg + 1 [ b b a a 9 9 8 8 ]
957 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
958 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
960 * SX1503 and SX1506 deviate from that data layout, instead storing
961 * their contents as follows:
963 * reg [ f f e e d d c c ]
964 * reg + 1 [ 7 7 6 6 5 5 4 4 ]
965 * reg + 2 [ b b a a 9 9 8 8 ]
966 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
968 * so, taking that into account, we swap two
969 * inner bytes of a 4-byte result
972 if (reg == data->reg_sense &&
973 data->ngpios == 16 &&
974 (data->model == SX150X_123 ||
975 data->model == SX150X_456)) {
976 a = val & 0x00ff0000;
977 b = val & 0x0000ff00;
988 * In order to mask the differences between 16 and 8 bit expander
989 * devices we set up a sligthly ficticious regmap that pretends to be
990 * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh
991 * pair/quartet) registers and transparently reconstructs those
992 * registers via multiple I2C/SMBus reads
994 * This way the rest of the driver code, interfacing with the chip via
995 * regmap API, can work assuming that each GPIO pin is represented by
996 * a group of bits at an offset proportional to GPIO number within a
999 static int sx150x_regmap_reg_read(void *context, unsigned int reg,
1000 unsigned int *result)
1003 struct sx150x_pinctrl *pctl = context;
1004 struct i2c_client *i2c = pctl->client;
1005 const int width = sx150x_regmap_reg_width(pctl, reg);
1006 unsigned int idx, val;
1009 * There are four potential cases covered by this function:
1011 * 1) 8-pin chip, single configuration bit register
1013 * This is trivial the code below just needs to read:
1014 * reg [ 7 6 5 4 3 2 1 0 ]
1016 * 2) 8-pin chip, double configuration bit register (RegSense)
1018 * The read will be done as follows:
1019 * reg [ 7 7 6 6 5 5 4 4 ]
1020 * reg + 1 [ 3 3 2 2 1 1 0 0 ]
1022 * 3) 16-pin chip, single configuration bit register
1024 * The read will be done as follows:
1025 * reg [ f e d c b a 9 8 ]
1026 * reg + 1 [ 7 6 5 4 3 2 1 0 ]
1028 * 4) 16-pin chip, double configuration bit register (RegSense)
1030 * The read will be done as follows:
1031 * reg [ f f e e d d c c ]
1032 * reg + 1 [ b b a a 9 9 8 8 ]
1033 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
1034 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
1037 for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
1040 ret = i2c_smbus_read_byte_data(i2c, idx);
1047 *result = sx150x_maybe_swizzle(pctl, reg, val);
1052 static int sx150x_regmap_reg_write(void *context, unsigned int reg,
1056 struct sx150x_pinctrl *pctl = context;
1057 struct i2c_client *i2c = pctl->client;
1058 const int width = sx150x_regmap_reg_width(pctl, reg);
1060 val = sx150x_maybe_swizzle(pctl, reg, val);
1062 n = (width - 1) & ~7;
1064 const u8 byte = (val >> n) & 0xff;
1066 ret = i2c_smbus_write_byte_data(i2c, reg, byte);
1077 static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
1079 struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
1081 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
1084 static const struct regmap_config sx150x_regmap_config = {
1088 .cache_type = REGCACHE_RBTREE,
1090 .reg_read = sx150x_regmap_reg_read,
1091 .reg_write = sx150x_regmap_reg_write,
1093 .max_register = SX150X_MAX_REGISTER,
1094 .volatile_reg = sx150x_reg_volatile,
1097 static int sx150x_probe(struct i2c_client *client,
1098 const struct i2c_device_id *id)
1100 static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
1101 I2C_FUNC_SMBUS_WRITE_WORD_DATA;
1102 struct device *dev = &client->dev;
1103 struct sx150x_pinctrl *pctl;
1106 if (!i2c_check_functionality(client->adapter, i2c_funcs))
1109 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1113 i2c_set_clientdata(client, pctl);
1116 pctl->client = client;
1119 pctl->data = of_device_get_match_data(dev);
1121 pctl->data = (struct sx150x_device_data *)id->driver_data;
1126 pctl->regmap = devm_regmap_init(dev, NULL, pctl,
1127 &sx150x_regmap_config);
1128 if (IS_ERR(pctl->regmap)) {
1129 ret = PTR_ERR(pctl->regmap);
1130 dev_err(dev, "Failed to allocate register map: %d\n",
1135 mutex_init(&pctl->lock);
1137 ret = sx150x_init_hw(pctl);
1142 pctl->pinctrl_desc.name = "sx150x-pinctrl";
1143 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
1144 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
1145 pctl->pinctrl_desc.pins = pctl->data->pins;
1146 pctl->pinctrl_desc.npins = pctl->data->npins;
1147 pctl->pinctrl_desc.owner = THIS_MODULE;
1149 ret = devm_pinctrl_register_and_init(dev, &pctl->pinctrl_desc,
1150 pctl, &pctl->pctldev);
1152 dev_err(dev, "Failed to register pinctrl device\n");
1156 /* Register GPIO controller */
1157 pctl->gpio.base = -1;
1158 pctl->gpio.ngpio = pctl->data->npins;
1159 pctl->gpio.get_direction = sx150x_gpio_get_direction;
1160 pctl->gpio.direction_input = sx150x_gpio_direction_input;
1161 pctl->gpio.direction_output = sx150x_gpio_direction_output;
1162 pctl->gpio.get = sx150x_gpio_get;
1163 pctl->gpio.set = sx150x_gpio_set;
1164 pctl->gpio.set_config = gpiochip_generic_config;
1165 pctl->gpio.parent = dev;
1166 #ifdef CONFIG_OF_GPIO
1167 pctl->gpio.of_node = dev->of_node;
1169 pctl->gpio.can_sleep = true;
1170 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
1171 if (!pctl->gpio.label)
1175 * Setting multiple pins is not safe when all pins are not
1176 * handled by the same regmap register. The oscio pin (present
1177 * on the SX150X_789 chips) lives in its own register, so
1178 * would require locking that is not in place at this time.
1180 if (pctl->data->model != SX150X_789)
1181 pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
1183 /* Add Interrupt support if an irq is specified */
1184 if (client->irq > 0) {
1185 struct gpio_irq_chip *girq;
1187 pctl->irq_chip.irq_mask = sx150x_irq_mask;
1188 pctl->irq_chip.irq_unmask = sx150x_irq_unmask;
1189 pctl->irq_chip.irq_set_type = sx150x_irq_set_type;
1190 pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
1191 pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
1192 pctl->irq_chip.name = devm_kstrdup(dev, client->name,
1194 if (!pctl->irq_chip.name)
1197 pctl->irq.masked = ~0;
1198 pctl->irq.sense = 0;
1201 * Because sx150x_irq_threaded_fn invokes all of the
1202 * nested interrupt handlers via handle_nested_irq,
1203 * any "handler" assigned to struct gpio_irq_chip
1204 * below is going to be ignored, so the choice of the
1205 * function does not matter that much.
1207 * We set it to handle_bad_irq to avoid confusion,
1208 * plus it will be instantly noticeable if it is ever
1209 * called (should not happen)
1211 girq = &pctl->gpio.irq;
1212 girq->chip = &pctl->irq_chip;
1213 /* This will let us handle the parent IRQ in the driver */
1214 girq->parent_handler = NULL;
1215 girq->num_parents = 0;
1216 girq->parents = NULL;
1217 girq->default_type = IRQ_TYPE_NONE;
1218 girq->handler = handle_bad_irq;
1219 girq->threaded = true;
1221 ret = devm_request_threaded_irq(dev, client->irq, NULL,
1222 sx150x_irq_thread_fn,
1223 IRQF_ONESHOT | IRQF_SHARED |
1224 IRQF_TRIGGER_FALLING,
1225 pctl->irq_chip.name, pctl);
1230 ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
1235 * Pin control functions need to be enabled AFTER registering the
1236 * GPIO chip because sx150x_pinconf_set() calls
1237 * sx150x_gpio_direction_output().
1239 ret = pinctrl_enable(pctl->pctldev);
1241 dev_err(dev, "Failed to enable pinctrl device\n");
1245 ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
1246 0, 0, pctl->data->npins);
1253 static struct i2c_driver sx150x_driver = {
1255 .name = "sx150x-pinctrl",
1256 .of_match_table = of_match_ptr(sx150x_of_match),
1258 .probe = sx150x_probe,
1259 .id_table = sx150x_id,
1262 static int __init sx150x_init(void)
1264 return i2c_add_driver(&sx150x_driver);
1266 subsys_initcall(sx150x_init);