drivers/pinctrl/pinctrl-single.c

   1 /*
   2  * Generic device tree based pinctrl driver for one register per pin
   3  * type pinmux controllers
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/list.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <linux/irqchip/chained_irq.h>
  21
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30
  31 #include <linux/platform_data/pinctrl-single.h>
  32
  33 #include "core.h"
  34 #include "devicetree.h"
  35 #include "pinconf.h"
  36 #include "pinmux.h"
  37
  38 #define DRIVER_NAME                     "pinctrl-single"
  39 #define PCS_OFF_DISABLED                ~0U
  40
  41 /**
  42  * struct pcs_func_vals - mux function register offset and value pair
  43  * @reg:        register virtual address
  44  * @val:        register value
  45  * @mask:       mask
  46  */
  47 struct pcs_func_vals {
  48         void __iomem *reg;
  49         unsigned val;
  50         unsigned mask;
  51 };
  52
  53 /**
  54  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  55  * and value, enable, disable, mask
  56  * @param:      config parameter
  57  * @val:        user input bits in the pinconf register
  58  * @enable:     enable bits in the pinconf register
  59  * @disable:    disable bits in the pinconf register
  60  * @mask:       mask bits in the register value
  61  */
  62 struct pcs_conf_vals {
  63         enum pin_config_param param;
  64         unsigned val;
  65         unsigned enable;
  66         unsigned disable;
  67         unsigned mask;
  68 };
  69
  70 /**
  71  * struct pcs_conf_type - pinconf property name, pinconf param pair
  72  * @name:       property name in DTS file
  73  * @param:      config parameter
  74  */
  75 struct pcs_conf_type {
  76         const char *name;
  77         enum pin_config_param param;
  78 };
  79
  80 /**
  81  * struct pcs_function - pinctrl function
  82  * @name:       pinctrl function name
  83  * @vals:       register and vals array
  84  * @nvals:      number of entries in vals array
  85  * @pgnames:    array of pingroup names the function uses
  86  * @npgnames:   number of pingroup names the function uses
  87  * @conf:       array of pin configurations
  88  * @nconfs:     number of pin configurations available
  89  * @node:       list node
  90  */
  91 struct pcs_function {
  92         const char *name;
  93         struct pcs_func_vals *vals;
  94         unsigned nvals;
  95         const char **pgnames;
  96         int npgnames;
  97         struct pcs_conf_vals *conf;
  98         int nconfs;
  99         struct list_head node;
 100 };
 101
 102 /**
 103  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
 104  * @offset:     offset base of pins
 105  * @npins:      number pins with the same mux value of gpio function
 106  * @gpiofunc:   mux value of gpio function
 107  * @node:       list node
 108  */
 109 struct pcs_gpiofunc_range {
 110         unsigned offset;
 111         unsigned npins;
 112         unsigned gpiofunc;
 113         struct list_head node;
 114 };
 115
 116 /**
 117  * struct pcs_data - wrapper for data needed by pinctrl framework
 118  * @pa:         pindesc array
 119  * @cur:        index to current element
 120  *
 121  * REVISIT: We should be able to drop this eventually by adding
 122  * support for registering pins individually in the pinctrl
 123  * framework for those drivers that don't need a static array.
 124  */
 125 struct pcs_data {
 126         struct pinctrl_pin_desc *pa;
 127         int cur;
 128 };
 129
 130 /**
 131  * struct pcs_soc_data - SoC specific settings
 132  * @flags:      initial SoC specific PCS_FEAT_xxx values
 133  * @irq:        optional interrupt for the controller
 134  * @irq_enable_mask:    optional SoC specific interrupt enable mask
 135  * @irq_status_mask:    optional SoC specific interrupt status mask
 136  * @rearm:      optional SoC specific wake-up rearm function
 137  */
 138 struct pcs_soc_data {
 139         unsigned flags;
 140         int irq;
 141         unsigned irq_enable_mask;
 142         unsigned irq_status_mask;
 143         void (*rearm)(void);
 144 };
 145
 146 /**
 147  * struct pcs_device - pinctrl device instance
 148  * @res:        resources
 149  * @base:       virtual address of the controller
 150  * @saved_vals: saved values for the controller
 151  * @size:       size of the ioremapped area
 152  * @dev:        device entry
 153  * @np:         device tree node
 154  * @pctl:       pin controller device
 155  * @flags:      mask of PCS_FEAT_xxx values
 156  * @missing_nr_pinctrl_cells: for legacy binding, may go away
 157  * @socdata:    soc specific data
 158  * @lock:       spinlock for register access
 159  * @mutex:      mutex protecting the lists
 160  * @width:      bits per mux register
 161  * @fmask:      function register mask
 162  * @fshift:     function register shift
 163  * @foff:       value to turn mux off
 164  * @fmax:       max number of functions in fmask
 165  * @bits_per_mux: number of bits per mux
 166  * @bits_per_pin: number of bits per pin
 167  * @pins:       physical pins on the SoC
 168  * @gpiofuncs:  list of gpio functions
 169  * @irqs:       list of interrupt registers
 170  * @chip:       chip container for this instance
 171  * @domain:     IRQ domain for this instance
 172  * @desc:       pin controller descriptor
 173  * @read:       register read function to use
 174  * @write:      register write function to use
 175  */
 176 struct pcs_device {
 177         struct resource *res;
 178         void __iomem *base;
 179         void *saved_vals;
 180         unsigned size;
 181         struct device *dev;
 182         struct device_node *np;
 183         struct pinctrl_dev *pctl;
 184         unsigned flags;
 185 #define PCS_CONTEXT_LOSS_OFF    (1 << 3)
 186 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
 187 #define PCS_FEAT_IRQ            (1 << 1)
 188 #define PCS_FEAT_PINCONF        (1 << 0)
 189         struct property *missing_nr_pinctrl_cells;
 190         struct pcs_soc_data socdata;
 191         raw_spinlock_t lock;
 192         struct mutex mutex;
 193         unsigned width;
 194         unsigned fmask;
 195         unsigned fshift;
 196         unsigned foff;
 197         unsigned fmax;
 198         bool bits_per_mux;
 199         unsigned bits_per_pin;
 200         struct pcs_data pins;
 201         struct list_head gpiofuncs;
 202         struct list_head irqs;
 203         struct irq_chip chip;
 204         struct irq_domain *domain;
 205         struct pinctrl_desc desc;
 206         unsigned (*read)(void __iomem *reg);
 207         void (*write)(unsigned val, void __iomem *reg);
 208 };
 209
 210 #define PCS_QUIRK_HAS_SHARED_IRQ        (pcs->flags & PCS_QUIRK_SHARED_IRQ)
 211 #define PCS_HAS_IRQ             (pcs->flags & PCS_FEAT_IRQ)
 212 #define PCS_HAS_PINCONF         (pcs->flags & PCS_FEAT_PINCONF)
 213
 214 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 215                            unsigned long *config);
 216 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 217                            unsigned long *configs, unsigned num_configs);
 218
 219 static enum pin_config_param pcs_bias[] = {
 220         PIN_CONFIG_BIAS_PULL_DOWN,
 221         PIN_CONFIG_BIAS_PULL_UP,
 222 };
 223
 224 /*
 225  * This lock class tells lockdep that irqchip core that this single
 226  * pinctrl can be in a different category than its parents, so it won't
 227  * report false recursion.
 228  */
 229 static struct lock_class_key pcs_lock_class;
 230
 231 /* Class for the IRQ request mutex */
 232 static struct lock_class_key pcs_request_class;
 233
 234 /*
 235  * REVISIT: Reads and writes could eventually use regmap or something
 236  * generic. But at least on omaps, some mux registers are performance
 237  * critical as they may need to be remuxed every time before and after
 238  * idle. Adding tests for register access width for every read and
 239  * write like regmap is doing is not desired, and caching the registers
 240  * does not help in this case.
 241  */
 242
 243 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
 244 {
 245         return readb(reg);
 246 }
 247
 248 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
 249 {
 250         return readw(reg);
 251 }
 252
 253 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
 254 {
 255         return readl(reg);
 256 }
 257
 258 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
 259 {
 260         writeb(val, reg);
 261 }
 262
 263 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
 264 {
 265         writew(val, reg);
 266 }
 267
 268 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
 269 {
 270         writel(val, reg);
 271 }
 272
 273 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
 274                                         struct seq_file *s,
 275                                         unsigned pin)
 276 {
 277         struct pcs_device *pcs;
 278         unsigned val, mux_bytes;
 279         unsigned long offset;
 280         size_t pa;
 281
 282         pcs = pinctrl_dev_get_drvdata(pctldev);
 283
 284         mux_bytes = pcs->width / BITS_PER_BYTE;
 285         offset = pin * mux_bytes;
 286         val = pcs->read(pcs->base + offset);
 287         pa = pcs->res->start + offset;
 288
 289         seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
 290 }
 291
 292 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
 293                                 struct pinctrl_map *map, unsigned num_maps)
 294 {
 295         struct pcs_device *pcs;
 296
 297         pcs = pinctrl_dev_get_drvdata(pctldev);
 298         devm_kfree(pcs->dev, map);
 299 }
 300
 301 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 302                                 struct device_node *np_config,
 303                                 struct pinctrl_map **map, unsigned *num_maps);
 304
 305 static const struct pinctrl_ops pcs_pinctrl_ops = {
 306         .get_groups_count = pinctrl_generic_get_group_count,
 307         .get_group_name = pinctrl_generic_get_group_name,
 308         .get_group_pins = pinctrl_generic_get_group_pins,
 309         .pin_dbg_show = pcs_pin_dbg_show,
 310         .dt_node_to_map = pcs_dt_node_to_map,
 311         .dt_free_map = pcs_dt_free_map,
 312 };
 313
 314 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
 315                             struct pcs_function **func)
 316 {
 317         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 318         struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
 319         const struct pinctrl_setting_mux *setting;
 320         struct function_desc *function;
 321         unsigned fselector;
 322
 323         /* If pin is not described in DTS & enabled, mux_setting is NULL. */
 324         setting = pdesc->mux_setting;
 325         if (!setting)
 326                 return -ENOTSUPP;
 327         fselector = setting->func;
 328         function = pinmux_generic_get_function(pctldev, fselector);
 329         *func = function->data;
 330         if (!(*func)) {
 331                 dev_err(pcs->dev, "%s could not find function%i\n",
 332                         __func__, fselector);
 333                 return -ENOTSUPP;
 334         }
 335         return 0;
 336 }
 337
 338 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
 339         unsigned group)
 340 {
 341         struct pcs_device *pcs;
 342         struct function_desc *function;
 343         struct pcs_function *func;
 344         int i;
 345
 346         pcs = pinctrl_dev_get_drvdata(pctldev);
 347         /* If function mask is null, needn't enable it. */
 348         if (!pcs->fmask)
 349                 return 0;
 350         function = pinmux_generic_get_function(pctldev, fselector);
 351         func = function->data;
 352         if (!func)
 353                 return -EINVAL;
 354
 355         dev_dbg(pcs->dev, "enabling %s function%i\n",
 356                 func->name, fselector);
 357
 358         for (i = 0; i < func->nvals; i++) {
 359                 struct pcs_func_vals *vals;
 360                 unsigned long flags;
 361                 unsigned val, mask;
 362
 363                 vals = &func->vals[i];
 364                 raw_spin_lock_irqsave(&pcs->lock, flags);
 365                 val = pcs->read(vals->reg);
 366
 367                 if (pcs->bits_per_mux)
 368                         mask = vals->mask;
 369                 else
 370                         mask = pcs->fmask;
 371
 372                 val &= ~mask;
 373                 val |= (vals->val & mask);
 374                 pcs->write(val, vals->reg);
 375                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
 382                             struct pinctrl_gpio_range *range, unsigned pin)
 383 {
 384         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 385         struct pcs_gpiofunc_range *frange = NULL;
 386         struct list_head *pos, *tmp;
 387         int mux_bytes = 0;
 388         unsigned data;
 389
 390         /* If function mask is null, return directly. */
 391         if (!pcs->fmask)
 392                 return -ENOTSUPP;
 393
 394         list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
 395                 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
 396                 if (pin >= frange->offset + frange->npins
 397                         || pin < frange->offset)
 398                         continue;
 399                 mux_bytes = pcs->width / BITS_PER_BYTE;
 400
 401                 if (pcs->bits_per_mux) {
 402                         int byte_num, offset, pin_shift;
 403
 404                         byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
 405                         offset = (byte_num / mux_bytes) * mux_bytes;
 406                         pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
 407                                     pcs->bits_per_pin;
 408
 409                         data = pcs->read(pcs->base + offset);
 410                         data &= ~(pcs->fmask << pin_shift);
 411                         data |= frange->gpiofunc << pin_shift;
 412                         pcs->write(data, pcs->base + offset);
 413                 } else {
 414                         data = pcs->read(pcs->base + pin * mux_bytes);
 415                         data &= ~pcs->fmask;
 416                         data |= frange->gpiofunc;
 417                         pcs->write(data, pcs->base + pin * mux_bytes);
 418                 }
 419                 break;
 420         }
 421         return 0;
 422 }
 423
 424 static const struct pinmux_ops pcs_pinmux_ops = {
 425         .get_functions_count = pinmux_generic_get_function_count,
 426         .get_function_name = pinmux_generic_get_function_name,
 427         .get_function_groups = pinmux_generic_get_function_groups,
 428         .set_mux = pcs_set_mux,
 429         .gpio_request_enable = pcs_request_gpio,
 430 };
 431
 432 /* Clear BIAS value */
 433 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
 434 {
 435         unsigned long config;
 436         int i;
 437         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 438                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 439                 pcs_pinconf_set(pctldev, pin, &config, 1);
 440         }
 441 }
 442
 443 /*
 444  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
 445  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
 446  */
 447 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
 448 {
 449         unsigned long config;
 450         int i;
 451
 452         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 453                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 454                 if (!pcs_pinconf_get(pctldev, pin, &config))
 455                         goto out;
 456         }
 457         return true;
 458 out:
 459         return false;
 460 }
 461
 462 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
 463                                 unsigned pin, unsigned long *config)
 464 {
 465         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 466         struct pcs_function *func;
 467         enum pin_config_param param;
 468         unsigned offset = 0, data = 0, i, j, ret;
 469
 470         ret = pcs_get_function(pctldev, pin, &func);
 471         if (ret)
 472                 return ret;
 473
 474         for (i = 0; i < func->nconfs; i++) {
 475                 param = pinconf_to_config_param(*config);
 476                 if (param == PIN_CONFIG_BIAS_DISABLE) {
 477                         if (pcs_pinconf_bias_disable(pctldev, pin)) {
 478                                 *config = 0;
 479                                 return 0;
 480                         } else {
 481                                 return -ENOTSUPP;
 482                         }
 483                 } else if (param != func->conf[i].param) {
 484                         continue;
 485                 }
 486
 487                 offset = pin * (pcs->width / BITS_PER_BYTE);
 488                 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
 489                 switch (func->conf[i].param) {
 490                 /* 4 parameters */
 491                 case PIN_CONFIG_BIAS_PULL_DOWN:
 492                 case PIN_CONFIG_BIAS_PULL_UP:
 493                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 494                         if ((data != func->conf[i].enable) ||
 495                             (data == func->conf[i].disable))
 496                                 return -ENOTSUPP;
 497                         *config = 0;
 498                         break;
 499                 /* 2 parameters */
 500                 case PIN_CONFIG_INPUT_SCHMITT:
 501                         for (j = 0; j < func->nconfs; j++) {
 502                                 switch (func->conf[j].param) {
 503                                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 504                                         if (data != func->conf[j].enable)
 505                                                 return -ENOTSUPP;
 506                                         break;
 507                                 default:
 508                                         break;
 509                                 }
 510                         }
 511                         *config = data;
 512                         break;
 513                 case PIN_CONFIG_DRIVE_STRENGTH:
 514                 case PIN_CONFIG_SLEW_RATE:
 515                 case PIN_CONFIG_LOW_POWER_MODE:
 516                 default:
 517                         *config = data;
 518                         break;
 519                 }
 520                 return 0;
 521         }
 522         return -ENOTSUPP;
 523 }
 524
 525 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
 526                                 unsigned pin, unsigned long *configs,
 527                                 unsigned num_configs)
 528 {
 529         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 530         struct pcs_function *func;
 531         unsigned offset = 0, shift = 0, i, data, ret;
 532         u32 arg;
 533         int j;
 534
 535         ret = pcs_get_function(pctldev, pin, &func);
 536         if (ret)
 537                 return ret;
 538
 539         for (j = 0; j < num_configs; j++) {
 540                 for (i = 0; i < func->nconfs; i++) {
 541                         if (pinconf_to_config_param(configs[j])
 542                                 != func->conf[i].param)
 543                                 continue;
 544
 545                         offset = pin * (pcs->width / BITS_PER_BYTE);
 546                         data = pcs->read(pcs->base + offset);
 547                         arg = pinconf_to_config_argument(configs[j]);
 548                         switch (func->conf[i].param) {
 549                         /* 2 parameters */
 550                         case PIN_CONFIG_INPUT_SCHMITT:
 551                         case PIN_CONFIG_DRIVE_STRENGTH:
 552                         case PIN_CONFIG_SLEW_RATE:
 553                         case PIN_CONFIG_LOW_POWER_MODE:
 554                                 shift = ffs(func->conf[i].mask) - 1;
 555                                 data &= ~func->conf[i].mask;
 556                                 data |= (arg << shift) & func->conf[i].mask;
 557                                 break;
 558                         /* 4 parameters */
 559                         case PIN_CONFIG_BIAS_DISABLE:
 560                                 pcs_pinconf_clear_bias(pctldev, pin);
 561                                 break;
 562                         case PIN_CONFIG_BIAS_PULL_DOWN:
 563                         case PIN_CONFIG_BIAS_PULL_UP:
 564                                 if (arg)
 565                                         pcs_pinconf_clear_bias(pctldev, pin);
 566                                 fallthrough;
 567                         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 568                                 data &= ~func->conf[i].mask;
 569                                 if (arg)
 570                                         data |= func->conf[i].enable;
 571                                 else
 572                                         data |= func->conf[i].disable;
 573                                 break;
 574                         default:
 575                                 return -ENOTSUPP;
 576                         }
 577                         pcs->write(data, pcs->base + offset);
 578
 579                         break;
 580                 }
 581                 if (i >= func->nconfs)
 582                         return -ENOTSUPP;
 583         } /* for each config */
 584
 585         return 0;
 586 }
 587
 588 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
 589                                 unsigned group, unsigned long *config)
 590 {
 591         const unsigned *pins;
 592         unsigned npins, old = 0;
 593         int i, ret;
 594
 595         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 596         if (ret)
 597                 return ret;
 598         for (i = 0; i < npins; i++) {
 599                 if (pcs_pinconf_get(pctldev, pins[i], config))
 600                         return -ENOTSUPP;
 601                 /* configs do not match between two pins */
 602                 if (i && (old != *config))
 603                         return -ENOTSUPP;
 604                 old = *config;
 605         }
 606         return 0;
 607 }
 608
 609 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
 610                                 unsigned group, unsigned long *configs,
 611                                 unsigned num_configs)
 612 {
 613         const unsigned *pins;
 614         unsigned npins;
 615         int i, ret;
 616
 617         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 618         if (ret)
 619                 return ret;
 620         for (i = 0; i < npins; i++) {
 621                 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
 622                         return -ENOTSUPP;
 623         }
 624         return 0;
 625 }
 626
 627 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 628                                 struct seq_file *s, unsigned pin)
 629 {
 630 }
 631
 632 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 633                                 struct seq_file *s, unsigned selector)
 634 {
 635 }
 636
 637 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 638                                         struct seq_file *s,
 639                                         unsigned long config)
 640 {
 641         pinconf_generic_dump_config(pctldev, s, config);
 642 }
 643
 644 static const struct pinconf_ops pcs_pinconf_ops = {
 645         .pin_config_get = pcs_pinconf_get,
 646         .pin_config_set = pcs_pinconf_set,
 647         .pin_config_group_get = pcs_pinconf_group_get,
 648         .pin_config_group_set = pcs_pinconf_group_set,
 649         .pin_config_dbg_show = pcs_pinconf_dbg_show,
 650         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
 651         .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
 652         .is_generic = true,
 653 };
 654
 655 /**
 656  * pcs_add_pin() - add a pin to the static per controller pin array
 657  * @pcs: pcs driver instance
 658  * @offset: register offset from base
 659  */
 660 static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
 661 {
 662         struct pcs_soc_data *pcs_soc = &pcs->socdata;
 663         struct pinctrl_pin_desc *pin;
 664         int i;
 665
 666         i = pcs->pins.cur;
 667         if (i >= pcs->desc.npins) {
 668                 dev_err(pcs->dev, "too many pins, max %i\n",
 669                         pcs->desc.npins);
 670                 return -ENOMEM;
 671         }
 672
 673         if (pcs_soc->irq_enable_mask) {
 674                 unsigned val;
 675
 676                 val = pcs->read(pcs->base + offset);
 677                 if (val & pcs_soc->irq_enable_mask) {
 678                         dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
 679                                 (unsigned long)pcs->res->start + offset, val);
 680                         val &= ~pcs_soc->irq_enable_mask;
 681                         pcs->write(val, pcs->base + offset);
 682                 }
 683         }
 684
 685         pin = &pcs->pins.pa[i];
 686         pin->number = i;
 687         pcs->pins.cur++;
 688
 689         return i;
 690 }
 691
 692 /**
 693  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
 694  * @pcs: pcs driver instance
 695  *
 696  * In case of errors, resources are freed in pcs_free_resources.
 697  *
 698  * If your hardware needs holes in the address space, then just set
 699  * up multiple driver instances.
 700  */
 701 static int pcs_allocate_pin_table(struct pcs_device *pcs)
 702 {
 703         int mux_bytes, nr_pins, i;
 704
 705         mux_bytes = pcs->width / BITS_PER_BYTE;
 706
 707         if (pcs->bits_per_mux) {
 708                 pcs->bits_per_pin = fls(pcs->fmask);
 709                 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
 710         } else {
 711                 nr_pins = pcs->size / mux_bytes;
 712         }
 713
 714         dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 715         pcs->pins.pa = devm_kcalloc(pcs->dev,
 716                                 nr_pins, sizeof(*pcs->pins.pa),
 717                                 GFP_KERNEL);
 718         if (!pcs->pins.pa)
 719                 return -ENOMEM;
 720
 721         pcs->desc.pins = pcs->pins.pa;
 722         pcs->desc.npins = nr_pins;
 723
 724         for (i = 0; i < pcs->desc.npins; i++) {
 725                 unsigned offset;
 726                 int res;
 727                 int byte_num;
 728
 729                 if (pcs->bits_per_mux) {
 730                         byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
 731                         offset = (byte_num / mux_bytes) * mux_bytes;
 732                 } else {
 733                         offset = i * mux_bytes;
 734                 }
 735                 res = pcs_add_pin(pcs, offset);
 736                 if (res < 0) {
 737                         dev_err(pcs->dev, "error adding pins: %i\n", res);
 738                         return res;
 739                 }
 740         }
 741
 742         return 0;
 743 }
 744
 745 /**
 746  * pcs_add_function() - adds a new function to the function list
 747  * @pcs: pcs driver instance
 748  * @fcn: new function allocated
 749  * @name: name of the function
 750  * @vals: array of mux register value pairs used by the function
 751  * @nvals: number of mux register value pairs
 752  * @pgnames: array of pingroup names for the function
 753  * @npgnames: number of pingroup names
 754  *
 755  * Caller must take care of locking.
 756  */
 757 static int pcs_add_function(struct pcs_device *pcs,
 758                             struct pcs_function **fcn,
 759                             const char *name,
 760                             struct pcs_func_vals *vals,
 761                             unsigned int nvals,
 762                             const char **pgnames,
 763                             unsigned int npgnames)
 764 {
 765         struct pcs_function *function;
 766         int selector;
 767
 768         function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
 769         if (!function)
 770                 return -ENOMEM;
 771
 772         function->vals = vals;
 773         function->nvals = nvals;
 774         function->name = name;
 775
 776         selector = pinmux_generic_add_function(pcs->pctl, name,
 777                                                pgnames, npgnames,
 778                                                function);
 779         if (selector < 0) {
 780                 devm_kfree(pcs->dev, function);
 781                 *fcn = NULL;
 782         } else {
 783                 *fcn = function;
 784         }
 785
 786         return selector;
 787 }
 788
 789 /**
 790  * pcs_get_pin_by_offset() - get a pin index based on the register offset
 791  * @pcs: pcs driver instance
 792  * @offset: register offset from the base
 793  *
 794  * Note that this is OK as long as the pins are in a static array.
 795  */
 796 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 797 {
 798         unsigned index;
 799
 800         if (offset >= pcs->size) {
 801                 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
 802                         offset, pcs->size);
 803                 return -EINVAL;
 804         }
 805
 806         if (pcs->bits_per_mux)
 807                 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
 808         else
 809                 index = offset / (pcs->width / BITS_PER_BYTE);
 810
 811         return index;
 812 }
 813
 814 /*
 815  * check whether data matches enable bits or disable bits
 816  * Return value: 1 for matching enable bits, 0 for matching disable bits,
 817  *               and negative value for matching failure.
 818  */
 819 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
 820 {
 821         int ret = -EINVAL;
 822
 823         if (data == enable)
 824                 ret = 1;
 825         else if (data == disable)
 826                 ret = 0;
 827         return ret;
 828 }
 829
 830 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
 831                        unsigned value, unsigned enable, unsigned disable,
 832                        unsigned mask)
 833 {
 834         (*conf)->param = param;
 835         (*conf)->val = value;
 836         (*conf)->enable = enable;
 837         (*conf)->disable = disable;
 838         (*conf)->mask = mask;
 839         (*conf)++;
 840 }
 841
 842 static void add_setting(unsigned long **setting, enum pin_config_param param,
 843                         unsigned arg)
 844 {
 845         **setting = pinconf_to_config_packed(param, arg);
 846         (*setting)++;
 847 }
 848
 849 /* add pinconf setting with 2 parameters */
 850 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
 851                           const char *name, enum pin_config_param param,
 852                           struct pcs_conf_vals **conf, unsigned long **settings)
 853 {
 854         unsigned value[2], shift;
 855         int ret;
 856
 857         ret = of_property_read_u32_array(np, name, value, 2);
 858         if (ret)
 859                 return;
 860         /* set value & mask */
 861         value[0] &= value[1];
 862         shift = ffs(value[1]) - 1;
 863         /* skip enable & disable */
 864         add_config(conf, param, value[0], 0, 0, value[1]);
 865         add_setting(settings, param, value[0] >> shift);
 866 }
 867
 868 /* add pinconf setting with 4 parameters */
 869 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
 870                           const char *name, enum pin_config_param param,
 871                           struct pcs_conf_vals **conf, unsigned long **settings)
 872 {
 873         unsigned value[4];
 874         int ret;
 875
 876         /* value to set, enable, disable, mask */
 877         ret = of_property_read_u32_array(np, name, value, 4);
 878         if (ret)
 879                 return;
 880         if (!value[3]) {
 881                 dev_err(pcs->dev, "mask field of the property can't be 0\n");
 882                 return;
 883         }
 884         value[0] &= value[3];
 885         value[1] &= value[3];
 886         value[2] &= value[3];
 887         ret = pcs_config_match(value[0], value[1], value[2]);
 888         if (ret < 0)
 889                 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
 890         add_config(conf, param, value[0], value[1], value[2], value[3]);
 891         add_setting(settings, param, ret);
 892 }
 893
 894 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
 895                              struct pcs_function *func,
 896                              struct pinctrl_map **map)
 897
 898 {
 899         struct pinctrl_map *m = *map;
 900         int i = 0, nconfs = 0;
 901         unsigned long *settings = NULL, *s = NULL;
 902         struct pcs_conf_vals *conf = NULL;
 903         static const struct pcs_conf_type prop2[] = {
 904                 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
 905                 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
 906                 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
 907                 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
 908         };
 909         static const struct pcs_conf_type prop4[] = {
 910                 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
 911                 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
 912                 { "pinctrl-single,input-schmitt-enable",
 913                         PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
 914         };
 915
 916         /* If pinconf isn't supported, don't parse properties in below. */
 917         if (!PCS_HAS_PINCONF)
 918                 return -ENOTSUPP;
 919
 920         /* cacluate how much properties are supported in current node */
 921         for (i = 0; i < ARRAY_SIZE(prop2); i++) {
 922                 if (of_find_property(np, prop2[i].name, NULL))
 923                         nconfs++;
 924         }
 925         for (i = 0; i < ARRAY_SIZE(prop4); i++) {
 926                 if (of_find_property(np, prop4[i].name, NULL))
 927                         nconfs++;
 928         }
 929         if (!nconfs)
 930                 return -ENOTSUPP;
 931
 932         func->conf = devm_kcalloc(pcs->dev,
 933                                   nconfs, sizeof(struct pcs_conf_vals),
 934                                   GFP_KERNEL);
 935         if (!func->conf)
 936                 return -ENOMEM;
 937         func->nconfs = nconfs;
 938         conf = &(func->conf[0]);
 939         m++;
 940         settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
 941                                 GFP_KERNEL);
 942         if (!settings)
 943                 return -ENOMEM;
 944         s = &settings[0];
 945
 946         for (i = 0; i < ARRAY_SIZE(prop2); i++)
 947                 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
 948                               &conf, &s);
 949         for (i = 0; i < ARRAY_SIZE(prop4); i++)
 950                 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
 951                               &conf, &s);
 952         m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
 953         m->data.configs.group_or_pin = np->name;
 954         m->data.configs.configs = settings;
 955         m->data.configs.num_configs = nconfs;
 956         return 0;
 957 }
 958
 959 /**
 960  * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
 961  * @pcs: pinctrl driver instance
 962  * @np: device node of the mux entry
 963  * @map: map entry
 964  * @num_maps: number of map
 965  * @pgnames: pingroup names
 966  *
 967  * Note that this binding currently supports only sets of one register + value.
 968  *
 969  * Also note that this driver tries to avoid understanding pin and function
 970  * names because of the extra bloat they would cause especially in the case of
 971  * a large number of pins. This driver just sets what is specified for the board
 972  * in the .dts file. Further user space debugging tools can be developed to
 973  * decipher the pin and function names using debugfs.
 974  *
 975  * If you are concerned about the boot time, set up the static pins in
 976  * the bootloader, and only set up selected pins as device tree entries.
 977  */
 978 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
 979                                                 struct device_node *np,
 980                                                 struct pinctrl_map **map,
 981                                                 unsigned *num_maps,
 982                                                 const char **pgnames)
 983 {
 984         const char *name = "pinctrl-single,pins";
 985         struct pcs_func_vals *vals;
 986         int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
 987         struct pcs_function *function = NULL;
 988
 989         rows = pinctrl_count_index_with_args(np, name);
 990         if (rows <= 0) {
 991                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
 992                 return -EINVAL;
 993         }
 994
 995         vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
 996         if (!vals)
 997                 return -ENOMEM;
 998
 999         pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1000         if (!pins)
1001                 goto free_vals;
1002
1003         for (i = 0; i < rows; i++) {
1004                 struct of_phandle_args pinctrl_spec;
1005                 unsigned int offset;
1006                 int pin;
1007
1008                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1009                 if (res)
1010                         return res;
1011
1012                 if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
1013                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1014                                 pinctrl_spec.args_count);
1015                         break;
1016                 }
1017
1018                 offset = pinctrl_spec.args[0];
1019                 vals[found].reg = pcs->base + offset;
1020
1021                 switch (pinctrl_spec.args_count) {
1022                 case 2:
1023                         vals[found].val = pinctrl_spec.args[1];
1024                         break;
1025                 case 3:
1026                         vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
1027                         break;
1028                 }
1029
1030                 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1031                         pinctrl_spec.np, offset, vals[found].val);
1032
1033                 pin = pcs_get_pin_by_offset(pcs, offset);
1034                 if (pin < 0) {
1035                         dev_err(pcs->dev,
1036                                 "could not add functions for %pOFn %ux\n",
1037                                 np, offset);
1038                         break;
1039                 }
1040                 pins[found++] = pin;
1041         }
1042
1043         pgnames[0] = np->name;
1044         mutex_lock(&pcs->mutex);
1045         fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1046                                 pgnames, 1);
1047         if (fsel < 0) {
1048                 res = fsel;
1049                 goto free_pins;
1050         }
1051
1052         gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1053         if (gsel < 0) {
1054                 res = gsel;
1055                 goto free_function;
1056         }
1057
1058         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1059         (*map)->data.mux.group = np->name;
1060         (*map)->data.mux.function = np->name;
1061
1062         if (PCS_HAS_PINCONF && function) {
1063                 res = pcs_parse_pinconf(pcs, np, function, map);
1064                 if (res == 0)
1065                         *num_maps = 2;
1066                 else if (res == -ENOTSUPP)
1067                         *num_maps = 1;
1068                 else
1069                         goto free_pingroups;
1070         } else {
1071                 *num_maps = 1;
1072         }
1073         mutex_unlock(&pcs->mutex);
1074
1075         return 0;
1076
1077 free_pingroups:
1078         pinctrl_generic_remove_group(pcs->pctl, gsel);
1079         *num_maps = 1;
1080 free_function:
1081         pinmux_generic_remove_function(pcs->pctl, fsel);
1082 free_pins:
1083         mutex_unlock(&pcs->mutex);
1084         devm_kfree(pcs->dev, pins);
1085
1086 free_vals:
1087         devm_kfree(pcs->dev, vals);
1088
1089         return res;
1090 }
1091
1092 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1093                                                 struct device_node *np,
1094                                                 struct pinctrl_map **map,
1095                                                 unsigned *num_maps,
1096                                                 const char **pgnames)
1097 {
1098         const char *name = "pinctrl-single,bits";
1099         struct pcs_func_vals *vals;
1100         int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1101         int npins_in_row;
1102         struct pcs_function *function = NULL;
1103
1104         rows = pinctrl_count_index_with_args(np, name);
1105         if (rows <= 0) {
1106                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1107                 return -EINVAL;
1108         }
1109
1110         npins_in_row = pcs->width / pcs->bits_per_pin;
1111
1112         vals = devm_kzalloc(pcs->dev,
1113                             array3_size(rows, npins_in_row, sizeof(*vals)),
1114                             GFP_KERNEL);
1115         if (!vals)
1116                 return -ENOMEM;
1117
1118         pins = devm_kzalloc(pcs->dev,
1119                             array3_size(rows, npins_in_row, sizeof(*pins)),
1120                             GFP_KERNEL);
1121         if (!pins)
1122                 goto free_vals;
1123
1124         for (i = 0; i < rows; i++) {
1125                 struct of_phandle_args pinctrl_spec;
1126                 unsigned offset, val;
1127                 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1128                 unsigned pin_num_from_lsb;
1129                 int pin;
1130
1131                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1132                 if (res)
1133                         return res;
1134
1135                 if (pinctrl_spec.args_count < 3) {
1136                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1137                                 pinctrl_spec.args_count);
1138                         break;
1139                 }
1140
1141                 /* Index plus two value cells */
1142                 offset = pinctrl_spec.args[0];
1143                 val = pinctrl_spec.args[1];
1144                 mask = pinctrl_spec.args[2];
1145
1146                 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1147                         pinctrl_spec.np, offset, val, mask);
1148
1149                 /* Parse pins in each row from LSB */
1150                 while (mask) {
1151                         bit_pos = __ffs(mask);
1152                         pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1153                         mask_pos = ((pcs->fmask) << bit_pos);
1154                         val_pos = val & mask_pos;
1155                         submask = mask & mask_pos;
1156
1157                         if ((mask & mask_pos) == 0) {
1158                                 dev_err(pcs->dev,
1159                                         "Invalid mask for %pOFn at 0x%x\n",
1160                                         np, offset);
1161                                 break;
1162                         }
1163
1164                         mask &= ~mask_pos;
1165
1166                         if (submask != mask_pos) {
1167                                 dev_warn(pcs->dev,
1168                                                 "Invalid submask 0x%x for %pOFn at 0x%x\n",
1169                                                 submask, np, offset);
1170                                 continue;
1171                         }
1172
1173                         vals[found].mask = submask;
1174                         vals[found].reg = pcs->base + offset;
1175                         vals[found].val = val_pos;
1176
1177                         pin = pcs_get_pin_by_offset(pcs, offset);
1178                         if (pin < 0) {
1179                                 dev_err(pcs->dev,
1180                                         "could not add functions for %pOFn %ux\n",
1181                                         np, offset);
1182                                 break;
1183                         }
1184                         pins[found++] = pin + pin_num_from_lsb;
1185                 }
1186         }
1187
1188         pgnames[0] = np->name;
1189         mutex_lock(&pcs->mutex);
1190         fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1191                                 pgnames, 1);
1192         if (fsel < 0) {
1193                 res = fsel;
1194                 goto free_pins;
1195         }
1196
1197         gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1198         if (gsel < 0) {
1199                 res = gsel;
1200                 goto free_function;
1201         }
1202
1203         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1204         (*map)->data.mux.group = np->name;
1205         (*map)->data.mux.function = np->name;
1206
1207         if (PCS_HAS_PINCONF) {
1208                 dev_err(pcs->dev, "pinconf not supported\n");
1209                 goto free_pingroups;
1210         }
1211
1212         *num_maps = 1;
1213         mutex_unlock(&pcs->mutex);
1214
1215         return 0;
1216
1217 free_pingroups:
1218         pinctrl_generic_remove_group(pcs->pctl, gsel);
1219         *num_maps = 1;
1220 free_function:
1221         pinmux_generic_remove_function(pcs->pctl, fsel);
1222 free_pins:
1223         mutex_unlock(&pcs->mutex);
1224         devm_kfree(pcs->dev, pins);
1225
1226 free_vals:
1227         devm_kfree(pcs->dev, vals);
1228
1229         return res;
1230 }
1231 /**
1232  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1233  * @pctldev: pinctrl instance
1234  * @np_config: device tree pinmux entry
1235  * @map: array of map entries
1236  * @num_maps: number of maps
1237  */
1238 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1239                                 struct device_node *np_config,
1240                                 struct pinctrl_map **map, unsigned *num_maps)
1241 {
1242         struct pcs_device *pcs;
1243         const char **pgnames;
1244         int ret;
1245
1246         pcs = pinctrl_dev_get_drvdata(pctldev);
1247
1248         /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1249         *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1250         if (!*map)
1251                 return -ENOMEM;
1252
1253         *num_maps = 0;
1254
1255         pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1256         if (!pgnames) {
1257                 ret = -ENOMEM;
1258                 goto free_map;
1259         }
1260
1261         if (pcs->bits_per_mux) {
1262                 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1263                                 num_maps, pgnames);
1264                 if (ret < 0) {
1265                         dev_err(pcs->dev, "no pins entries for %pOFn\n",
1266                                 np_config);
1267                         goto free_pgnames;
1268                 }
1269         } else {
1270                 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1271                                 num_maps, pgnames);
1272                 if (ret < 0) {
1273                         dev_err(pcs->dev, "no pins entries for %pOFn\n",
1274                                 np_config);
1275                         goto free_pgnames;
1276                 }
1277         }
1278
1279         return 0;
1280
1281 free_pgnames:
1282         devm_kfree(pcs->dev, pgnames);
1283 free_map:
1284         devm_kfree(pcs->dev, *map);
1285
1286         return ret;
1287 }
1288
1289 /**
1290  * pcs_irq_free() - free interrupt
1291  * @pcs: pcs driver instance
1292  */
1293 static void pcs_irq_free(struct pcs_device *pcs)
1294 {
1295         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1296
1297         if (pcs_soc->irq < 0)
1298                 return;
1299
1300         if (pcs->domain)
1301                 irq_domain_remove(pcs->domain);
1302
1303         if (PCS_QUIRK_HAS_SHARED_IRQ)
1304                 free_irq(pcs_soc->irq, pcs_soc);
1305         else
1306                 irq_set_chained_handler(pcs_soc->irq, NULL);
1307 }
1308
1309 /**
1310  * pcs_free_resources() - free memory used by this driver
1311  * @pcs: pcs driver instance
1312  */
1313 static void pcs_free_resources(struct pcs_device *pcs)
1314 {
1315         pcs_irq_free(pcs);
1316         pinctrl_unregister(pcs->pctl);
1317
1318 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1319         if (pcs->missing_nr_pinctrl_cells)
1320                 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1321 #endif
1322 }
1323
1324 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1325 {
1326         const char *propname = "pinctrl-single,gpio-range";
1327         const char *cellname = "#pinctrl-single,gpio-range-cells";
1328         struct of_phandle_args gpiospec;
1329         struct pcs_gpiofunc_range *range;
1330         int ret, i;
1331
1332         for (i = 0; ; i++) {
1333                 ret = of_parse_phandle_with_args(node, propname, cellname,
1334                                                  i, &gpiospec);
1335                 /* Do not treat it as error. Only treat it as end condition. */
1336                 if (ret) {
1337                         ret = 0;
1338                         break;
1339                 }
1340                 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1341                 if (!range) {
1342                         ret = -ENOMEM;
1343                         break;
1344                 }
1345                 range->offset = gpiospec.args[0];
1346                 range->npins = gpiospec.args[1];
1347                 range->gpiofunc = gpiospec.args[2];
1348                 mutex_lock(&pcs->mutex);
1349                 list_add_tail(&range->node, &pcs->gpiofuncs);
1350                 mutex_unlock(&pcs->mutex);
1351         }
1352         return ret;
1353 }
1354
1355 /**
1356  * struct pcs_interrupt
1357  * @reg:        virtual address of interrupt register
1358  * @hwirq:      hardware irq number
1359  * @irq:        virtual irq number
1360  * @node:       list node
1361  */
1362 struct pcs_interrupt {
1363         void __iomem *reg;
1364         irq_hw_number_t hwirq;
1365         unsigned int irq;
1366         struct list_head node;
1367 };
1368
1369 /**
1370  * pcs_irq_set() - enables or disables an interrupt
1371  * @pcs_soc: SoC specific settings
1372  * @irq: interrupt
1373  * @enable: enable or disable the interrupt
1374  *
1375  * Note that this currently assumes one interrupt per pinctrl
1376  * register that is typically used for wake-up events.
1377  */
1378 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1379                                int irq, const bool enable)
1380 {
1381         struct pcs_device *pcs;
1382         struct list_head *pos;
1383         unsigned mask;
1384
1385         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1386         list_for_each(pos, &pcs->irqs) {
1387                 struct pcs_interrupt *pcswi;
1388                 unsigned soc_mask;
1389
1390                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1391                 if (irq != pcswi->irq)
1392                         continue;
1393
1394                 soc_mask = pcs_soc->irq_enable_mask;
1395                 raw_spin_lock(&pcs->lock);
1396                 mask = pcs->read(pcswi->reg);
1397                 if (enable)
1398                         mask |= soc_mask;
1399                 else
1400                         mask &= ~soc_mask;
1401                 pcs->write(mask, pcswi->reg);
1402
1403                 /* flush posted write */
1404                 mask = pcs->read(pcswi->reg);
1405                 raw_spin_unlock(&pcs->lock);
1406         }
1407
1408         if (pcs_soc->rearm)
1409                 pcs_soc->rearm();
1410 }
1411
1412 /**
1413  * pcs_irq_mask() - mask pinctrl interrupt
1414  * @d: interrupt data
1415  */
1416 static void pcs_irq_mask(struct irq_data *d)
1417 {
1418         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1419
1420         pcs_irq_set(pcs_soc, d->irq, false);
1421 }
1422
1423 /**
1424  * pcs_irq_unmask() - unmask pinctrl interrupt
1425  * @d: interrupt data
1426  */
1427 static void pcs_irq_unmask(struct irq_data *d)
1428 {
1429         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1430
1431         pcs_irq_set(pcs_soc, d->irq, true);
1432 }
1433
1434 /**
1435  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1436  * @d: interrupt data
1437  * @state: wake-up state
1438  *
1439  * Note that this should be called only for suspend and resume.
1440  * For runtime PM, the wake-up events should be enabled by default.
1441  */
1442 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1443 {
1444         if (state)
1445                 pcs_irq_unmask(d);
1446         else
1447                 pcs_irq_mask(d);
1448
1449         return 0;
1450 }
1451
1452 /**
1453  * pcs_irq_handle() - common interrupt handler
1454  * @pcs_soc: SoC specific settings
1455  *
1456  * Note that this currently assumes we have one interrupt bit per
1457  * mux register. This interrupt is typically used for wake-up events.
1458  * For more complex interrupts different handlers can be specified.
1459  */
1460 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1461 {
1462         struct pcs_device *pcs;
1463         struct list_head *pos;
1464         int count = 0;
1465
1466         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1467         list_for_each(pos, &pcs->irqs) {
1468                 struct pcs_interrupt *pcswi;
1469                 unsigned mask;
1470
1471                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1472                 raw_spin_lock(&pcs->lock);
1473                 mask = pcs->read(pcswi->reg);
1474                 raw_spin_unlock(&pcs->lock);
1475                 if (mask & pcs_soc->irq_status_mask) {
1476                         generic_handle_irq(irq_find_mapping(pcs->domain,
1477                                                             pcswi->hwirq));
1478                         count++;
1479                 }
1480         }
1481
1482         return count;
1483 }
1484
1485 /**
1486  * pcs_irq_handler() - handler for the shared interrupt case
1487  * @irq: interrupt
1488  * @d: data
1489  *
1490  * Use this for cases where multiple instances of
1491  * pinctrl-single share a single interrupt like on omaps.
1492  */
1493 static irqreturn_t pcs_irq_handler(int irq, void *d)
1494 {
1495         struct pcs_soc_data *pcs_soc = d;
1496
1497         return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1498 }
1499
1500 /**
1501  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1502  * @desc: interrupt descriptor
1503  *
1504  * Use this if you have a separate interrupt for each
1505  * pinctrl-single instance.
1506  */
1507 static void pcs_irq_chain_handler(struct irq_desc *desc)
1508 {
1509         struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1510         struct irq_chip *chip;
1511
1512         chip = irq_desc_get_chip(desc);
1513         chained_irq_enter(chip, desc);
1514         pcs_irq_handle(pcs_soc);
1515         /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1516         chained_irq_exit(chip, desc);
1517 }
1518
1519 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1520                              irq_hw_number_t hwirq)
1521 {
1522         struct pcs_soc_data *pcs_soc = d->host_data;
1523         struct pcs_device *pcs;
1524         struct pcs_interrupt *pcswi;
1525
1526         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1527         pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1528         if (!pcswi)
1529                 return -ENOMEM;
1530
1531         pcswi->reg = pcs->base + hwirq;
1532         pcswi->hwirq = hwirq;
1533         pcswi->irq = irq;
1534
1535         mutex_lock(&pcs->mutex);
1536         list_add_tail(&pcswi->node, &pcs->irqs);
1537         mutex_unlock(&pcs->mutex);
1538
1539         irq_set_chip_data(irq, pcs_soc);
1540         irq_set_chip_and_handler(irq, &pcs->chip,
1541                                  handle_level_irq);
1542         irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1543         irq_set_noprobe(irq);
1544
1545         return 0;
1546 }
1547
1548 static const struct irq_domain_ops pcs_irqdomain_ops = {
1549         .map = pcs_irqdomain_map,
1550         .xlate = irq_domain_xlate_onecell,
1551 };
1552
1553 /**
1554  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1555  * @pcs: pcs driver instance
1556  * @np: device node pointer
1557  */
1558 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1559                                         struct device_node *np)
1560 {
1561         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1562         const char *name = "pinctrl";
1563         int num_irqs;
1564
1565         if (!pcs_soc->irq_enable_mask ||
1566             !pcs_soc->irq_status_mask) {
1567                 pcs_soc->irq = -1;
1568                 return -EINVAL;
1569         }
1570
1571         INIT_LIST_HEAD(&pcs->irqs);
1572         pcs->chip.name = name;
1573         pcs->chip.irq_ack = pcs_irq_mask;
1574         pcs->chip.irq_mask = pcs_irq_mask;
1575         pcs->chip.irq_unmask = pcs_irq_unmask;
1576         pcs->chip.irq_set_wake = pcs_irq_set_wake;
1577
1578         if (PCS_QUIRK_HAS_SHARED_IRQ) {
1579                 int res;
1580
1581                 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1582                                   IRQF_SHARED | IRQF_NO_SUSPEND |
1583                                   IRQF_NO_THREAD,
1584                                   name, pcs_soc);
1585                 if (res) {
1586                         pcs_soc->irq = -1;
1587                         return res;
1588                 }
1589         } else {
1590                 irq_set_chained_handler_and_data(pcs_soc->irq,
1591                                                  pcs_irq_chain_handler,
1592                                                  pcs_soc);
1593         }
1594
1595         /*
1596          * We can use the register offset as the hardirq
1597          * number as irq_domain_add_simple maps them lazily.
1598          * This way we can easily support more than one
1599          * interrupt per function if needed.
1600          */
1601         num_irqs = pcs->size;
1602
1603         pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1604                                             &pcs_irqdomain_ops,
1605                                             pcs_soc);
1606         if (!pcs->domain) {
1607                 irq_set_chained_handler(pcs_soc->irq, NULL);
1608                 return -EINVAL;
1609         }
1610
1611         return 0;
1612 }
1613
1614 #ifdef CONFIG_PM
1615 static int pcs_save_context(struct pcs_device *pcs)
1616 {
1617         int i, mux_bytes;
1618         u64 *regsl;
1619         u32 *regsw;
1620         u16 *regshw;
1621
1622         mux_bytes = pcs->width / BITS_PER_BYTE;
1623
1624         if (!pcs->saved_vals) {
1625                 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1626                 if (!pcs->saved_vals)
1627                         return -ENOMEM;
1628         }
1629
1630         switch (pcs->width) {
1631         case 64:
1632                 regsl = pcs->saved_vals;
1633                 for (i = 0; i < pcs->size; i += mux_bytes)
1634                         *regsl++ = pcs->read(pcs->base + i);
1635                 break;
1636         case 32:
1637                 regsw = pcs->saved_vals;
1638                 for (i = 0; i < pcs->size; i += mux_bytes)
1639                         *regsw++ = pcs->read(pcs->base + i);
1640                 break;
1641         case 16:
1642                 regshw = pcs->saved_vals;
1643                 for (i = 0; i < pcs->size; i += mux_bytes)
1644                         *regshw++ = pcs->read(pcs->base + i);
1645                 break;
1646         }
1647
1648         return 0;
1649 }
1650
1651 static void pcs_restore_context(struct pcs_device *pcs)
1652 {
1653         int i, mux_bytes;
1654         u64 *regsl;
1655         u32 *regsw;
1656         u16 *regshw;
1657
1658         mux_bytes = pcs->width / BITS_PER_BYTE;
1659
1660         switch (pcs->width) {
1661         case 64:
1662                 regsl = pcs->saved_vals;
1663                 for (i = 0; i < pcs->size; i += mux_bytes)
1664                         pcs->write(*regsl++, pcs->base + i);
1665                 break;
1666         case 32:
1667                 regsw = pcs->saved_vals;
1668                 for (i = 0; i < pcs->size; i += mux_bytes)
1669                         pcs->write(*regsw++, pcs->base + i);
1670                 break;
1671         case 16:
1672                 regshw = pcs->saved_vals;
1673                 for (i = 0; i < pcs->size; i += mux_bytes)
1674                         pcs->write(*regshw++, pcs->base + i);
1675                 break;
1676         }
1677 }
1678
1679 static int pinctrl_single_suspend(struct platform_device *pdev,
1680                                         pm_message_t state)
1681 {
1682         struct pcs_device *pcs;
1683
1684         pcs = platform_get_drvdata(pdev);
1685         if (!pcs)
1686                 return -EINVAL;
1687
1688         if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1689                 int ret;
1690
1691                 ret = pcs_save_context(pcs);
1692                 if (ret < 0)
1693                         return ret;
1694         }
1695
1696         return pinctrl_force_sleep(pcs->pctl);
1697 }
1698
1699 static int pinctrl_single_resume(struct platform_device *pdev)
1700 {
1701         struct pcs_device *pcs;
1702
1703         pcs = platform_get_drvdata(pdev);
1704         if (!pcs)
1705                 return -EINVAL;
1706
1707         if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1708                 pcs_restore_context(pcs);
1709
1710         return pinctrl_force_default(pcs->pctl);
1711 }
1712 #endif
1713
1714 /**
1715  * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1716  * @pcs: pinctrl driver instance
1717  * @np: device tree node
1718  * @cells: number of cells
1719  *
1720  * Handle legacy binding with no #pinctrl-cells. This should be
1721  * always two pinctrl-single,bit-per-mux and one for others.
1722  * At some point we may want to consider removing this.
1723  */
1724 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1725                                            struct device_node *np,
1726                                            int cells)
1727 {
1728         struct property *p;
1729         const char *name = "#pinctrl-cells";
1730         int error;
1731         u32 val;
1732
1733         error = of_property_read_u32(np, name, &val);
1734         if (!error)
1735                 return 0;
1736
1737         dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1738                  name, cells);
1739
1740         p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1741         if (!p)
1742                 return -ENOMEM;
1743
1744         p->length = sizeof(__be32);
1745         p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1746         if (!p->value)
1747                 return -ENOMEM;
1748         *(__be32 *)p->value = cpu_to_be32(cells);
1749
1750         p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1751         if (!p->name)
1752                 return -ENOMEM;
1753
1754         pcs->missing_nr_pinctrl_cells = p;
1755
1756 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1757         error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1758 #endif
1759
1760         return error;
1761 }
1762
1763 static int pcs_probe(struct platform_device *pdev)
1764 {
1765         struct device_node *np = pdev->dev.of_node;
1766         struct pcs_pdata *pdata;
1767         struct resource *res;
1768         struct pcs_device *pcs;
1769         const struct pcs_soc_data *soc;
1770         int ret;
1771
1772         soc = of_device_get_match_data(&pdev->dev);
1773         if (WARN_ON(!soc))
1774                 return -EINVAL;
1775
1776         pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1777         if (!pcs)
1778                 return -ENOMEM;
1779
1780         pcs->dev = &pdev->dev;
1781         pcs->np = np;
1782         raw_spin_lock_init(&pcs->lock);
1783         mutex_init(&pcs->mutex);
1784         INIT_LIST_HEAD(&pcs->gpiofuncs);
1785         pcs->flags = soc->flags;
1786         memcpy(&pcs->socdata, soc, sizeof(*soc));
1787
1788         ret = of_property_read_u32(np, "pinctrl-single,register-width",
1789                                    &pcs->width);
1790         if (ret) {
1791                 dev_err(pcs->dev, "register width not specified\n");
1792
1793                 return ret;
1794         }
1795
1796         ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1797                                    &pcs->fmask);
1798         if (!ret) {
1799                 pcs->fshift = __ffs(pcs->fmask);
1800                 pcs->fmax = pcs->fmask >> pcs->fshift;
1801         } else {
1802                 /* If mask property doesn't exist, function mux is invalid. */
1803                 pcs->fmask = 0;
1804                 pcs->fshift = 0;
1805                 pcs->fmax = 0;
1806         }
1807
1808         ret = of_property_read_u32(np, "pinctrl-single,function-off",
1809                                         &pcs->foff);
1810         if (ret)
1811                 pcs->foff = PCS_OFF_DISABLED;
1812
1813         pcs->bits_per_mux = of_property_read_bool(np,
1814                                                   "pinctrl-single,bit-per-mux");
1815         ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1816                                               pcs->bits_per_mux ? 2 : 1);
1817         if (ret) {
1818                 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1819
1820                 return ret;
1821         }
1822
1823         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1824         if (!res) {
1825                 dev_err(pcs->dev, "could not get resource\n");
1826                 return -ENODEV;
1827         }
1828
1829         pcs->res = devm_request_mem_region(pcs->dev, res->start,
1830                         resource_size(res), DRIVER_NAME);
1831         if (!pcs->res) {
1832                 dev_err(pcs->dev, "could not get mem_region\n");
1833                 return -EBUSY;
1834         }
1835
1836         pcs->size = resource_size(pcs->res);
1837         pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1838         if (!pcs->base) {
1839                 dev_err(pcs->dev, "could not ioremap\n");
1840                 return -ENODEV;
1841         }
1842
1843         platform_set_drvdata(pdev, pcs);
1844
1845         switch (pcs->width) {
1846         case 8:
1847                 pcs->read = pcs_readb;
1848                 pcs->write = pcs_writeb;
1849                 break;
1850         case 16:
1851                 pcs->read = pcs_readw;
1852                 pcs->write = pcs_writew;
1853                 break;
1854         case 32:
1855                 pcs->read = pcs_readl;
1856                 pcs->write = pcs_writel;
1857                 break;
1858         default:
1859                 break;
1860         }
1861
1862         pcs->desc.name = DRIVER_NAME;
1863         pcs->desc.pctlops = &pcs_pinctrl_ops;
1864         pcs->desc.pmxops = &pcs_pinmux_ops;
1865         if (PCS_HAS_PINCONF)
1866                 pcs->desc.confops = &pcs_pinconf_ops;
1867         pcs->desc.owner = THIS_MODULE;
1868
1869         ret = pcs_allocate_pin_table(pcs);
1870         if (ret < 0)
1871                 goto free;
1872
1873         ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1874         if (ret) {
1875                 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1876                 goto free;
1877         }
1878
1879         ret = pcs_add_gpio_func(np, pcs);
1880         if (ret < 0)
1881                 goto free;
1882
1883         pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1884         if (pcs->socdata.irq)
1885                 pcs->flags |= PCS_FEAT_IRQ;
1886
1887         /* We still need auxdata for some omaps for PRM interrupts */
1888         pdata = dev_get_platdata(&pdev->dev);
1889         if (pdata) {
1890                 if (pdata->rearm)
1891                         pcs->socdata.rearm = pdata->rearm;
1892                 if (pdata->irq) {
1893                         pcs->socdata.irq = pdata->irq;
1894                         pcs->flags |= PCS_FEAT_IRQ;
1895                 }
1896         }
1897
1898         if (PCS_HAS_IRQ) {
1899                 ret = pcs_irq_init_chained_handler(pcs, np);
1900                 if (ret < 0)
1901                         dev_warn(pcs->dev, "initialized with no interrupts\n");
1902         }
1903
1904         dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1905
1906         return pinctrl_enable(pcs->pctl);
1907
1908 free:
1909         pcs_free_resources(pcs);
1910
1911         return ret;
1912 }
1913
1914 static int pcs_remove(struct platform_device *pdev)
1915 {
1916         struct pcs_device *pcs = platform_get_drvdata(pdev);
1917
1918         if (!pcs)
1919                 return 0;
1920
1921         pcs_free_resources(pcs);
1922
1923         return 0;
1924 }
1925
1926 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1927         .flags = PCS_QUIRK_SHARED_IRQ,
1928         .irq_enable_mask = (1 << 14),   /* OMAP_WAKEUP_EN */
1929         .irq_status_mask = (1 << 15),   /* OMAP_WAKEUP_EVENT */
1930 };
1931
1932 static const struct pcs_soc_data pinctrl_single_dra7 = {
1933         .irq_enable_mask = (1 << 24),   /* WAKEUPENABLE */
1934         .irq_status_mask = (1 << 25),   /* WAKEUPEVENT */
1935 };
1936
1937 static const struct pcs_soc_data pinctrl_single_am437x = {
1938         .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1939         .irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */
1940         .irq_status_mask = (1 << 30),   /* OMAP_WAKEUP_EVENT */
1941 };
1942
1943 static const struct pcs_soc_data pinctrl_single = {
1944 };
1945
1946 static const struct pcs_soc_data pinconf_single = {
1947         .flags = PCS_FEAT_PINCONF,
1948 };
1949
1950 static const struct of_device_id pcs_of_match[] = {
1951         { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1952         { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1953         { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1954         { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1955         { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1956         { .compatible = "pinctrl-single", .data = &pinctrl_single },
1957         { .compatible = "pinconf-single", .data = &pinconf_single },
1958         { },
1959 };
1960 MODULE_DEVICE_TABLE(of, pcs_of_match);
1961
1962 static struct platform_driver pcs_driver = {
1963         .probe          = pcs_probe,
1964         .remove         = pcs_remove,
1965         .driver = {
1966                 .name           = DRIVER_NAME,
1967                 .of_match_table = pcs_of_match,
1968         },
1969 #ifdef CONFIG_PM
1970         .suspend = pinctrl_single_suspend,
1971         .resume = pinctrl_single_resume,
1972 #endif
1973 };
1974
1975 module_platform_driver(pcs_driver);
1976
1977 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1978 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1979 MODULE_LICENSE("GPL v2");