2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
5 * Copyright (C) 2012 Texas Instruments, Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/list.h>
18 #include <linux/interrupt.h>
20 #include <linux/irqchip/chained_irq.h>
23 #include <linux/of_device.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
34 #include "devicetree.h"
38 #define DRIVER_NAME "pinctrl-single"
39 #define PCS_OFF_DISABLED ~0U
42 * struct pcs_func_vals - mux function register offset and value pair
43 * @reg: register virtual address
44 * @val: register value
46 struct pcs_func_vals {
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
54 * and value, enable, disable, mask
55 * @param: config parameter
56 * @val: user input bits in the pinconf register
57 * @enable: enable bits in the pinconf register
58 * @disable: disable bits in the pinconf register
59 * @mask: mask bits in the register value
61 struct pcs_conf_vals {
62 enum pin_config_param param;
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
71 * @name: property name in DTS file
72 * @param: config parameter
74 struct pcs_conf_type {
76 enum pin_config_param param;
80 * struct pcs_function - pinctrl function
81 * @name: pinctrl function name
82 * @vals: register and vals array
83 * @nvals: number of entries in vals array
84 * @pgnames: array of pingroup names the function uses
85 * @npgnames: number of pingroup names the function uses
90 struct pcs_func_vals *vals;
94 struct pcs_conf_vals *conf;
96 struct list_head node;
100 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
101 * @offset: offset base of pins
102 * @npins: number pins with the same mux value of gpio function
103 * @gpiofunc: mux value of gpio function
106 struct pcs_gpiofunc_range {
110 struct list_head node;
114 * struct pcs_data - wrapper for data needed by pinctrl framework
116 * @cur: index to current element
118 * REVISIT: We should be able to drop this eventually by adding
119 * support for registering pins individually in the pinctrl
120 * framework for those drivers that don't need a static array.
123 struct pinctrl_pin_desc *pa;
128 * struct pcs_soc_data - SoC specific settings
129 * @flags: initial SoC specific PCS_FEAT_xxx values
130 * @irq: optional interrupt for the controller
131 * @irq_enable_mask: optional SoC specific interrupt enable mask
132 * @irq_status_mask: optional SoC specific interrupt status mask
133 * @rearm: optional SoC specific wake-up rearm function
135 struct pcs_soc_data {
138 unsigned irq_enable_mask;
139 unsigned irq_status_mask;
144 * struct pcs_device - pinctrl device instance
146 * @base: virtual address of the controller
147 * @size: size of the ioremapped area
149 * @np: device tree node
150 * @pctl: pin controller device
151 * @flags: mask of PCS_FEAT_xxx values
152 * @missing_nr_pinctrl_cells: for legacy binding, may go away
153 * @socdata: soc specific data
154 * @lock: spinlock for register access
155 * @mutex: mutex protecting the lists
156 * @width: bits per mux register
157 * @fmask: function register mask
158 * @fshift: function register shift
159 * @foff: value to turn mux off
160 * @fmax: max number of functions in fmask
161 * @bits_per_mux: number of bits per mux
162 * @bits_per_pin: number of bits per pin
163 * @pins: physical pins on the SoC
164 * @gpiofuncs: list of gpio functions
165 * @irqs: list of interrupt registers
166 * @chip: chip container for this instance
167 * @domain: IRQ domain for this instance
168 * @desc: pin controller descriptor
169 * @read: register read function to use
170 * @write: register write function to use
173 struct resource *res;
177 struct device_node *np;
178 struct pinctrl_dev *pctl;
180 #define PCS_QUIRK_SHARED_IRQ (1 << 2)
181 #define PCS_FEAT_IRQ (1 << 1)
182 #define PCS_FEAT_PINCONF (1 << 0)
183 struct property *missing_nr_pinctrl_cells;
184 struct pcs_soc_data socdata;
193 unsigned bits_per_pin;
194 struct pcs_data pins;
195 struct list_head gpiofuncs;
196 struct list_head irqs;
197 struct irq_chip chip;
198 struct irq_domain *domain;
199 struct pinctrl_desc desc;
200 unsigned (*read)(void __iomem *reg);
201 void (*write)(unsigned val, void __iomem *reg);
204 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
205 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
206 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
208 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
209 unsigned long *config);
210 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
211 unsigned long *configs, unsigned num_configs);
213 static enum pin_config_param pcs_bias[] = {
214 PIN_CONFIG_BIAS_PULL_DOWN,
215 PIN_CONFIG_BIAS_PULL_UP,
219 * This lock class tells lockdep that irqchip core that this single
220 * pinctrl can be in a different category than its parents, so it won't
221 * report false recursion.
223 static struct lock_class_key pcs_lock_class;
225 /* Class for the IRQ request mutex */
226 static struct lock_class_key pcs_request_class;
229 * REVISIT: Reads and writes could eventually use regmap or something
230 * generic. But at least on omaps, some mux registers are performance
231 * critical as they may need to be remuxed every time before and after
232 * idle. Adding tests for register access width for every read and
233 * write like regmap is doing is not desired, and caching the registers
234 * does not help in this case.
237 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
242 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
247 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
252 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
257 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
262 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
267 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
271 struct pcs_device *pcs;
272 unsigned val, mux_bytes;
273 unsigned long offset;
276 pcs = pinctrl_dev_get_drvdata(pctldev);
278 mux_bytes = pcs->width / BITS_PER_BYTE;
279 offset = pin * mux_bytes;
280 val = pcs->read(pcs->base + offset);
281 pa = pcs->res->start + offset;
283 seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
286 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
287 struct pinctrl_map *map, unsigned num_maps)
289 struct pcs_device *pcs;
291 pcs = pinctrl_dev_get_drvdata(pctldev);
292 devm_kfree(pcs->dev, map);
295 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
296 struct device_node *np_config,
297 struct pinctrl_map **map, unsigned *num_maps);
299 static const struct pinctrl_ops pcs_pinctrl_ops = {
300 .get_groups_count = pinctrl_generic_get_group_count,
301 .get_group_name = pinctrl_generic_get_group_name,
302 .get_group_pins = pinctrl_generic_get_group_pins,
303 .pin_dbg_show = pcs_pin_dbg_show,
304 .dt_node_to_map = pcs_dt_node_to_map,
305 .dt_free_map = pcs_dt_free_map,
308 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
309 struct pcs_function **func)
311 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
312 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
313 const struct pinctrl_setting_mux *setting;
314 struct function_desc *function;
317 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
318 setting = pdesc->mux_setting;
321 fselector = setting->func;
322 function = pinmux_generic_get_function(pctldev, fselector);
323 *func = function->data;
325 dev_err(pcs->dev, "%s could not find function%i\n",
326 __func__, fselector);
332 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
335 struct pcs_device *pcs;
336 struct function_desc *function;
337 struct pcs_function *func;
340 pcs = pinctrl_dev_get_drvdata(pctldev);
341 /* If function mask is null, needn't enable it. */
344 function = pinmux_generic_get_function(pctldev, fselector);
345 func = function->data;
349 dev_dbg(pcs->dev, "enabling %s function%i\n",
350 func->name, fselector);
352 for (i = 0; i < func->nvals; i++) {
353 struct pcs_func_vals *vals;
357 vals = &func->vals[i];
358 raw_spin_lock_irqsave(&pcs->lock, flags);
359 val = pcs->read(vals->reg);
361 if (pcs->bits_per_mux)
367 val |= (vals->val & mask);
368 pcs->write(val, vals->reg);
369 raw_spin_unlock_irqrestore(&pcs->lock, flags);
375 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
376 struct pinctrl_gpio_range *range, unsigned pin)
378 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
379 struct pcs_gpiofunc_range *frange = NULL;
380 struct list_head *pos, *tmp;
384 /* If function mask is null, return directly. */
388 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
389 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
390 if (pin >= frange->offset + frange->npins
391 || pin < frange->offset)
393 mux_bytes = pcs->width / BITS_PER_BYTE;
395 if (pcs->bits_per_mux) {
396 int byte_num, offset, pin_shift;
398 byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
399 offset = (byte_num / mux_bytes) * mux_bytes;
400 pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
403 data = pcs->read(pcs->base + offset);
404 data &= ~(pcs->fmask << pin_shift);
405 data |= frange->gpiofunc << pin_shift;
406 pcs->write(data, pcs->base + offset);
408 data = pcs->read(pcs->base + pin * mux_bytes);
410 data |= frange->gpiofunc;
411 pcs->write(data, pcs->base + pin * mux_bytes);
418 static const struct pinmux_ops pcs_pinmux_ops = {
419 .get_functions_count = pinmux_generic_get_function_count,
420 .get_function_name = pinmux_generic_get_function_name,
421 .get_function_groups = pinmux_generic_get_function_groups,
422 .set_mux = pcs_set_mux,
423 .gpio_request_enable = pcs_request_gpio,
426 /* Clear BIAS value */
427 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
429 unsigned long config;
431 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
432 config = pinconf_to_config_packed(pcs_bias[i], 0);
433 pcs_pinconf_set(pctldev, pin, &config, 1);
438 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
439 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
441 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
443 unsigned long config;
446 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
447 config = pinconf_to_config_packed(pcs_bias[i], 0);
448 if (!pcs_pinconf_get(pctldev, pin, &config))
456 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
457 unsigned pin, unsigned long *config)
459 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
460 struct pcs_function *func;
461 enum pin_config_param param;
462 unsigned offset = 0, data = 0, i, j, ret;
464 ret = pcs_get_function(pctldev, pin, &func);
468 for (i = 0; i < func->nconfs; i++) {
469 param = pinconf_to_config_param(*config);
470 if (param == PIN_CONFIG_BIAS_DISABLE) {
471 if (pcs_pinconf_bias_disable(pctldev, pin)) {
477 } else if (param != func->conf[i].param) {
481 offset = pin * (pcs->width / BITS_PER_BYTE);
482 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
483 switch (func->conf[i].param) {
485 case PIN_CONFIG_BIAS_PULL_DOWN:
486 case PIN_CONFIG_BIAS_PULL_UP:
487 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
488 if ((data != func->conf[i].enable) ||
489 (data == func->conf[i].disable))
494 case PIN_CONFIG_INPUT_SCHMITT:
495 for (j = 0; j < func->nconfs; j++) {
496 switch (func->conf[j].param) {
497 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
498 if (data != func->conf[j].enable)
507 case PIN_CONFIG_DRIVE_STRENGTH:
508 case PIN_CONFIG_SLEW_RATE:
509 case PIN_CONFIG_LOW_POWER_MODE:
519 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
520 unsigned pin, unsigned long *configs,
521 unsigned num_configs)
523 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
524 struct pcs_function *func;
525 unsigned offset = 0, shift = 0, i, data, ret;
529 ret = pcs_get_function(pctldev, pin, &func);
533 for (j = 0; j < num_configs; j++) {
534 for (i = 0; i < func->nconfs; i++) {
535 if (pinconf_to_config_param(configs[j])
536 != func->conf[i].param)
539 offset = pin * (pcs->width / BITS_PER_BYTE);
540 data = pcs->read(pcs->base + offset);
541 arg = pinconf_to_config_argument(configs[j]);
542 switch (func->conf[i].param) {
544 case PIN_CONFIG_INPUT_SCHMITT:
545 case PIN_CONFIG_DRIVE_STRENGTH:
546 case PIN_CONFIG_SLEW_RATE:
547 case PIN_CONFIG_LOW_POWER_MODE:
548 shift = ffs(func->conf[i].mask) - 1;
549 data &= ~func->conf[i].mask;
550 data |= (arg << shift) & func->conf[i].mask;
553 case PIN_CONFIG_BIAS_DISABLE:
554 pcs_pinconf_clear_bias(pctldev, pin);
556 case PIN_CONFIG_BIAS_PULL_DOWN:
557 case PIN_CONFIG_BIAS_PULL_UP:
559 pcs_pinconf_clear_bias(pctldev, pin);
561 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
562 data &= ~func->conf[i].mask;
564 data |= func->conf[i].enable;
566 data |= func->conf[i].disable;
571 pcs->write(data, pcs->base + offset);
575 if (i >= func->nconfs)
577 } /* for each config */
582 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
583 unsigned group, unsigned long *config)
585 const unsigned *pins;
586 unsigned npins, old = 0;
589 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
592 for (i = 0; i < npins; i++) {
593 if (pcs_pinconf_get(pctldev, pins[i], config))
595 /* configs do not match between two pins */
596 if (i && (old != *config))
603 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
604 unsigned group, unsigned long *configs,
605 unsigned num_configs)
607 const unsigned *pins;
611 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
614 for (i = 0; i < npins; i++) {
615 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
621 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
622 struct seq_file *s, unsigned pin)
626 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
627 struct seq_file *s, unsigned selector)
631 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
633 unsigned long config)
635 pinconf_generic_dump_config(pctldev, s, config);
638 static const struct pinconf_ops pcs_pinconf_ops = {
639 .pin_config_get = pcs_pinconf_get,
640 .pin_config_set = pcs_pinconf_set,
641 .pin_config_group_get = pcs_pinconf_group_get,
642 .pin_config_group_set = pcs_pinconf_group_set,
643 .pin_config_dbg_show = pcs_pinconf_dbg_show,
644 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
645 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
650 * pcs_add_pin() - add a pin to the static per controller pin array
651 * @pcs: pcs driver instance
652 * @offset: register offset from base
654 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
657 struct pcs_soc_data *pcs_soc = &pcs->socdata;
658 struct pinctrl_pin_desc *pin;
662 if (i >= pcs->desc.npins) {
663 dev_err(pcs->dev, "too many pins, max %i\n",
668 if (pcs_soc->irq_enable_mask) {
671 val = pcs->read(pcs->base + offset);
672 if (val & pcs_soc->irq_enable_mask) {
673 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
674 (unsigned long)pcs->res->start + offset, val);
675 val &= ~pcs_soc->irq_enable_mask;
676 pcs->write(val, pcs->base + offset);
680 pin = &pcs->pins.pa[i];
688 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
689 * @pcs: pcs driver instance
691 * In case of errors, resources are freed in pcs_free_resources.
693 * If your hardware needs holes in the address space, then just set
694 * up multiple driver instances.
696 static int pcs_allocate_pin_table(struct pcs_device *pcs)
698 int mux_bytes, nr_pins, i;
699 int num_pins_in_register = 0;
701 mux_bytes = pcs->width / BITS_PER_BYTE;
703 if (pcs->bits_per_mux) {
704 pcs->bits_per_pin = fls(pcs->fmask);
705 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
706 num_pins_in_register = pcs->width / pcs->bits_per_pin;
708 nr_pins = pcs->size / mux_bytes;
711 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
712 pcs->pins.pa = devm_kzalloc(pcs->dev,
713 sizeof(*pcs->pins.pa) * nr_pins,
718 pcs->desc.pins = pcs->pins.pa;
719 pcs->desc.npins = nr_pins;
721 for (i = 0; i < pcs->desc.npins; i++) {
727 if (pcs->bits_per_mux) {
728 byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
729 offset = (byte_num / mux_bytes) * mux_bytes;
730 pin_pos = i % num_pins_in_register;
732 offset = i * mux_bytes;
734 res = pcs_add_pin(pcs, offset, pin_pos);
736 dev_err(pcs->dev, "error adding pins: %i\n", res);
745 * pcs_add_function() - adds a new function to the function list
746 * @pcs: pcs driver instance
747 * @np: device node of the mux entry
748 * @name: name of the function
749 * @vals: array of mux register value pairs used by the function
750 * @nvals: number of mux register value pairs
751 * @pgnames: array of pingroup names for the function
752 * @npgnames: number of pingroup names
754 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
755 struct device_node *np,
757 struct pcs_func_vals *vals,
759 const char **pgnames,
762 struct pcs_function *function;
765 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
769 function->vals = vals;
770 function->nvals = nvals;
772 res = pinmux_generic_add_function(pcs->pctl, name,
782 * pcs_get_pin_by_offset() - get a pin index based on the register offset
783 * @pcs: pcs driver instance
784 * @offset: register offset from the base
786 * Note that this is OK as long as the pins are in a static array.
788 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
792 if (offset >= pcs->size) {
793 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
798 if (pcs->bits_per_mux)
799 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
801 index = offset / (pcs->width / BITS_PER_BYTE);
807 * check whether data matches enable bits or disable bits
808 * Return value: 1 for matching enable bits, 0 for matching disable bits,
809 * and negative value for matching failure.
811 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
817 else if (data == disable)
822 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
823 unsigned value, unsigned enable, unsigned disable,
826 (*conf)->param = param;
827 (*conf)->val = value;
828 (*conf)->enable = enable;
829 (*conf)->disable = disable;
830 (*conf)->mask = mask;
834 static void add_setting(unsigned long **setting, enum pin_config_param param,
837 **setting = pinconf_to_config_packed(param, arg);
841 /* add pinconf setting with 2 parameters */
842 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
843 const char *name, enum pin_config_param param,
844 struct pcs_conf_vals **conf, unsigned long **settings)
846 unsigned value[2], shift;
849 ret = of_property_read_u32_array(np, name, value, 2);
852 /* set value & mask */
853 value[0] &= value[1];
854 shift = ffs(value[1]) - 1;
855 /* skip enable & disable */
856 add_config(conf, param, value[0], 0, 0, value[1]);
857 add_setting(settings, param, value[0] >> shift);
860 /* add pinconf setting with 4 parameters */
861 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
862 const char *name, enum pin_config_param param,
863 struct pcs_conf_vals **conf, unsigned long **settings)
868 /* value to set, enable, disable, mask */
869 ret = of_property_read_u32_array(np, name, value, 4);
873 dev_err(pcs->dev, "mask field of the property can't be 0\n");
876 value[0] &= value[3];
877 value[1] &= value[3];
878 value[2] &= value[3];
879 ret = pcs_config_match(value[0], value[1], value[2]);
881 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
882 add_config(conf, param, value[0], value[1], value[2], value[3]);
883 add_setting(settings, param, ret);
886 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
887 struct pcs_function *func,
888 struct pinctrl_map **map)
891 struct pinctrl_map *m = *map;
892 int i = 0, nconfs = 0;
893 unsigned long *settings = NULL, *s = NULL;
894 struct pcs_conf_vals *conf = NULL;
895 static const struct pcs_conf_type prop2[] = {
896 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
897 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
898 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
899 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
901 static const struct pcs_conf_type prop4[] = {
902 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
903 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
904 { "pinctrl-single,input-schmitt-enable",
905 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
908 /* If pinconf isn't supported, don't parse properties in below. */
909 if (!PCS_HAS_PINCONF)
912 /* cacluate how much properties are supported in current node */
913 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
914 if (of_find_property(np, prop2[i].name, NULL))
917 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
918 if (of_find_property(np, prop4[i].name, NULL))
924 func->conf = devm_kzalloc(pcs->dev,
925 sizeof(struct pcs_conf_vals) * nconfs,
929 func->nconfs = nconfs;
930 conf = &(func->conf[0]);
932 settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
938 for (i = 0; i < ARRAY_SIZE(prop2); i++)
939 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
941 for (i = 0; i < ARRAY_SIZE(prop4); i++)
942 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
944 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
945 m->data.configs.group_or_pin = np->name;
946 m->data.configs.configs = settings;
947 m->data.configs.num_configs = nconfs;
952 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
953 * @pctldev: pin controller device
954 * @pcs: pinctrl driver instance
955 * @np: device node of the mux entry
957 * @num_maps: number of map
958 * @pgnames: pingroup names
960 * Note that this binding currently supports only sets of one register + value.
962 * Also note that this driver tries to avoid understanding pin and function
963 * names because of the extra bloat they would cause especially in the case of
964 * a large number of pins. This driver just sets what is specified for the board
965 * in the .dts file. Further user space debugging tools can be developed to
966 * decipher the pin and function names using debugfs.
968 * If you are concerned about the boot time, set up the static pins in
969 * the bootloader, and only set up selected pins as device tree entries.
971 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
972 struct device_node *np,
973 struct pinctrl_map **map,
975 const char **pgnames)
977 const char *name = "pinctrl-single,pins";
978 struct pcs_func_vals *vals;
979 int rows, *pins, found = 0, res = -ENOMEM, i;
980 struct pcs_function *function;
982 rows = pinctrl_count_index_with_args(np, name);
984 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
988 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
992 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
996 for (i = 0; i < rows; i++) {
997 struct of_phandle_args pinctrl_spec;
1001 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1005 if (pinctrl_spec.args_count < 2) {
1006 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1007 pinctrl_spec.args_count);
1011 /* Index plus one value cell */
1012 offset = pinctrl_spec.args[0];
1013 vals[found].reg = pcs->base + offset;
1014 vals[found].val = pinctrl_spec.args[1];
1016 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n",
1017 pinctrl_spec.np->name, offset, pinctrl_spec.args[1]);
1019 pin = pcs_get_pin_by_offset(pcs, offset);
1022 "could not add functions for %s %ux\n",
1026 pins[found++] = pin;
1029 pgnames[0] = np->name;
1030 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1036 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1040 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1041 (*map)->data.mux.group = np->name;
1042 (*map)->data.mux.function = np->name;
1044 if (PCS_HAS_PINCONF) {
1045 res = pcs_parse_pinconf(pcs, np, function, map);
1047 goto free_pingroups;
1055 pinctrl_generic_remove_last_group(pcs->pctl);
1058 pinmux_generic_remove_last_function(pcs->pctl);
1061 devm_kfree(pcs->dev, pins);
1064 devm_kfree(pcs->dev, vals);
1069 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1070 struct device_node *np,
1071 struct pinctrl_map **map,
1073 const char **pgnames)
1075 const char *name = "pinctrl-single,bits";
1076 struct pcs_func_vals *vals;
1077 int rows, *pins, found = 0, res = -ENOMEM, i;
1079 struct pcs_function *function;
1081 rows = pinctrl_count_index_with_args(np, name);
1083 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1087 npins_in_row = pcs->width / pcs->bits_per_pin;
1089 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1094 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1099 for (i = 0; i < rows; i++) {
1100 struct of_phandle_args pinctrl_spec;
1101 unsigned offset, val;
1102 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1103 unsigned pin_num_from_lsb;
1106 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1110 if (pinctrl_spec.args_count < 3) {
1111 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1112 pinctrl_spec.args_count);
1116 /* Index plus two value cells */
1117 offset = pinctrl_spec.args[0];
1118 val = pinctrl_spec.args[1];
1119 mask = pinctrl_spec.args[2];
1121 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n",
1122 pinctrl_spec.np->name, offset, val, mask);
1124 /* Parse pins in each row from LSB */
1126 bit_pos = __ffs(mask);
1127 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1128 mask_pos = ((pcs->fmask) << bit_pos);
1129 val_pos = val & mask_pos;
1130 submask = mask & mask_pos;
1132 if ((mask & mask_pos) == 0) {
1134 "Invalid mask for %s at 0x%x\n",
1141 if (submask != mask_pos) {
1143 "Invalid submask 0x%x for %s at 0x%x\n",
1144 submask, np->name, offset);
1148 vals[found].mask = submask;
1149 vals[found].reg = pcs->base + offset;
1150 vals[found].val = val_pos;
1152 pin = pcs_get_pin_by_offset(pcs, offset);
1155 "could not add functions for %s %ux\n",
1159 pins[found++] = pin + pin_num_from_lsb;
1163 pgnames[0] = np->name;
1164 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1170 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1174 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1175 (*map)->data.mux.group = np->name;
1176 (*map)->data.mux.function = np->name;
1178 if (PCS_HAS_PINCONF) {
1179 dev_err(pcs->dev, "pinconf not supported\n");
1180 goto free_pingroups;
1187 pinctrl_generic_remove_last_group(pcs->pctl);
1190 pinmux_generic_remove_last_function(pcs->pctl);
1192 devm_kfree(pcs->dev, pins);
1195 devm_kfree(pcs->dev, vals);
1200 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1201 * @pctldev: pinctrl instance
1202 * @np_config: device tree pinmux entry
1203 * @map: array of map entries
1204 * @num_maps: number of maps
1206 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1207 struct device_node *np_config,
1208 struct pinctrl_map **map, unsigned *num_maps)
1210 struct pcs_device *pcs;
1211 const char **pgnames;
1214 pcs = pinctrl_dev_get_drvdata(pctldev);
1216 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1217 *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1223 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1229 if (pcs->bits_per_mux) {
1230 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1233 dev_err(pcs->dev, "no pins entries for %s\n",
1238 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1241 dev_err(pcs->dev, "no pins entries for %s\n",
1250 devm_kfree(pcs->dev, pgnames);
1252 devm_kfree(pcs->dev, *map);
1258 * pcs_irq_free() - free interrupt
1259 * @pcs: pcs driver instance
1261 static void pcs_irq_free(struct pcs_device *pcs)
1263 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1265 if (pcs_soc->irq < 0)
1269 irq_domain_remove(pcs->domain);
1271 if (PCS_QUIRK_HAS_SHARED_IRQ)
1272 free_irq(pcs_soc->irq, pcs_soc);
1274 irq_set_chained_handler(pcs_soc->irq, NULL);
1278 * pcs_free_resources() - free memory used by this driver
1279 * @pcs: pcs driver instance
1281 static void pcs_free_resources(struct pcs_device *pcs)
1284 pinctrl_unregister(pcs->pctl);
1286 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1287 if (pcs->missing_nr_pinctrl_cells)
1288 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1292 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1294 const char *propname = "pinctrl-single,gpio-range";
1295 const char *cellname = "#pinctrl-single,gpio-range-cells";
1296 struct of_phandle_args gpiospec;
1297 struct pcs_gpiofunc_range *range;
1300 for (i = 0; ; i++) {
1301 ret = of_parse_phandle_with_args(node, propname, cellname,
1303 /* Do not treat it as error. Only treat it as end condition. */
1308 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1313 range->offset = gpiospec.args[0];
1314 range->npins = gpiospec.args[1];
1315 range->gpiofunc = gpiospec.args[2];
1316 mutex_lock(&pcs->mutex);
1317 list_add_tail(&range->node, &pcs->gpiofuncs);
1318 mutex_unlock(&pcs->mutex);
1323 * @reg: virtual address of interrupt register
1324 * @hwirq: hardware irq number
1325 * @irq: virtual irq number
1328 struct pcs_interrupt {
1330 irq_hw_number_t hwirq;
1332 struct list_head node;
1336 * pcs_irq_set() - enables or disables an interrupt
1338 * Note that this currently assumes one interrupt per pinctrl
1339 * register that is typically used for wake-up events.
1341 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1342 int irq, const bool enable)
1344 struct pcs_device *pcs;
1345 struct list_head *pos;
1348 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1349 list_for_each(pos, &pcs->irqs) {
1350 struct pcs_interrupt *pcswi;
1353 pcswi = list_entry(pos, struct pcs_interrupt, node);
1354 if (irq != pcswi->irq)
1357 soc_mask = pcs_soc->irq_enable_mask;
1358 raw_spin_lock(&pcs->lock);
1359 mask = pcs->read(pcswi->reg);
1364 pcs->write(mask, pcswi->reg);
1366 /* flush posted write */
1367 mask = pcs->read(pcswi->reg);
1368 raw_spin_unlock(&pcs->lock);
1376 * pcs_irq_mask() - mask pinctrl interrupt
1377 * @d: interrupt data
1379 static void pcs_irq_mask(struct irq_data *d)
1381 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1383 pcs_irq_set(pcs_soc, d->irq, false);
1387 * pcs_irq_unmask() - unmask pinctrl interrupt
1388 * @d: interrupt data
1390 static void pcs_irq_unmask(struct irq_data *d)
1392 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1394 pcs_irq_set(pcs_soc, d->irq, true);
1398 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1399 * @d: interrupt data
1400 * @state: wake-up state
1402 * Note that this should be called only for suspend and resume.
1403 * For runtime PM, the wake-up events should be enabled by default.
1405 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1416 * pcs_irq_handle() - common interrupt handler
1417 * @pcs_irq: interrupt data
1419 * Note that this currently assumes we have one interrupt bit per
1420 * mux register. This interrupt is typically used for wake-up events.
1421 * For more complex interrupts different handlers can be specified.
1423 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1425 struct pcs_device *pcs;
1426 struct list_head *pos;
1429 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1430 list_for_each(pos, &pcs->irqs) {
1431 struct pcs_interrupt *pcswi;
1434 pcswi = list_entry(pos, struct pcs_interrupt, node);
1435 raw_spin_lock(&pcs->lock);
1436 mask = pcs->read(pcswi->reg);
1437 raw_spin_unlock(&pcs->lock);
1438 if (mask & pcs_soc->irq_status_mask) {
1439 generic_handle_irq(irq_find_mapping(pcs->domain,
1449 * pcs_irq_handler() - handler for the shared interrupt case
1453 * Use this for cases where multiple instances of
1454 * pinctrl-single share a single interrupt like on omaps.
1456 static irqreturn_t pcs_irq_handler(int irq, void *d)
1458 struct pcs_soc_data *pcs_soc = d;
1460 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1464 * pcs_irq_handle() - handler for the dedicated chained interrupt case
1466 * @desc: interrupt descriptor
1468 * Use this if you have a separate interrupt for each
1469 * pinctrl-single instance.
1471 static void pcs_irq_chain_handler(struct irq_desc *desc)
1473 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1474 struct irq_chip *chip;
1476 chip = irq_desc_get_chip(desc);
1477 chained_irq_enter(chip, desc);
1478 pcs_irq_handle(pcs_soc);
1479 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1480 chained_irq_exit(chip, desc);
1483 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1484 irq_hw_number_t hwirq)
1486 struct pcs_soc_data *pcs_soc = d->host_data;
1487 struct pcs_device *pcs;
1488 struct pcs_interrupt *pcswi;
1490 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1491 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1495 pcswi->reg = pcs->base + hwirq;
1496 pcswi->hwirq = hwirq;
1499 mutex_lock(&pcs->mutex);
1500 list_add_tail(&pcswi->node, &pcs->irqs);
1501 mutex_unlock(&pcs->mutex);
1503 irq_set_chip_data(irq, pcs_soc);
1504 irq_set_chip_and_handler(irq, &pcs->chip,
1506 irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1507 irq_set_noprobe(irq);
1512 static const struct irq_domain_ops pcs_irqdomain_ops = {
1513 .map = pcs_irqdomain_map,
1514 .xlate = irq_domain_xlate_onecell,
1518 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1519 * @pcs: pcs driver instance
1520 * @np: device node pointer
1522 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1523 struct device_node *np)
1525 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1526 const char *name = "pinctrl";
1529 if (!pcs_soc->irq_enable_mask ||
1530 !pcs_soc->irq_status_mask) {
1535 INIT_LIST_HEAD(&pcs->irqs);
1536 pcs->chip.name = name;
1537 pcs->chip.irq_ack = pcs_irq_mask;
1538 pcs->chip.irq_mask = pcs_irq_mask;
1539 pcs->chip.irq_unmask = pcs_irq_unmask;
1540 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1542 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1545 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1546 IRQF_SHARED | IRQF_NO_SUSPEND |
1554 irq_set_chained_handler_and_data(pcs_soc->irq,
1555 pcs_irq_chain_handler,
1560 * We can use the register offset as the hardirq
1561 * number as irq_domain_add_simple maps them lazily.
1562 * This way we can easily support more than one
1563 * interrupt per function if needed.
1565 num_irqs = pcs->size;
1567 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1571 irq_set_chained_handler(pcs_soc->irq, NULL);
1579 static int pinctrl_single_suspend(struct platform_device *pdev,
1582 struct pcs_device *pcs;
1584 pcs = platform_get_drvdata(pdev);
1588 return pinctrl_force_sleep(pcs->pctl);
1591 static int pinctrl_single_resume(struct platform_device *pdev)
1593 struct pcs_device *pcs;
1595 pcs = platform_get_drvdata(pdev);
1599 return pinctrl_force_default(pcs->pctl);
1604 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1605 * @pcs: pinctrl driver instance
1606 * @np: device tree node
1607 * @cells: number of cells
1609 * Handle legacy binding with no #pinctrl-cells. This should be
1610 * always two pinctrl-single,bit-per-mux and one for others.
1611 * At some point we may want to consider removing this.
1613 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1614 struct device_node *np,
1618 const char *name = "#pinctrl-cells";
1622 error = of_property_read_u32(np, name, &val);
1626 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1629 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1633 p->length = sizeof(__be32);
1634 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1637 *(__be32 *)p->value = cpu_to_be32(cells);
1639 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1643 pcs->missing_nr_pinctrl_cells = p;
1645 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1646 error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1652 static int pcs_probe(struct platform_device *pdev)
1654 struct device_node *np = pdev->dev.of_node;
1655 struct pcs_pdata *pdata;
1656 struct resource *res;
1657 struct pcs_device *pcs;
1658 const struct pcs_soc_data *soc;
1661 soc = of_device_get_match_data(&pdev->dev);
1665 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1669 pcs->dev = &pdev->dev;
1671 raw_spin_lock_init(&pcs->lock);
1672 mutex_init(&pcs->mutex);
1673 INIT_LIST_HEAD(&pcs->gpiofuncs);
1674 pcs->flags = soc->flags;
1675 memcpy(&pcs->socdata, soc, sizeof(*soc));
1677 ret = of_property_read_u32(np, "pinctrl-single,register-width",
1680 dev_err(pcs->dev, "register width not specified\n");
1685 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1688 pcs->fshift = __ffs(pcs->fmask);
1689 pcs->fmax = pcs->fmask >> pcs->fshift;
1691 /* If mask property doesn't exist, function mux is invalid. */
1697 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1700 pcs->foff = PCS_OFF_DISABLED;
1702 pcs->bits_per_mux = of_property_read_bool(np,
1703 "pinctrl-single,bit-per-mux");
1704 ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1705 pcs->bits_per_mux ? 2 : 1);
1707 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1712 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1714 dev_err(pcs->dev, "could not get resource\n");
1718 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1719 resource_size(res), DRIVER_NAME);
1721 dev_err(pcs->dev, "could not get mem_region\n");
1725 pcs->size = resource_size(pcs->res);
1726 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1728 dev_err(pcs->dev, "could not ioremap\n");
1732 platform_set_drvdata(pdev, pcs);
1734 switch (pcs->width) {
1736 pcs->read = pcs_readb;
1737 pcs->write = pcs_writeb;
1740 pcs->read = pcs_readw;
1741 pcs->write = pcs_writew;
1744 pcs->read = pcs_readl;
1745 pcs->write = pcs_writel;
1751 pcs->desc.name = DRIVER_NAME;
1752 pcs->desc.pctlops = &pcs_pinctrl_ops;
1753 pcs->desc.pmxops = &pcs_pinmux_ops;
1754 if (PCS_HAS_PINCONF)
1755 pcs->desc.confops = &pcs_pinconf_ops;
1756 pcs->desc.owner = THIS_MODULE;
1758 ret = pcs_allocate_pin_table(pcs);
1762 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1764 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1768 ret = pcs_add_gpio_func(np, pcs);
1772 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1773 if (pcs->socdata.irq)
1774 pcs->flags |= PCS_FEAT_IRQ;
1776 /* We still need auxdata for some omaps for PRM interrupts */
1777 pdata = dev_get_platdata(&pdev->dev);
1780 pcs->socdata.rearm = pdata->rearm;
1782 pcs->socdata.irq = pdata->irq;
1783 pcs->flags |= PCS_FEAT_IRQ;
1788 ret = pcs_irq_init_chained_handler(pcs, np);
1790 dev_warn(pcs->dev, "initialized with no interrupts\n");
1793 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1795 return pinctrl_enable(pcs->pctl);
1798 pcs_free_resources(pcs);
1803 static int pcs_remove(struct platform_device *pdev)
1805 struct pcs_device *pcs = platform_get_drvdata(pdev);
1810 pcs_free_resources(pcs);
1815 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1816 .flags = PCS_QUIRK_SHARED_IRQ,
1817 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
1818 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
1821 static const struct pcs_soc_data pinctrl_single_dra7 = {
1822 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1823 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
1826 static const struct pcs_soc_data pinctrl_single_am437x = {
1827 .flags = PCS_QUIRK_SHARED_IRQ,
1828 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
1829 .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
1832 static const struct pcs_soc_data pinctrl_single = {
1835 static const struct pcs_soc_data pinconf_single = {
1836 .flags = PCS_FEAT_PINCONF,
1839 static const struct of_device_id pcs_of_match[] = {
1840 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1841 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1842 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1843 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1844 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1845 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1846 { .compatible = "pinconf-single", .data = &pinconf_single },
1849 MODULE_DEVICE_TABLE(of, pcs_of_match);
1851 static struct platform_driver pcs_driver = {
1853 .remove = pcs_remove,
1855 .name = DRIVER_NAME,
1856 .of_match_table = pcs_of_match,
1859 .suspend = pinctrl_single_suspend,
1860 .resume = pinctrl_single_resume,
1864 module_platform_driver(pcs_driver);
1866 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1867 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1868 MODULE_LICENSE("GPL v2");