drivers/pinctrl/pinctrl-single.c

   1 /*
   2  * Generic device tree based pinctrl driver for one register per pin
   3  * type pinmux controllers
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/list.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <linux/irqchip/chained_irq.h>
  21
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30
  31 #include <linux/platform_data/pinctrl-single.h>
  32
  33 #include "core.h"
  34 #include "devicetree.h"
  35 #include "pinconf.h"
  36 #include "pinmux.h"
  37
  38 #define DRIVER_NAME                     "pinctrl-single"
  39 #define PCS_OFF_DISABLED                ~0U
  40
  41 /**
  42  * struct pcs_func_vals - mux function register offset and value pair
  43  * @reg:        register virtual address
  44  * @val:        register value
  45  * @mask:       mask
  46  */
  47 struct pcs_func_vals {
  48         void __iomem *reg;
  49         unsigned val;
  50         unsigned mask;
  51 };
  52
  53 /**
  54  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  55  * and value, enable, disable, mask
  56  * @param:      config parameter
  57  * @val:        user input bits in the pinconf register
  58  * @enable:     enable bits in the pinconf register
  59  * @disable:    disable bits in the pinconf register
  60  * @mask:       mask bits in the register value
  61  */
  62 struct pcs_conf_vals {
  63         enum pin_config_param param;
  64         unsigned val;
  65         unsigned enable;
  66         unsigned disable;
  67         unsigned mask;
  68 };
  69
  70 /**
  71  * struct pcs_conf_type - pinconf property name, pinconf param pair
  72  * @name:       property name in DTS file
  73  * @param:      config parameter
  74  */
  75 struct pcs_conf_type {
  76         const char *name;
  77         enum pin_config_param param;
  78 };
  79
  80 /**
  81  * struct pcs_function - pinctrl function
  82  * @name:       pinctrl function name
  83  * @vals:       register and vals array
  84  * @nvals:      number of entries in vals array
  85  * @pgnames:    array of pingroup names the function uses
  86  * @npgnames:   number of pingroup names the function uses
  87  * @conf:       array of pin configurations
  88  * @nconfs:     number of pin configurations available
  89  * @node:       list node
  90  */
  91 struct pcs_function {
  92         const char *name;
  93         struct pcs_func_vals *vals;
  94         unsigned nvals;
  95         const char **pgnames;
  96         int npgnames;
  97         struct pcs_conf_vals *conf;
  98         int nconfs;
  99         struct list_head node;
 100 };
 101
 102 /**
 103  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
 104  * @offset:     offset base of pins
 105  * @npins:      number pins with the same mux value of gpio function
 106  * @gpiofunc:   mux value of gpio function
 107  * @node:       list node
 108  */
 109 struct pcs_gpiofunc_range {
 110         unsigned offset;
 111         unsigned npins;
 112         unsigned gpiofunc;
 113         struct list_head node;
 114 };
 115
 116 /**
 117  * struct pcs_data - wrapper for data needed by pinctrl framework
 118  * @pa:         pindesc array
 119  * @cur:        index to current element
 120  *
 121  * REVISIT: We should be able to drop this eventually by adding
 122  * support for registering pins individually in the pinctrl
 123  * framework for those drivers that don't need a static array.
 124  */
 125 struct pcs_data {
 126         struct pinctrl_pin_desc *pa;
 127         int cur;
 128 };
 129
 130 /**
 131  * struct pcs_soc_data - SoC specific settings
 132  * @flags:      initial SoC specific PCS_FEAT_xxx values
 133  * @irq:        optional interrupt for the controller
 134  * @irq_enable_mask:    optional SoC specific interrupt enable mask
 135  * @irq_status_mask:    optional SoC specific interrupt status mask
 136  * @rearm:      optional SoC specific wake-up rearm function
 137  */
 138 struct pcs_soc_data {
 139         unsigned flags;
 140         int irq;
 141         unsigned irq_enable_mask;
 142         unsigned irq_status_mask;
 143         void (*rearm)(void);
 144 };
 145
 146 /**
 147  * struct pcs_device - pinctrl device instance
 148  * @res:        resources
 149  * @base:       virtual address of the controller
 150  * @saved_vals: saved values for the controller
 151  * @size:       size of the ioremapped area
 152  * @dev:        device entry
 153  * @np:         device tree node
 154  * @pctl:       pin controller device
 155  * @flags:      mask of PCS_FEAT_xxx values
 156  * @missing_nr_pinctrl_cells: for legacy binding, may go away
 157  * @socdata:    soc specific data
 158  * @lock:       spinlock for register access
 159  * @mutex:      mutex protecting the lists
 160  * @width:      bits per mux register
 161  * @fmask:      function register mask
 162  * @fshift:     function register shift
 163  * @foff:       value to turn mux off
 164  * @fmax:       max number of functions in fmask
 165  * @bits_per_mux: number of bits per mux
 166  * @bits_per_pin: number of bits per pin
 167  * @pins:       physical pins on the SoC
 168  * @gpiofuncs:  list of gpio functions
 169  * @irqs:       list of interrupt registers
 170  * @chip:       chip container for this instance
 171  * @domain:     IRQ domain for this instance
 172  * @desc:       pin controller descriptor
 173  * @read:       register read function to use
 174  * @write:      register write function to use
 175  */
 176 struct pcs_device {
 177         struct resource *res;
 178         void __iomem *base;
 179         void *saved_vals;
 180         unsigned size;
 181         struct device *dev;
 182         struct device_node *np;
 183         struct pinctrl_dev *pctl;
 184         unsigned flags;
 185 #define PCS_CONTEXT_LOSS_OFF    (1 << 3)
 186 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
 187 #define PCS_FEAT_IRQ            (1 << 1)
 188 #define PCS_FEAT_PINCONF        (1 << 0)
 189         struct property *missing_nr_pinctrl_cells;
 190         struct pcs_soc_data socdata;
 191         raw_spinlock_t lock;
 192         struct mutex mutex;
 193         unsigned width;
 194         unsigned fmask;
 195         unsigned fshift;
 196         unsigned foff;
 197         unsigned fmax;
 198         bool bits_per_mux;
 199         unsigned bits_per_pin;
 200         struct pcs_data pins;
 201         struct list_head gpiofuncs;
 202         struct list_head irqs;
 203         struct irq_chip chip;
 204         struct irq_domain *domain;
 205         struct pinctrl_desc desc;
 206         unsigned (*read)(void __iomem *reg);
 207         void (*write)(unsigned val, void __iomem *reg);
 208 };
 209
 210 #define PCS_QUIRK_HAS_SHARED_IRQ        (pcs->flags & PCS_QUIRK_SHARED_IRQ)
 211 #define PCS_HAS_IRQ             (pcs->flags & PCS_FEAT_IRQ)
 212 #define PCS_HAS_PINCONF         (pcs->flags & PCS_FEAT_PINCONF)
 213
 214 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 215                            unsigned long *config);
 216 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 217                            unsigned long *configs, unsigned num_configs);
 218
 219 static enum pin_config_param pcs_bias[] = {
 220         PIN_CONFIG_BIAS_PULL_DOWN,
 221         PIN_CONFIG_BIAS_PULL_UP,
 222 };
 223
 224 /*
 225  * This lock class tells lockdep that irqchip core that this single
 226  * pinctrl can be in a different category than its parents, so it won't
 227  * report false recursion.
 228  */
 229 static struct lock_class_key pcs_lock_class;
 230
 231 /* Class for the IRQ request mutex */
 232 static struct lock_class_key pcs_request_class;
 233
 234 /*
 235  * REVISIT: Reads and writes could eventually use regmap or something
 236  * generic. But at least on omaps, some mux registers are performance
 237  * critical as they may need to be remuxed every time before and after
 238  * idle. Adding tests for register access width for every read and
 239  * write like regmap is doing is not desired, and caching the registers
 240  * does not help in this case.
 241  */
 242
 243 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
 244 {
 245         return readb(reg);
 246 }
 247
 248 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
 249 {
 250         return readw(reg);
 251 }
 252
 253 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
 254 {
 255         return readl(reg);
 256 }
 257
 258 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
 259 {
 260         writeb(val, reg);
 261 }
 262
 263 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
 264 {
 265         writew(val, reg);
 266 }
 267
 268 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
 269 {
 270         writel(val, reg);
 271 }
 272
 273 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
 274                                         struct seq_file *s,
 275                                         unsigned pin)
 276 {
 277         struct pcs_device *pcs;
 278         unsigned val, mux_bytes;
 279         unsigned long offset;
 280         size_t pa;
 281
 282         pcs = pinctrl_dev_get_drvdata(pctldev);
 283
 284         mux_bytes = pcs->width / BITS_PER_BYTE;
 285         offset = pin * mux_bytes;
 286         val = pcs->read(pcs->base + offset);
 287         pa = pcs->res->start + offset;
 288
 289         seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
 290 }
 291
 292 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
 293                                 struct pinctrl_map *map, unsigned num_maps)
 294 {
 295         struct pcs_device *pcs;
 296
 297         pcs = pinctrl_dev_get_drvdata(pctldev);
 298         devm_kfree(pcs->dev, map);
 299 }
 300
 301 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 302                                 struct device_node *np_config,
 303                                 struct pinctrl_map **map, unsigned *num_maps);
 304
 305 static const struct pinctrl_ops pcs_pinctrl_ops = {
 306         .get_groups_count = pinctrl_generic_get_group_count,
 307         .get_group_name = pinctrl_generic_get_group_name,
 308         .get_group_pins = pinctrl_generic_get_group_pins,
 309         .pin_dbg_show = pcs_pin_dbg_show,
 310         .dt_node_to_map = pcs_dt_node_to_map,
 311         .dt_free_map = pcs_dt_free_map,
 312 };
 313
 314 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
 315                             struct pcs_function **func)
 316 {
 317         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 318         struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
 319         const struct pinctrl_setting_mux *setting;
 320         struct function_desc *function;
 321         unsigned fselector;
 322
 323         /* If pin is not described in DTS & enabled, mux_setting is NULL. */
 324         setting = pdesc->mux_setting;
 325         if (!setting)
 326                 return -ENOTSUPP;
 327         fselector = setting->func;
 328         function = pinmux_generic_get_function(pctldev, fselector);
 329         *func = function->data;
 330         if (!(*func)) {
 331                 dev_err(pcs->dev, "%s could not find function%i\n",
 332                         __func__, fselector);
 333                 return -ENOTSUPP;
 334         }
 335         return 0;
 336 }
 337
 338 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
 339         unsigned group)
 340 {
 341         struct pcs_device *pcs;
 342         struct function_desc *function;
 343         struct pcs_function *func;
 344         int i;
 345
 346         pcs = pinctrl_dev_get_drvdata(pctldev);
 347         /* If function mask is null, needn't enable it. */
 348         if (!pcs->fmask)
 349                 return 0;
 350         function = pinmux_generic_get_function(pctldev, fselector);
 351         func = function->data;
 352         if (!func)
 353                 return -EINVAL;
 354
 355         dev_dbg(pcs->dev, "enabling %s function%i\n",
 356                 func->name, fselector);
 357
 358         for (i = 0; i < func->nvals; i++) {
 359                 struct pcs_func_vals *vals;
 360                 unsigned long flags;
 361                 unsigned val, mask;
 362
 363                 vals = &func->vals[i];
 364                 raw_spin_lock_irqsave(&pcs->lock, flags);
 365                 val = pcs->read(vals->reg);
 366
 367                 if (pcs->bits_per_mux)
 368                         mask = vals->mask;
 369                 else
 370                         mask = pcs->fmask;
 371
 372                 val &= ~mask;
 373                 val |= (vals->val & mask);
 374                 pcs->write(val, vals->reg);
 375                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
 382                             struct pinctrl_gpio_range *range, unsigned pin)
 383 {
 384         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 385         struct pcs_gpiofunc_range *frange = NULL;
 386         struct list_head *pos, *tmp;
 387         int mux_bytes = 0;
 388         unsigned data;
 389
 390         /* If function mask is null, return directly. */
 391         if (!pcs->fmask)
 392                 return -ENOTSUPP;
 393
 394         list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
 395                 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
 396                 if (pin >= frange->offset + frange->npins
 397                         || pin < frange->offset)
 398                         continue;
 399                 mux_bytes = pcs->width / BITS_PER_BYTE;
 400
 401                 if (pcs->bits_per_mux) {
 402                         int byte_num, offset, pin_shift;
 403
 404                         byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
 405                         offset = (byte_num / mux_bytes) * mux_bytes;
 406                         pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
 407                                     pcs->bits_per_pin;
 408
 409                         data = pcs->read(pcs->base + offset);
 410                         data &= ~(pcs->fmask << pin_shift);
 411                         data |= frange->gpiofunc << pin_shift;
 412                         pcs->write(data, pcs->base + offset);
 413                 } else {
 414                         data = pcs->read(pcs->base + pin * mux_bytes);
 415                         data &= ~pcs->fmask;
 416                         data |= frange->gpiofunc;
 417                         pcs->write(data, pcs->base + pin * mux_bytes);
 418                 }
 419                 break;
 420         }
 421         return 0;
 422 }
 423
 424 static const struct pinmux_ops pcs_pinmux_ops = {
 425         .get_functions_count = pinmux_generic_get_function_count,
 426         .get_function_name = pinmux_generic_get_function_name,
 427         .get_function_groups = pinmux_generic_get_function_groups,
 428         .set_mux = pcs_set_mux,
 429         .gpio_request_enable = pcs_request_gpio,
 430 };
 431
 432 /* Clear BIAS value */
 433 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
 434 {
 435         unsigned long config;
 436         int i;
 437         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 438                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 439                 pcs_pinconf_set(pctldev, pin, &config, 1);
 440         }
 441 }
 442
 443 /*
 444  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
 445  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
 446  */
 447 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
 448 {
 449         unsigned long config;
 450         int i;
 451
 452         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 453                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 454                 if (!pcs_pinconf_get(pctldev, pin, &config))
 455                         goto out;
 456         }
 457         return true;
 458 out:
 459         return false;
 460 }
 461
 462 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
 463                                 unsigned pin, unsigned long *config)
 464 {
 465         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 466         struct pcs_function *func;
 467         enum pin_config_param param;
 468         unsigned offset = 0, data = 0, i, j, ret;
 469
 470         ret = pcs_get_function(pctldev, pin, &func);
 471         if (ret)
 472                 return ret;
 473
 474         for (i = 0; i < func->nconfs; i++) {
 475                 param = pinconf_to_config_param(*config);
 476                 if (param == PIN_CONFIG_BIAS_DISABLE) {
 477                         if (pcs_pinconf_bias_disable(pctldev, pin)) {
 478                                 *config = 0;
 479                                 return 0;
 480                         } else {
 481                                 return -ENOTSUPP;
 482                         }
 483                 } else if (param != func->conf[i].param) {
 484                         continue;
 485                 }
 486
 487                 offset = pin * (pcs->width / BITS_PER_BYTE);
 488                 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
 489                 switch (func->conf[i].param) {
 490                 /* 4 parameters */
 491                 case PIN_CONFIG_BIAS_PULL_DOWN:
 492                 case PIN_CONFIG_BIAS_PULL_UP:
 493                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 494                         if ((data != func->conf[i].enable) ||
 495                             (data == func->conf[i].disable))
 496                                 return -ENOTSUPP;
 497                         *config = 0;
 498                         break;
 499                 /* 2 parameters */
 500                 case PIN_CONFIG_INPUT_SCHMITT:
 501                         for (j = 0; j < func->nconfs; j++) {
 502                                 switch (func->conf[j].param) {
 503                                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 504                                         if (data != func->conf[j].enable)
 505                                                 return -ENOTSUPP;
 506                                         break;
 507                                 default:
 508                                         break;
 509                                 }
 510                         }
 511                         *config = data;
 512                         break;
 513                 case PIN_CONFIG_DRIVE_STRENGTH:
 514                 case PIN_CONFIG_SLEW_RATE:
 515                 case PIN_CONFIG_LOW_POWER_MODE:
 516                 default:
 517                         *config = data;
 518                         break;
 519                 }
 520                 return 0;
 521         }
 522         return -ENOTSUPP;
 523 }
 524
 525 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
 526                                 unsigned pin, unsigned long *configs,
 527                                 unsigned num_configs)
 528 {
 529         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 530         struct pcs_function *func;
 531         unsigned offset = 0, shift = 0, i, data, ret;
 532         u32 arg;
 533         int j;
 534
 535         ret = pcs_get_function(pctldev, pin, &func);
 536         if (ret)
 537                 return ret;
 538
 539         for (j = 0; j < num_configs; j++) {
 540                 for (i = 0; i < func->nconfs; i++) {
 541                         if (pinconf_to_config_param(configs[j])
 542                                 != func->conf[i].param)
 543                                 continue;
 544
 545                         offset = pin * (pcs->width / BITS_PER_BYTE);
 546                         data = pcs->read(pcs->base + offset);
 547                         arg = pinconf_to_config_argument(configs[j]);
 548                         switch (func->conf[i].param) {
 549                         /* 2 parameters */
 550                         case PIN_CONFIG_INPUT_SCHMITT:
 551                         case PIN_CONFIG_DRIVE_STRENGTH:
 552                         case PIN_CONFIG_SLEW_RATE:
 553                         case PIN_CONFIG_LOW_POWER_MODE:
 554                                 shift = ffs(func->conf[i].mask) - 1;
 555                                 data &= ~func->conf[i].mask;
 556                                 data |= (arg << shift) & func->conf[i].mask;
 557                                 break;
 558                         /* 4 parameters */
 559                         case PIN_CONFIG_BIAS_DISABLE:
 560                                 pcs_pinconf_clear_bias(pctldev, pin);
 561                                 break;
 562                         case PIN_CONFIG_BIAS_PULL_DOWN:
 563                         case PIN_CONFIG_BIAS_PULL_UP:
 564                                 if (arg)
 565                                         pcs_pinconf_clear_bias(pctldev, pin);
 566                                 fallthrough;
 567                         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 568                                 data &= ~func->conf[i].mask;
 569                                 if (arg)
 570                                         data |= func->conf[i].enable;
 571                                 else
 572                                         data |= func->conf[i].disable;
 573                                 break;
 574                         default:
 575                                 return -ENOTSUPP;
 576                         }
 577                         pcs->write(data, pcs->base + offset);
 578
 579                         break;
 580                 }
 581                 if (i >= func->nconfs)
 582                         return -ENOTSUPP;
 583         } /* for each config */
 584
 585         return 0;
 586 }
 587
 588 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
 589                                 unsigned group, unsigned long *config)
 590 {
 591         const unsigned *pins;
 592         unsigned npins, old = 0;
 593         int i, ret;
 594
 595         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 596         if (ret)
 597                 return ret;
 598         for (i = 0; i < npins; i++) {
 599                 if (pcs_pinconf_get(pctldev, pins[i], config))
 600                         return -ENOTSUPP;
 601                 /* configs do not match between two pins */
 602                 if (i && (old != *config))
 603                         return -ENOTSUPP;
 604                 old = *config;
 605         }
 606         return 0;
 607 }
 608
 609 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
 610                                 unsigned group, unsigned long *configs,
 611                                 unsigned num_configs)
 612 {
 613         const unsigned *pins;
 614         unsigned npins;
 615         int i, ret;
 616
 617         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 618         if (ret)
 619                 return ret;
 620         for (i = 0; i < npins; i++) {
 621                 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
 622                         return -ENOTSUPP;
 623         }
 624         return 0;
 625 }
 626
 627 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 628                                 struct seq_file *s, unsigned pin)
 629 {
 630 }
 631
 632 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 633                                 struct seq_file *s, unsigned selector)
 634 {
 635 }
 636
 637 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 638                                         struct seq_file *s,
 639                                         unsigned long config)
 640 {
 641         pinconf_generic_dump_config(pctldev, s, config);
 642 }
 643
 644 static const struct pinconf_ops pcs_pinconf_ops = {
 645         .pin_config_get = pcs_pinconf_get,
 646         .pin_config_set = pcs_pinconf_set,
 647         .pin_config_group_get = pcs_pinconf_group_get,
 648         .pin_config_group_set = pcs_pinconf_group_set,
 649         .pin_config_dbg_show = pcs_pinconf_dbg_show,
 650         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
 651         .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
 652         .is_generic = true,
 653 };
 654
 655 /**
 656  * pcs_add_pin() - add a pin to the static per controller pin array
 657  * @pcs: pcs driver instance
 658  * @offset: register offset from base
 659  * @pin_pos: unused
 660  */
 661 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
 662                 unsigned pin_pos)
 663 {
 664         struct pcs_soc_data *pcs_soc = &pcs->socdata;
 665         struct pinctrl_pin_desc *pin;
 666         int i;
 667
 668         i = pcs->pins.cur;
 669         if (i >= pcs->desc.npins) {
 670                 dev_err(pcs->dev, "too many pins, max %i\n",
 671                         pcs->desc.npins);
 672                 return -ENOMEM;
 673         }
 674
 675         if (pcs_soc->irq_enable_mask) {
 676                 unsigned val;
 677
 678                 val = pcs->read(pcs->base + offset);
 679                 if (val & pcs_soc->irq_enable_mask) {
 680                         dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
 681                                 (unsigned long)pcs->res->start + offset, val);
 682                         val &= ~pcs_soc->irq_enable_mask;
 683                         pcs->write(val, pcs->base + offset);
 684                 }
 685         }
 686
 687         pin = &pcs->pins.pa[i];
 688         pin->number = i;
 689         pcs->pins.cur++;
 690
 691         return i;
 692 }
 693
 694 /**
 695  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
 696  * @pcs: pcs driver instance
 697  *
 698  * In case of errors, resources are freed in pcs_free_resources.
 699  *
 700  * If your hardware needs holes in the address space, then just set
 701  * up multiple driver instances.
 702  */
 703 static int pcs_allocate_pin_table(struct pcs_device *pcs)
 704 {
 705         int mux_bytes, nr_pins, i;
 706         int num_pins_in_register = 0;
 707
 708         mux_bytes = pcs->width / BITS_PER_BYTE;
 709
 710         if (pcs->bits_per_mux) {
 711                 pcs->bits_per_pin = fls(pcs->fmask);
 712                 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
 713                 num_pins_in_register = pcs->width / pcs->bits_per_pin;
 714         } else {
 715                 nr_pins = pcs->size / mux_bytes;
 716         }
 717
 718         dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 719         pcs->pins.pa = devm_kcalloc(pcs->dev,
 720                                 nr_pins, sizeof(*pcs->pins.pa),
 721                                 GFP_KERNEL);
 722         if (!pcs->pins.pa)
 723                 return -ENOMEM;
 724
 725         pcs->desc.pins = pcs->pins.pa;
 726         pcs->desc.npins = nr_pins;
 727
 728         for (i = 0; i < pcs->desc.npins; i++) {
 729                 unsigned offset;
 730                 int res;
 731                 int byte_num;
 732                 int pin_pos = 0;
 733
 734                 if (pcs->bits_per_mux) {
 735                         byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
 736                         offset = (byte_num / mux_bytes) * mux_bytes;
 737                         pin_pos = i % num_pins_in_register;
 738                 } else {
 739                         offset = i * mux_bytes;
 740                 }
 741                 res = pcs_add_pin(pcs, offset, pin_pos);
 742                 if (res < 0) {
 743                         dev_err(pcs->dev, "error adding pins: %i\n", res);
 744                         return res;
 745                 }
 746         }
 747
 748         return 0;
 749 }
 750
 751 /**
 752  * pcs_add_function() - adds a new function to the function list
 753  * @pcs: pcs driver instance
 754  * @fcn: new function allocated
 755  * @name: name of the function
 756  * @vals: array of mux register value pairs used by the function
 757  * @nvals: number of mux register value pairs
 758  * @pgnames: array of pingroup names for the function
 759  * @npgnames: number of pingroup names
 760  *
 761  * Caller must take care of locking.
 762  */
 763 static int pcs_add_function(struct pcs_device *pcs,
 764                             struct pcs_function **fcn,
 765                             const char *name,
 766                             struct pcs_func_vals *vals,
 767                             unsigned int nvals,
 768                             const char **pgnames,
 769                             unsigned int npgnames)
 770 {
 771         struct pcs_function *function;
 772         int selector;
 773
 774         function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
 775         if (!function)
 776                 return -ENOMEM;
 777
 778         function->vals = vals;
 779         function->nvals = nvals;
 780         function->name = name;
 781
 782         selector = pinmux_generic_add_function(pcs->pctl, name,
 783                                                pgnames, npgnames,
 784                                                function);
 785         if (selector < 0) {
 786                 devm_kfree(pcs->dev, function);
 787                 *fcn = NULL;
 788         } else {
 789                 *fcn = function;
 790         }
 791
 792         return selector;
 793 }
 794
 795 /**
 796  * pcs_get_pin_by_offset() - get a pin index based on the register offset
 797  * @pcs: pcs driver instance
 798  * @offset: register offset from the base
 799  *
 800  * Note that this is OK as long as the pins are in a static array.
 801  */
 802 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 803 {
 804         unsigned index;
 805
 806         if (offset >= pcs->size) {
 807                 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
 808                         offset, pcs->size);
 809                 return -EINVAL;
 810         }
 811
 812         if (pcs->bits_per_mux)
 813                 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
 814         else
 815                 index = offset / (pcs->width / BITS_PER_BYTE);
 816
 817         return index;
 818 }
 819
 820 /*
 821  * check whether data matches enable bits or disable bits
 822  * Return value: 1 for matching enable bits, 0 for matching disable bits,
 823  *               and negative value for matching failure.
 824  */
 825 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
 826 {
 827         int ret = -EINVAL;
 828
 829         if (data == enable)
 830                 ret = 1;
 831         else if (data == disable)
 832                 ret = 0;
 833         return ret;
 834 }
 835
 836 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
 837                        unsigned value, unsigned enable, unsigned disable,
 838                        unsigned mask)
 839 {
 840         (*conf)->param = param;
 841         (*conf)->val = value;
 842         (*conf)->enable = enable;
 843         (*conf)->disable = disable;
 844         (*conf)->mask = mask;
 845         (*conf)++;
 846 }
 847
 848 static void add_setting(unsigned long **setting, enum pin_config_param param,
 849                         unsigned arg)
 850 {
 851         **setting = pinconf_to_config_packed(param, arg);
 852         (*setting)++;
 853 }
 854
 855 /* add pinconf setting with 2 parameters */
 856 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
 857                           const char *name, enum pin_config_param param,
 858                           struct pcs_conf_vals **conf, unsigned long **settings)
 859 {
 860         unsigned value[2], shift;
 861         int ret;
 862
 863         ret = of_property_read_u32_array(np, name, value, 2);
 864         if (ret)
 865                 return;
 866         /* set value & mask */
 867         value[0] &= value[1];
 868         shift = ffs(value[1]) - 1;
 869         /* skip enable & disable */
 870         add_config(conf, param, value[0], 0, 0, value[1]);
 871         add_setting(settings, param, value[0] >> shift);
 872 }
 873
 874 /* add pinconf setting with 4 parameters */
 875 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
 876                           const char *name, enum pin_config_param param,
 877                           struct pcs_conf_vals **conf, unsigned long **settings)
 878 {
 879         unsigned value[4];
 880         int ret;
 881
 882         /* value to set, enable, disable, mask */
 883         ret = of_property_read_u32_array(np, name, value, 4);
 884         if (ret)
 885                 return;
 886         if (!value[3]) {
 887                 dev_err(pcs->dev, "mask field of the property can't be 0\n");
 888                 return;
 889         }
 890         value[0] &= value[3];
 891         value[1] &= value[3];
 892         value[2] &= value[3];
 893         ret = pcs_config_match(value[0], value[1], value[2]);
 894         if (ret < 0)
 895                 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
 896         add_config(conf, param, value[0], value[1], value[2], value[3]);
 897         add_setting(settings, param, ret);
 898 }
 899
 900 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
 901                              struct pcs_function *func,
 902                              struct pinctrl_map **map)
 903
 904 {
 905         struct pinctrl_map *m = *map;
 906         int i = 0, nconfs = 0;
 907         unsigned long *settings = NULL, *s = NULL;
 908         struct pcs_conf_vals *conf = NULL;
 909         static const struct pcs_conf_type prop2[] = {
 910                 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
 911                 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
 912                 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
 913                 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
 914         };
 915         static const struct pcs_conf_type prop4[] = {
 916                 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
 917                 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
 918                 { "pinctrl-single,input-schmitt-enable",
 919                         PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
 920         };
 921
 922         /* If pinconf isn't supported, don't parse properties in below. */
 923         if (!PCS_HAS_PINCONF)
 924                 return -ENOTSUPP;
 925
 926         /* cacluate how much properties are supported in current node */
 927         for (i = 0; i < ARRAY_SIZE(prop2); i++) {
 928                 if (of_find_property(np, prop2[i].name, NULL))
 929                         nconfs++;
 930         }
 931         for (i = 0; i < ARRAY_SIZE(prop4); i++) {
 932                 if (of_find_property(np, prop4[i].name, NULL))
 933                         nconfs++;
 934         }
 935         if (!nconfs)
 936                 return -ENOTSUPP;
 937
 938         func->conf = devm_kcalloc(pcs->dev,
 939                                   nconfs, sizeof(struct pcs_conf_vals),
 940                                   GFP_KERNEL);
 941         if (!func->conf)
 942                 return -ENOMEM;
 943         func->nconfs = nconfs;
 944         conf = &(func->conf[0]);
 945         m++;
 946         settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
 947                                 GFP_KERNEL);
 948         if (!settings)
 949                 return -ENOMEM;
 950         s = &settings[0];
 951
 952         for (i = 0; i < ARRAY_SIZE(prop2); i++)
 953                 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
 954                               &conf, &s);
 955         for (i = 0; i < ARRAY_SIZE(prop4); i++)
 956                 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
 957                               &conf, &s);
 958         m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
 959         m->data.configs.group_or_pin = np->name;
 960         m->data.configs.configs = settings;
 961         m->data.configs.num_configs = nconfs;
 962         return 0;
 963 }
 964
 965 /**
 966  * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
 967  * @pcs: pinctrl driver instance
 968  * @np: device node of the mux entry
 969  * @map: map entry
 970  * @num_maps: number of map
 971  * @pgnames: pingroup names
 972  *
 973  * Note that this binding currently supports only sets of one register + value.
 974  *
 975  * Also note that this driver tries to avoid understanding pin and function
 976  * names because of the extra bloat they would cause especially in the case of
 977  * a large number of pins. This driver just sets what is specified for the board
 978  * in the .dts file. Further user space debugging tools can be developed to
 979  * decipher the pin and function names using debugfs.
 980  *
 981  * If you are concerned about the boot time, set up the static pins in
 982  * the bootloader, and only set up selected pins as device tree entries.
 983  */
 984 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
 985                                                 struct device_node *np,
 986                                                 struct pinctrl_map **map,
 987                                                 unsigned *num_maps,
 988                                                 const char **pgnames)
 989 {
 990         const char *name = "pinctrl-single,pins";
 991         struct pcs_func_vals *vals;
 992         int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
 993         struct pcs_function *function = NULL;
 994
 995         rows = pinctrl_count_index_with_args(np, name);
 996         if (rows <= 0) {
 997                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
 998                 return -EINVAL;
 999         }
1000
1001         vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1002         if (!vals)
1003                 return -ENOMEM;
1004
1005         pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1006         if (!pins)
1007                 goto free_vals;
1008
1009         for (i = 0; i < rows; i++) {
1010                 struct of_phandle_args pinctrl_spec;
1011                 unsigned int offset;
1012                 int pin;
1013
1014                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1015                 if (res)
1016                         return res;
1017
1018                 if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
1019                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1020                                 pinctrl_spec.args_count);
1021                         break;
1022                 }
1023
1024                 offset = pinctrl_spec.args[0];
1025                 vals[found].reg = pcs->base + offset;
1026
1027                 switch (pinctrl_spec.args_count) {
1028                 case 2:
1029                         vals[found].val = pinctrl_spec.args[1];
1030                         break;
1031                 case 3:
1032                         vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
1033                         break;
1034                 }
1035
1036                 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1037                         pinctrl_spec.np, offset, vals[found].val);
1038
1039                 pin = pcs_get_pin_by_offset(pcs, offset);
1040                 if (pin < 0) {
1041                         dev_err(pcs->dev,
1042                                 "could not add functions for %pOFn %ux\n",
1043                                 np, offset);
1044                         break;
1045                 }
1046                 pins[found++] = pin;
1047         }
1048
1049         pgnames[0] = np->name;
1050         mutex_lock(&pcs->mutex);
1051         fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1052                                 pgnames, 1);
1053         if (fsel < 0) {
1054                 res = fsel;
1055                 goto free_pins;
1056         }
1057
1058         gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1059         if (gsel < 0) {
1060                 res = gsel;
1061                 goto free_function;
1062         }
1063
1064         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1065         (*map)->data.mux.group = np->name;
1066         (*map)->data.mux.function = np->name;
1067
1068         if (PCS_HAS_PINCONF && function) {
1069                 res = pcs_parse_pinconf(pcs, np, function, map);
1070                 if (res == 0)
1071                         *num_maps = 2;
1072                 else if (res == -ENOTSUPP)
1073                         *num_maps = 1;
1074                 else
1075                         goto free_pingroups;
1076         } else {
1077                 *num_maps = 1;
1078         }
1079         mutex_unlock(&pcs->mutex);
1080
1081         return 0;
1082
1083 free_pingroups:
1084         pinctrl_generic_remove_group(pcs->pctl, gsel);
1085         *num_maps = 1;
1086 free_function:
1087         pinmux_generic_remove_function(pcs->pctl, fsel);
1088 free_pins:
1089         mutex_unlock(&pcs->mutex);
1090         devm_kfree(pcs->dev, pins);
1091
1092 free_vals:
1093         devm_kfree(pcs->dev, vals);
1094
1095         return res;
1096 }
1097
1098 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1099                                                 struct device_node *np,
1100                                                 struct pinctrl_map **map,
1101                                                 unsigned *num_maps,
1102                                                 const char **pgnames)
1103 {
1104         const char *name = "pinctrl-single,bits";
1105         struct pcs_func_vals *vals;
1106         int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1107         int npins_in_row;
1108         struct pcs_function *function = NULL;
1109
1110         rows = pinctrl_count_index_with_args(np, name);
1111         if (rows <= 0) {
1112                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1113                 return -EINVAL;
1114         }
1115
1116         npins_in_row = pcs->width / pcs->bits_per_pin;
1117
1118         vals = devm_kzalloc(pcs->dev,
1119                             array3_size(rows, npins_in_row, sizeof(*vals)),
1120                             GFP_KERNEL);
1121         if (!vals)
1122                 return -ENOMEM;
1123
1124         pins = devm_kzalloc(pcs->dev,
1125                             array3_size(rows, npins_in_row, sizeof(*pins)),
1126                             GFP_KERNEL);
1127         if (!pins)
1128                 goto free_vals;
1129
1130         for (i = 0; i < rows; i++) {
1131                 struct of_phandle_args pinctrl_spec;
1132                 unsigned offset, val;
1133                 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1134                 unsigned pin_num_from_lsb;
1135                 int pin;
1136
1137                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1138                 if (res)
1139                         return res;
1140
1141                 if (pinctrl_spec.args_count < 3) {
1142                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1143                                 pinctrl_spec.args_count);
1144                         break;
1145                 }
1146
1147                 /* Index plus two value cells */
1148                 offset = pinctrl_spec.args[0];
1149                 val = pinctrl_spec.args[1];
1150                 mask = pinctrl_spec.args[2];
1151
1152                 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1153                         pinctrl_spec.np, offset, val, mask);
1154
1155                 /* Parse pins in each row from LSB */
1156                 while (mask) {
1157                         bit_pos = __ffs(mask);
1158                         pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1159                         mask_pos = ((pcs->fmask) << bit_pos);
1160                         val_pos = val & mask_pos;
1161                         submask = mask & mask_pos;
1162
1163                         if ((mask & mask_pos) == 0) {
1164                                 dev_err(pcs->dev,
1165                                         "Invalid mask for %pOFn at 0x%x\n",
1166                                         np, offset);
1167                                 break;
1168                         }
1169
1170                         mask &= ~mask_pos;
1171
1172                         if (submask != mask_pos) {
1173                                 dev_warn(pcs->dev,
1174                                                 "Invalid submask 0x%x for %pOFn at 0x%x\n",
1175                                                 submask, np, offset);
1176                                 continue;
1177                         }
1178
1179                         vals[found].mask = submask;
1180                         vals[found].reg = pcs->base + offset;
1181                         vals[found].val = val_pos;
1182
1183                         pin = pcs_get_pin_by_offset(pcs, offset);
1184                         if (pin < 0) {
1185                                 dev_err(pcs->dev,
1186                                         "could not add functions for %pOFn %ux\n",
1187                                         np, offset);
1188                                 break;
1189                         }
1190                         pins[found++] = pin + pin_num_from_lsb;
1191                 }
1192         }
1193
1194         pgnames[0] = np->name;
1195         mutex_lock(&pcs->mutex);
1196         fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1197                                 pgnames, 1);
1198         if (fsel < 0) {
1199                 res = fsel;
1200                 goto free_pins;
1201         }
1202
1203         gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1204         if (gsel < 0) {
1205                 res = gsel;
1206                 goto free_function;
1207         }
1208
1209         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1210         (*map)->data.mux.group = np->name;
1211         (*map)->data.mux.function = np->name;
1212
1213         if (PCS_HAS_PINCONF) {
1214                 dev_err(pcs->dev, "pinconf not supported\n");
1215                 goto free_pingroups;
1216         }
1217
1218         *num_maps = 1;
1219         mutex_unlock(&pcs->mutex);
1220
1221         return 0;
1222
1223 free_pingroups:
1224         pinctrl_generic_remove_group(pcs->pctl, gsel);
1225         *num_maps = 1;
1226 free_function:
1227         pinmux_generic_remove_function(pcs->pctl, fsel);
1228 free_pins:
1229         mutex_unlock(&pcs->mutex);
1230         devm_kfree(pcs->dev, pins);
1231
1232 free_vals:
1233         devm_kfree(pcs->dev, vals);
1234
1235         return res;
1236 }
1237 /**
1238  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1239  * @pctldev: pinctrl instance
1240  * @np_config: device tree pinmux entry
1241  * @map: array of map entries
1242  * @num_maps: number of maps
1243  */
1244 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1245                                 struct device_node *np_config,
1246                                 struct pinctrl_map **map, unsigned *num_maps)
1247 {
1248         struct pcs_device *pcs;
1249         const char **pgnames;
1250         int ret;
1251
1252         pcs = pinctrl_dev_get_drvdata(pctldev);
1253
1254         /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1255         *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1256         if (!*map)
1257                 return -ENOMEM;
1258
1259         *num_maps = 0;
1260
1261         pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1262         if (!pgnames) {
1263                 ret = -ENOMEM;
1264                 goto free_map;
1265         }
1266
1267         if (pcs->bits_per_mux) {
1268                 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1269                                 num_maps, pgnames);
1270                 if (ret < 0) {
1271                         dev_err(pcs->dev, "no pins entries for %pOFn\n",
1272                                 np_config);
1273                         goto free_pgnames;
1274                 }
1275         } else {
1276                 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1277                                 num_maps, pgnames);
1278                 if (ret < 0) {
1279                         dev_err(pcs->dev, "no pins entries for %pOFn\n",
1280                                 np_config);
1281                         goto free_pgnames;
1282                 }
1283         }
1284
1285         return 0;
1286
1287 free_pgnames:
1288         devm_kfree(pcs->dev, pgnames);
1289 free_map:
1290         devm_kfree(pcs->dev, *map);
1291
1292         return ret;
1293 }
1294
1295 /**
1296  * pcs_irq_free() - free interrupt
1297  * @pcs: pcs driver instance
1298  */
1299 static void pcs_irq_free(struct pcs_device *pcs)
1300 {
1301         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1302
1303         if (pcs_soc->irq < 0)
1304                 return;
1305
1306         if (pcs->domain)
1307                 irq_domain_remove(pcs->domain);
1308
1309         if (PCS_QUIRK_HAS_SHARED_IRQ)
1310                 free_irq(pcs_soc->irq, pcs_soc);
1311         else
1312                 irq_set_chained_handler(pcs_soc->irq, NULL);
1313 }
1314
1315 /**
1316  * pcs_free_resources() - free memory used by this driver
1317  * @pcs: pcs driver instance
1318  */
1319 static void pcs_free_resources(struct pcs_device *pcs)
1320 {
1321         pcs_irq_free(pcs);
1322         pinctrl_unregister(pcs->pctl);
1323
1324 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1325         if (pcs->missing_nr_pinctrl_cells)
1326                 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1327 #endif
1328 }
1329
1330 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1331 {
1332         const char *propname = "pinctrl-single,gpio-range";
1333         const char *cellname = "#pinctrl-single,gpio-range-cells";
1334         struct of_phandle_args gpiospec;
1335         struct pcs_gpiofunc_range *range;
1336         int ret, i;
1337
1338         for (i = 0; ; i++) {
1339                 ret = of_parse_phandle_with_args(node, propname, cellname,
1340                                                  i, &gpiospec);
1341                 /* Do not treat it as error. Only treat it as end condition. */
1342                 if (ret) {
1343                         ret = 0;
1344                         break;
1345                 }
1346                 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1347                 if (!range) {
1348                         ret = -ENOMEM;
1349                         break;
1350                 }
1351                 range->offset = gpiospec.args[0];
1352                 range->npins = gpiospec.args[1];
1353                 range->gpiofunc = gpiospec.args[2];
1354                 mutex_lock(&pcs->mutex);
1355                 list_add_tail(&range->node, &pcs->gpiofuncs);
1356                 mutex_unlock(&pcs->mutex);
1357         }
1358         return ret;
1359 }
1360
1361 /**
1362  * struct pcs_interrupt
1363  * @reg:        virtual address of interrupt register
1364  * @hwirq:      hardware irq number
1365  * @irq:        virtual irq number
1366  * @node:       list node
1367  */
1368 struct pcs_interrupt {
1369         void __iomem *reg;
1370         irq_hw_number_t hwirq;
1371         unsigned int irq;
1372         struct list_head node;
1373 };
1374
1375 /**
1376  * pcs_irq_set() - enables or disables an interrupt
1377  * @pcs_soc: SoC specific settings
1378  * @irq: interrupt
1379  * @enable: enable or disable the interrupt
1380  *
1381  * Note that this currently assumes one interrupt per pinctrl
1382  * register that is typically used for wake-up events.
1383  */
1384 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1385                                int irq, const bool enable)
1386 {
1387         struct pcs_device *pcs;
1388         struct list_head *pos;
1389         unsigned mask;
1390
1391         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1392         list_for_each(pos, &pcs->irqs) {
1393                 struct pcs_interrupt *pcswi;
1394                 unsigned soc_mask;
1395
1396                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1397                 if (irq != pcswi->irq)
1398                         continue;
1399
1400                 soc_mask = pcs_soc->irq_enable_mask;
1401                 raw_spin_lock(&pcs->lock);
1402                 mask = pcs->read(pcswi->reg);
1403                 if (enable)
1404                         mask |= soc_mask;
1405                 else
1406                         mask &= ~soc_mask;
1407                 pcs->write(mask, pcswi->reg);
1408
1409                 /* flush posted write */
1410                 mask = pcs->read(pcswi->reg);
1411                 raw_spin_unlock(&pcs->lock);
1412         }
1413
1414         if (pcs_soc->rearm)
1415                 pcs_soc->rearm();
1416 }
1417
1418 /**
1419  * pcs_irq_mask() - mask pinctrl interrupt
1420  * @d: interrupt data
1421  */
1422 static void pcs_irq_mask(struct irq_data *d)
1423 {
1424         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1425
1426         pcs_irq_set(pcs_soc, d->irq, false);
1427 }
1428
1429 /**
1430  * pcs_irq_unmask() - unmask pinctrl interrupt
1431  * @d: interrupt data
1432  */
1433 static void pcs_irq_unmask(struct irq_data *d)
1434 {
1435         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1436
1437         pcs_irq_set(pcs_soc, d->irq, true);
1438 }
1439
1440 /**
1441  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1442  * @d: interrupt data
1443  * @state: wake-up state
1444  *
1445  * Note that this should be called only for suspend and resume.
1446  * For runtime PM, the wake-up events should be enabled by default.
1447  */
1448 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1449 {
1450         if (state)
1451                 pcs_irq_unmask(d);
1452         else
1453                 pcs_irq_mask(d);
1454
1455         return 0;
1456 }
1457
1458 /**
1459  * pcs_irq_handle() - common interrupt handler
1460  * @pcs_soc: SoC specific settings
1461  *
1462  * Note that this currently assumes we have one interrupt bit per
1463  * mux register. This interrupt is typically used for wake-up events.
1464  * For more complex interrupts different handlers can be specified.
1465  */
1466 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1467 {
1468         struct pcs_device *pcs;
1469         struct list_head *pos;
1470         int count = 0;
1471
1472         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1473         list_for_each(pos, &pcs->irqs) {
1474                 struct pcs_interrupt *pcswi;
1475                 unsigned mask;
1476
1477                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1478                 raw_spin_lock(&pcs->lock);
1479                 mask = pcs->read(pcswi->reg);
1480                 raw_spin_unlock(&pcs->lock);
1481                 if (mask & pcs_soc->irq_status_mask) {
1482                         generic_handle_irq(irq_find_mapping(pcs->domain,
1483                                                             pcswi->hwirq));
1484                         count++;
1485                 }
1486         }
1487
1488         return count;
1489 }
1490
1491 /**
1492  * pcs_irq_handler() - handler for the shared interrupt case
1493  * @irq: interrupt
1494  * @d: data
1495  *
1496  * Use this for cases where multiple instances of
1497  * pinctrl-single share a single interrupt like on omaps.
1498  */
1499 static irqreturn_t pcs_irq_handler(int irq, void *d)
1500 {
1501         struct pcs_soc_data *pcs_soc = d;
1502
1503         return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1504 }
1505
1506 /**
1507  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1508  * @desc: interrupt descriptor
1509  *
1510  * Use this if you have a separate interrupt for each
1511  * pinctrl-single instance.
1512  */
1513 static void pcs_irq_chain_handler(struct irq_desc *desc)
1514 {
1515         struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1516         struct irq_chip *chip;
1517
1518         chip = irq_desc_get_chip(desc);
1519         chained_irq_enter(chip, desc);
1520         pcs_irq_handle(pcs_soc);
1521         /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1522         chained_irq_exit(chip, desc);
1523 }
1524
1525 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1526                              irq_hw_number_t hwirq)
1527 {
1528         struct pcs_soc_data *pcs_soc = d->host_data;
1529         struct pcs_device *pcs;
1530         struct pcs_interrupt *pcswi;
1531
1532         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1533         pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1534         if (!pcswi)
1535                 return -ENOMEM;
1536
1537         pcswi->reg = pcs->base + hwirq;
1538         pcswi->hwirq = hwirq;
1539         pcswi->irq = irq;
1540
1541         mutex_lock(&pcs->mutex);
1542         list_add_tail(&pcswi->node, &pcs->irqs);
1543         mutex_unlock(&pcs->mutex);
1544
1545         irq_set_chip_data(irq, pcs_soc);
1546         irq_set_chip_and_handler(irq, &pcs->chip,
1547                                  handle_level_irq);
1548         irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1549         irq_set_noprobe(irq);
1550
1551         return 0;
1552 }
1553
1554 static const struct irq_domain_ops pcs_irqdomain_ops = {
1555         .map = pcs_irqdomain_map,
1556         .xlate = irq_domain_xlate_onecell,
1557 };
1558
1559 /**
1560  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1561  * @pcs: pcs driver instance
1562  * @np: device node pointer
1563  */
1564 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1565                                         struct device_node *np)
1566 {
1567         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1568         const char *name = "pinctrl";
1569         int num_irqs;
1570
1571         if (!pcs_soc->irq_enable_mask ||
1572             !pcs_soc->irq_status_mask) {
1573                 pcs_soc->irq = -1;
1574                 return -EINVAL;
1575         }
1576
1577         INIT_LIST_HEAD(&pcs->irqs);
1578         pcs->chip.name = name;
1579         pcs->chip.irq_ack = pcs_irq_mask;
1580         pcs->chip.irq_mask = pcs_irq_mask;
1581         pcs->chip.irq_unmask = pcs_irq_unmask;
1582         pcs->chip.irq_set_wake = pcs_irq_set_wake;
1583
1584         if (PCS_QUIRK_HAS_SHARED_IRQ) {
1585                 int res;
1586
1587                 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1588                                   IRQF_SHARED | IRQF_NO_SUSPEND |
1589                                   IRQF_NO_THREAD,
1590                                   name, pcs_soc);
1591                 if (res) {
1592                         pcs_soc->irq = -1;
1593                         return res;
1594                 }
1595         } else {
1596                 irq_set_chained_handler_and_data(pcs_soc->irq,
1597                                                  pcs_irq_chain_handler,
1598                                                  pcs_soc);
1599         }
1600
1601         /*
1602          * We can use the register offset as the hardirq
1603          * number as irq_domain_add_simple maps them lazily.
1604          * This way we can easily support more than one
1605          * interrupt per function if needed.
1606          */
1607         num_irqs = pcs->size;
1608
1609         pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1610                                             &pcs_irqdomain_ops,
1611                                             pcs_soc);
1612         if (!pcs->domain) {
1613                 irq_set_chained_handler(pcs_soc->irq, NULL);
1614                 return -EINVAL;
1615         }
1616
1617         return 0;
1618 }
1619
1620 #ifdef CONFIG_PM
1621 static int pcs_save_context(struct pcs_device *pcs)
1622 {
1623         int i, mux_bytes;
1624         u64 *regsl;
1625         u32 *regsw;
1626         u16 *regshw;
1627
1628         mux_bytes = pcs->width / BITS_PER_BYTE;
1629
1630         if (!pcs->saved_vals) {
1631                 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1632                 if (!pcs->saved_vals)
1633                         return -ENOMEM;
1634         }
1635
1636         switch (pcs->width) {
1637         case 64:
1638                 regsl = pcs->saved_vals;
1639                 for (i = 0; i < pcs->size; i += mux_bytes)
1640                         *regsl++ = pcs->read(pcs->base + i);
1641                 break;
1642         case 32:
1643                 regsw = pcs->saved_vals;
1644                 for (i = 0; i < pcs->size; i += mux_bytes)
1645                         *regsw++ = pcs->read(pcs->base + i);
1646                 break;
1647         case 16:
1648                 regshw = pcs->saved_vals;
1649                 for (i = 0; i < pcs->size; i += mux_bytes)
1650                         *regshw++ = pcs->read(pcs->base + i);
1651                 break;
1652         }
1653
1654         return 0;
1655 }
1656
1657 static void pcs_restore_context(struct pcs_device *pcs)
1658 {
1659         int i, mux_bytes;
1660         u64 *regsl;
1661         u32 *regsw;
1662         u16 *regshw;
1663
1664         mux_bytes = pcs->width / BITS_PER_BYTE;
1665
1666         switch (pcs->width) {
1667         case 64:
1668                 regsl = pcs->saved_vals;
1669                 for (i = 0; i < pcs->size; i += mux_bytes)
1670                         pcs->write(*regsl++, pcs->base + i);
1671                 break;
1672         case 32:
1673                 regsw = pcs->saved_vals;
1674                 for (i = 0; i < pcs->size; i += mux_bytes)
1675                         pcs->write(*regsw++, pcs->base + i);
1676                 break;
1677         case 16:
1678                 regshw = pcs->saved_vals;
1679                 for (i = 0; i < pcs->size; i += mux_bytes)
1680                         pcs->write(*regshw++, pcs->base + i);
1681                 break;
1682         }
1683 }
1684
1685 static int pinctrl_single_suspend(struct platform_device *pdev,
1686                                         pm_message_t state)
1687 {
1688         struct pcs_device *pcs;
1689
1690         pcs = platform_get_drvdata(pdev);
1691         if (!pcs)
1692                 return -EINVAL;
1693
1694         if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1695                 int ret;
1696
1697                 ret = pcs_save_context(pcs);
1698                 if (ret < 0)
1699                         return ret;
1700         }
1701
1702         return pinctrl_force_sleep(pcs->pctl);
1703 }
1704
1705 static int pinctrl_single_resume(struct platform_device *pdev)
1706 {
1707         struct pcs_device *pcs;
1708
1709         pcs = platform_get_drvdata(pdev);
1710         if (!pcs)
1711                 return -EINVAL;
1712
1713         if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1714                 pcs_restore_context(pcs);
1715
1716         return pinctrl_force_default(pcs->pctl);
1717 }
1718 #endif
1719
1720 /**
1721  * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1722  * @pcs: pinctrl driver instance
1723  * @np: device tree node
1724  * @cells: number of cells
1725  *
1726  * Handle legacy binding with no #pinctrl-cells. This should be
1727  * always two pinctrl-single,bit-per-mux and one for others.
1728  * At some point we may want to consider removing this.
1729  */
1730 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1731                                            struct device_node *np,
1732                                            int cells)
1733 {
1734         struct property *p;
1735         const char *name = "#pinctrl-cells";
1736         int error;
1737         u32 val;
1738
1739         error = of_property_read_u32(np, name, &val);
1740         if (!error)
1741                 return 0;
1742
1743         dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1744                  name, cells);
1745
1746         p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1747         if (!p)
1748                 return -ENOMEM;
1749
1750         p->length = sizeof(__be32);
1751         p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1752         if (!p->value)
1753                 return -ENOMEM;
1754         *(__be32 *)p->value = cpu_to_be32(cells);
1755
1756         p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1757         if (!p->name)
1758                 return -ENOMEM;
1759
1760         pcs->missing_nr_pinctrl_cells = p;
1761
1762 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1763         error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1764 #endif
1765
1766         return error;
1767 }
1768
1769 static int pcs_probe(struct platform_device *pdev)
1770 {
1771         struct device_node *np = pdev->dev.of_node;
1772         struct pcs_pdata *pdata;
1773         struct resource *res;
1774         struct pcs_device *pcs;
1775         const struct pcs_soc_data *soc;
1776         int ret;
1777
1778         soc = of_device_get_match_data(&pdev->dev);
1779         if (WARN_ON(!soc))
1780                 return -EINVAL;
1781
1782         pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1783         if (!pcs)
1784                 return -ENOMEM;
1785
1786         pcs->dev = &pdev->dev;
1787         pcs->np = np;
1788         raw_spin_lock_init(&pcs->lock);
1789         mutex_init(&pcs->mutex);
1790         INIT_LIST_HEAD(&pcs->gpiofuncs);
1791         pcs->flags = soc->flags;
1792         memcpy(&pcs->socdata, soc, sizeof(*soc));
1793
1794         ret = of_property_read_u32(np, "pinctrl-single,register-width",
1795                                    &pcs->width);
1796         if (ret) {
1797                 dev_err(pcs->dev, "register width not specified\n");
1798
1799                 return ret;
1800         }
1801
1802         ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1803                                    &pcs->fmask);
1804         if (!ret) {
1805                 pcs->fshift = __ffs(pcs->fmask);
1806                 pcs->fmax = pcs->fmask >> pcs->fshift;
1807         } else {
1808                 /* If mask property doesn't exist, function mux is invalid. */
1809                 pcs->fmask = 0;
1810                 pcs->fshift = 0;
1811                 pcs->fmax = 0;
1812         }
1813
1814         ret = of_property_read_u32(np, "pinctrl-single,function-off",
1815                                         &pcs->foff);
1816         if (ret)
1817                 pcs->foff = PCS_OFF_DISABLED;
1818
1819         pcs->bits_per_mux = of_property_read_bool(np,
1820                                                   "pinctrl-single,bit-per-mux");
1821         ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1822                                               pcs->bits_per_mux ? 2 : 1);
1823         if (ret) {
1824                 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1825
1826                 return ret;
1827         }
1828
1829         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1830         if (!res) {
1831                 dev_err(pcs->dev, "could not get resource\n");
1832                 return -ENODEV;
1833         }
1834
1835         pcs->res = devm_request_mem_region(pcs->dev, res->start,
1836                         resource_size(res), DRIVER_NAME);
1837         if (!pcs->res) {
1838                 dev_err(pcs->dev, "could not get mem_region\n");
1839                 return -EBUSY;
1840         }
1841
1842         pcs->size = resource_size(pcs->res);
1843         pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1844         if (!pcs->base) {
1845                 dev_err(pcs->dev, "could not ioremap\n");
1846                 return -ENODEV;
1847         }
1848
1849         platform_set_drvdata(pdev, pcs);
1850
1851         switch (pcs->width) {
1852         case 8:
1853                 pcs->read = pcs_readb;
1854                 pcs->write = pcs_writeb;
1855                 break;
1856         case 16:
1857                 pcs->read = pcs_readw;
1858                 pcs->write = pcs_writew;
1859                 break;
1860         case 32:
1861                 pcs->read = pcs_readl;
1862                 pcs->write = pcs_writel;
1863                 break;
1864         default:
1865                 break;
1866         }
1867
1868         pcs->desc.name = DRIVER_NAME;
1869         pcs->desc.pctlops = &pcs_pinctrl_ops;
1870         pcs->desc.pmxops = &pcs_pinmux_ops;
1871         if (PCS_HAS_PINCONF)
1872                 pcs->desc.confops = &pcs_pinconf_ops;
1873         pcs->desc.owner = THIS_MODULE;
1874
1875         ret = pcs_allocate_pin_table(pcs);
1876         if (ret < 0)
1877                 goto free;
1878
1879         ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1880         if (ret) {
1881                 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1882                 goto free;
1883         }
1884
1885         ret = pcs_add_gpio_func(np, pcs);
1886         if (ret < 0)
1887                 goto free;
1888
1889         pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1890         if (pcs->socdata.irq)
1891                 pcs->flags |= PCS_FEAT_IRQ;
1892
1893         /* We still need auxdata for some omaps for PRM interrupts */
1894         pdata = dev_get_platdata(&pdev->dev);
1895         if (pdata) {
1896                 if (pdata->rearm)
1897                         pcs->socdata.rearm = pdata->rearm;
1898                 if (pdata->irq) {
1899                         pcs->socdata.irq = pdata->irq;
1900                         pcs->flags |= PCS_FEAT_IRQ;
1901                 }
1902         }
1903
1904         if (PCS_HAS_IRQ) {
1905                 ret = pcs_irq_init_chained_handler(pcs, np);
1906                 if (ret < 0)
1907                         dev_warn(pcs->dev, "initialized with no interrupts\n");
1908         }
1909
1910         dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1911
1912         return pinctrl_enable(pcs->pctl);
1913
1914 free:
1915         pcs_free_resources(pcs);
1916
1917         return ret;
1918 }
1919
1920 static int pcs_remove(struct platform_device *pdev)
1921 {
1922         struct pcs_device *pcs = platform_get_drvdata(pdev);
1923
1924         if (!pcs)
1925                 return 0;
1926
1927         pcs_free_resources(pcs);
1928
1929         return 0;
1930 }
1931
1932 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1933         .flags = PCS_QUIRK_SHARED_IRQ,
1934         .irq_enable_mask = (1 << 14),   /* OMAP_WAKEUP_EN */
1935         .irq_status_mask = (1 << 15),   /* OMAP_WAKEUP_EVENT */
1936 };
1937
1938 static const struct pcs_soc_data pinctrl_single_dra7 = {
1939         .irq_enable_mask = (1 << 24),   /* WAKEUPENABLE */
1940         .irq_status_mask = (1 << 25),   /* WAKEUPEVENT */
1941 };
1942
1943 static const struct pcs_soc_data pinctrl_single_am437x = {
1944         .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1945         .irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */
1946         .irq_status_mask = (1 << 30),   /* OMAP_WAKEUP_EVENT */
1947 };
1948
1949 static const struct pcs_soc_data pinctrl_single = {
1950 };
1951
1952 static const struct pcs_soc_data pinconf_single = {
1953         .flags = PCS_FEAT_PINCONF,
1954 };
1955
1956 static const struct of_device_id pcs_of_match[] = {
1957         { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1958         { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1959         { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1960         { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1961         { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1962         { .compatible = "pinctrl-single", .data = &pinctrl_single },
1963         { .compatible = "pinconf-single", .data = &pinconf_single },
1964         { },
1965 };
1966 MODULE_DEVICE_TABLE(of, pcs_of_match);
1967
1968 static struct platform_driver pcs_driver = {
1969         .probe          = pcs_probe,
1970         .remove         = pcs_remove,
1971         .driver = {
1972                 .name           = DRIVER_NAME,
1973                 .of_match_table = pcs_of_match,
1974         },
1975 #ifdef CONFIG_PM
1976         .suspend = pinctrl_single_suspend,
1977         .resume = pinctrl_single_resume,
1978 #endif
1979 };
1980
1981 module_platform_driver(pcs_driver);
1982
1983 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1984 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1985 MODULE_LICENSE("GPL v2");