2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
5 * Copyright (C) 2012 Texas Instruments, Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/list.h>
18 #include <linux/interrupt.h>
20 #include <linux/irqchip/chained_irq.h>
23 #include <linux/of_device.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
34 #include "devicetree.h"
38 #define DRIVER_NAME "pinctrl-single"
39 #define PCS_OFF_DISABLED ~0U
42 * struct pcs_func_vals - mux function register offset and value pair
43 * @reg: register virtual address
44 * @val: register value
47 struct pcs_func_vals {
54 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
55 * and value, enable, disable, mask
56 * @param: config parameter
57 * @val: user input bits in the pinconf register
58 * @enable: enable bits in the pinconf register
59 * @disable: disable bits in the pinconf register
60 * @mask: mask bits in the register value
62 struct pcs_conf_vals {
63 enum pin_config_param param;
71 * struct pcs_conf_type - pinconf property name, pinconf param pair
72 * @name: property name in DTS file
73 * @param: config parameter
75 struct pcs_conf_type {
77 enum pin_config_param param;
81 * struct pcs_function - pinctrl function
82 * @name: pinctrl function name
83 * @vals: register and vals array
84 * @nvals: number of entries in vals array
85 * @pgnames: array of pingroup names the function uses
86 * @npgnames: number of pingroup names the function uses
87 * @conf: array of pin configurations
88 * @nconfs: number of pin configurations available
93 struct pcs_func_vals *vals;
97 struct pcs_conf_vals *conf;
99 struct list_head node;
103 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
104 * @offset: offset base of pins
105 * @npins: number pins with the same mux value of gpio function
106 * @gpiofunc: mux value of gpio function
109 struct pcs_gpiofunc_range {
113 struct list_head node;
117 * struct pcs_data - wrapper for data needed by pinctrl framework
119 * @cur: index to current element
121 * REVISIT: We should be able to drop this eventually by adding
122 * support for registering pins individually in the pinctrl
123 * framework for those drivers that don't need a static array.
126 struct pinctrl_pin_desc *pa;
131 * struct pcs_soc_data - SoC specific settings
132 * @flags: initial SoC specific PCS_FEAT_xxx values
133 * @irq: optional interrupt for the controller
134 * @irq_enable_mask: optional SoC specific interrupt enable mask
135 * @irq_status_mask: optional SoC specific interrupt status mask
136 * @rearm: optional SoC specific wake-up rearm function
138 struct pcs_soc_data {
141 unsigned irq_enable_mask;
142 unsigned irq_status_mask;
147 * struct pcs_device - pinctrl device instance
149 * @base: virtual address of the controller
150 * @saved_vals: saved values for the controller
151 * @size: size of the ioremapped area
153 * @np: device tree node
154 * @pctl: pin controller device
155 * @flags: mask of PCS_FEAT_xxx values
156 * @missing_nr_pinctrl_cells: for legacy binding, may go away
157 * @socdata: soc specific data
158 * @lock: spinlock for register access
159 * @mutex: mutex protecting the lists
160 * @width: bits per mux register
161 * @fmask: function register mask
162 * @fshift: function register shift
163 * @foff: value to turn mux off
164 * @fmax: max number of functions in fmask
165 * @bits_per_mux: number of bits per mux
166 * @bits_per_pin: number of bits per pin
167 * @pins: physical pins on the SoC
168 * @gpiofuncs: list of gpio functions
169 * @irqs: list of interrupt registers
170 * @chip: chip container for this instance
171 * @domain: IRQ domain for this instance
172 * @desc: pin controller descriptor
173 * @read: register read function to use
174 * @write: register write function to use
177 struct resource *res;
182 struct device_node *np;
183 struct pinctrl_dev *pctl;
185 #define PCS_CONTEXT_LOSS_OFF (1 << 3)
186 #define PCS_QUIRK_SHARED_IRQ (1 << 2)
187 #define PCS_FEAT_IRQ (1 << 1)
188 #define PCS_FEAT_PINCONF (1 << 0)
189 struct property *missing_nr_pinctrl_cells;
190 struct pcs_soc_data socdata;
199 unsigned bits_per_pin;
200 struct pcs_data pins;
201 struct list_head gpiofuncs;
202 struct list_head irqs;
203 struct irq_chip chip;
204 struct irq_domain *domain;
205 struct pinctrl_desc desc;
206 unsigned (*read)(void __iomem *reg);
207 void (*write)(unsigned val, void __iomem *reg);
210 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
211 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
212 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
214 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
215 unsigned long *config);
216 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
217 unsigned long *configs, unsigned num_configs);
219 static enum pin_config_param pcs_bias[] = {
220 PIN_CONFIG_BIAS_PULL_DOWN,
221 PIN_CONFIG_BIAS_PULL_UP,
225 * This lock class tells lockdep that irqchip core that this single
226 * pinctrl can be in a different category than its parents, so it won't
227 * report false recursion.
229 static struct lock_class_key pcs_lock_class;
231 /* Class for the IRQ request mutex */
232 static struct lock_class_key pcs_request_class;
235 * REVISIT: Reads and writes could eventually use regmap or something
236 * generic. But at least on omaps, some mux registers are performance
237 * critical as they may need to be remuxed every time before and after
238 * idle. Adding tests for register access width for every read and
239 * write like regmap is doing is not desired, and caching the registers
240 * does not help in this case.
243 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
248 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
253 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
258 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
263 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
268 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
273 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
277 struct pcs_device *pcs;
278 unsigned val, mux_bytes;
279 unsigned long offset;
282 pcs = pinctrl_dev_get_drvdata(pctldev);
284 mux_bytes = pcs->width / BITS_PER_BYTE;
285 offset = pin * mux_bytes;
286 val = pcs->read(pcs->base + offset);
287 pa = pcs->res->start + offset;
289 seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
292 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
293 struct pinctrl_map *map, unsigned num_maps)
295 struct pcs_device *pcs;
297 pcs = pinctrl_dev_get_drvdata(pctldev);
298 devm_kfree(pcs->dev, map);
301 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
302 struct device_node *np_config,
303 struct pinctrl_map **map, unsigned *num_maps);
305 static const struct pinctrl_ops pcs_pinctrl_ops = {
306 .get_groups_count = pinctrl_generic_get_group_count,
307 .get_group_name = pinctrl_generic_get_group_name,
308 .get_group_pins = pinctrl_generic_get_group_pins,
309 .pin_dbg_show = pcs_pin_dbg_show,
310 .dt_node_to_map = pcs_dt_node_to_map,
311 .dt_free_map = pcs_dt_free_map,
314 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
315 struct pcs_function **func)
317 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
318 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
319 const struct pinctrl_setting_mux *setting;
320 struct function_desc *function;
323 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
324 setting = pdesc->mux_setting;
327 fselector = setting->func;
328 function = pinmux_generic_get_function(pctldev, fselector);
329 *func = function->data;
331 dev_err(pcs->dev, "%s could not find function%i\n",
332 __func__, fselector);
338 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
341 struct pcs_device *pcs;
342 struct function_desc *function;
343 struct pcs_function *func;
346 pcs = pinctrl_dev_get_drvdata(pctldev);
347 /* If function mask is null, needn't enable it. */
350 function = pinmux_generic_get_function(pctldev, fselector);
351 func = function->data;
355 dev_dbg(pcs->dev, "enabling %s function%i\n",
356 func->name, fselector);
358 for (i = 0; i < func->nvals; i++) {
359 struct pcs_func_vals *vals;
363 vals = &func->vals[i];
364 raw_spin_lock_irqsave(&pcs->lock, flags);
365 val = pcs->read(vals->reg);
367 if (pcs->bits_per_mux)
373 val |= (vals->val & mask);
374 pcs->write(val, vals->reg);
375 raw_spin_unlock_irqrestore(&pcs->lock, flags);
381 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
382 struct pinctrl_gpio_range *range, unsigned pin)
384 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
385 struct pcs_gpiofunc_range *frange = NULL;
386 struct list_head *pos, *tmp;
390 /* If function mask is null, return directly. */
394 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
395 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
396 if (pin >= frange->offset + frange->npins
397 || pin < frange->offset)
399 mux_bytes = pcs->width / BITS_PER_BYTE;
401 if (pcs->bits_per_mux) {
402 int byte_num, offset, pin_shift;
404 byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
405 offset = (byte_num / mux_bytes) * mux_bytes;
406 pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
409 data = pcs->read(pcs->base + offset);
410 data &= ~(pcs->fmask << pin_shift);
411 data |= frange->gpiofunc << pin_shift;
412 pcs->write(data, pcs->base + offset);
414 data = pcs->read(pcs->base + pin * mux_bytes);
416 data |= frange->gpiofunc;
417 pcs->write(data, pcs->base + pin * mux_bytes);
424 static const struct pinmux_ops pcs_pinmux_ops = {
425 .get_functions_count = pinmux_generic_get_function_count,
426 .get_function_name = pinmux_generic_get_function_name,
427 .get_function_groups = pinmux_generic_get_function_groups,
428 .set_mux = pcs_set_mux,
429 .gpio_request_enable = pcs_request_gpio,
432 /* Clear BIAS value */
433 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
435 unsigned long config;
437 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
438 config = pinconf_to_config_packed(pcs_bias[i], 0);
439 pcs_pinconf_set(pctldev, pin, &config, 1);
444 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
445 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
447 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
449 unsigned long config;
452 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
453 config = pinconf_to_config_packed(pcs_bias[i], 0);
454 if (!pcs_pinconf_get(pctldev, pin, &config))
462 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
463 unsigned pin, unsigned long *config)
465 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
466 struct pcs_function *func;
467 enum pin_config_param param;
468 unsigned offset = 0, data = 0, i, j, ret;
470 ret = pcs_get_function(pctldev, pin, &func);
474 for (i = 0; i < func->nconfs; i++) {
475 param = pinconf_to_config_param(*config);
476 if (param == PIN_CONFIG_BIAS_DISABLE) {
477 if (pcs_pinconf_bias_disable(pctldev, pin)) {
483 } else if (param != func->conf[i].param) {
487 offset = pin * (pcs->width / BITS_PER_BYTE);
488 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
489 switch (func->conf[i].param) {
491 case PIN_CONFIG_BIAS_PULL_DOWN:
492 case PIN_CONFIG_BIAS_PULL_UP:
493 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
494 if ((data != func->conf[i].enable) ||
495 (data == func->conf[i].disable))
500 case PIN_CONFIG_INPUT_SCHMITT:
501 for (j = 0; j < func->nconfs; j++) {
502 switch (func->conf[j].param) {
503 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
504 if (data != func->conf[j].enable)
513 case PIN_CONFIG_DRIVE_STRENGTH:
514 case PIN_CONFIG_SLEW_RATE:
515 case PIN_CONFIG_LOW_POWER_MODE:
525 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
526 unsigned pin, unsigned long *configs,
527 unsigned num_configs)
529 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
530 struct pcs_function *func;
531 unsigned offset = 0, shift = 0, i, data, ret;
535 ret = pcs_get_function(pctldev, pin, &func);
539 for (j = 0; j < num_configs; j++) {
540 for (i = 0; i < func->nconfs; i++) {
541 if (pinconf_to_config_param(configs[j])
542 != func->conf[i].param)
545 offset = pin * (pcs->width / BITS_PER_BYTE);
546 data = pcs->read(pcs->base + offset);
547 arg = pinconf_to_config_argument(configs[j]);
548 switch (func->conf[i].param) {
550 case PIN_CONFIG_INPUT_SCHMITT:
551 case PIN_CONFIG_DRIVE_STRENGTH:
552 case PIN_CONFIG_SLEW_RATE:
553 case PIN_CONFIG_LOW_POWER_MODE:
554 shift = ffs(func->conf[i].mask) - 1;
555 data &= ~func->conf[i].mask;
556 data |= (arg << shift) & func->conf[i].mask;
559 case PIN_CONFIG_BIAS_DISABLE:
560 pcs_pinconf_clear_bias(pctldev, pin);
562 case PIN_CONFIG_BIAS_PULL_DOWN:
563 case PIN_CONFIG_BIAS_PULL_UP:
565 pcs_pinconf_clear_bias(pctldev, pin);
567 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
568 data &= ~func->conf[i].mask;
570 data |= func->conf[i].enable;
572 data |= func->conf[i].disable;
577 pcs->write(data, pcs->base + offset);
581 if (i >= func->nconfs)
583 } /* for each config */
588 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
589 unsigned group, unsigned long *config)
591 const unsigned *pins;
592 unsigned npins, old = 0;
595 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
598 for (i = 0; i < npins; i++) {
599 if (pcs_pinconf_get(pctldev, pins[i], config))
601 /* configs do not match between two pins */
602 if (i && (old != *config))
609 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
610 unsigned group, unsigned long *configs,
611 unsigned num_configs)
613 const unsigned *pins;
617 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
620 for (i = 0; i < npins; i++) {
621 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
627 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
628 struct seq_file *s, unsigned pin)
632 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
633 struct seq_file *s, unsigned selector)
637 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
639 unsigned long config)
641 pinconf_generic_dump_config(pctldev, s, config);
644 static const struct pinconf_ops pcs_pinconf_ops = {
645 .pin_config_get = pcs_pinconf_get,
646 .pin_config_set = pcs_pinconf_set,
647 .pin_config_group_get = pcs_pinconf_group_get,
648 .pin_config_group_set = pcs_pinconf_group_set,
649 .pin_config_dbg_show = pcs_pinconf_dbg_show,
650 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
651 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
656 * pcs_add_pin() - add a pin to the static per controller pin array
657 * @pcs: pcs driver instance
658 * @offset: register offset from base
661 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
664 struct pcs_soc_data *pcs_soc = &pcs->socdata;
665 struct pinctrl_pin_desc *pin;
669 if (i >= pcs->desc.npins) {
670 dev_err(pcs->dev, "too many pins, max %i\n",
675 if (pcs_soc->irq_enable_mask) {
678 val = pcs->read(pcs->base + offset);
679 if (val & pcs_soc->irq_enable_mask) {
680 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
681 (unsigned long)pcs->res->start + offset, val);
682 val &= ~pcs_soc->irq_enable_mask;
683 pcs->write(val, pcs->base + offset);
687 pin = &pcs->pins.pa[i];
695 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
696 * @pcs: pcs driver instance
698 * In case of errors, resources are freed in pcs_free_resources.
700 * If your hardware needs holes in the address space, then just set
701 * up multiple driver instances.
703 static int pcs_allocate_pin_table(struct pcs_device *pcs)
705 int mux_bytes, nr_pins, i;
706 int num_pins_in_register = 0;
708 mux_bytes = pcs->width / BITS_PER_BYTE;
710 if (pcs->bits_per_mux) {
711 pcs->bits_per_pin = fls(pcs->fmask);
712 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
713 num_pins_in_register = pcs->width / pcs->bits_per_pin;
715 nr_pins = pcs->size / mux_bytes;
718 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
719 pcs->pins.pa = devm_kcalloc(pcs->dev,
720 nr_pins, sizeof(*pcs->pins.pa),
725 pcs->desc.pins = pcs->pins.pa;
726 pcs->desc.npins = nr_pins;
728 for (i = 0; i < pcs->desc.npins; i++) {
734 if (pcs->bits_per_mux) {
735 byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
736 offset = (byte_num / mux_bytes) * mux_bytes;
737 pin_pos = i % num_pins_in_register;
739 offset = i * mux_bytes;
741 res = pcs_add_pin(pcs, offset, pin_pos);
743 dev_err(pcs->dev, "error adding pins: %i\n", res);
752 * pcs_add_function() - adds a new function to the function list
753 * @pcs: pcs driver instance
754 * @fcn: new function allocated
755 * @name: name of the function
756 * @vals: array of mux register value pairs used by the function
757 * @nvals: number of mux register value pairs
758 * @pgnames: array of pingroup names for the function
759 * @npgnames: number of pingroup names
761 * Caller must take care of locking.
763 static int pcs_add_function(struct pcs_device *pcs,
764 struct pcs_function **fcn,
766 struct pcs_func_vals *vals,
768 const char **pgnames,
769 unsigned int npgnames)
771 struct pcs_function *function;
774 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
778 function->vals = vals;
779 function->nvals = nvals;
780 function->name = name;
782 selector = pinmux_generic_add_function(pcs->pctl, name,
786 devm_kfree(pcs->dev, function);
796 * pcs_get_pin_by_offset() - get a pin index based on the register offset
797 * @pcs: pcs driver instance
798 * @offset: register offset from the base
800 * Note that this is OK as long as the pins are in a static array.
802 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
806 if (offset >= pcs->size) {
807 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
812 if (pcs->bits_per_mux)
813 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
815 index = offset / (pcs->width / BITS_PER_BYTE);
821 * check whether data matches enable bits or disable bits
822 * Return value: 1 for matching enable bits, 0 for matching disable bits,
823 * and negative value for matching failure.
825 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
831 else if (data == disable)
836 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
837 unsigned value, unsigned enable, unsigned disable,
840 (*conf)->param = param;
841 (*conf)->val = value;
842 (*conf)->enable = enable;
843 (*conf)->disable = disable;
844 (*conf)->mask = mask;
848 static void add_setting(unsigned long **setting, enum pin_config_param param,
851 **setting = pinconf_to_config_packed(param, arg);
855 /* add pinconf setting with 2 parameters */
856 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
857 const char *name, enum pin_config_param param,
858 struct pcs_conf_vals **conf, unsigned long **settings)
860 unsigned value[2], shift;
863 ret = of_property_read_u32_array(np, name, value, 2);
866 /* set value & mask */
867 value[0] &= value[1];
868 shift = ffs(value[1]) - 1;
869 /* skip enable & disable */
870 add_config(conf, param, value[0], 0, 0, value[1]);
871 add_setting(settings, param, value[0] >> shift);
874 /* add pinconf setting with 4 parameters */
875 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
876 const char *name, enum pin_config_param param,
877 struct pcs_conf_vals **conf, unsigned long **settings)
882 /* value to set, enable, disable, mask */
883 ret = of_property_read_u32_array(np, name, value, 4);
887 dev_err(pcs->dev, "mask field of the property can't be 0\n");
890 value[0] &= value[3];
891 value[1] &= value[3];
892 value[2] &= value[3];
893 ret = pcs_config_match(value[0], value[1], value[2]);
895 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
896 add_config(conf, param, value[0], value[1], value[2], value[3]);
897 add_setting(settings, param, ret);
900 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
901 struct pcs_function *func,
902 struct pinctrl_map **map)
905 struct pinctrl_map *m = *map;
906 int i = 0, nconfs = 0;
907 unsigned long *settings = NULL, *s = NULL;
908 struct pcs_conf_vals *conf = NULL;
909 static const struct pcs_conf_type prop2[] = {
910 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
911 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
912 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
913 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
915 static const struct pcs_conf_type prop4[] = {
916 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
917 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
918 { "pinctrl-single,input-schmitt-enable",
919 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
922 /* If pinconf isn't supported, don't parse properties in below. */
923 if (!PCS_HAS_PINCONF)
926 /* cacluate how much properties are supported in current node */
927 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
928 if (of_find_property(np, prop2[i].name, NULL))
931 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
932 if (of_find_property(np, prop4[i].name, NULL))
938 func->conf = devm_kcalloc(pcs->dev,
939 nconfs, sizeof(struct pcs_conf_vals),
943 func->nconfs = nconfs;
944 conf = &(func->conf[0]);
946 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
952 for (i = 0; i < ARRAY_SIZE(prop2); i++)
953 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
955 for (i = 0; i < ARRAY_SIZE(prop4); i++)
956 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
958 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
959 m->data.configs.group_or_pin = np->name;
960 m->data.configs.configs = settings;
961 m->data.configs.num_configs = nconfs;
966 * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
967 * @pcs: pinctrl driver instance
968 * @np: device node of the mux entry
970 * @num_maps: number of map
971 * @pgnames: pingroup names
973 * Note that this binding currently supports only sets of one register + value.
975 * Also note that this driver tries to avoid understanding pin and function
976 * names because of the extra bloat they would cause especially in the case of
977 * a large number of pins. This driver just sets what is specified for the board
978 * in the .dts file. Further user space debugging tools can be developed to
979 * decipher the pin and function names using debugfs.
981 * If you are concerned about the boot time, set up the static pins in
982 * the bootloader, and only set up selected pins as device tree entries.
984 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
985 struct device_node *np,
986 struct pinctrl_map **map,
988 const char **pgnames)
990 const char *name = "pinctrl-single,pins";
991 struct pcs_func_vals *vals;
992 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
993 struct pcs_function *function = NULL;
995 rows = pinctrl_count_index_with_args(np, name);
997 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1001 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1005 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1009 for (i = 0; i < rows; i++) {
1010 struct of_phandle_args pinctrl_spec;
1011 unsigned int offset;
1014 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1018 if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) {
1019 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1020 pinctrl_spec.args_count);
1024 offset = pinctrl_spec.args[0];
1025 vals[found].reg = pcs->base + offset;
1027 switch (pinctrl_spec.args_count) {
1029 vals[found].val = pinctrl_spec.args[1];
1032 vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
1036 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1037 pinctrl_spec.np, offset, vals[found].val);
1039 pin = pcs_get_pin_by_offset(pcs, offset);
1042 "could not add functions for %pOFn %ux\n",
1046 pins[found++] = pin;
1049 pgnames[0] = np->name;
1050 mutex_lock(&pcs->mutex);
1051 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1058 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1064 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1065 (*map)->data.mux.group = np->name;
1066 (*map)->data.mux.function = np->name;
1068 if (PCS_HAS_PINCONF && function) {
1069 res = pcs_parse_pinconf(pcs, np, function, map);
1072 else if (res == -ENOTSUPP)
1075 goto free_pingroups;
1079 mutex_unlock(&pcs->mutex);
1084 pinctrl_generic_remove_group(pcs->pctl, gsel);
1087 pinmux_generic_remove_function(pcs->pctl, fsel);
1089 mutex_unlock(&pcs->mutex);
1090 devm_kfree(pcs->dev, pins);
1093 devm_kfree(pcs->dev, vals);
1098 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1099 struct device_node *np,
1100 struct pinctrl_map **map,
1102 const char **pgnames)
1104 const char *name = "pinctrl-single,bits";
1105 struct pcs_func_vals *vals;
1106 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1108 struct pcs_function *function = NULL;
1110 rows = pinctrl_count_index_with_args(np, name);
1112 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1116 npins_in_row = pcs->width / pcs->bits_per_pin;
1118 vals = devm_kzalloc(pcs->dev,
1119 array3_size(rows, npins_in_row, sizeof(*vals)),
1124 pins = devm_kzalloc(pcs->dev,
1125 array3_size(rows, npins_in_row, sizeof(*pins)),
1130 for (i = 0; i < rows; i++) {
1131 struct of_phandle_args pinctrl_spec;
1132 unsigned offset, val;
1133 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1134 unsigned pin_num_from_lsb;
1137 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1141 if (pinctrl_spec.args_count < 3) {
1142 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1143 pinctrl_spec.args_count);
1147 /* Index plus two value cells */
1148 offset = pinctrl_spec.args[0];
1149 val = pinctrl_spec.args[1];
1150 mask = pinctrl_spec.args[2];
1152 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1153 pinctrl_spec.np, offset, val, mask);
1155 /* Parse pins in each row from LSB */
1157 bit_pos = __ffs(mask);
1158 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1159 mask_pos = ((pcs->fmask) << bit_pos);
1160 val_pos = val & mask_pos;
1161 submask = mask & mask_pos;
1163 if ((mask & mask_pos) == 0) {
1165 "Invalid mask for %pOFn at 0x%x\n",
1172 if (submask != mask_pos) {
1174 "Invalid submask 0x%x for %pOFn at 0x%x\n",
1175 submask, np, offset);
1179 vals[found].mask = submask;
1180 vals[found].reg = pcs->base + offset;
1181 vals[found].val = val_pos;
1183 pin = pcs_get_pin_by_offset(pcs, offset);
1186 "could not add functions for %pOFn %ux\n",
1190 pins[found++] = pin + pin_num_from_lsb;
1194 pgnames[0] = np->name;
1195 mutex_lock(&pcs->mutex);
1196 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1203 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1209 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1210 (*map)->data.mux.group = np->name;
1211 (*map)->data.mux.function = np->name;
1213 if (PCS_HAS_PINCONF) {
1214 dev_err(pcs->dev, "pinconf not supported\n");
1215 goto free_pingroups;
1219 mutex_unlock(&pcs->mutex);
1224 pinctrl_generic_remove_group(pcs->pctl, gsel);
1227 pinmux_generic_remove_function(pcs->pctl, fsel);
1229 mutex_unlock(&pcs->mutex);
1230 devm_kfree(pcs->dev, pins);
1233 devm_kfree(pcs->dev, vals);
1238 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1239 * @pctldev: pinctrl instance
1240 * @np_config: device tree pinmux entry
1241 * @map: array of map entries
1242 * @num_maps: number of maps
1244 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1245 struct device_node *np_config,
1246 struct pinctrl_map **map, unsigned *num_maps)
1248 struct pcs_device *pcs;
1249 const char **pgnames;
1252 pcs = pinctrl_dev_get_drvdata(pctldev);
1254 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1255 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1261 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1267 if (pcs->bits_per_mux) {
1268 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1271 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1276 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1279 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1288 devm_kfree(pcs->dev, pgnames);
1290 devm_kfree(pcs->dev, *map);
1296 * pcs_irq_free() - free interrupt
1297 * @pcs: pcs driver instance
1299 static void pcs_irq_free(struct pcs_device *pcs)
1301 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1303 if (pcs_soc->irq < 0)
1307 irq_domain_remove(pcs->domain);
1309 if (PCS_QUIRK_HAS_SHARED_IRQ)
1310 free_irq(pcs_soc->irq, pcs_soc);
1312 irq_set_chained_handler(pcs_soc->irq, NULL);
1316 * pcs_free_resources() - free memory used by this driver
1317 * @pcs: pcs driver instance
1319 static void pcs_free_resources(struct pcs_device *pcs)
1322 pinctrl_unregister(pcs->pctl);
1324 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1325 if (pcs->missing_nr_pinctrl_cells)
1326 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1330 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1332 const char *propname = "pinctrl-single,gpio-range";
1333 const char *cellname = "#pinctrl-single,gpio-range-cells";
1334 struct of_phandle_args gpiospec;
1335 struct pcs_gpiofunc_range *range;
1338 for (i = 0; ; i++) {
1339 ret = of_parse_phandle_with_args(node, propname, cellname,
1341 /* Do not treat it as error. Only treat it as end condition. */
1346 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1351 range->offset = gpiospec.args[0];
1352 range->npins = gpiospec.args[1];
1353 range->gpiofunc = gpiospec.args[2];
1354 mutex_lock(&pcs->mutex);
1355 list_add_tail(&range->node, &pcs->gpiofuncs);
1356 mutex_unlock(&pcs->mutex);
1362 * struct pcs_interrupt
1363 * @reg: virtual address of interrupt register
1364 * @hwirq: hardware irq number
1365 * @irq: virtual irq number
1368 struct pcs_interrupt {
1370 irq_hw_number_t hwirq;
1372 struct list_head node;
1376 * pcs_irq_set() - enables or disables an interrupt
1377 * @pcs_soc: SoC specific settings
1379 * @enable: enable or disable the interrupt
1381 * Note that this currently assumes one interrupt per pinctrl
1382 * register that is typically used for wake-up events.
1384 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1385 int irq, const bool enable)
1387 struct pcs_device *pcs;
1388 struct list_head *pos;
1391 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1392 list_for_each(pos, &pcs->irqs) {
1393 struct pcs_interrupt *pcswi;
1396 pcswi = list_entry(pos, struct pcs_interrupt, node);
1397 if (irq != pcswi->irq)
1400 soc_mask = pcs_soc->irq_enable_mask;
1401 raw_spin_lock(&pcs->lock);
1402 mask = pcs->read(pcswi->reg);
1407 pcs->write(mask, pcswi->reg);
1409 /* flush posted write */
1410 mask = pcs->read(pcswi->reg);
1411 raw_spin_unlock(&pcs->lock);
1419 * pcs_irq_mask() - mask pinctrl interrupt
1420 * @d: interrupt data
1422 static void pcs_irq_mask(struct irq_data *d)
1424 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1426 pcs_irq_set(pcs_soc, d->irq, false);
1430 * pcs_irq_unmask() - unmask pinctrl interrupt
1431 * @d: interrupt data
1433 static void pcs_irq_unmask(struct irq_data *d)
1435 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1437 pcs_irq_set(pcs_soc, d->irq, true);
1441 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1442 * @d: interrupt data
1443 * @state: wake-up state
1445 * Note that this should be called only for suspend and resume.
1446 * For runtime PM, the wake-up events should be enabled by default.
1448 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1459 * pcs_irq_handle() - common interrupt handler
1460 * @pcs_soc: SoC specific settings
1462 * Note that this currently assumes we have one interrupt bit per
1463 * mux register. This interrupt is typically used for wake-up events.
1464 * For more complex interrupts different handlers can be specified.
1466 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1468 struct pcs_device *pcs;
1469 struct list_head *pos;
1472 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1473 list_for_each(pos, &pcs->irqs) {
1474 struct pcs_interrupt *pcswi;
1477 pcswi = list_entry(pos, struct pcs_interrupt, node);
1478 raw_spin_lock(&pcs->lock);
1479 mask = pcs->read(pcswi->reg);
1480 raw_spin_unlock(&pcs->lock);
1481 if (mask & pcs_soc->irq_status_mask) {
1482 generic_handle_irq(irq_find_mapping(pcs->domain,
1492 * pcs_irq_handler() - handler for the shared interrupt case
1496 * Use this for cases where multiple instances of
1497 * pinctrl-single share a single interrupt like on omaps.
1499 static irqreturn_t pcs_irq_handler(int irq, void *d)
1501 struct pcs_soc_data *pcs_soc = d;
1503 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1507 * pcs_irq_handle() - handler for the dedicated chained interrupt case
1508 * @desc: interrupt descriptor
1510 * Use this if you have a separate interrupt for each
1511 * pinctrl-single instance.
1513 static void pcs_irq_chain_handler(struct irq_desc *desc)
1515 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1516 struct irq_chip *chip;
1518 chip = irq_desc_get_chip(desc);
1519 chained_irq_enter(chip, desc);
1520 pcs_irq_handle(pcs_soc);
1521 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1522 chained_irq_exit(chip, desc);
1525 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1526 irq_hw_number_t hwirq)
1528 struct pcs_soc_data *pcs_soc = d->host_data;
1529 struct pcs_device *pcs;
1530 struct pcs_interrupt *pcswi;
1532 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1533 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1537 pcswi->reg = pcs->base + hwirq;
1538 pcswi->hwirq = hwirq;
1541 mutex_lock(&pcs->mutex);
1542 list_add_tail(&pcswi->node, &pcs->irqs);
1543 mutex_unlock(&pcs->mutex);
1545 irq_set_chip_data(irq, pcs_soc);
1546 irq_set_chip_and_handler(irq, &pcs->chip,
1548 irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1549 irq_set_noprobe(irq);
1554 static const struct irq_domain_ops pcs_irqdomain_ops = {
1555 .map = pcs_irqdomain_map,
1556 .xlate = irq_domain_xlate_onecell,
1560 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1561 * @pcs: pcs driver instance
1562 * @np: device node pointer
1564 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1565 struct device_node *np)
1567 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1568 const char *name = "pinctrl";
1571 if (!pcs_soc->irq_enable_mask ||
1572 !pcs_soc->irq_status_mask) {
1577 INIT_LIST_HEAD(&pcs->irqs);
1578 pcs->chip.name = name;
1579 pcs->chip.irq_ack = pcs_irq_mask;
1580 pcs->chip.irq_mask = pcs_irq_mask;
1581 pcs->chip.irq_unmask = pcs_irq_unmask;
1582 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1584 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1587 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1588 IRQF_SHARED | IRQF_NO_SUSPEND |
1596 irq_set_chained_handler_and_data(pcs_soc->irq,
1597 pcs_irq_chain_handler,
1602 * We can use the register offset as the hardirq
1603 * number as irq_domain_add_simple maps them lazily.
1604 * This way we can easily support more than one
1605 * interrupt per function if needed.
1607 num_irqs = pcs->size;
1609 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1613 irq_set_chained_handler(pcs_soc->irq, NULL);
1621 static int pcs_save_context(struct pcs_device *pcs)
1628 mux_bytes = pcs->width / BITS_PER_BYTE;
1630 if (!pcs->saved_vals) {
1631 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1632 if (!pcs->saved_vals)
1636 switch (pcs->width) {
1638 regsl = pcs->saved_vals;
1639 for (i = 0; i < pcs->size; i += mux_bytes)
1640 *regsl++ = pcs->read(pcs->base + i);
1643 regsw = pcs->saved_vals;
1644 for (i = 0; i < pcs->size; i += mux_bytes)
1645 *regsw++ = pcs->read(pcs->base + i);
1648 regshw = pcs->saved_vals;
1649 for (i = 0; i < pcs->size; i += mux_bytes)
1650 *regshw++ = pcs->read(pcs->base + i);
1657 static void pcs_restore_context(struct pcs_device *pcs)
1664 mux_bytes = pcs->width / BITS_PER_BYTE;
1666 switch (pcs->width) {
1668 regsl = pcs->saved_vals;
1669 for (i = 0; i < pcs->size; i += mux_bytes)
1670 pcs->write(*regsl++, pcs->base + i);
1673 regsw = pcs->saved_vals;
1674 for (i = 0; i < pcs->size; i += mux_bytes)
1675 pcs->write(*regsw++, pcs->base + i);
1678 regshw = pcs->saved_vals;
1679 for (i = 0; i < pcs->size; i += mux_bytes)
1680 pcs->write(*regshw++, pcs->base + i);
1685 static int pinctrl_single_suspend(struct platform_device *pdev,
1688 struct pcs_device *pcs;
1690 pcs = platform_get_drvdata(pdev);
1694 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1697 ret = pcs_save_context(pcs);
1702 return pinctrl_force_sleep(pcs->pctl);
1705 static int pinctrl_single_resume(struct platform_device *pdev)
1707 struct pcs_device *pcs;
1709 pcs = platform_get_drvdata(pdev);
1713 if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1714 pcs_restore_context(pcs);
1716 return pinctrl_force_default(pcs->pctl);
1721 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1722 * @pcs: pinctrl driver instance
1723 * @np: device tree node
1724 * @cells: number of cells
1726 * Handle legacy binding with no #pinctrl-cells. This should be
1727 * always two pinctrl-single,bit-per-mux and one for others.
1728 * At some point we may want to consider removing this.
1730 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1731 struct device_node *np,
1735 const char *name = "#pinctrl-cells";
1739 error = of_property_read_u32(np, name, &val);
1743 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1746 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1750 p->length = sizeof(__be32);
1751 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1754 *(__be32 *)p->value = cpu_to_be32(cells);
1756 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1760 pcs->missing_nr_pinctrl_cells = p;
1762 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1763 error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1769 static int pcs_probe(struct platform_device *pdev)
1771 struct device_node *np = pdev->dev.of_node;
1772 struct pcs_pdata *pdata;
1773 struct resource *res;
1774 struct pcs_device *pcs;
1775 const struct pcs_soc_data *soc;
1778 soc = of_device_get_match_data(&pdev->dev);
1782 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1786 pcs->dev = &pdev->dev;
1788 raw_spin_lock_init(&pcs->lock);
1789 mutex_init(&pcs->mutex);
1790 INIT_LIST_HEAD(&pcs->gpiofuncs);
1791 pcs->flags = soc->flags;
1792 memcpy(&pcs->socdata, soc, sizeof(*soc));
1794 ret = of_property_read_u32(np, "pinctrl-single,register-width",
1797 dev_err(pcs->dev, "register width not specified\n");
1802 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1805 pcs->fshift = __ffs(pcs->fmask);
1806 pcs->fmax = pcs->fmask >> pcs->fshift;
1808 /* If mask property doesn't exist, function mux is invalid. */
1814 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1817 pcs->foff = PCS_OFF_DISABLED;
1819 pcs->bits_per_mux = of_property_read_bool(np,
1820 "pinctrl-single,bit-per-mux");
1821 ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1822 pcs->bits_per_mux ? 2 : 1);
1824 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1829 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1831 dev_err(pcs->dev, "could not get resource\n");
1835 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1836 resource_size(res), DRIVER_NAME);
1838 dev_err(pcs->dev, "could not get mem_region\n");
1842 pcs->size = resource_size(pcs->res);
1843 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1845 dev_err(pcs->dev, "could not ioremap\n");
1849 platform_set_drvdata(pdev, pcs);
1851 switch (pcs->width) {
1853 pcs->read = pcs_readb;
1854 pcs->write = pcs_writeb;
1857 pcs->read = pcs_readw;
1858 pcs->write = pcs_writew;
1861 pcs->read = pcs_readl;
1862 pcs->write = pcs_writel;
1868 pcs->desc.name = DRIVER_NAME;
1869 pcs->desc.pctlops = &pcs_pinctrl_ops;
1870 pcs->desc.pmxops = &pcs_pinmux_ops;
1871 if (PCS_HAS_PINCONF)
1872 pcs->desc.confops = &pcs_pinconf_ops;
1873 pcs->desc.owner = THIS_MODULE;
1875 ret = pcs_allocate_pin_table(pcs);
1879 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1881 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1885 ret = pcs_add_gpio_func(np, pcs);
1889 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1890 if (pcs->socdata.irq)
1891 pcs->flags |= PCS_FEAT_IRQ;
1893 /* We still need auxdata for some omaps for PRM interrupts */
1894 pdata = dev_get_platdata(&pdev->dev);
1897 pcs->socdata.rearm = pdata->rearm;
1899 pcs->socdata.irq = pdata->irq;
1900 pcs->flags |= PCS_FEAT_IRQ;
1905 ret = pcs_irq_init_chained_handler(pcs, np);
1907 dev_warn(pcs->dev, "initialized with no interrupts\n");
1910 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1912 return pinctrl_enable(pcs->pctl);
1915 pcs_free_resources(pcs);
1920 static int pcs_remove(struct platform_device *pdev)
1922 struct pcs_device *pcs = platform_get_drvdata(pdev);
1927 pcs_free_resources(pcs);
1932 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1933 .flags = PCS_QUIRK_SHARED_IRQ,
1934 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
1935 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
1938 static const struct pcs_soc_data pinctrl_single_dra7 = {
1939 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1940 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
1943 static const struct pcs_soc_data pinctrl_single_am437x = {
1944 .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1945 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
1946 .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
1949 static const struct pcs_soc_data pinctrl_single = {
1952 static const struct pcs_soc_data pinconf_single = {
1953 .flags = PCS_FEAT_PINCONF,
1956 static const struct of_device_id pcs_of_match[] = {
1957 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1958 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1959 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1960 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1961 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1962 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1963 { .compatible = "pinconf-single", .data = &pinconf_single },
1966 MODULE_DEVICE_TABLE(of, pcs_of_match);
1968 static struct platform_driver pcs_driver = {
1970 .remove = pcs_remove,
1972 .name = DRIVER_NAME,
1973 .of_match_table = pcs_of_match,
1976 .suspend = pinctrl_single_suspend,
1977 .resume = pinctrl_single_resume,
1981 module_platform_driver(pcs_driver);
1983 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1984 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1985 MODULE_LICENSE("GPL v2");