1 // SPDX-License-Identifier: GPL-2.0-only
3 * Pinctrl driver for Rockchip SoCs
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
21 #include <linux/bitops.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/pinctrl/machine.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/clk.h>
32 #include <linux/regmap.h>
33 #include <linux/mfd/syscon.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
39 /* GPIO control registers */
40 #define GPIO_SWPORT_DR 0x00
41 #define GPIO_SWPORT_DDR 0x04
42 #define GPIO_INTEN 0x30
43 #define GPIO_INTMASK 0x34
44 #define GPIO_INTTYPE_LEVEL 0x38
45 #define GPIO_INT_POLARITY 0x3c
46 #define GPIO_INT_STATUS 0x40
47 #define GPIO_INT_RAWSTATUS 0x44
48 #define GPIO_DEBOUNCE 0x48
49 #define GPIO_PORTS_EOI 0x4c
50 #define GPIO_EXT_PORT 0x50
51 #define GPIO_LS_SYNC 0x60
53 enum rockchip_pinctrl_type {
67 * Encode variants of iomux registers into a type variable
69 #define IOMUX_GPIO_ONLY BIT(0)
70 #define IOMUX_WIDTH_4BIT BIT(1)
71 #define IOMUX_SOURCE_PMU BIT(2)
72 #define IOMUX_UNROUTED BIT(3)
73 #define IOMUX_WIDTH_3BIT BIT(4)
74 #define IOMUX_WIDTH_2BIT BIT(5)
77 * struct rockchip_iomux
78 * @type: iomux variant using IOMUX_* constants
79 * @offset: if initialized to -1 it will be autocalculated, by specifying
80 * an initial offset value the relevant source offset can be reset
81 * to a new value for autocalculating the following iomux registers.
83 struct rockchip_iomux {
89 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
91 enum rockchip_pin_drv_type {
92 DRV_TYPE_IO_DEFAULT = 0,
93 DRV_TYPE_IO_1V8_OR_3V0,
95 DRV_TYPE_IO_1V8_3V0_AUTO,
101 * enum type index corresponding to rockchip_pull_list arrays index.
103 enum rockchip_pin_pull_type {
104 PULL_TYPE_IO_DEFAULT = 0,
105 PULL_TYPE_IO_1V8_ONLY,
110 * struct rockchip_drv
111 * @drv_type: drive strength variant using rockchip_perpin_drv_type
112 * @offset: if initialized to -1 it will be autocalculated, by specifying
113 * an initial offset value the relevant source offset can be reset
114 * to a new value for autocalculating the following drive strength
115 * registers. if used chips own cal_drv func instead to calculate
116 * registers offset, the variant could be ignored.
118 struct rockchip_drv {
119 enum rockchip_pin_drv_type drv_type;
124 * struct rockchip_pin_bank
125 * @reg_base: register base of the gpio bank
126 * @regmap_pull: optional separate register for additional pull settings
127 * @clk: clock of the gpio bank
128 * @irq: interrupt of the gpio bank
129 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
130 * @pin_base: first pin number
131 * @nr_pins: number of pins in this bank
132 * @name: name of the bank
133 * @bank_num: number of the bank, to account for holes
134 * @iomux: array describing the 4 iomux sources of the bank
135 * @drv: array describing the 4 drive strength sources of the bank
136 * @pull_type: array describing the 4 pull type sources of the bank
137 * @valid: is all necessary information present
138 * @of_node: dt node of this bank
139 * @drvdata: common pinctrl basedata
140 * @domain: irqdomain of the gpio bank
141 * @gpio_chip: gpiolib chip
142 * @grange: gpio range
143 * @slock: spinlock for the gpio bank
144 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
145 * @recalced_mask: bit mask to indicate a need to recalulate the mask
146 * @route_mask: bits describing the routing pins of per bank
148 struct rockchip_pin_bank {
149 void __iomem *reg_base;
150 struct regmap *regmap_pull;
158 struct rockchip_iomux iomux[4];
159 struct rockchip_drv drv[4];
160 enum rockchip_pin_pull_type pull_type[4];
162 struct device_node *of_node;
163 struct rockchip_pinctrl *drvdata;
164 struct irq_domain *domain;
165 struct gpio_chip gpio_chip;
166 struct pinctrl_gpio_range grange;
167 raw_spinlock_t slock;
168 u32 toggle_edge_mode;
173 #define PIN_BANK(id, pins, label) \
186 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
192 { .type = iom0, .offset = -1 }, \
193 { .type = iom1, .offset = -1 }, \
194 { .type = iom2, .offset = -1 }, \
195 { .type = iom3, .offset = -1 }, \
199 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
211 { .drv_type = type0, .offset = -1 }, \
212 { .drv_type = type1, .offset = -1 }, \
213 { .drv_type = type2, .offset = -1 }, \
214 { .drv_type = type3, .offset = -1 }, \
218 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
219 drv2, drv3, pull0, pull1, \
232 { .drv_type = drv0, .offset = -1 }, \
233 { .drv_type = drv1, .offset = -1 }, \
234 { .drv_type = drv2, .offset = -1 }, \
235 { .drv_type = drv3, .offset = -1 }, \
237 .pull_type[0] = pull0, \
238 .pull_type[1] = pull1, \
239 .pull_type[2] = pull2, \
240 .pull_type[3] = pull3, \
243 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
244 iom2, iom3, drv0, drv1, drv2, \
245 drv3, offset0, offset1, \
252 { .type = iom0, .offset = -1 }, \
253 { .type = iom1, .offset = -1 }, \
254 { .type = iom2, .offset = -1 }, \
255 { .type = iom3, .offset = -1 }, \
258 { .drv_type = drv0, .offset = offset0 }, \
259 { .drv_type = drv1, .offset = offset1 }, \
260 { .drv_type = drv2, .offset = offset2 }, \
261 { .drv_type = drv3, .offset = offset3 }, \
265 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
266 label, iom0, iom1, iom2, \
267 iom3, drv0, drv1, drv2, \
268 drv3, offset0, offset1, \
269 offset2, offset3, pull0, \
270 pull1, pull2, pull3) \
276 { .type = iom0, .offset = -1 }, \
277 { .type = iom1, .offset = -1 }, \
278 { .type = iom2, .offset = -1 }, \
279 { .type = iom3, .offset = -1 }, \
282 { .drv_type = drv0, .offset = offset0 }, \
283 { .drv_type = drv1, .offset = offset1 }, \
284 { .drv_type = drv2, .offset = offset2 }, \
285 { .drv_type = drv3, .offset = offset3 }, \
287 .pull_type[0] = pull0, \
288 .pull_type[1] = pull1, \
289 .pull_type[2] = pull2, \
290 .pull_type[3] = pull3, \
294 * struct rockchip_mux_recalced_data: represent a pin iomux data.
297 * @bit: index at register.
298 * @reg: register offset.
301 struct rockchip_mux_recalced_data {
309 enum rockchip_mux_route_location {
310 ROCKCHIP_ROUTE_SAME = 0,
316 * struct rockchip_mux_recalced_data: represent a pin iomux data.
317 * @bank_num: bank number.
318 * @pin: index at register or used to calc index.
319 * @func: the min pin.
320 * @route_location: the mux route location (same, pmu, grf).
321 * @route_offset: the max pin.
322 * @route_val: the register offset.
324 struct rockchip_mux_route_data {
328 enum rockchip_mux_route_location route_location;
333 struct rockchip_pin_ctrl {
334 struct rockchip_pin_bank *pin_banks;
338 enum rockchip_pinctrl_type type;
343 struct rockchip_mux_recalced_data *iomux_recalced;
345 struct rockchip_mux_route_data *iomux_routes;
348 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
349 int pin_num, struct regmap **regmap,
351 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
352 int pin_num, struct regmap **regmap,
354 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
355 int pin_num, struct regmap **regmap,
359 struct rockchip_pin_config {
361 unsigned long *configs;
362 unsigned int nconfigs;
366 * struct rockchip_pin_group: represent group of pins of a pinmux function.
367 * @name: name of the pin group, used to lookup the group.
368 * @pins: the pins included in this group.
369 * @npins: number of pins included in this group.
370 * @data: local pin configuration
372 struct rockchip_pin_group {
376 struct rockchip_pin_config *data;
380 * struct rockchip_pmx_func: represent a pin function.
381 * @name: name of the pin function, used to lookup the function.
382 * @groups: one or more names of pin groups that provide this function.
383 * @ngroups: number of groups included in @groups.
385 struct rockchip_pmx_func {
391 struct rockchip_pinctrl {
392 struct regmap *regmap_base;
394 struct regmap *regmap_pull;
395 struct regmap *regmap_pmu;
397 struct rockchip_pin_ctrl *ctrl;
398 struct pinctrl_desc pctl;
399 struct pinctrl_dev *pctl_dev;
400 struct rockchip_pin_group *groups;
401 unsigned int ngroups;
402 struct rockchip_pmx_func *functions;
403 unsigned int nfunctions;
406 static struct regmap_config rockchip_regmap_config = {
412 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
413 const struct rockchip_pinctrl *info,
418 for (i = 0; i < info->ngroups; i++) {
419 if (!strcmp(info->groups[i].name, name))
420 return &info->groups[i];
427 * given a pin number that is local to a pin controller, find out the pin bank
428 * and the register base of the pin bank.
430 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
433 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
435 while (pin >= (b->pin_base + b->nr_pins))
441 static struct rockchip_pin_bank *bank_num_to_bank(
442 struct rockchip_pinctrl *info,
445 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
448 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
449 if (b->bank_num == num)
453 return ERR_PTR(-EINVAL);
457 * Pinctrl_ops handling
460 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
462 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
464 return info->ngroups;
467 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
470 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
472 return info->groups[selector].name;
475 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
476 unsigned selector, const unsigned **pins,
479 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
481 if (selector >= info->ngroups)
484 *pins = info->groups[selector].pins;
485 *npins = info->groups[selector].npins;
490 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
491 struct device_node *np,
492 struct pinctrl_map **map, unsigned *num_maps)
494 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
495 const struct rockchip_pin_group *grp;
496 struct pinctrl_map *new_map;
497 struct device_node *parent;
502 * first find the group of this node and check if we need to create
503 * config maps for pins
505 grp = pinctrl_name_to_group(info, np->name);
507 dev_err(info->dev, "unable to find group for node %pOFn\n",
512 map_num += grp->npins;
514 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
522 parent = of_get_parent(np);
527 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
528 new_map[0].data.mux.function = parent->name;
529 new_map[0].data.mux.group = np->name;
532 /* create config map */
534 for (i = 0; i < grp->npins; i++) {
535 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
536 new_map[i].data.configs.group_or_pin =
537 pin_get_name(pctldev, grp->pins[i]);
538 new_map[i].data.configs.configs = grp->data[i].configs;
539 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
542 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
543 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
548 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
549 struct pinctrl_map *map, unsigned num_maps)
554 static const struct pinctrl_ops rockchip_pctrl_ops = {
555 .get_groups_count = rockchip_get_groups_count,
556 .get_group_name = rockchip_get_group_name,
557 .get_group_pins = rockchip_get_group_pins,
558 .dt_node_to_map = rockchip_dt_node_to_map,
559 .dt_free_map = rockchip_dt_free_map,
566 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
630 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
664 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
758 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
780 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
781 int *reg, u8 *bit, int *mask)
783 struct rockchip_pinctrl *info = bank->drvdata;
784 struct rockchip_pin_ctrl *ctrl = info->ctrl;
785 struct rockchip_mux_recalced_data *data;
788 for (i = 0; i < ctrl->niomux_recalced; i++) {
789 data = &ctrl->iomux_recalced[i];
790 if (data->num == bank->bank_num &&
795 if (i >= ctrl->niomux_recalced)
803 static struct rockchip_mux_route_data px30_mux_route_data[] = {
809 .route_offset = 0x184,
810 .route_val = BIT(16 + 7),
816 .route_offset = 0x184,
817 .route_val = BIT(16 + 7) | BIT(7),
823 .route_offset = 0x184,
824 .route_val = BIT(16 + 8),
830 .route_offset = 0x184,
831 .route_val = BIT(16 + 8) | BIT(8),
837 .route_offset = 0x184,
838 .route_val = BIT(16 + 10),
844 .route_offset = 0x184,
845 .route_val = BIT(16 + 10) | BIT(10),
851 .route_offset = 0x184,
852 .route_val = BIT(16 + 9),
858 .route_offset = 0x184,
859 .route_val = BIT(16 + 9) | BIT(9),
863 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
869 .route_offset = 0x144,
870 .route_val = BIT(16 + 3) | BIT(16 + 4),
876 .route_offset = 0x144,
877 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
883 .route_offset = 0x144,
884 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
890 .route_offset = 0x144,
891 .route_val = BIT(16 + 5),
897 .route_offset = 0x144,
898 .route_val = BIT(16 + 5) | BIT(5),
904 .route_offset = 0x144,
905 .route_val = BIT(16 + 6),
911 .route_offset = 0x144,
912 .route_val = BIT(16 + 6) | BIT(6),
916 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
918 /* non-iomuxed emmc/flash pins on flash-dqs */
922 .route_location = ROCKCHIP_ROUTE_GRF,
923 .route_offset = 0xa0,
924 .route_val = BIT(16 + 11),
926 /* non-iomuxed emmc/flash pins on emmc-clk */
930 .route_location = ROCKCHIP_ROUTE_GRF,
931 .route_offset = 0xa0,
932 .route_val = BIT(16 + 11) | BIT(11),
936 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
942 .route_offset = 0x50,
943 .route_val = BIT(16),
949 .route_offset = 0x50,
950 .route_val = BIT(16) | BIT(0),
956 .route_offset = 0x50,
957 .route_val = BIT(16 + 1),
963 .route_offset = 0x50,
964 .route_val = BIT(16 + 1) | BIT(1),
970 .route_offset = 0x50,
971 .route_val = BIT(16 + 2),
977 .route_offset = 0x50,
978 .route_val = BIT(16 + 2) | BIT(2),
984 .route_offset = 0x50,
985 .route_val = BIT(16 + 3),
991 .route_offset = 0x50,
992 .route_val = BIT(16 + 3) | BIT(3),
998 .route_offset = 0x50,
999 .route_val = BIT(16 + 4),
1005 .route_offset = 0x50,
1006 .route_val = BIT(16 + 4) | BIT(4),
1012 .route_offset = 0x50,
1013 .route_val = BIT(16 + 5),
1019 .route_offset = 0x50,
1020 .route_val = BIT(16 + 5) | BIT(5),
1026 .route_offset = 0x50,
1027 .route_val = BIT(16 + 7),
1033 .route_offset = 0x50,
1034 .route_val = BIT(16 + 7) | BIT(7),
1040 .route_offset = 0x50,
1041 .route_val = BIT(16 + 8),
1047 .route_offset = 0x50,
1048 .route_val = BIT(16 + 8) | BIT(8),
1054 .route_offset = 0x50,
1055 .route_val = BIT(16 + 11),
1061 .route_offset = 0x50,
1062 .route_val = BIT(16 + 11) | BIT(11),
1066 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
1068 /* edphdmi_cecinoutt1 */
1072 .route_offset = 0x264,
1073 .route_val = BIT(16 + 12) | BIT(12),
1075 /* edphdmi_cecinout */
1079 .route_offset = 0x264,
1080 .route_val = BIT(16 + 12),
1084 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
1090 .route_offset = 0x314,
1091 .route_val = BIT(16 + 0) | BIT(0),
1097 .route_offset = 0x314,
1098 .route_val = BIT(16 + 2) | BIT(16 + 3),
1104 .route_offset = 0x314,
1105 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
1111 .route_offset = 0x608,
1112 .route_val = BIT(16 + 8) | BIT(16 + 9),
1118 .route_offset = 0x608,
1119 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
1125 .route_offset = 0x608,
1126 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
1128 /* i2s-8ch-1-sclktxm0 */
1132 .route_offset = 0x308,
1133 .route_val = BIT(16 + 3),
1135 /* i2s-8ch-1-sclkrxm0 */
1139 .route_offset = 0x308,
1140 .route_val = BIT(16 + 3),
1142 /* i2s-8ch-1-sclktxm1 */
1146 .route_offset = 0x308,
1147 .route_val = BIT(16 + 3) | BIT(3),
1149 /* i2s-8ch-1-sclkrxm1 */
1153 .route_offset = 0x308,
1154 .route_val = BIT(16 + 3) | BIT(3),
1160 .route_offset = 0x308,
1161 .route_val = BIT(16 + 12) | BIT(16 + 13),
1167 .route_offset = 0x308,
1168 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1174 .route_offset = 0x308,
1175 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1181 .route_offset = 0x600,
1182 .route_val = BIT(16 + 2) | BIT(2),
1188 .route_offset = 0x314,
1189 .route_val = BIT(16 + 9),
1195 .route_offset = 0x314,
1196 .route_val = BIT(16 + 9) | BIT(9),
1202 .route_offset = 0x314,
1203 .route_val = BIT(16 + 10) | BIT(16 + 11),
1209 .route_offset = 0x314,
1210 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1216 .route_offset = 0x314,
1217 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1223 .route_offset = 0x314,
1224 .route_val = BIT(16 + 12) | BIT(16 + 13),
1230 .route_offset = 0x314,
1231 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
1237 .route_offset = 0x314,
1238 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
1244 .route_offset = 0x314,
1245 .route_val = BIT(16 + 14),
1251 .route_offset = 0x314,
1252 .route_val = BIT(16 + 14) | BIT(14),
1258 .route_offset = 0x314,
1259 .route_val = BIT(16 + 15),
1265 .route_offset = 0x314,
1266 .route_val = BIT(16 + 15) | BIT(15),
1270 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
1276 .route_offset = 0x50,
1277 .route_val = BIT(16) | BIT(16 + 1),
1283 .route_offset = 0x50,
1284 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
1290 .route_offset = 0x50,
1291 .route_val = BIT(16 + 2) | BIT(2),
1293 /* gmac-m1-optimized_rxd3 */
1297 .route_offset = 0x50,
1298 .route_val = BIT(16 + 10) | BIT(10),
1304 .route_offset = 0x50,
1305 .route_val = BIT(16 + 3),
1311 .route_offset = 0x50,
1312 .route_val = BIT(16 + 3) | BIT(3),
1318 .route_offset = 0x50,
1319 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
1325 .route_offset = 0x50,
1326 .route_val = BIT(16 + 6),
1332 .route_offset = 0x50,
1333 .route_val = BIT(16 + 6) | BIT(6),
1339 .route_offset = 0x50,
1340 .route_val = BIT(16 + 7) | BIT(7),
1346 .route_offset = 0x50,
1347 .route_val = BIT(16 + 8) | BIT(8),
1353 .route_offset = 0x50,
1354 .route_val = BIT(16 + 9) | BIT(9),
1358 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1364 .route_offset = 0xe21c,
1365 .route_val = BIT(16 + 10) | BIT(16 + 11),
1371 .route_offset = 0xe21c,
1372 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
1378 .route_offset = 0xe21c,
1379 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
1385 .route_offset = 0xe21c,
1386 .route_val = BIT(16 + 14),
1392 .route_offset = 0xe21c,
1393 .route_val = BIT(16 + 14) | BIT(14),
1397 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1398 int mux, u32 *loc, u32 *reg, u32 *value)
1400 struct rockchip_pinctrl *info = bank->drvdata;
1401 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1402 struct rockchip_mux_route_data *data;
1405 for (i = 0; i < ctrl->niomux_routes; i++) {
1406 data = &ctrl->iomux_routes[i];
1407 if ((data->bank_num == bank->bank_num) &&
1408 (data->pin == pin) && (data->func == mux))
1412 if (i >= ctrl->niomux_routes)
1415 *loc = data->route_location;
1416 *reg = data->route_offset;
1417 *value = data->route_val;
1422 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1424 struct rockchip_pinctrl *info = bank->drvdata;
1425 int iomux_num = (pin / 8);
1426 struct regmap *regmap;
1428 int reg, ret, mask, mux_type;
1434 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1435 dev_err(info->dev, "pin %d is unrouted\n", pin);
1439 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1440 return RK_FUNC_GPIO;
1442 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1443 ? info->regmap_pmu : info->regmap_base;
1445 /* get basic quadrupel of mux registers and the correct reg inside */
1446 mux_type = bank->iomux[iomux_num].type;
1447 reg = bank->iomux[iomux_num].offset;
1448 if (mux_type & IOMUX_WIDTH_4BIT) {
1451 bit = (pin % 4) * 4;
1453 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1456 bit = (pin % 8 % 5) * 3;
1459 bit = (pin % 8) * 2;
1463 if (bank->recalced_mask & BIT(pin))
1464 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1466 ret = regmap_read(regmap, reg, &val);
1470 return ((val >> bit) & mask);
1473 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1476 struct rockchip_pinctrl *info = bank->drvdata;
1477 int iomux_num = (pin / 8);
1482 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1483 dev_err(info->dev, "pin %d is unrouted\n", pin);
1487 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1488 if (mux != RK_FUNC_GPIO) {
1490 "pin %d only supports a gpio mux\n", pin);
1499 * Set a new mux function for a pin.
1501 * The register is divided into the upper and lower 16 bit. When changing
1502 * a value, the previous register value is not read and changed. Instead
1503 * it seems the changed bits are marked in the upper 16 bit, while the
1504 * changed value gets set in the same offset in the lower 16 bit.
1505 * All pin settings seem to be 2 bit wide in both the upper and lower
1507 * @bank: pin bank to change
1508 * @pin: pin to change
1509 * @mux: new mux function to set
1511 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1513 struct rockchip_pinctrl *info = bank->drvdata;
1514 int iomux_num = (pin / 8);
1515 struct regmap *regmap;
1516 int reg, ret, mask, mux_type;
1518 u32 data, rmask, route_location, route_reg, route_val;
1520 ret = rockchip_verify_mux(bank, pin, mux);
1524 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1527 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1528 bank->bank_num, pin, mux);
1530 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1531 ? info->regmap_pmu : info->regmap_base;
1533 /* get basic quadrupel of mux registers and the correct reg inside */
1534 mux_type = bank->iomux[iomux_num].type;
1535 reg = bank->iomux[iomux_num].offset;
1536 if (mux_type & IOMUX_WIDTH_4BIT) {
1539 bit = (pin % 4) * 4;
1541 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1544 bit = (pin % 8 % 5) * 3;
1547 bit = (pin % 8) * 2;
1551 if (bank->recalced_mask & BIT(pin))
1552 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1554 if (bank->route_mask & BIT(pin)) {
1555 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1556 &route_reg, &route_val)) {
1557 struct regmap *route_regmap = regmap;
1559 /* handle special locations */
1560 switch (route_location) {
1561 case ROCKCHIP_ROUTE_PMU:
1562 route_regmap = info->regmap_pmu;
1564 case ROCKCHIP_ROUTE_GRF:
1565 route_regmap = info->regmap_base;
1569 ret = regmap_write(route_regmap, route_reg, route_val);
1575 data = (mask << (bit + 16));
1576 rmask = data | (data >> 16);
1577 data |= (mux & mask) << bit;
1578 ret = regmap_update_bits(regmap, reg, rmask, data);
1583 #define PX30_PULL_PMU_OFFSET 0x10
1584 #define PX30_PULL_GRF_OFFSET 0x60
1585 #define PX30_PULL_BITS_PER_PIN 2
1586 #define PX30_PULL_PINS_PER_REG 8
1587 #define PX30_PULL_BANK_STRIDE 16
1589 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1590 int pin_num, struct regmap **regmap,
1593 struct rockchip_pinctrl *info = bank->drvdata;
1595 /* The first 32 pins of the first bank are located in PMU */
1596 if (bank->bank_num == 0) {
1597 *regmap = info->regmap_pmu;
1598 *reg = PX30_PULL_PMU_OFFSET;
1600 *regmap = info->regmap_base;
1601 *reg = PX30_PULL_GRF_OFFSET;
1603 /* correct the offset, as we're starting with the 2nd bank */
1605 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1608 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1609 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1610 *bit *= PX30_PULL_BITS_PER_PIN;
1613 #define PX30_DRV_PMU_OFFSET 0x20
1614 #define PX30_DRV_GRF_OFFSET 0xf0
1615 #define PX30_DRV_BITS_PER_PIN 2
1616 #define PX30_DRV_PINS_PER_REG 8
1617 #define PX30_DRV_BANK_STRIDE 16
1619 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1620 int pin_num, struct regmap **regmap,
1623 struct rockchip_pinctrl *info = bank->drvdata;
1625 /* The first 32 pins of the first bank are located in PMU */
1626 if (bank->bank_num == 0) {
1627 *regmap = info->regmap_pmu;
1628 *reg = PX30_DRV_PMU_OFFSET;
1630 *regmap = info->regmap_base;
1631 *reg = PX30_DRV_GRF_OFFSET;
1633 /* correct the offset, as we're starting with the 2nd bank */
1635 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1638 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1639 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1640 *bit *= PX30_DRV_BITS_PER_PIN;
1643 #define PX30_SCHMITT_PMU_OFFSET 0x38
1644 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1645 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1646 #define PX30_SCHMITT_BANK_STRIDE 16
1647 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1649 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1651 struct regmap **regmap,
1654 struct rockchip_pinctrl *info = bank->drvdata;
1657 if (bank->bank_num == 0) {
1658 *regmap = info->regmap_pmu;
1659 *reg = PX30_SCHMITT_PMU_OFFSET;
1660 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1662 *regmap = info->regmap_base;
1663 *reg = PX30_SCHMITT_GRF_OFFSET;
1664 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1665 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1668 *reg += ((pin_num / pins_per_reg) * 4);
1669 *bit = pin_num % pins_per_reg;
1674 #define RV1108_PULL_PMU_OFFSET 0x10
1675 #define RV1108_PULL_OFFSET 0x110
1676 #define RV1108_PULL_PINS_PER_REG 8
1677 #define RV1108_PULL_BITS_PER_PIN 2
1678 #define RV1108_PULL_BANK_STRIDE 16
1680 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1681 int pin_num, struct regmap **regmap,
1684 struct rockchip_pinctrl *info = bank->drvdata;
1686 /* The first 24 pins of the first bank are located in PMU */
1687 if (bank->bank_num == 0) {
1688 *regmap = info->regmap_pmu;
1689 *reg = RV1108_PULL_PMU_OFFSET;
1691 *reg = RV1108_PULL_OFFSET;
1692 *regmap = info->regmap_base;
1693 /* correct the offset, as we're starting with the 2nd bank */
1695 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1698 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1699 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1700 *bit *= RV1108_PULL_BITS_PER_PIN;
1703 #define RV1108_DRV_PMU_OFFSET 0x20
1704 #define RV1108_DRV_GRF_OFFSET 0x210
1705 #define RV1108_DRV_BITS_PER_PIN 2
1706 #define RV1108_DRV_PINS_PER_REG 8
1707 #define RV1108_DRV_BANK_STRIDE 16
1709 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1710 int pin_num, struct regmap **regmap,
1713 struct rockchip_pinctrl *info = bank->drvdata;
1715 /* The first 24 pins of the first bank are located in PMU */
1716 if (bank->bank_num == 0) {
1717 *regmap = info->regmap_pmu;
1718 *reg = RV1108_DRV_PMU_OFFSET;
1720 *regmap = info->regmap_base;
1721 *reg = RV1108_DRV_GRF_OFFSET;
1723 /* correct the offset, as we're starting with the 2nd bank */
1725 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1728 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1729 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1730 *bit *= RV1108_DRV_BITS_PER_PIN;
1733 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1734 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1735 #define RV1108_SCHMITT_BANK_STRIDE 8
1736 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1737 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1739 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1741 struct regmap **regmap,
1744 struct rockchip_pinctrl *info = bank->drvdata;
1747 if (bank->bank_num == 0) {
1748 *regmap = info->regmap_pmu;
1749 *reg = RV1108_SCHMITT_PMU_OFFSET;
1750 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1752 *regmap = info->regmap_base;
1753 *reg = RV1108_SCHMITT_GRF_OFFSET;
1754 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1755 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1757 *reg += ((pin_num / pins_per_reg) * 4);
1758 *bit = pin_num % pins_per_reg;
1763 #define RK3308_SCHMITT_PINS_PER_REG 8
1764 #define RK3308_SCHMITT_BANK_STRIDE 16
1765 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1767 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1768 int pin_num, struct regmap **regmap,
1771 struct rockchip_pinctrl *info = bank->drvdata;
1773 *regmap = info->regmap_base;
1774 *reg = RK3308_SCHMITT_GRF_OFFSET;
1776 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1777 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1778 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1783 #define RK2928_PULL_OFFSET 0x118
1784 #define RK2928_PULL_PINS_PER_REG 16
1785 #define RK2928_PULL_BANK_STRIDE 8
1787 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1788 int pin_num, struct regmap **regmap,
1791 struct rockchip_pinctrl *info = bank->drvdata;
1793 *regmap = info->regmap_base;
1794 *reg = RK2928_PULL_OFFSET;
1795 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1796 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1798 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1801 #define RK3128_PULL_OFFSET 0x118
1803 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1804 int pin_num, struct regmap **regmap,
1807 struct rockchip_pinctrl *info = bank->drvdata;
1809 *regmap = info->regmap_base;
1810 *reg = RK3128_PULL_OFFSET;
1811 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1812 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1814 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1817 #define RK3188_PULL_OFFSET 0x164
1818 #define RK3188_PULL_BITS_PER_PIN 2
1819 #define RK3188_PULL_PINS_PER_REG 8
1820 #define RK3188_PULL_BANK_STRIDE 16
1821 #define RK3188_PULL_PMU_OFFSET 0x64
1823 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1824 int pin_num, struct regmap **regmap,
1827 struct rockchip_pinctrl *info = bank->drvdata;
1829 /* The first 12 pins of the first bank are located elsewhere */
1830 if (bank->bank_num == 0 && pin_num < 12) {
1831 *regmap = info->regmap_pmu ? info->regmap_pmu
1832 : bank->regmap_pull;
1833 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1834 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1835 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1836 *bit *= RK3188_PULL_BITS_PER_PIN;
1838 *regmap = info->regmap_pull ? info->regmap_pull
1839 : info->regmap_base;
1840 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1842 /* correct the offset, as it is the 2nd pull register */
1844 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1845 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1848 * The bits in these registers have an inverse ordering
1849 * with the lowest pin being in bits 15:14 and the highest
1852 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1853 *bit *= RK3188_PULL_BITS_PER_PIN;
1857 #define RK3288_PULL_OFFSET 0x140
1858 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1859 int pin_num, struct regmap **regmap,
1862 struct rockchip_pinctrl *info = bank->drvdata;
1864 /* The first 24 pins of the first bank are located in PMU */
1865 if (bank->bank_num == 0) {
1866 *regmap = info->regmap_pmu;
1867 *reg = RK3188_PULL_PMU_OFFSET;
1869 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1870 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1871 *bit *= RK3188_PULL_BITS_PER_PIN;
1873 *regmap = info->regmap_base;
1874 *reg = RK3288_PULL_OFFSET;
1876 /* correct the offset, as we're starting with the 2nd bank */
1878 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1879 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1881 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1882 *bit *= RK3188_PULL_BITS_PER_PIN;
1886 #define RK3288_DRV_PMU_OFFSET 0x70
1887 #define RK3288_DRV_GRF_OFFSET 0x1c0
1888 #define RK3288_DRV_BITS_PER_PIN 2
1889 #define RK3288_DRV_PINS_PER_REG 8
1890 #define RK3288_DRV_BANK_STRIDE 16
1892 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1893 int pin_num, struct regmap **regmap,
1896 struct rockchip_pinctrl *info = bank->drvdata;
1898 /* The first 24 pins of the first bank are located in PMU */
1899 if (bank->bank_num == 0) {
1900 *regmap = info->regmap_pmu;
1901 *reg = RK3288_DRV_PMU_OFFSET;
1903 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1904 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1905 *bit *= RK3288_DRV_BITS_PER_PIN;
1907 *regmap = info->regmap_base;
1908 *reg = RK3288_DRV_GRF_OFFSET;
1910 /* correct the offset, as we're starting with the 2nd bank */
1912 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1913 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1915 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1916 *bit *= RK3288_DRV_BITS_PER_PIN;
1920 #define RK3228_PULL_OFFSET 0x100
1922 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1923 int pin_num, struct regmap **regmap,
1926 struct rockchip_pinctrl *info = bank->drvdata;
1928 *regmap = info->regmap_base;
1929 *reg = RK3228_PULL_OFFSET;
1930 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1931 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1933 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1934 *bit *= RK3188_PULL_BITS_PER_PIN;
1937 #define RK3228_DRV_GRF_OFFSET 0x200
1939 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1940 int pin_num, struct regmap **regmap,
1943 struct rockchip_pinctrl *info = bank->drvdata;
1945 *regmap = info->regmap_base;
1946 *reg = RK3228_DRV_GRF_OFFSET;
1947 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1948 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1950 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1951 *bit *= RK3288_DRV_BITS_PER_PIN;
1954 #define RK3308_PULL_OFFSET 0xa0
1956 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1957 int pin_num, struct regmap **regmap,
1960 struct rockchip_pinctrl *info = bank->drvdata;
1962 *regmap = info->regmap_base;
1963 *reg = RK3308_PULL_OFFSET;
1964 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1965 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1967 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1968 *bit *= RK3188_PULL_BITS_PER_PIN;
1971 #define RK3308_DRV_GRF_OFFSET 0x100
1973 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1974 int pin_num, struct regmap **regmap,
1977 struct rockchip_pinctrl *info = bank->drvdata;
1979 *regmap = info->regmap_base;
1980 *reg = RK3308_DRV_GRF_OFFSET;
1981 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1982 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1984 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1985 *bit *= RK3288_DRV_BITS_PER_PIN;
1988 #define RK3368_PULL_GRF_OFFSET 0x100
1989 #define RK3368_PULL_PMU_OFFSET 0x10
1991 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1992 int pin_num, struct regmap **regmap,
1995 struct rockchip_pinctrl *info = bank->drvdata;
1997 /* The first 32 pins of the first bank are located in PMU */
1998 if (bank->bank_num == 0) {
1999 *regmap = info->regmap_pmu;
2000 *reg = RK3368_PULL_PMU_OFFSET;
2002 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2003 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2004 *bit *= RK3188_PULL_BITS_PER_PIN;
2006 *regmap = info->regmap_base;
2007 *reg = RK3368_PULL_GRF_OFFSET;
2009 /* correct the offset, as we're starting with the 2nd bank */
2011 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2012 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2014 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2015 *bit *= RK3188_PULL_BITS_PER_PIN;
2019 #define RK3368_DRV_PMU_OFFSET 0x20
2020 #define RK3368_DRV_GRF_OFFSET 0x200
2022 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2023 int pin_num, struct regmap **regmap,
2026 struct rockchip_pinctrl *info = bank->drvdata;
2028 /* The first 32 pins of the first bank are located in PMU */
2029 if (bank->bank_num == 0) {
2030 *regmap = info->regmap_pmu;
2031 *reg = RK3368_DRV_PMU_OFFSET;
2033 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2034 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2035 *bit *= RK3288_DRV_BITS_PER_PIN;
2037 *regmap = info->regmap_base;
2038 *reg = RK3368_DRV_GRF_OFFSET;
2040 /* correct the offset, as we're starting with the 2nd bank */
2042 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2043 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2045 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2046 *bit *= RK3288_DRV_BITS_PER_PIN;
2050 #define RK3399_PULL_GRF_OFFSET 0xe040
2051 #define RK3399_PULL_PMU_OFFSET 0x40
2052 #define RK3399_DRV_3BITS_PER_PIN 3
2054 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2055 int pin_num, struct regmap **regmap,
2058 struct rockchip_pinctrl *info = bank->drvdata;
2060 /* The bank0:16 and bank1:32 pins are located in PMU */
2061 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
2062 *regmap = info->regmap_pmu;
2063 *reg = RK3399_PULL_PMU_OFFSET;
2065 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2067 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2068 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2069 *bit *= RK3188_PULL_BITS_PER_PIN;
2071 *regmap = info->regmap_base;
2072 *reg = RK3399_PULL_GRF_OFFSET;
2074 /* correct the offset, as we're starting with the 3rd bank */
2076 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2077 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2079 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2080 *bit *= RK3188_PULL_BITS_PER_PIN;
2084 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2085 int pin_num, struct regmap **regmap,
2088 struct rockchip_pinctrl *info = bank->drvdata;
2089 int drv_num = (pin_num / 8);
2091 /* The bank0:16 and bank1:32 pins are located in PMU */
2092 if ((bank->bank_num == 0) || (bank->bank_num == 1))
2093 *regmap = info->regmap_pmu;
2095 *regmap = info->regmap_base;
2097 *reg = bank->drv[drv_num].offset;
2098 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2099 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
2100 *bit = (pin_num % 8) * 3;
2102 *bit = (pin_num % 8) * 2;
2105 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
2106 { 2, 4, 8, 12, -1, -1, -1, -1 },
2107 { 3, 6, 9, 12, -1, -1, -1, -1 },
2108 { 5, 10, 15, 20, -1, -1, -1, -1 },
2109 { 4, 6, 8, 10, 12, 14, 16, 18 },
2110 { 4, 7, 10, 13, 16, 19, 22, 26 }
2113 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
2116 struct rockchip_pinctrl *info = bank->drvdata;
2117 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2118 struct regmap *regmap;
2120 u32 data, temp, rmask_bits;
2122 int drv_type = bank->drv[pin_num / 8].drv_type;
2124 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
2127 case DRV_TYPE_IO_1V8_3V0_AUTO:
2128 case DRV_TYPE_IO_3V3_ONLY:
2129 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2132 /* regular case, nothing to do */
2136 * drive-strength offset is special, as it is
2137 * spread over 2 registers
2139 ret = regmap_read(regmap, reg, &data);
2143 ret = regmap_read(regmap, reg + 0x4, &temp);
2148 * the bit data[15] contains bit 0 of the value
2149 * while temp[1:0] contains bits 2 and 1
2156 return rockchip_perpin_drv_list[drv_type][data];
2158 /* setting fully enclosed in the second register */
2163 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2169 case DRV_TYPE_IO_DEFAULT:
2170 case DRV_TYPE_IO_1V8_OR_3V0:
2171 case DRV_TYPE_IO_1V8_ONLY:
2172 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2175 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2180 ret = regmap_read(regmap, reg, &data);
2185 data &= (1 << rmask_bits) - 1;
2187 return rockchip_perpin_drv_list[drv_type][data];
2190 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
2191 int pin_num, int strength)
2193 struct rockchip_pinctrl *info = bank->drvdata;
2194 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2195 struct regmap *regmap;
2197 u32 data, rmask, rmask_bits, temp;
2199 int drv_type = bank->drv[pin_num / 8].drv_type;
2201 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
2202 bank->bank_num, pin_num, strength);
2204 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
2207 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
2208 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
2211 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
2212 ret = rockchip_perpin_drv_list[drv_type][i];
2218 dev_err(info->dev, "unsupported driver strength %d\n",
2224 case DRV_TYPE_IO_1V8_3V0_AUTO:
2225 case DRV_TYPE_IO_3V3_ONLY:
2226 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2229 /* regular case, nothing to do */
2233 * drive-strength offset is special, as it is spread
2234 * over 2 registers, the bit data[15] contains bit 0
2235 * of the value while temp[1:0] contains bits 2 and 1
2237 data = (ret & 0x1) << 15;
2238 temp = (ret >> 0x1) & 0x3;
2240 rmask = BIT(15) | BIT(31);
2242 ret = regmap_update_bits(regmap, reg, rmask, data);
2246 rmask = 0x3 | (0x3 << 16);
2247 temp |= (0x3 << 16);
2249 ret = regmap_update_bits(regmap, reg, rmask, temp);
2253 /* setting fully enclosed in the second register */
2258 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2263 case DRV_TYPE_IO_DEFAULT:
2264 case DRV_TYPE_IO_1V8_OR_3V0:
2265 case DRV_TYPE_IO_1V8_ONLY:
2266 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2269 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
2274 /* enable the write to the equivalent lower bits */
2275 data = ((1 << rmask_bits) - 1) << (bit + 16);
2276 rmask = data | (data >> 16);
2277 data |= (ret << bit);
2279 ret = regmap_update_bits(regmap, reg, rmask, data);
2284 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
2286 PIN_CONFIG_BIAS_DISABLE,
2287 PIN_CONFIG_BIAS_PULL_UP,
2288 PIN_CONFIG_BIAS_PULL_DOWN,
2289 PIN_CONFIG_BIAS_BUS_HOLD
2292 PIN_CONFIG_BIAS_DISABLE,
2293 PIN_CONFIG_BIAS_PULL_DOWN,
2294 PIN_CONFIG_BIAS_DISABLE,
2295 PIN_CONFIG_BIAS_PULL_UP
2299 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
2301 struct rockchip_pinctrl *info = bank->drvdata;
2302 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2303 struct regmap *regmap;
2304 int reg, ret, pull_type;
2308 /* rk3066b does support any pulls */
2309 if (ctrl->type == RK3066B)
2310 return PIN_CONFIG_BIAS_DISABLE;
2312 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2314 ret = regmap_read(regmap, reg, &data);
2318 switch (ctrl->type) {
2321 return !(data & BIT(bit))
2322 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
2323 : PIN_CONFIG_BIAS_DISABLE;
2331 pull_type = bank->pull_type[pin_num / 8];
2333 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2335 return rockchip_pull_list[pull_type][data];
2337 dev_err(info->dev, "unsupported pinctrl type\n");
2342 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2343 int pin_num, int pull)
2345 struct rockchip_pinctrl *info = bank->drvdata;
2346 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2347 struct regmap *regmap;
2348 int reg, ret, i, pull_type;
2352 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
2353 bank->bank_num, pin_num, pull);
2355 /* rk3066b does support any pulls */
2356 if (ctrl->type == RK3066B)
2357 return pull ? -EINVAL : 0;
2359 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2361 switch (ctrl->type) {
2364 data = BIT(bit + 16);
2365 if (pull == PIN_CONFIG_BIAS_DISABLE)
2367 ret = regmap_write(regmap, reg, data);
2376 pull_type = bank->pull_type[pin_num / 8];
2378 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2380 if (rockchip_pull_list[pull_type][i] == pull) {
2387 dev_err(info->dev, "unsupported pull setting %d\n",
2392 /* enable the write to the equivalent lower bits */
2393 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2394 rmask = data | (data >> 16);
2395 data |= (ret << bit);
2397 ret = regmap_update_bits(regmap, reg, rmask, data);
2400 dev_err(info->dev, "unsupported pinctrl type\n");
2407 #define RK3328_SCHMITT_BITS_PER_PIN 1
2408 #define RK3328_SCHMITT_PINS_PER_REG 16
2409 #define RK3328_SCHMITT_BANK_STRIDE 8
2410 #define RK3328_SCHMITT_GRF_OFFSET 0x380
2412 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2414 struct regmap **regmap,
2417 struct rockchip_pinctrl *info = bank->drvdata;
2419 *regmap = info->regmap_base;
2420 *reg = RK3328_SCHMITT_GRF_OFFSET;
2422 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2423 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2424 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2429 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2431 struct rockchip_pinctrl *info = bank->drvdata;
2432 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2433 struct regmap *regmap;
2438 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2442 ret = regmap_read(regmap, reg, &data);
2450 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2451 int pin_num, int enable)
2453 struct rockchip_pinctrl *info = bank->drvdata;
2454 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2455 struct regmap *regmap;
2460 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
2461 bank->bank_num, pin_num, enable);
2463 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2467 /* enable the write to the equivalent lower bits */
2468 data = BIT(bit + 16) | (enable << bit);
2469 rmask = BIT(bit + 16) | BIT(bit);
2471 return regmap_update_bits(regmap, reg, rmask, data);
2475 * Pinmux_ops handling
2478 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2480 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2482 return info->nfunctions;
2485 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2488 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2490 return info->functions[selector].name;
2493 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2494 unsigned selector, const char * const **groups,
2495 unsigned * const num_groups)
2497 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2499 *groups = info->functions[selector].groups;
2500 *num_groups = info->functions[selector].ngroups;
2505 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2508 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2509 const unsigned int *pins = info->groups[group].pins;
2510 const struct rockchip_pin_config *data = info->groups[group].data;
2511 struct rockchip_pin_bank *bank;
2514 dev_dbg(info->dev, "enable function %s group %s\n",
2515 info->functions[selector].name, info->groups[group].name);
2518 * for each pin in the pin group selected, program the corresponding
2519 * pin function number in the config register.
2521 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2522 bank = pin_to_bank(info, pins[cnt]);
2523 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2530 /* revert the already done pin settings */
2531 for (cnt--; cnt >= 0; cnt--)
2532 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2540 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
2542 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
2546 ret = clk_enable(bank->clk);
2548 dev_err(bank->drvdata->dev,
2549 "failed to enable clock for bank %s\n", bank->name);
2552 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2553 clk_disable(bank->clk);
2555 if (data & BIT(offset))
2556 return GPIO_LINE_DIRECTION_OUT;
2558 return GPIO_LINE_DIRECTION_IN;
2562 * The calls to gpio_direction_output() and gpio_direction_input()
2563 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2564 * function called from the gpiolib interface).
2566 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2567 int pin, bool input)
2569 struct rockchip_pin_bank *bank;
2571 unsigned long flags;
2574 bank = gpiochip_get_data(chip);
2576 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2580 clk_enable(bank->clk);
2581 raw_spin_lock_irqsave(&bank->slock, flags);
2583 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2584 /* set bit to 1 for output, 0 for input */
2589 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2591 raw_spin_unlock_irqrestore(&bank->slock, flags);
2592 clk_disable(bank->clk);
2597 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2598 struct pinctrl_gpio_range *range,
2599 unsigned offset, bool input)
2601 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2602 struct gpio_chip *chip;
2606 pin = offset - chip->base;
2607 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2608 offset, range->name, pin, input ? "input" : "output");
2610 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2614 static const struct pinmux_ops rockchip_pmx_ops = {
2615 .get_functions_count = rockchip_pmx_get_funcs_count,
2616 .get_function_name = rockchip_pmx_get_func_name,
2617 .get_function_groups = rockchip_pmx_get_groups,
2618 .set_mux = rockchip_pmx_set,
2619 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
2623 * Pinconf_ops handling
2626 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2627 enum pin_config_param pull)
2629 switch (ctrl->type) {
2632 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2633 pull == PIN_CONFIG_BIAS_DISABLE);
2635 return pull ? false : true;
2643 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2649 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2650 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2652 /* set the pin config settings for a specified pin */
2653 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2654 unsigned long *configs, unsigned num_configs)
2656 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2657 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2658 enum pin_config_param param;
2663 for (i = 0; i < num_configs; i++) {
2664 param = pinconf_to_config_param(configs[i]);
2665 arg = pinconf_to_config_argument(configs[i]);
2668 case PIN_CONFIG_BIAS_DISABLE:
2669 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2674 case PIN_CONFIG_BIAS_PULL_UP:
2675 case PIN_CONFIG_BIAS_PULL_DOWN:
2676 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2677 case PIN_CONFIG_BIAS_BUS_HOLD:
2678 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2684 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2689 case PIN_CONFIG_OUTPUT:
2690 rockchip_gpio_set(&bank->gpio_chip,
2691 pin - bank->pin_base, arg);
2692 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2693 pin - bank->pin_base, false);
2697 case PIN_CONFIG_DRIVE_STRENGTH:
2698 /* rk3288 is the first with per-pin drive-strength */
2699 if (!info->ctrl->drv_calc_reg)
2702 rc = rockchip_set_drive_perpin(bank,
2703 pin - bank->pin_base, arg);
2707 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2708 if (!info->ctrl->schmitt_calc_reg)
2711 rc = rockchip_set_schmitt(bank,
2712 pin - bank->pin_base, arg);
2720 } /* for each config */
2725 /* get the pin config settings for a specified pin */
2726 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2727 unsigned long *config)
2729 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2730 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2731 enum pin_config_param param = pinconf_to_config_param(*config);
2736 case PIN_CONFIG_BIAS_DISABLE:
2737 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2742 case PIN_CONFIG_BIAS_PULL_UP:
2743 case PIN_CONFIG_BIAS_PULL_DOWN:
2744 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2745 case PIN_CONFIG_BIAS_BUS_HOLD:
2746 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2749 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2754 case PIN_CONFIG_OUTPUT:
2755 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2756 if (rc != RK_FUNC_GPIO)
2759 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2765 case PIN_CONFIG_DRIVE_STRENGTH:
2766 /* rk3288 is the first with per-pin drive-strength */
2767 if (!info->ctrl->drv_calc_reg)
2770 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2776 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2777 if (!info->ctrl->schmitt_calc_reg)
2780 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2791 *config = pinconf_to_config_packed(param, arg);
2796 static const struct pinconf_ops rockchip_pinconf_ops = {
2797 .pin_config_get = rockchip_pinconf_get,
2798 .pin_config_set = rockchip_pinconf_set,
2802 static const struct of_device_id rockchip_bank_match[] = {
2803 { .compatible = "rockchip,gpio-bank" },
2804 { .compatible = "rockchip,rk3188-gpio-bank0" },
2808 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2809 struct device_node *np)
2811 struct device_node *child;
2813 for_each_child_of_node(np, child) {
2814 if (of_match_node(rockchip_bank_match, child))
2818 info->ngroups += of_get_child_count(child);
2822 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2823 struct rockchip_pin_group *grp,
2824 struct rockchip_pinctrl *info,
2827 struct rockchip_pin_bank *bank;
2834 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
2836 /* Initialise group */
2837 grp->name = np->name;
2840 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2841 * do sanity check and calculate pins number
2843 list = of_get_property(np, "rockchip,pins", &size);
2844 /* we do not check return since it's safe node passed down */
2845 size /= sizeof(*list);
2846 if (!size || size % 4) {
2847 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2851 grp->npins = size / 4;
2853 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
2855 grp->data = devm_kcalloc(info->dev,
2857 sizeof(struct rockchip_pin_config),
2859 if (!grp->pins || !grp->data)
2862 for (i = 0, j = 0; i < size; i += 4, j++) {
2863 const __be32 *phandle;
2864 struct device_node *np_config;
2866 num = be32_to_cpu(*list++);
2867 bank = bank_num_to_bank(info, num);
2869 return PTR_ERR(bank);
2871 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2872 grp->data[j].func = be32_to_cpu(*list++);
2878 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
2879 ret = pinconf_generic_parse_dt_config(np_config, NULL,
2880 &grp->data[j].configs, &grp->data[j].nconfigs);
2888 static int rockchip_pinctrl_parse_functions(struct device_node *np,
2889 struct rockchip_pinctrl *info,
2892 struct device_node *child;
2893 struct rockchip_pmx_func *func;
2894 struct rockchip_pin_group *grp;
2896 static u32 grp_index;
2899 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
2901 func = &info->functions[index];
2903 /* Initialise function */
2904 func->name = np->name;
2905 func->ngroups = of_get_child_count(np);
2906 if (func->ngroups <= 0)
2909 func->groups = devm_kcalloc(info->dev,
2910 func->ngroups, sizeof(char *), GFP_KERNEL);
2914 for_each_child_of_node(np, child) {
2915 func->groups[i] = child->name;
2916 grp = &info->groups[grp_index++];
2917 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
2927 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2928 struct rockchip_pinctrl *info)
2930 struct device *dev = &pdev->dev;
2931 struct device_node *np = dev->of_node;
2932 struct device_node *child;
2936 rockchip_pinctrl_child_count(info, np);
2938 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2939 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2941 info->functions = devm_kcalloc(dev,
2943 sizeof(struct rockchip_pmx_func),
2945 if (!info->functions)
2948 info->groups = devm_kcalloc(dev,
2950 sizeof(struct rockchip_pin_group),
2957 for_each_child_of_node(np, child) {
2958 if (of_match_node(rockchip_bank_match, child))
2961 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2963 dev_err(&pdev->dev, "failed to parse function\n");
2972 static int rockchip_pinctrl_register(struct platform_device *pdev,
2973 struct rockchip_pinctrl *info)
2975 struct pinctrl_desc *ctrldesc = &info->pctl;
2976 struct pinctrl_pin_desc *pindesc, *pdesc;
2977 struct rockchip_pin_bank *pin_bank;
2981 ctrldesc->name = "rockchip-pinctrl";
2982 ctrldesc->owner = THIS_MODULE;
2983 ctrldesc->pctlops = &rockchip_pctrl_ops;
2984 ctrldesc->pmxops = &rockchip_pmx_ops;
2985 ctrldesc->confops = &rockchip_pinconf_ops;
2987 pindesc = devm_kcalloc(&pdev->dev,
2988 info->ctrl->nr_pins, sizeof(*pindesc),
2993 ctrldesc->pins = pindesc;
2994 ctrldesc->npins = info->ctrl->nr_pins;
2997 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2998 pin_bank = &info->ctrl->pin_banks[bank];
2999 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
3001 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
3002 pin_bank->name, pin);
3007 ret = rockchip_pinctrl_parse_dt(pdev, info);
3011 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
3012 if (IS_ERR(info->pctl_dev)) {
3013 dev_err(&pdev->dev, "could not register pinctrl driver\n");
3014 return PTR_ERR(info->pctl_dev);
3017 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
3018 pin_bank = &info->ctrl->pin_banks[bank];
3019 pin_bank->grange.name = pin_bank->name;
3020 pin_bank->grange.id = bank;
3021 pin_bank->grange.pin_base = pin_bank->pin_base;
3022 pin_bank->grange.base = pin_bank->gpio_chip.base;
3023 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
3024 pin_bank->grange.gc = &pin_bank->gpio_chip;
3025 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
3035 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
3037 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3038 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
3039 unsigned long flags;
3042 clk_enable(bank->clk);
3043 raw_spin_lock_irqsave(&bank->slock, flags);
3046 data &= ~BIT(offset);
3048 data |= BIT(offset);
3051 raw_spin_unlock_irqrestore(&bank->slock, flags);
3052 clk_disable(bank->clk);
3056 * Returns the level of the pin for input direction and setting of the DR
3057 * register for output gpios.
3059 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
3061 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3064 clk_enable(bank->clk);
3065 data = readl(bank->reg_base + GPIO_EXT_PORT);
3066 clk_disable(bank->clk);
3073 * gpiolib gpio_direction_input callback function. The setting of the pin
3074 * mux function as 'gpio input' will be handled by the pinctrl subsystem
3077 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
3079 return pinctrl_gpio_direction_input(gc->base + offset);
3083 * gpiolib gpio_direction_output callback function. The setting of the pin
3084 * mux function as 'gpio output' will be handled by the pinctrl subsystem
3087 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
3088 unsigned offset, int value)
3090 rockchip_gpio_set(gc, offset, value);
3091 return pinctrl_gpio_direction_output(gc->base + offset);
3094 static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
3095 unsigned int offset, bool enable)
3097 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3098 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
3099 unsigned long flags;
3102 clk_enable(bank->clk);
3103 raw_spin_lock_irqsave(&bank->slock, flags);
3107 data |= BIT(offset);
3109 data &= ~BIT(offset);
3112 raw_spin_unlock_irqrestore(&bank->slock, flags);
3113 clk_disable(bank->clk);
3117 * gpiolib set_config callback function. The setting of the pin
3118 * mux function as 'gpio output' will be handled by the pinctrl subsystem
3121 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
3122 unsigned long config)
3124 enum pin_config_param param = pinconf_to_config_param(config);
3127 case PIN_CONFIG_INPUT_DEBOUNCE:
3128 rockchip_gpio_set_debounce(gc, offset, true);
3130 * Rockchip's gpio could only support up to one period
3131 * of the debounce clock(pclk), which is far away from
3132 * satisftying the requirement, as pclk is usually near
3133 * 100MHz shared by all peripherals. So the fact is it
3134 * has crippled debounce capability could only be useful
3135 * to prevent any spurious glitches from waking up the system
3136 * if the gpio is conguired as wakeup interrupt source. Let's
3137 * still return -ENOTSUPP as before, to make sure the caller
3138 * of gpiod_set_debounce won't change its behaviour.
3147 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
3148 * and a virtual IRQ, if not already present.
3150 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
3152 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3158 virq = irq_create_mapping(bank->domain, offset);
3160 return (virq) ? : -ENXIO;
3163 static const struct gpio_chip rockchip_gpiolib_chip = {
3164 .request = gpiochip_generic_request,
3165 .free = gpiochip_generic_free,
3166 .set = rockchip_gpio_set,
3167 .get = rockchip_gpio_get,
3168 .get_direction = rockchip_gpio_get_direction,
3169 .direction_input = rockchip_gpio_direction_input,
3170 .direction_output = rockchip_gpio_direction_output,
3171 .set_config = rockchip_gpio_set_config,
3172 .to_irq = rockchip_gpio_to_irq,
3173 .owner = THIS_MODULE,
3177 * Interrupt handling
3180 static void rockchip_irq_demux(struct irq_desc *desc)
3182 struct irq_chip *chip = irq_desc_get_chip(desc);
3183 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
3186 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
3188 chained_irq_enter(chip, desc);
3190 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
3193 unsigned int irq, virq;
3197 virq = irq_linear_revmap(bank->domain, irq);
3200 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
3204 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
3207 * Triggering IRQ on both rising and falling edge
3208 * needs manual intervention.
3210 if (bank->toggle_edge_mode & BIT(irq)) {
3211 u32 data, data_old, polarity;
3212 unsigned long flags;
3214 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
3216 raw_spin_lock_irqsave(&bank->slock, flags);
3218 polarity = readl_relaxed(bank->reg_base +
3220 if (data & BIT(irq))
3221 polarity &= ~BIT(irq);
3223 polarity |= BIT(irq);
3225 bank->reg_base + GPIO_INT_POLARITY);
3227 raw_spin_unlock_irqrestore(&bank->slock, flags);
3230 data = readl_relaxed(bank->reg_base +
3232 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
3235 generic_handle_irq(virq);
3238 chained_irq_exit(chip, desc);
3241 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
3243 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3244 struct rockchip_pin_bank *bank = gc->private;
3245 u32 mask = BIT(d->hwirq);
3249 unsigned long flags;
3252 /* make sure the pin is configured as gpio input */
3253 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
3257 clk_enable(bank->clk);
3258 raw_spin_lock_irqsave(&bank->slock, flags);
3260 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
3262 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
3264 raw_spin_unlock_irqrestore(&bank->slock, flags);
3266 if (type & IRQ_TYPE_EDGE_BOTH)
3267 irq_set_handler_locked(d, handle_edge_irq);
3269 irq_set_handler_locked(d, handle_level_irq);
3271 raw_spin_lock_irqsave(&bank->slock, flags);
3274 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
3275 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
3278 case IRQ_TYPE_EDGE_BOTH:
3279 bank->toggle_edge_mode |= mask;
3283 * Determine gpio state. If 1 next interrupt should be falling
3286 data = readl(bank->reg_base + GPIO_EXT_PORT);
3292 case IRQ_TYPE_EDGE_RISING:
3293 bank->toggle_edge_mode &= ~mask;
3297 case IRQ_TYPE_EDGE_FALLING:
3298 bank->toggle_edge_mode &= ~mask;
3302 case IRQ_TYPE_LEVEL_HIGH:
3303 bank->toggle_edge_mode &= ~mask;
3307 case IRQ_TYPE_LEVEL_LOW:
3308 bank->toggle_edge_mode &= ~mask;
3314 raw_spin_unlock_irqrestore(&bank->slock, flags);
3315 clk_disable(bank->clk);
3319 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
3320 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
3323 raw_spin_unlock_irqrestore(&bank->slock, flags);
3324 clk_disable(bank->clk);
3329 static void rockchip_irq_suspend(struct irq_data *d)
3331 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3332 struct rockchip_pin_bank *bank = gc->private;
3334 clk_enable(bank->clk);
3335 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
3336 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
3337 clk_disable(bank->clk);
3340 static void rockchip_irq_resume(struct irq_data *d)
3342 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3343 struct rockchip_pin_bank *bank = gc->private;
3345 clk_enable(bank->clk);
3346 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
3347 clk_disable(bank->clk);
3350 static void rockchip_irq_enable(struct irq_data *d)
3352 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3353 struct rockchip_pin_bank *bank = gc->private;
3355 clk_enable(bank->clk);
3356 irq_gc_mask_clr_bit(d);
3359 static void rockchip_irq_disable(struct irq_data *d)
3361 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
3362 struct rockchip_pin_bank *bank = gc->private;
3364 irq_gc_mask_set_bit(d);
3365 clk_disable(bank->clk);
3368 static int rockchip_interrupts_register(struct platform_device *pdev,
3369 struct rockchip_pinctrl *info)
3371 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3372 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3373 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
3374 struct irq_chip_generic *gc;
3378 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3380 dev_warn(&pdev->dev, "bank %s is not valid\n",
3385 ret = clk_enable(bank->clk);
3387 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
3392 bank->domain = irq_domain_add_linear(bank->of_node, 32,
3393 &irq_generic_chip_ops, NULL);
3394 if (!bank->domain) {
3395 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
3397 clk_disable(bank->clk);
3401 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
3402 "rockchip_gpio_irq", handle_level_irq,
3403 clr, 0, IRQ_GC_INIT_MASK_CACHE);
3405 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
3407 irq_domain_remove(bank->domain);
3408 clk_disable(bank->clk);
3413 * Linux assumes that all interrupts start out disabled/masked.
3414 * Our driver only uses the concept of masked and always keeps
3415 * things enabled, so for us that's all masked and all enabled.
3417 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3418 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3420 gc = irq_get_domain_generic_chip(bank->domain, 0);
3421 gc->reg_base = bank->reg_base;
3423 gc->chip_types[0].regs.mask = GPIO_INTMASK;
3424 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
3425 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
3426 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
3427 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
3428 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
3429 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
3430 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
3431 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
3432 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
3433 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
3434 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3436 irq_set_chained_handler_and_data(bank->irq,
3437 rockchip_irq_demux, bank);
3439 /* map the gpio irqs here, when the clock is still running */
3440 for (j = 0 ; j < 32 ; j++)
3441 irq_create_mapping(bank->domain, j);
3443 clk_disable(bank->clk);
3449 static int rockchip_gpiolib_register(struct platform_device *pdev,
3450 struct rockchip_pinctrl *info)
3452 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3453 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3454 struct gpio_chip *gc;
3458 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3460 dev_warn(&pdev->dev, "bank %s is not valid\n",
3465 bank->gpio_chip = rockchip_gpiolib_chip;
3467 gc = &bank->gpio_chip;
3468 gc->base = bank->pin_base;
3469 gc->ngpio = bank->nr_pins;
3470 gc->parent = &pdev->dev;
3471 gc->of_node = bank->of_node;
3472 gc->label = bank->name;
3474 ret = gpiochip_add_data(gc, bank);
3476 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
3482 rockchip_interrupts_register(pdev, info);
3487 for (--i, --bank; i >= 0; --i, --bank) {
3490 gpiochip_remove(&bank->gpio_chip);
3495 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
3496 struct rockchip_pinctrl *info)
3498 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3499 struct rockchip_pin_bank *bank = ctrl->pin_banks;
3502 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3505 gpiochip_remove(&bank->gpio_chip);
3511 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
3512 struct rockchip_pinctrl *info)
3514 struct resource res;
3517 if (of_address_to_resource(bank->of_node, 0, &res)) {
3518 dev_err(info->dev, "cannot find IO resource for bank\n");
3522 bank->reg_base = devm_ioremap_resource(info->dev, &res);
3523 if (IS_ERR(bank->reg_base))
3524 return PTR_ERR(bank->reg_base);
3527 * special case, where parts of the pull setting-registers are
3528 * part of the PMU register space
3530 if (of_device_is_compatible(bank->of_node,
3531 "rockchip,rk3188-gpio-bank0")) {
3532 struct device_node *node;
3534 node = of_parse_phandle(bank->of_node->parent,
3537 if (of_address_to_resource(bank->of_node, 1, &res)) {
3538 dev_err(info->dev, "cannot find IO resource for bank\n");
3542 base = devm_ioremap_resource(info->dev, &res);
3544 return PTR_ERR(base);
3545 rockchip_regmap_config.max_register =
3546 resource_size(&res) - 4;
3547 rockchip_regmap_config.name =
3548 "rockchip,rk3188-gpio-bank0-pull";
3549 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
3551 &rockchip_regmap_config);
3556 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3558 bank->clk = of_clk_get(bank->of_node, 0);
3559 if (IS_ERR(bank->clk))
3560 return PTR_ERR(bank->clk);
3562 return clk_prepare(bank->clk);
3565 static const struct of_device_id rockchip_pinctrl_dt_match[];
3567 /* retrieve the soc specific data */
3568 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3569 struct rockchip_pinctrl *d,
3570 struct platform_device *pdev)
3572 const struct of_device_id *match;
3573 struct device_node *node = pdev->dev.of_node;
3574 struct device_node *np;
3575 struct rockchip_pin_ctrl *ctrl;
3576 struct rockchip_pin_bank *bank;
3577 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3579 match = of_match_node(rockchip_pinctrl_dt_match, node);
3580 ctrl = (struct rockchip_pin_ctrl *)match->data;
3582 for_each_child_of_node(node, np) {
3583 if (!of_find_property(np, "gpio-controller", NULL))
3586 bank = ctrl->pin_banks;
3587 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3588 if (!strcmp(bank->name, np->name)) {
3591 if (!rockchip_get_bank_data(bank, d))
3599 grf_offs = ctrl->grf_mux_offset;
3600 pmu_offs = ctrl->pmu_mux_offset;
3601 drv_pmu_offs = ctrl->pmu_drv_offset;
3602 drv_grf_offs = ctrl->grf_drv_offset;
3603 bank = ctrl->pin_banks;
3604 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3607 raw_spin_lock_init(&bank->slock);
3609 bank->pin_base = ctrl->nr_pins;
3610 ctrl->nr_pins += bank->nr_pins;
3612 /* calculate iomux and drv offsets */
3613 for (j = 0; j < 4; j++) {
3614 struct rockchip_iomux *iom = &bank->iomux[j];
3615 struct rockchip_drv *drv = &bank->drv[j];
3618 if (bank_pins >= bank->nr_pins)
3621 /* preset iomux offset value, set new start value */
3622 if (iom->offset >= 0) {
3623 if (iom->type & IOMUX_SOURCE_PMU)
3624 pmu_offs = iom->offset;
3626 grf_offs = iom->offset;
3627 } else { /* set current iomux offset */
3628 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3629 pmu_offs : grf_offs;
3632 /* preset drv offset value, set new start value */
3633 if (drv->offset >= 0) {
3634 if (iom->type & IOMUX_SOURCE_PMU)
3635 drv_pmu_offs = drv->offset;
3637 drv_grf_offs = drv->offset;
3638 } else { /* set current drv offset */
3639 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3640 drv_pmu_offs : drv_grf_offs;
3643 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3644 i, j, iom->offset, drv->offset);
3647 * Increase offset according to iomux width.
3648 * 4bit iomux'es are spread over two registers.
3650 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3652 IOMUX_WIDTH_2BIT)) ? 8 : 4;
3653 if (iom->type & IOMUX_SOURCE_PMU)
3659 * Increase offset according to drv width.
3660 * 3bit drive-strenth'es are spread over two registers.
3662 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3663 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3668 if (iom->type & IOMUX_SOURCE_PMU)
3669 drv_pmu_offs += inc;
3671 drv_grf_offs += inc;
3676 /* calculate the per-bank recalced_mask */
3677 for (j = 0; j < ctrl->niomux_recalced; j++) {
3680 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3681 pin = ctrl->iomux_recalced[j].pin;
3682 bank->recalced_mask |= BIT(pin);
3686 /* calculate the per-bank route_mask */
3687 for (j = 0; j < ctrl->niomux_routes; j++) {
3690 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3691 pin = ctrl->iomux_routes[j].pin;
3692 bank->route_mask |= BIT(pin);
3700 #define RK3288_GRF_GPIO6C_IOMUX 0x64
3701 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3703 static u32 rk3288_grf_gpio6c_iomux;
3705 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3707 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3708 int ret = pinctrl_force_sleep(info->pctl_dev);
3714 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3715 * the setting here, and restore it at resume.
3717 if (info->ctrl->type == RK3288) {
3718 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3719 &rk3288_grf_gpio6c_iomux);
3721 pinctrl_force_default(info->pctl_dev);
3729 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3731 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3732 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3733 rk3288_grf_gpio6c_iomux |
3734 GPIO6C6_SEL_WRITE_ENABLE);
3739 return pinctrl_force_default(info->pctl_dev);
3742 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3743 rockchip_pinctrl_resume);
3745 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3747 struct rockchip_pinctrl *info;
3748 struct device *dev = &pdev->dev;
3749 struct rockchip_pin_ctrl *ctrl;
3750 struct device_node *np = pdev->dev.of_node, *node;
3751 struct resource *res;
3755 if (!dev->of_node) {
3756 dev_err(dev, "device tree node not found\n");
3760 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3766 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3768 dev_err(dev, "driver data not available\n");
3773 node = of_parse_phandle(np, "rockchip,grf", 0);
3775 info->regmap_base = syscon_node_to_regmap(node);
3776 if (IS_ERR(info->regmap_base))
3777 return PTR_ERR(info->regmap_base);
3779 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3780 base = devm_ioremap_resource(&pdev->dev, res);
3782 return PTR_ERR(base);
3784 rockchip_regmap_config.max_register = resource_size(res) - 4;
3785 rockchip_regmap_config.name = "rockchip,pinctrl";
3786 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3787 &rockchip_regmap_config);
3789 /* to check for the old dt-bindings */
3790 info->reg_size = resource_size(res);
3792 /* Honor the old binding, with pull registers as 2nd resource */
3793 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3794 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3795 base = devm_ioremap_resource(&pdev->dev, res);
3797 return PTR_ERR(base);
3799 rockchip_regmap_config.max_register =
3800 resource_size(res) - 4;
3801 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3802 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3804 &rockchip_regmap_config);
3808 /* try to find the optional reference to the pmu syscon */
3809 node = of_parse_phandle(np, "rockchip,pmu", 0);
3811 info->regmap_pmu = syscon_node_to_regmap(node);
3812 if (IS_ERR(info->regmap_pmu))
3813 return PTR_ERR(info->regmap_pmu);
3816 ret = rockchip_gpiolib_register(pdev, info);
3820 ret = rockchip_pinctrl_register(pdev, info);
3822 rockchip_gpiolib_unregister(pdev, info);
3826 platform_set_drvdata(pdev, info);
3831 static struct rockchip_pin_bank px30_pin_banks[] = {
3832 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3837 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3842 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3847 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3854 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3855 .pin_banks = px30_pin_banks,
3856 .nr_banks = ARRAY_SIZE(px30_pin_banks),
3857 .label = "PX30-GPIO",
3859 .grf_mux_offset = 0x0,
3860 .pmu_mux_offset = 0x0,
3861 .iomux_routes = px30_mux_route_data,
3862 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3863 .pull_calc_reg = px30_calc_pull_reg_and_bit,
3864 .drv_calc_reg = px30_calc_drv_reg_and_bit,
3865 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3868 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3869 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3873 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3874 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3875 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3878 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3879 .pin_banks = rv1108_pin_banks,
3880 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3881 .label = "RV1108-GPIO",
3883 .grf_mux_offset = 0x10,
3884 .pmu_mux_offset = 0x0,
3885 .iomux_recalced = rv1108_mux_recalced_data,
3886 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
3887 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3888 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
3889 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
3892 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3893 PIN_BANK(0, 32, "gpio0"),
3894 PIN_BANK(1, 32, "gpio1"),
3895 PIN_BANK(2, 32, "gpio2"),
3896 PIN_BANK(3, 32, "gpio3"),
3899 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3900 .pin_banks = rk2928_pin_banks,
3901 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3902 .label = "RK2928-GPIO",
3904 .grf_mux_offset = 0xa8,
3905 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3908 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3909 PIN_BANK(0, 32, "gpio0"),
3910 PIN_BANK(1, 32, "gpio1"),
3911 PIN_BANK(2, 32, "gpio2"),
3914 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3915 .pin_banks = rk3036_pin_banks,
3916 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3917 .label = "RK3036-GPIO",
3919 .grf_mux_offset = 0xa8,
3920 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3923 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3924 PIN_BANK(0, 32, "gpio0"),
3925 PIN_BANK(1, 32, "gpio1"),
3926 PIN_BANK(2, 32, "gpio2"),
3927 PIN_BANK(3, 32, "gpio3"),
3928 PIN_BANK(4, 32, "gpio4"),
3929 PIN_BANK(6, 16, "gpio6"),
3932 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3933 .pin_banks = rk3066a_pin_banks,
3934 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3935 .label = "RK3066a-GPIO",
3937 .grf_mux_offset = 0xa8,
3938 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3941 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3942 PIN_BANK(0, 32, "gpio0"),
3943 PIN_BANK(1, 32, "gpio1"),
3944 PIN_BANK(2, 32, "gpio2"),
3945 PIN_BANK(3, 32, "gpio3"),
3948 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3949 .pin_banks = rk3066b_pin_banks,
3950 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3951 .label = "RK3066b-GPIO",
3953 .grf_mux_offset = 0x60,
3956 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3957 PIN_BANK(0, 32, "gpio0"),
3958 PIN_BANK(1, 32, "gpio1"),
3959 PIN_BANK(2, 32, "gpio2"),
3960 PIN_BANK(3, 32, "gpio3"),
3963 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3964 .pin_banks = rk3128_pin_banks,
3965 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3966 .label = "RK3128-GPIO",
3968 .grf_mux_offset = 0xa8,
3969 .iomux_recalced = rk3128_mux_recalced_data,
3970 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3971 .iomux_routes = rk3128_mux_route_data,
3972 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3973 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3976 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3977 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3978 PIN_BANK(1, 32, "gpio1"),
3979 PIN_BANK(2, 32, "gpio2"),
3980 PIN_BANK(3, 32, "gpio3"),
3983 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3984 .pin_banks = rk3188_pin_banks,
3985 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3986 .label = "RK3188-GPIO",
3988 .grf_mux_offset = 0x60,
3989 .iomux_routes = rk3188_mux_route_data,
3990 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
3991 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
3994 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3995 PIN_BANK(0, 32, "gpio0"),
3996 PIN_BANK(1, 32, "gpio1"),
3997 PIN_BANK(2, 32, "gpio2"),
3998 PIN_BANK(3, 32, "gpio3"),
4001 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
4002 .pin_banks = rk3228_pin_banks,
4003 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
4004 .label = "RK3228-GPIO",
4006 .grf_mux_offset = 0x0,
4007 .iomux_routes = rk3228_mux_route_data,
4008 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
4009 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
4010 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
4013 static struct rockchip_pin_bank rk3288_pin_banks[] = {
4014 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
4019 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
4024 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
4025 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
4026 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4031 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
4036 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
4037 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
4042 PIN_BANK(8, 16, "gpio8"),
4045 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
4046 .pin_banks = rk3288_pin_banks,
4047 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
4048 .label = "RK3288-GPIO",
4050 .grf_mux_offset = 0x0,
4051 .pmu_mux_offset = 0x84,
4052 .iomux_routes = rk3288_mux_route_data,
4053 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
4054 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
4055 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
4058 static struct rockchip_pin_bank rk3308_pin_banks[] = {
4059 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
4063 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
4067 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
4071 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
4075 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
4081 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
4082 .pin_banks = rk3308_pin_banks,
4083 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
4084 .label = "RK3308-GPIO",
4086 .grf_mux_offset = 0x0,
4087 .iomux_recalced = rk3308_mux_recalced_data,
4088 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
4089 .iomux_routes = rk3308_mux_route_data,
4090 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
4091 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
4092 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
4093 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
4096 static struct rockchip_pin_bank rk3328_pin_banks[] = {
4097 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
4098 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
4099 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
4103 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
4110 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
4111 .pin_banks = rk3328_pin_banks,
4112 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
4113 .label = "RK3328-GPIO",
4115 .grf_mux_offset = 0x0,
4116 .iomux_recalced = rk3328_mux_recalced_data,
4117 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
4118 .iomux_routes = rk3328_mux_route_data,
4119 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
4120 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
4121 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
4122 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
4125 static struct rockchip_pin_bank rk3368_pin_banks[] = {
4126 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4131 PIN_BANK(1, 32, "gpio1"),
4132 PIN_BANK(2, 32, "gpio2"),
4133 PIN_BANK(3, 32, "gpio3"),
4136 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
4137 .pin_banks = rk3368_pin_banks,
4138 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
4139 .label = "RK3368-GPIO",
4141 .grf_mux_offset = 0x0,
4142 .pmu_mux_offset = 0x0,
4143 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
4144 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
4147 static struct rockchip_pin_bank rk3399_pin_banks[] = {
4148 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
4153 DRV_TYPE_IO_1V8_ONLY,
4154 DRV_TYPE_IO_1V8_ONLY,
4155 DRV_TYPE_IO_DEFAULT,
4156 DRV_TYPE_IO_DEFAULT,
4161 PULL_TYPE_IO_1V8_ONLY,
4162 PULL_TYPE_IO_1V8_ONLY,
4163 PULL_TYPE_IO_DEFAULT,
4164 PULL_TYPE_IO_DEFAULT
4166 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
4170 DRV_TYPE_IO_1V8_OR_3V0,
4171 DRV_TYPE_IO_1V8_OR_3V0,
4172 DRV_TYPE_IO_1V8_OR_3V0,
4173 DRV_TYPE_IO_1V8_OR_3V0,
4179 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
4180 DRV_TYPE_IO_1V8_OR_3V0,
4181 DRV_TYPE_IO_1V8_ONLY,
4182 DRV_TYPE_IO_1V8_ONLY,
4183 PULL_TYPE_IO_DEFAULT,
4184 PULL_TYPE_IO_DEFAULT,
4185 PULL_TYPE_IO_1V8_ONLY,
4186 PULL_TYPE_IO_1V8_ONLY
4188 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
4189 DRV_TYPE_IO_3V3_ONLY,
4190 DRV_TYPE_IO_3V3_ONLY,
4191 DRV_TYPE_IO_1V8_OR_3V0
4193 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
4194 DRV_TYPE_IO_1V8_3V0_AUTO,
4195 DRV_TYPE_IO_1V8_OR_3V0,
4196 DRV_TYPE_IO_1V8_OR_3V0
4200 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
4201 .pin_banks = rk3399_pin_banks,
4202 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
4203 .label = "RK3399-GPIO",
4205 .grf_mux_offset = 0xe000,
4206 .pmu_mux_offset = 0x0,
4207 .grf_drv_offset = 0xe100,
4208 .pmu_drv_offset = 0x80,
4209 .iomux_routes = rk3399_mux_route_data,
4210 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
4211 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
4212 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
4215 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4216 { .compatible = "rockchip,px30-pinctrl",
4217 .data = &px30_pin_ctrl },
4218 { .compatible = "rockchip,rv1108-pinctrl",
4219 .data = &rv1108_pin_ctrl },
4220 { .compatible = "rockchip,rk2928-pinctrl",
4221 .data = &rk2928_pin_ctrl },
4222 { .compatible = "rockchip,rk3036-pinctrl",
4223 .data = &rk3036_pin_ctrl },
4224 { .compatible = "rockchip,rk3066a-pinctrl",
4225 .data = &rk3066a_pin_ctrl },
4226 { .compatible = "rockchip,rk3066b-pinctrl",
4227 .data = &rk3066b_pin_ctrl },
4228 { .compatible = "rockchip,rk3128-pinctrl",
4229 .data = (void *)&rk3128_pin_ctrl },
4230 { .compatible = "rockchip,rk3188-pinctrl",
4231 .data = &rk3188_pin_ctrl },
4232 { .compatible = "rockchip,rk3228-pinctrl",
4233 .data = &rk3228_pin_ctrl },
4234 { .compatible = "rockchip,rk3288-pinctrl",
4235 .data = &rk3288_pin_ctrl },
4236 { .compatible = "rockchip,rk3308-pinctrl",
4237 .data = &rk3308_pin_ctrl },
4238 { .compatible = "rockchip,rk3328-pinctrl",
4239 .data = &rk3328_pin_ctrl },
4240 { .compatible = "rockchip,rk3368-pinctrl",
4241 .data = &rk3368_pin_ctrl },
4242 { .compatible = "rockchip,rk3399-pinctrl",
4243 .data = &rk3399_pin_ctrl },
4247 static struct platform_driver rockchip_pinctrl_driver = {
4248 .probe = rockchip_pinctrl_probe,
4250 .name = "rockchip-pinctrl",
4251 .pm = &rockchip_pinctrl_dev_pm_ops,
4252 .of_match_table = rockchip_pinctrl_dt_match,
4256 static int __init rockchip_pinctrl_drv_register(void)
4258 return platform_driver_register(&rockchip_pinctrl_driver);
4260 postcore_initcall(rockchip_pinctrl_drv_register);