drivers/pinctrl/pinctrl-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Pinctrl driver for Rockchip SoCs
   4  *
   5  * Copyright (c) 2013 MundoReader S.L.
   6  * Author: Heiko Stuebner <heiko@sntech.de>
   7  *
   8  * With some ideas taken from pinctrl-samsung:
   9  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  10  *              http://www.samsung.com
  11  * Copyright (c) 2012 Linaro Ltd
  12  *              https://www.linaro.org
  13  *
  14  * and pinctrl-at91:
  15  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/io.h>
  22 #include <linux/bitops.h>
  23 #include <linux/gpio/driver.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/pinctrl/machine.h>
  28 #include <linux/pinctrl/pinconf.h>
  29 #include <linux/pinctrl/pinctrl.h>
  30 #include <linux/pinctrl/pinmux.h>
  31 #include <linux/pinctrl/pinconf-generic.h>
  32 #include <linux/irqchip/chained_irq.h>
  33 #include <linux/clk.h>
  34 #include <linux/regmap.h>
  35 #include <linux/mfd/syscon.h>
  36 #include <linux/string_helpers.h>
  37
  38 #include <dt-bindings/pinctrl/rockchip.h>
  39
  40 #include "core.h"
  41 #include "pinconf.h"
  42 #include "pinctrl-rockchip.h"
  43
  44 /*
  45  * Generate a bitmask for setting a value (v) with a write mask bit in hiword
  46  * register 31:16 area.
  47  */
  48 #define WRITE_MASK_VAL(h, l, v) \
  49         (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
  50
  51 /*
  52  * Encode variants of iomux registers into a type variable
  53  */
  54 #define IOMUX_GPIO_ONLY         BIT(0)
  55 #define IOMUX_WIDTH_4BIT        BIT(1)
  56 #define IOMUX_SOURCE_PMU        BIT(2)
  57 #define IOMUX_UNROUTED          BIT(3)
  58 #define IOMUX_WIDTH_3BIT        BIT(4)
  59 #define IOMUX_WIDTH_2BIT        BIT(5)
  60 #define IOMUX_L_SOURCE_PMU      BIT(6)
  61
  62 #define PIN_BANK(id, pins, label)                       \
  63         {                                               \
  64                 .bank_num       = id,                   \
  65                 .nr_pins        = pins,                 \
  66                 .name           = label,                \
  67                 .iomux          = {                     \
  68                         { .offset = -1 },               \
  69                         { .offset = -1 },               \
  70                         { .offset = -1 },               \
  71                         { .offset = -1 },               \
  72                 },                                      \
  73         }
  74
  75 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
  76         {                                                               \
  77                 .bank_num       = id,                                   \
  78                 .nr_pins        = pins,                                 \
  79                 .name           = label,                                \
  80                 .iomux          = {                                     \
  81                         { .type = iom0, .offset = -1 },                 \
  82                         { .type = iom1, .offset = -1 },                 \
  83                         { .type = iom2, .offset = -1 },                 \
  84                         { .type = iom3, .offset = -1 },                 \
  85                 },                                                      \
  86         }
  87
  88 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
  89         {                                                               \
  90                 .bank_num       = id,                                   \
  91                 .nr_pins        = pins,                                 \
  92                 .name           = label,                                \
  93                 .iomux          = {                                     \
  94                         { .offset = -1 },                               \
  95                         { .offset = -1 },                               \
  96                         { .offset = -1 },                               \
  97                         { .offset = -1 },                               \
  98                 },                                                      \
  99                 .drv            = {                                     \
 100                         { .drv_type = type0, .offset = -1 },            \
 101                         { .drv_type = type1, .offset = -1 },            \
 102                         { .drv_type = type2, .offset = -1 },            \
 103                         { .drv_type = type3, .offset = -1 },            \
 104                 },                                                      \
 105         }
 106
 107 #define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1,    \
 108                                         iom2, iom3, pull0, pull1,       \
 109                                         pull2, pull3)                   \
 110         {                                                               \
 111                 .bank_num       = id,                                   \
 112                 .nr_pins        = pins,                                 \
 113                 .name           = label,                                \
 114                 .iomux          = {                                     \
 115                         { .type = iom0, .offset = -1 },                 \
 116                         { .type = iom1, .offset = -1 },                 \
 117                         { .type = iom2, .offset = -1 },                 \
 118                         { .type = iom3, .offset = -1 },                 \
 119                 },                                                      \
 120                 .pull_type[0] = pull0,                                  \
 121                 .pull_type[1] = pull1,                                  \
 122                 .pull_type[2] = pull2,                                  \
 123                 .pull_type[3] = pull3,                                  \
 124         }
 125
 126 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,      \
 127                                       drv2, drv3, pull0, pull1,         \
 128                                       pull2, pull3)                     \
 129         {                                                               \
 130                 .bank_num       = id,                                   \
 131                 .nr_pins        = pins,                                 \
 132                 .name           = label,                                \
 133                 .iomux          = {                                     \
 134                         { .offset = -1 },                               \
 135                         { .offset = -1 },                               \
 136                         { .offset = -1 },                               \
 137                         { .offset = -1 },                               \
 138                 },                                                      \
 139                 .drv            = {                                     \
 140                         { .drv_type = drv0, .offset = -1 },             \
 141                         { .drv_type = drv1, .offset = -1 },             \
 142                         { .drv_type = drv2, .offset = -1 },             \
 143                         { .drv_type = drv3, .offset = -1 },             \
 144                 },                                                      \
 145                 .pull_type[0] = pull0,                                  \
 146                 .pull_type[1] = pull1,                                  \
 147                 .pull_type[2] = pull2,                                  \
 148                 .pull_type[3] = pull3,                                  \
 149         }
 150
 151 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2,  \
 152                                     iom3, offset0, offset1, offset2,    \
 153                                     offset3)                            \
 154         {                                                               \
 155                 .bank_num       = id,                                   \
 156                 .nr_pins        = pins,                                 \
 157                 .name           = label,                                \
 158                 .iomux          = {                                     \
 159                         { .type = iom0, .offset = offset0 },            \
 160                         { .type = iom1, .offset = offset1 },            \
 161                         { .type = iom2, .offset = offset2 },            \
 162                         { .type = iom3, .offset = offset3 },            \
 163                 },                                                      \
 164         }
 165
 166 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 167                                         iom2, iom3, drv0, drv1, drv2,   \
 168                                         drv3, offset0, offset1,         \
 169                                         offset2, offset3)               \
 170         {                                                               \
 171                 .bank_num       = id,                                   \
 172                 .nr_pins        = pins,                                 \
 173                 .name           = label,                                \
 174                 .iomux          = {                                     \
 175                         { .type = iom0, .offset = -1 },                 \
 176                         { .type = iom1, .offset = -1 },                 \
 177                         { .type = iom2, .offset = -1 },                 \
 178                         { .type = iom3, .offset = -1 },                 \
 179                 },                                                      \
 180                 .drv            = {                                     \
 181                         { .drv_type = drv0, .offset = offset0 },        \
 182                         { .drv_type = drv1, .offset = offset1 },        \
 183                         { .drv_type = drv2, .offset = offset2 },        \
 184                         { .drv_type = drv3, .offset = offset3 },        \
 185                 },                                                      \
 186         }
 187
 188 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 189                                               label, iom0, iom1, iom2,  \
 190                                               iom3, drv0, drv1, drv2,   \
 191                                               drv3, offset0, offset1,   \
 192                                               offset2, offset3, pull0,  \
 193                                               pull1, pull2, pull3)      \
 194         {                                                               \
 195                 .bank_num       = id,                                   \
 196                 .nr_pins        = pins,                                 \
 197                 .name           = label,                                \
 198                 .iomux          = {                                     \
 199                         { .type = iom0, .offset = -1 },                 \
 200                         { .type = iom1, .offset = -1 },                 \
 201                         { .type = iom2, .offset = -1 },                 \
 202                         { .type = iom3, .offset = -1 },                 \
 203                 },                                                      \
 204                 .drv            = {                                     \
 205                         { .drv_type = drv0, .offset = offset0 },        \
 206                         { .drv_type = drv1, .offset = offset1 },        \
 207                         { .drv_type = drv2, .offset = offset2 },        \
 208                         { .drv_type = drv3, .offset = offset3 },        \
 209                 },                                                      \
 210                 .pull_type[0] = pull0,                                  \
 211                 .pull_type[1] = pull1,                                  \
 212                 .pull_type[2] = pull2,                                  \
 213                 .pull_type[3] = pull3,                                  \
 214         }
 215
 216 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG)         \
 217         {                                                               \
 218                 .bank_num       = ID,                                   \
 219                 .pin            = PIN,                                  \
 220                 .func           = FUNC,                                 \
 221                 .route_offset   = REG,                                  \
 222                 .route_val      = VAL,                                  \
 223                 .route_location = FLAG,                                 \
 224         }
 225
 226 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL)       \
 227         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
 228
 229 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL)        \
 230         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
 231
 232 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL)        \
 233         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
 234
 235 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P)                     \
 236         PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
 237
 238 static struct regmap_config rockchip_regmap_config = {
 239         .reg_bits = 32,
 240         .val_bits = 32,
 241         .reg_stride = 4,
 242 };
 243
 244 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
 245                                         const struct rockchip_pinctrl *info,
 246                                         const char *name)
 247 {
 248         int i;
 249
 250         for (i = 0; i < info->ngroups; i++) {
 251                 if (!strcmp(info->groups[i].name, name))
 252                         return &info->groups[i];
 253         }
 254
 255         return NULL;
 256 }
 257
 258 /*
 259  * given a pin number that is local to a pin controller, find out the pin bank
 260  * and the register base of the pin bank.
 261  */
 262 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 263                                                                 unsigned pin)
 264 {
 265         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 266
 267         while (pin >= (b->pin_base + b->nr_pins))
 268                 b++;
 269
 270         return b;
 271 }
 272
 273 static struct rockchip_pin_bank *bank_num_to_bank(
 274                                         struct rockchip_pinctrl *info,
 275                                         unsigned num)
 276 {
 277         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 278         int i;
 279
 280         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 281                 if (b->bank_num == num)
 282                         return b;
 283         }
 284
 285         return ERR_PTR(-EINVAL);
 286 }
 287
 288 /*
 289  * Pinctrl_ops handling
 290  */
 291
 292 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 293 {
 294         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 295
 296         return info->ngroups;
 297 }
 298
 299 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 300                                                         unsigned selector)
 301 {
 302         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 303
 304         return info->groups[selector].name;
 305 }
 306
 307 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 308                                       unsigned selector, const unsigned **pins,
 309                                       unsigned *npins)
 310 {
 311         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 312
 313         if (selector >= info->ngroups)
 314                 return -EINVAL;
 315
 316         *pins = info->groups[selector].pins;
 317         *npins = info->groups[selector].npins;
 318
 319         return 0;
 320 }
 321
 322 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 323                                  struct device_node *np,
 324                                  struct pinctrl_map **map, unsigned *num_maps)
 325 {
 326         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 327         const struct rockchip_pin_group *grp;
 328         struct device *dev = info->dev;
 329         struct pinctrl_map *new_map;
 330         struct device_node *parent;
 331         int map_num = 1;
 332         int i;
 333
 334         /*
 335          * first find the group of this node and check if we need to create
 336          * config maps for pins
 337          */
 338         grp = pinctrl_name_to_group(info, np->name);
 339         if (!grp) {
 340                 dev_err(dev, "unable to find group for node %pOFn\n", np);
 341                 return -EINVAL;
 342         }
 343
 344         map_num += grp->npins;
 345
 346         new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
 347         if (!new_map)
 348                 return -ENOMEM;
 349
 350         *map = new_map;
 351         *num_maps = map_num;
 352
 353         /* create mux map */
 354         parent = of_get_parent(np);
 355         if (!parent) {
 356                 kfree(new_map);
 357                 return -EINVAL;
 358         }
 359         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 360         new_map[0].data.mux.function = parent->name;
 361         new_map[0].data.mux.group = np->name;
 362         of_node_put(parent);
 363
 364         /* create config map */
 365         new_map++;
 366         for (i = 0; i < grp->npins; i++) {
 367                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 368                 new_map[i].data.configs.group_or_pin =
 369                                 pin_get_name(pctldev, grp->pins[i]);
 370                 new_map[i].data.configs.configs = grp->data[i].configs;
 371                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 372         }
 373
 374         dev_dbg(dev, "maps: function %s group %s num %d\n",
 375                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 376
 377         return 0;
 378 }
 379
 380 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 381                                     struct pinctrl_map *map, unsigned num_maps)
 382 {
 383         kfree(map);
 384 }
 385
 386 static const struct pinctrl_ops rockchip_pctrl_ops = {
 387         .get_groups_count       = rockchip_get_groups_count,
 388         .get_group_name         = rockchip_get_group_name,
 389         .get_group_pins         = rockchip_get_group_pins,
 390         .dt_node_to_map         = rockchip_dt_node_to_map,
 391         .dt_free_map            = rockchip_dt_free_map,
 392 };
 393
 394 /*
 395  * Hardware access
 396  */
 397
 398 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
 399         {
 400                 .num = 1,
 401                 .pin = 0,
 402                 .reg = 0x418,
 403                 .bit = 0,
 404                 .mask = 0x3
 405         }, {
 406                 .num = 1,
 407                 .pin = 1,
 408                 .reg = 0x418,
 409                 .bit = 2,
 410                 .mask = 0x3
 411         }, {
 412                 .num = 1,
 413                 .pin = 2,
 414                 .reg = 0x418,
 415                 .bit = 4,
 416                 .mask = 0x3
 417         }, {
 418                 .num = 1,
 419                 .pin = 3,
 420                 .reg = 0x418,
 421                 .bit = 6,
 422                 .mask = 0x3
 423         }, {
 424                 .num = 1,
 425                 .pin = 4,
 426                 .reg = 0x418,
 427                 .bit = 8,
 428                 .mask = 0x3
 429         }, {
 430                 .num = 1,
 431                 .pin = 5,
 432                 .reg = 0x418,
 433                 .bit = 10,
 434                 .mask = 0x3
 435         }, {
 436                 .num = 1,
 437                 .pin = 6,
 438                 .reg = 0x418,
 439                 .bit = 12,
 440                 .mask = 0x3
 441         }, {
 442                 .num = 1,
 443                 .pin = 7,
 444                 .reg = 0x418,
 445                 .bit = 14,
 446                 .mask = 0x3
 447         }, {
 448                 .num = 1,
 449                 .pin = 8,
 450                 .reg = 0x41c,
 451                 .bit = 0,
 452                 .mask = 0x3
 453         }, {
 454                 .num = 1,
 455                 .pin = 9,
 456                 .reg = 0x41c,
 457                 .bit = 2,
 458                 .mask = 0x3
 459         },
 460 };
 461
 462 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
 463         {
 464                 .num = 0,
 465                 .pin = 20,
 466                 .reg = 0x10000,
 467                 .bit = 0,
 468                 .mask = 0xf
 469         },
 470         {
 471                 .num = 0,
 472                 .pin = 21,
 473                 .reg = 0x10000,
 474                 .bit = 4,
 475                 .mask = 0xf
 476         },
 477         {
 478                 .num = 0,
 479                 .pin = 22,
 480                 .reg = 0x10000,
 481                 .bit = 8,
 482                 .mask = 0xf
 483         },
 484         {
 485                 .num = 0,
 486                 .pin = 23,
 487                 .reg = 0x10000,
 488                 .bit = 12,
 489                 .mask = 0xf
 490         },
 491 };
 492
 493 static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
 494         {
 495                 .num = 2,
 496                 .pin = 20,
 497                 .reg = 0xe8,
 498                 .bit = 0,
 499                 .mask = 0x7
 500         }, {
 501                 .num = 2,
 502                 .pin = 21,
 503                 .reg = 0xe8,
 504                 .bit = 4,
 505                 .mask = 0x7
 506         }, {
 507                 .num = 2,
 508                 .pin = 22,
 509                 .reg = 0xe8,
 510                 .bit = 8,
 511                 .mask = 0x7
 512         }, {
 513                 .num = 2,
 514                 .pin = 23,
 515                 .reg = 0xe8,
 516                 .bit = 12,
 517                 .mask = 0x7
 518         }, {
 519                 .num = 2,
 520                 .pin = 24,
 521                 .reg = 0xd4,
 522                 .bit = 12,
 523                 .mask = 0x7
 524         },
 525 };
 526
 527 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
 528         {
 529                 /* gpio1b6_sel */
 530                 .num = 1,
 531                 .pin = 14,
 532                 .reg = 0x28,
 533                 .bit = 12,
 534                 .mask = 0xf
 535         }, {
 536                 /* gpio1b7_sel */
 537                 .num = 1,
 538                 .pin = 15,
 539                 .reg = 0x2c,
 540                 .bit = 0,
 541                 .mask = 0x3
 542         }, {
 543                 /* gpio1c2_sel */
 544                 .num = 1,
 545                 .pin = 18,
 546                 .reg = 0x30,
 547                 .bit = 4,
 548                 .mask = 0xf
 549         }, {
 550                 /* gpio1c3_sel */
 551                 .num = 1,
 552                 .pin = 19,
 553                 .reg = 0x30,
 554                 .bit = 8,
 555                 .mask = 0xf
 556         }, {
 557                 /* gpio1c4_sel */
 558                 .num = 1,
 559                 .pin = 20,
 560                 .reg = 0x30,
 561                 .bit = 12,
 562                 .mask = 0xf
 563         }, {
 564                 /* gpio1c5_sel */
 565                 .num = 1,
 566                 .pin = 21,
 567                 .reg = 0x34,
 568                 .bit = 0,
 569                 .mask = 0xf
 570         }, {
 571                 /* gpio1c6_sel */
 572                 .num = 1,
 573                 .pin = 22,
 574                 .reg = 0x34,
 575                 .bit = 4,
 576                 .mask = 0xf
 577         }, {
 578                 /* gpio1c7_sel */
 579                 .num = 1,
 580                 .pin = 23,
 581                 .reg = 0x34,
 582                 .bit = 8,
 583                 .mask = 0xf
 584         }, {
 585                 /* gpio2a2_sel */
 586                 .num = 2,
 587                 .pin = 2,
 588                 .reg = 0x40,
 589                 .bit = 4,
 590                 .mask = 0x3
 591         }, {
 592                 /* gpio2a3_sel */
 593                 .num = 2,
 594                 .pin = 3,
 595                 .reg = 0x40,
 596                 .bit = 6,
 597                 .mask = 0x3
 598         }, {
 599                 /* gpio2c0_sel */
 600                 .num = 2,
 601                 .pin = 16,
 602                 .reg = 0x50,
 603                 .bit = 0,
 604                 .mask = 0x3
 605         }, {
 606                 /* gpio3b2_sel */
 607                 .num = 3,
 608                 .pin = 10,
 609                 .reg = 0x68,
 610                 .bit = 4,
 611                 .mask = 0x3
 612         }, {
 613                 /* gpio3b3_sel */
 614                 .num = 3,
 615                 .pin = 11,
 616                 .reg = 0x68,
 617                 .bit = 6,
 618                 .mask = 0x3
 619         }, {
 620                 /* gpio3b4_sel */
 621                 .num = 3,
 622                 .pin = 12,
 623                 .reg = 0x68,
 624                 .bit = 8,
 625                 .mask = 0xf
 626         }, {
 627                 /* gpio3b5_sel */
 628                 .num = 3,
 629                 .pin = 13,
 630                 .reg = 0x68,
 631                 .bit = 12,
 632                 .mask = 0xf
 633         },
 634 };
 635
 636 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 637         {
 638                 .num = 2,
 639                 .pin = 12,
 640                 .reg = 0x24,
 641                 .bit = 8,
 642                 .mask = 0x3
 643         }, {
 644                 .num = 2,
 645                 .pin = 15,
 646                 .reg = 0x28,
 647                 .bit = 0,
 648                 .mask = 0x7
 649         }, {
 650                 .num = 2,
 651                 .pin = 23,
 652                 .reg = 0x30,
 653                 .bit = 14,
 654                 .mask = 0x3
 655         },
 656 };
 657
 658 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
 659                                       int *reg, u8 *bit, int *mask)
 660 {
 661         struct rockchip_pinctrl *info = bank->drvdata;
 662         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 663         struct rockchip_mux_recalced_data *data;
 664         int i;
 665
 666         for (i = 0; i < ctrl->niomux_recalced; i++) {
 667                 data = &ctrl->iomux_recalced[i];
 668                 if (data->num == bank->bank_num &&
 669                     data->pin == pin)
 670                         break;
 671         }
 672
 673         if (i >= ctrl->niomux_recalced)
 674                 return;
 675
 676         *reg = data->reg;
 677         *mask = data->mask;
 678         *bit = data->bit;
 679 }
 680
 681 static struct rockchip_mux_route_data px30_mux_route_data[] = {
 682         RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
 683         RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
 684         RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
 685         RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
 686         RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
 687         RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
 688         RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
 689         RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
 690         RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
 691         RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
 692         RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
 693         RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
 694         RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
 695         RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
 696         RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
 697         RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
 698         RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
 699         RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
 700         RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
 701         RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
 702         RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
 703         RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
 704         RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
 705         RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
 706         RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
 707         RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
 708         RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
 709         RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
 710         RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
 711         RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
 712         RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
 713         RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
 714         RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
 715         RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
 716         RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
 717         RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
 718         RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
 719         RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
 720         RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
 721         RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
 722         RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
 723         RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
 724         RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
 725         RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
 726         RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
 727         RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
 728         RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
 729         RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
 730 };
 731
 732 static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
 733         RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
 734         RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
 735
 736         RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
 737         RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
 738         RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
 739
 740         RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
 741         RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
 742
 743         RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
 744         RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
 745
 746         RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
 747         RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
 748
 749         RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
 750         RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
 751         RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
 752
 753         RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
 754         RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
 755
 756         RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
 757         RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
 758         RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
 759
 760         RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
 761         RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
 762         RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
 763
 764         RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
 765         RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
 766
 767         RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
 768         RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
 769
 770         RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
 771         RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
 772
 773         RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
 774         RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
 775
 776         RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
 777         RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
 778
 779         RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
 780         RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
 781
 782         RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
 783         RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
 784
 785         RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
 786         RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
 787         RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
 788
 789         RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
 790         RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
 791         RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
 792
 793         RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
 794         RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
 795         RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
 796
 797         RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
 798         RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
 799
 800         RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
 801         RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
 802
 803         RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
 804         RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
 805
 806         RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
 807         RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
 808
 809         RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
 810         RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
 811
 812         RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
 813         RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
 814
 815         RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
 816         RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
 817
 818         RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
 819         RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
 820
 821         RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
 822         RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
 823         RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
 824
 825         RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
 826         RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
 827 };
 828
 829 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
 830         RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
 831         RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
 832         RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
 833         RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
 834         RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
 835         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
 836         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
 837 };
 838
 839 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
 840         RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
 841         RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
 842 };
 843
 844 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
 845         RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
 846         RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
 847         RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
 848         RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
 849         RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
 850         RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
 851         RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
 852         RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
 853         RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
 854         RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
 855         RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
 856         RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
 857         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
 858         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
 859         RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
 860         RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
 861         RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
 862         RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
 863 };
 864
 865 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
 866         RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
 867         RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
 868 };
 869
 870 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
 871         RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
 872         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
 873         RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
 874         RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
 875         RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
 876         RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
 877         RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
 878         RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
 879         RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
 880         RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
 881         RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
 882         RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
 883         RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
 884         RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
 885         RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
 886         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
 887         RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
 888         RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
 889         RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
 890         RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
 891         RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
 892         RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
 893         RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
 894         RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
 895         RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
 896         RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
 897 };
 898
 899 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
 900         RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
 901         RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
 902         RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
 903         RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
 904         RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
 905         RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
 906         RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
 907         RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
 908         RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
 909         RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
 910         RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
 911         RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
 912 };
 913
 914 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
 915         RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
 916         RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
 917         RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
 918         RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
 919         RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
 920 };
 921
 922 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
 923         RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
 924         RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
 925         RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
 926         RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
 927         RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
 928         RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
 929         RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
 930         RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
 931         RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
 932         RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
 933         RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
 934         RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
 935         RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
 936         RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
 937         RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
 938         RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
 939         RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
 940         RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
 941         RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
 942         RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
 943         RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
 944         RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
 945         RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
 946         RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
 947         RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
 948         RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
 949         RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
 950         RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
 951         RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
 952         RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
 953         RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
 954         RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
 955         RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
 956         RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
 957         RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
 958         RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
 959         RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
 960         RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
 961         RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
 962         RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
 963         RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
 964         RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
 965         RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
 966         RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
 967         RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
 968         RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
 969         RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
 970         RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
 971         RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
 972         RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
 973         RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
 974         RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
 975         RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
 976         RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
 977         RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
 978         RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
 979         RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
 980         RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
 981         RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
 982         RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
 983         RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
 984         RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
 985         RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
 986         RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
 987         RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
 988         RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
 989         RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
 990         RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
 991         RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
 992         RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
 993         RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
 994         RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
 995         RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
 996         RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
 997         RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
 998         RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
 999         RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1000         RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1001         RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1002         RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1003         RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1004         RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1005         RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1006         RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1007         RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1008         RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1009         RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1010         RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1011         RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1012         RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1013         RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1014         RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1015         RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1016 };
1017
1018 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1019                                    int mux, u32 *loc, u32 *reg, u32 *value)
1020 {
1021         struct rockchip_pinctrl *info = bank->drvdata;
1022         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1023         struct rockchip_mux_route_data *data;
1024         int i;
1025
1026         for (i = 0; i < ctrl->niomux_routes; i++) {
1027                 data = &ctrl->iomux_routes[i];
1028                 if ((data->bank_num == bank->bank_num) &&
1029                     (data->pin == pin) && (data->func == mux))
1030                         break;
1031         }
1032
1033         if (i >= ctrl->niomux_routes)
1034                 return false;
1035
1036         *loc = data->route_location;
1037         *reg = data->route_offset;
1038         *value = data->route_val;
1039
1040         return true;
1041 }
1042
1043 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1044 {
1045         struct rockchip_pinctrl *info = bank->drvdata;
1046         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1047         int iomux_num = (pin / 8);
1048         struct regmap *regmap;
1049         unsigned int val;
1050         int reg, ret, mask, mux_type;
1051         u8 bit;
1052
1053         if (iomux_num > 3)
1054                 return -EINVAL;
1055
1056         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1057                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1058                 return -EINVAL;
1059         }
1060
1061         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1062                 return RK_FUNC_GPIO;
1063
1064         if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1065                 regmap = info->regmap_pmu;
1066         else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1067                 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1068         else
1069                 regmap = info->regmap_base;
1070
1071         /* get basic quadrupel of mux registers and the correct reg inside */
1072         mux_type = bank->iomux[iomux_num].type;
1073         reg = bank->iomux[iomux_num].offset;
1074         if (mux_type & IOMUX_WIDTH_4BIT) {
1075                 if ((pin % 8) >= 4)
1076                         reg += 0x4;
1077                 bit = (pin % 4) * 4;
1078                 mask = 0xf;
1079         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1080                 if ((pin % 8) >= 5)
1081                         reg += 0x4;
1082                 bit = (pin % 8 % 5) * 3;
1083                 mask = 0x7;
1084         } else {
1085                 bit = (pin % 8) * 2;
1086                 mask = 0x3;
1087         }
1088
1089         if (bank->recalced_mask & BIT(pin))
1090                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1091
1092         if (ctrl->type == RK3588) {
1093                 if (bank->bank_num == 0) {
1094                         if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1095                                 u32 reg0 = 0;
1096
1097                                 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1098                                 ret = regmap_read(regmap, reg0, &val);
1099                                 if (ret)
1100                                         return ret;
1101
1102                                 if (!(val & BIT(8)))
1103                                         return ((val >> bit) & mask);
1104
1105                                 reg = reg + 0x8000; /* BUS_IOC_BASE */
1106                                 regmap = info->regmap_base;
1107                         }
1108                 } else if (bank->bank_num > 0) {
1109                         reg += 0x8000; /* BUS_IOC_BASE */
1110                 }
1111         }
1112
1113         ret = regmap_read(regmap, reg, &val);
1114         if (ret)
1115                 return ret;
1116
1117         return ((val >> bit) & mask);
1118 }
1119
1120 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1121                                int pin, int mux)
1122 {
1123         struct rockchip_pinctrl *info = bank->drvdata;
1124         struct device *dev = info->dev;
1125         int iomux_num = (pin / 8);
1126
1127         if (iomux_num > 3)
1128                 return -EINVAL;
1129
1130         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1131                 dev_err(dev, "pin %d is unrouted\n", pin);
1132                 return -EINVAL;
1133         }
1134
1135         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1136                 if (mux != RK_FUNC_GPIO) {
1137                         dev_err(dev, "pin %d only supports a gpio mux\n", pin);
1138                         return -ENOTSUPP;
1139                 }
1140         }
1141
1142         return 0;
1143 }
1144
1145 /*
1146  * Set a new mux function for a pin.
1147  *
1148  * The register is divided into the upper and lower 16 bit. When changing
1149  * a value, the previous register value is not read and changed. Instead
1150  * it seems the changed bits are marked in the upper 16 bit, while the
1151  * changed value gets set in the same offset in the lower 16 bit.
1152  * All pin settings seem to be 2 bit wide in both the upper and lower
1153  * parts.
1154  * @bank: pin bank to change
1155  * @pin: pin to change
1156  * @mux: new mux function to set
1157  */
1158 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1159 {
1160         struct rockchip_pinctrl *info = bank->drvdata;
1161         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1162         struct device *dev = info->dev;
1163         int iomux_num = (pin / 8);
1164         struct regmap *regmap;
1165         int reg, ret, mask, mux_type;
1166         u8 bit;
1167         u32 data, rmask, route_location, route_reg, route_val;
1168
1169         ret = rockchip_verify_mux(bank, pin, mux);
1170         if (ret < 0)
1171                 return ret;
1172
1173         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1174                 return 0;
1175
1176         dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1177
1178         if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1179                 regmap = info->regmap_pmu;
1180         else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1181                 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1182         else
1183                 regmap = info->regmap_base;
1184
1185         /* get basic quadrupel of mux registers and the correct reg inside */
1186         mux_type = bank->iomux[iomux_num].type;
1187         reg = bank->iomux[iomux_num].offset;
1188         if (mux_type & IOMUX_WIDTH_4BIT) {
1189                 if ((pin % 8) >= 4)
1190                         reg += 0x4;
1191                 bit = (pin % 4) * 4;
1192                 mask = 0xf;
1193         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1194                 if ((pin % 8) >= 5)
1195                         reg += 0x4;
1196                 bit = (pin % 8 % 5) * 3;
1197                 mask = 0x7;
1198         } else {
1199                 bit = (pin % 8) * 2;
1200                 mask = 0x3;
1201         }
1202
1203         if (bank->recalced_mask & BIT(pin))
1204                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1205
1206         if (ctrl->type == RK3588) {
1207                 if (bank->bank_num == 0) {
1208                         if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1209                                 if (mux < 8) {
1210                                         reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
1211                                         data = (mask << (bit + 16));
1212                                         rmask = data | (data >> 16);
1213                                         data |= (mux & mask) << bit;
1214                                         ret = regmap_update_bits(regmap, reg, rmask, data);
1215                                 } else {
1216                                         u32 reg0 = 0;
1217
1218                                         reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1219                                         data = (mask << (bit + 16));
1220                                         rmask = data | (data >> 16);
1221                                         data |= 8 << bit;
1222                                         ret = regmap_update_bits(regmap, reg0, rmask, data);
1223
1224                                         reg0 = reg + 0x8000; /* BUS_IOC_BASE */
1225                                         data = (mask << (bit + 16));
1226                                         rmask = data | (data >> 16);
1227                                         data |= mux << bit;
1228                                         regmap = info->regmap_base;
1229                                         ret |= regmap_update_bits(regmap, reg0, rmask, data);
1230                                 }
1231                         } else {
1232                                 data = (mask << (bit + 16));
1233                                 rmask = data | (data >> 16);
1234                                 data |= (mux & mask) << bit;
1235                                 ret = regmap_update_bits(regmap, reg, rmask, data);
1236                         }
1237                         return ret;
1238                 } else if (bank->bank_num > 0) {
1239                         reg += 0x8000; /* BUS_IOC_BASE */
1240                 }
1241         }
1242
1243         if (mux > mask)
1244                 return -EINVAL;
1245
1246         if (bank->route_mask & BIT(pin)) {
1247                 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1248                                            &route_reg, &route_val)) {
1249                         struct regmap *route_regmap = regmap;
1250
1251                         /* handle special locations */
1252                         switch (route_location) {
1253                         case ROCKCHIP_ROUTE_PMU:
1254                                 route_regmap = info->regmap_pmu;
1255                                 break;
1256                         case ROCKCHIP_ROUTE_GRF:
1257                                 route_regmap = info->regmap_base;
1258                                 break;
1259                         }
1260
1261                         ret = regmap_write(route_regmap, route_reg, route_val);
1262                         if (ret)
1263                                 return ret;
1264                 }
1265         }
1266
1267         data = (mask << (bit + 16));
1268         rmask = data | (data >> 16);
1269         data |= (mux & mask) << bit;
1270         ret = regmap_update_bits(regmap, reg, rmask, data);
1271
1272         return ret;
1273 }
1274
1275 #define PX30_PULL_PMU_OFFSET            0x10
1276 #define PX30_PULL_GRF_OFFSET            0x60
1277 #define PX30_PULL_BITS_PER_PIN          2
1278 #define PX30_PULL_PINS_PER_REG          8
1279 #define PX30_PULL_BANK_STRIDE           16
1280
1281 static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1282                                       int pin_num, struct regmap **regmap,
1283                                       int *reg, u8 *bit)
1284 {
1285         struct rockchip_pinctrl *info = bank->drvdata;
1286
1287         /* The first 32 pins of the first bank are located in PMU */
1288         if (bank->bank_num == 0) {
1289                 *regmap = info->regmap_pmu;
1290                 *reg = PX30_PULL_PMU_OFFSET;
1291         } else {
1292                 *regmap = info->regmap_base;
1293                 *reg = PX30_PULL_GRF_OFFSET;
1294
1295                 /* correct the offset, as we're starting with the 2nd bank */
1296                 *reg -= 0x10;
1297                 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1298         }
1299
1300         *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1301         *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1302         *bit *= PX30_PULL_BITS_PER_PIN;
1303
1304         return 0;
1305 }
1306
1307 #define PX30_DRV_PMU_OFFSET             0x20
1308 #define PX30_DRV_GRF_OFFSET             0xf0
1309 #define PX30_DRV_BITS_PER_PIN           2
1310 #define PX30_DRV_PINS_PER_REG           8
1311 #define PX30_DRV_BANK_STRIDE            16
1312
1313 static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1314                                      int pin_num, struct regmap **regmap,
1315                                      int *reg, u8 *bit)
1316 {
1317         struct rockchip_pinctrl *info = bank->drvdata;
1318
1319         /* The first 32 pins of the first bank are located in PMU */
1320         if (bank->bank_num == 0) {
1321                 *regmap = info->regmap_pmu;
1322                 *reg = PX30_DRV_PMU_OFFSET;
1323         } else {
1324                 *regmap = info->regmap_base;
1325                 *reg = PX30_DRV_GRF_OFFSET;
1326
1327                 /* correct the offset, as we're starting with the 2nd bank */
1328                 *reg -= 0x10;
1329                 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1330         }
1331
1332         *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1333         *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1334         *bit *= PX30_DRV_BITS_PER_PIN;
1335
1336         return 0;
1337 }
1338
1339 #define PX30_SCHMITT_PMU_OFFSET                 0x38
1340 #define PX30_SCHMITT_GRF_OFFSET                 0xc0
1341 #define PX30_SCHMITT_PINS_PER_PMU_REG           16
1342 #define PX30_SCHMITT_BANK_STRIDE                16
1343 #define PX30_SCHMITT_PINS_PER_GRF_REG           8
1344
1345 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1346                                          int pin_num,
1347                                          struct regmap **regmap,
1348                                          int *reg, u8 *bit)
1349 {
1350         struct rockchip_pinctrl *info = bank->drvdata;
1351         int pins_per_reg;
1352
1353         if (bank->bank_num == 0) {
1354                 *regmap = info->regmap_pmu;
1355                 *reg = PX30_SCHMITT_PMU_OFFSET;
1356                 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1357         } else {
1358                 *regmap = info->regmap_base;
1359                 *reg = PX30_SCHMITT_GRF_OFFSET;
1360                 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1361                 *reg += (bank->bank_num  - 1) * PX30_SCHMITT_BANK_STRIDE;
1362         }
1363
1364         *reg += ((pin_num / pins_per_reg) * 4);
1365         *bit = pin_num % pins_per_reg;
1366
1367         return 0;
1368 }
1369
1370 #define RV1108_PULL_PMU_OFFSET          0x10
1371 #define RV1108_PULL_OFFSET              0x110
1372 #define RV1108_PULL_PINS_PER_REG        8
1373 #define RV1108_PULL_BITS_PER_PIN        2
1374 #define RV1108_PULL_BANK_STRIDE         16
1375
1376 static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1377                                         int pin_num, struct regmap **regmap,
1378                                         int *reg, u8 *bit)
1379 {
1380         struct rockchip_pinctrl *info = bank->drvdata;
1381
1382         /* The first 24 pins of the first bank are located in PMU */
1383         if (bank->bank_num == 0) {
1384                 *regmap = info->regmap_pmu;
1385                 *reg = RV1108_PULL_PMU_OFFSET;
1386         } else {
1387                 *reg = RV1108_PULL_OFFSET;
1388                 *regmap = info->regmap_base;
1389                 /* correct the offset, as we're starting with the 2nd bank */
1390                 *reg -= 0x10;
1391                 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1392         }
1393
1394         *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1395         *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1396         *bit *= RV1108_PULL_BITS_PER_PIN;
1397
1398         return 0;
1399 }
1400
1401 #define RV1108_DRV_PMU_OFFSET           0x20
1402 #define RV1108_DRV_GRF_OFFSET           0x210
1403 #define RV1108_DRV_BITS_PER_PIN         2
1404 #define RV1108_DRV_PINS_PER_REG         8
1405 #define RV1108_DRV_BANK_STRIDE          16
1406
1407 static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1408                                        int pin_num, struct regmap **regmap,
1409                                        int *reg, u8 *bit)
1410 {
1411         struct rockchip_pinctrl *info = bank->drvdata;
1412
1413         /* The first 24 pins of the first bank are located in PMU */
1414         if (bank->bank_num == 0) {
1415                 *regmap = info->regmap_pmu;
1416                 *reg = RV1108_DRV_PMU_OFFSET;
1417         } else {
1418                 *regmap = info->regmap_base;
1419                 *reg = RV1108_DRV_GRF_OFFSET;
1420
1421                 /* correct the offset, as we're starting with the 2nd bank */
1422                 *reg -= 0x10;
1423                 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1424         }
1425
1426         *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1427         *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1428         *bit *= RV1108_DRV_BITS_PER_PIN;
1429
1430         return 0;
1431 }
1432
1433 #define RV1108_SCHMITT_PMU_OFFSET               0x30
1434 #define RV1108_SCHMITT_GRF_OFFSET               0x388
1435 #define RV1108_SCHMITT_BANK_STRIDE              8
1436 #define RV1108_SCHMITT_PINS_PER_GRF_REG         16
1437 #define RV1108_SCHMITT_PINS_PER_PMU_REG         8
1438
1439 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1440                                            int pin_num,
1441                                            struct regmap **regmap,
1442                                            int *reg, u8 *bit)
1443 {
1444         struct rockchip_pinctrl *info = bank->drvdata;
1445         int pins_per_reg;
1446
1447         if (bank->bank_num == 0) {
1448                 *regmap = info->regmap_pmu;
1449                 *reg = RV1108_SCHMITT_PMU_OFFSET;
1450                 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1451         } else {
1452                 *regmap = info->regmap_base;
1453                 *reg = RV1108_SCHMITT_GRF_OFFSET;
1454                 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1455                 *reg += (bank->bank_num  - 1) * RV1108_SCHMITT_BANK_STRIDE;
1456         }
1457         *reg += ((pin_num / pins_per_reg) * 4);
1458         *bit = pin_num % pins_per_reg;
1459
1460         return 0;
1461 }
1462
1463 #define RV1126_PULL_PMU_OFFSET          0x40
1464 #define RV1126_PULL_GRF_GPIO1A0_OFFSET  0x10108
1465 #define RV1126_PULL_PINS_PER_REG        8
1466 #define RV1126_PULL_BITS_PER_PIN        2
1467 #define RV1126_PULL_BANK_STRIDE         16
1468 #define RV1126_GPIO_C4_D7(p)            (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
1469
1470 static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1471                                         int pin_num, struct regmap **regmap,
1472                                         int *reg, u8 *bit)
1473 {
1474         struct rockchip_pinctrl *info = bank->drvdata;
1475
1476         /* The first 24 pins of the first bank are located in PMU */
1477         if (bank->bank_num == 0) {
1478                 if (RV1126_GPIO_C4_D7(pin_num)) {
1479                         *regmap = info->regmap_base;
1480                         *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1481                         *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
1482                         *bit = pin_num % RV1126_PULL_PINS_PER_REG;
1483                         *bit *= RV1126_PULL_BITS_PER_PIN;
1484                         return 0;
1485                 }
1486                 *regmap = info->regmap_pmu;
1487                 *reg = RV1126_PULL_PMU_OFFSET;
1488         } else {
1489                 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1490                 *regmap = info->regmap_base;
1491                 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
1492         }
1493
1494         *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
1495         *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
1496         *bit *= RV1126_PULL_BITS_PER_PIN;
1497
1498         return 0;
1499 }
1500
1501 #define RV1126_DRV_PMU_OFFSET           0x20
1502 #define RV1126_DRV_GRF_GPIO1A0_OFFSET   0x10090
1503 #define RV1126_DRV_BITS_PER_PIN         4
1504 #define RV1126_DRV_PINS_PER_REG         4
1505 #define RV1126_DRV_BANK_STRIDE          32
1506
1507 static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1508                                        int pin_num, struct regmap **regmap,
1509                                        int *reg, u8 *bit)
1510 {
1511         struct rockchip_pinctrl *info = bank->drvdata;
1512
1513         /* The first 24 pins of the first bank are located in PMU */
1514         if (bank->bank_num == 0) {
1515                 if (RV1126_GPIO_C4_D7(pin_num)) {
1516                         *regmap = info->regmap_base;
1517                         *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1518                         *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
1519                         *reg -= 0x4;
1520                         *bit = pin_num % RV1126_DRV_PINS_PER_REG;
1521                         *bit *= RV1126_DRV_BITS_PER_PIN;
1522                         return 0;
1523                 }
1524                 *regmap = info->regmap_pmu;
1525                 *reg = RV1126_DRV_PMU_OFFSET;
1526         } else {
1527                 *regmap = info->regmap_base;
1528                 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1529                 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
1530         }
1531
1532         *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
1533         *bit = pin_num % RV1126_DRV_PINS_PER_REG;
1534         *bit *= RV1126_DRV_BITS_PER_PIN;
1535
1536         return 0;
1537 }
1538
1539 #define RV1126_SCHMITT_PMU_OFFSET               0x60
1540 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET       0x10188
1541 #define RV1126_SCHMITT_BANK_STRIDE              16
1542 #define RV1126_SCHMITT_PINS_PER_GRF_REG         8
1543 #define RV1126_SCHMITT_PINS_PER_PMU_REG         8
1544
1545 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1546                                            int pin_num,
1547                                            struct regmap **regmap,
1548                                            int *reg, u8 *bit)
1549 {
1550         struct rockchip_pinctrl *info = bank->drvdata;
1551         int pins_per_reg;
1552
1553         if (bank->bank_num == 0) {
1554                 if (RV1126_GPIO_C4_D7(pin_num)) {
1555                         *regmap = info->regmap_base;
1556                         *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1557                         *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
1558                         *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
1559                         return 0;
1560                 }
1561                 *regmap = info->regmap_pmu;
1562                 *reg = RV1126_SCHMITT_PMU_OFFSET;
1563                 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
1564         } else {
1565                 *regmap = info->regmap_base;
1566                 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1567                 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
1568                 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
1569         }
1570         *reg += ((pin_num / pins_per_reg) * 4);
1571         *bit = pin_num % pins_per_reg;
1572
1573         return 0;
1574 }
1575
1576 #define RK3308_SCHMITT_PINS_PER_REG             8
1577 #define RK3308_SCHMITT_BANK_STRIDE              16
1578 #define RK3308_SCHMITT_GRF_OFFSET               0x1a0
1579
1580 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1581                                     int pin_num, struct regmap **regmap,
1582                                     int *reg, u8 *bit)
1583 {
1584         struct rockchip_pinctrl *info = bank->drvdata;
1585
1586         *regmap = info->regmap_base;
1587         *reg = RK3308_SCHMITT_GRF_OFFSET;
1588
1589         *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1590         *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1591         *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1592
1593         return 0;
1594 }
1595
1596 #define RK2928_PULL_OFFSET              0x118
1597 #define RK2928_PULL_PINS_PER_REG        16
1598 #define RK2928_PULL_BANK_STRIDE         8
1599
1600 static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1601                                         int pin_num, struct regmap **regmap,
1602                                         int *reg, u8 *bit)
1603 {
1604         struct rockchip_pinctrl *info = bank->drvdata;
1605
1606         *regmap = info->regmap_base;
1607         *reg = RK2928_PULL_OFFSET;
1608         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1609         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1610
1611         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1612
1613         return 0;
1614 };
1615
1616 #define RK3128_PULL_OFFSET      0x118
1617
1618 static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1619                                         int pin_num, struct regmap **regmap,
1620                                         int *reg, u8 *bit)
1621 {
1622         struct rockchip_pinctrl *info = bank->drvdata;
1623
1624         *regmap = info->regmap_base;
1625         *reg = RK3128_PULL_OFFSET;
1626         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1627         *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1628
1629         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1630
1631         return 0;
1632 }
1633
1634 #define RK3188_PULL_OFFSET              0x164
1635 #define RK3188_PULL_BITS_PER_PIN        2
1636 #define RK3188_PULL_PINS_PER_REG        8
1637 #define RK3188_PULL_BANK_STRIDE         16
1638 #define RK3188_PULL_PMU_OFFSET          0x64
1639
1640 static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1641                                         int pin_num, struct regmap **regmap,
1642                                         int *reg, u8 *bit)
1643 {
1644         struct rockchip_pinctrl *info = bank->drvdata;
1645
1646         /* The first 12 pins of the first bank are located elsewhere */
1647         if (bank->bank_num == 0 && pin_num < 12) {
1648                 *regmap = info->regmap_pmu ? info->regmap_pmu
1649                                            : bank->regmap_pull;
1650                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1651                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1652                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1653                 *bit *= RK3188_PULL_BITS_PER_PIN;
1654         } else {
1655                 *regmap = info->regmap_pull ? info->regmap_pull
1656                                             : info->regmap_base;
1657                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1658
1659                 /* correct the offset, as it is the 2nd pull register */
1660                 *reg -= 4;
1661                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1662                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1663
1664                 /*
1665                  * The bits in these registers have an inverse ordering
1666                  * with the lowest pin being in bits 15:14 and the highest
1667                  * pin in bits 1:0
1668                  */
1669                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1670                 *bit *= RK3188_PULL_BITS_PER_PIN;
1671         }
1672
1673         return 0;
1674 }
1675
1676 #define RK3288_PULL_OFFSET              0x140
1677 static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1678                                         int pin_num, struct regmap **regmap,
1679                                         int *reg, u8 *bit)
1680 {
1681         struct rockchip_pinctrl *info = bank->drvdata;
1682
1683         /* The first 24 pins of the first bank are located in PMU */
1684         if (bank->bank_num == 0) {
1685                 *regmap = info->regmap_pmu;
1686                 *reg = RK3188_PULL_PMU_OFFSET;
1687
1688                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1689                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1690                 *bit *= RK3188_PULL_BITS_PER_PIN;
1691         } else {
1692                 *regmap = info->regmap_base;
1693                 *reg = RK3288_PULL_OFFSET;
1694
1695                 /* correct the offset, as we're starting with the 2nd bank */
1696                 *reg -= 0x10;
1697                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1698                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1699
1700                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1701                 *bit *= RK3188_PULL_BITS_PER_PIN;
1702         }
1703
1704         return 0;
1705 }
1706
1707 #define RK3288_DRV_PMU_OFFSET           0x70
1708 #define RK3288_DRV_GRF_OFFSET           0x1c0
1709 #define RK3288_DRV_BITS_PER_PIN         2
1710 #define RK3288_DRV_PINS_PER_REG         8
1711 #define RK3288_DRV_BANK_STRIDE          16
1712
1713 static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1714                                        int pin_num, struct regmap **regmap,
1715                                        int *reg, u8 *bit)
1716 {
1717         struct rockchip_pinctrl *info = bank->drvdata;
1718
1719         /* The first 24 pins of the first bank are located in PMU */
1720         if (bank->bank_num == 0) {
1721                 *regmap = info->regmap_pmu;
1722                 *reg = RK3288_DRV_PMU_OFFSET;
1723
1724                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1725                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1726                 *bit *= RK3288_DRV_BITS_PER_PIN;
1727         } else {
1728                 *regmap = info->regmap_base;
1729                 *reg = RK3288_DRV_GRF_OFFSET;
1730
1731                 /* correct the offset, as we're starting with the 2nd bank */
1732                 *reg -= 0x10;
1733                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1734                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1735
1736                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1737                 *bit *= RK3288_DRV_BITS_PER_PIN;
1738         }
1739
1740         return 0;
1741 }
1742
1743 #define RK3228_PULL_OFFSET              0x100
1744
1745 static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1746                                         int pin_num, struct regmap **regmap,
1747                                         int *reg, u8 *bit)
1748 {
1749         struct rockchip_pinctrl *info = bank->drvdata;
1750
1751         *regmap = info->regmap_base;
1752         *reg = RK3228_PULL_OFFSET;
1753         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1754         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1755
1756         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1757         *bit *= RK3188_PULL_BITS_PER_PIN;
1758
1759         return 0;
1760 }
1761
1762 #define RK3228_DRV_GRF_OFFSET           0x200
1763
1764 static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1765                                        int pin_num, struct regmap **regmap,
1766                                        int *reg, u8 *bit)
1767 {
1768         struct rockchip_pinctrl *info = bank->drvdata;
1769
1770         *regmap = info->regmap_base;
1771         *reg = RK3228_DRV_GRF_OFFSET;
1772         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1773         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1774
1775         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1776         *bit *= RK3288_DRV_BITS_PER_PIN;
1777
1778         return 0;
1779 }
1780
1781 #define RK3308_PULL_OFFSET              0xa0
1782
1783 static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1784                                         int pin_num, struct regmap **regmap,
1785                                         int *reg, u8 *bit)
1786 {
1787         struct rockchip_pinctrl *info = bank->drvdata;
1788
1789         *regmap = info->regmap_base;
1790         *reg = RK3308_PULL_OFFSET;
1791         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1792         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1793
1794         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1795         *bit *= RK3188_PULL_BITS_PER_PIN;
1796
1797         return 0;
1798 }
1799
1800 #define RK3308_DRV_GRF_OFFSET           0x100
1801
1802 static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1803                                        int pin_num, struct regmap **regmap,
1804                                        int *reg, u8 *bit)
1805 {
1806         struct rockchip_pinctrl *info = bank->drvdata;
1807
1808         *regmap = info->regmap_base;
1809         *reg = RK3308_DRV_GRF_OFFSET;
1810         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1811         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1812
1813         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1814         *bit *= RK3288_DRV_BITS_PER_PIN;
1815
1816         return 0;
1817 }
1818
1819 #define RK3368_PULL_GRF_OFFSET          0x100
1820 #define RK3368_PULL_PMU_OFFSET          0x10
1821
1822 static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1823                                         int pin_num, struct regmap **regmap,
1824                                         int *reg, u8 *bit)
1825 {
1826         struct rockchip_pinctrl *info = bank->drvdata;
1827
1828         /* The first 32 pins of the first bank are located in PMU */
1829         if (bank->bank_num == 0) {
1830                 *regmap = info->regmap_pmu;
1831                 *reg = RK3368_PULL_PMU_OFFSET;
1832
1833                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1834                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1835                 *bit *= RK3188_PULL_BITS_PER_PIN;
1836         } else {
1837                 *regmap = info->regmap_base;
1838                 *reg = RK3368_PULL_GRF_OFFSET;
1839
1840                 /* correct the offset, as we're starting with the 2nd bank */
1841                 *reg -= 0x10;
1842                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1843                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1844
1845                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1846                 *bit *= RK3188_PULL_BITS_PER_PIN;
1847         }
1848
1849         return 0;
1850 }
1851
1852 #define RK3368_DRV_PMU_OFFSET           0x20
1853 #define RK3368_DRV_GRF_OFFSET           0x200
1854
1855 static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1856                                        int pin_num, struct regmap **regmap,
1857                                        int *reg, u8 *bit)
1858 {
1859         struct rockchip_pinctrl *info = bank->drvdata;
1860
1861         /* The first 32 pins of the first bank are located in PMU */
1862         if (bank->bank_num == 0) {
1863                 *regmap = info->regmap_pmu;
1864                 *reg = RK3368_DRV_PMU_OFFSET;
1865
1866                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1867                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1868                 *bit *= RK3288_DRV_BITS_PER_PIN;
1869         } else {
1870                 *regmap = info->regmap_base;
1871                 *reg = RK3368_DRV_GRF_OFFSET;
1872
1873                 /* correct the offset, as we're starting with the 2nd bank */
1874                 *reg -= 0x10;
1875                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1876                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1877
1878                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1879                 *bit *= RK3288_DRV_BITS_PER_PIN;
1880         }
1881
1882         return 0;
1883 }
1884
1885 #define RK3399_PULL_GRF_OFFSET          0xe040
1886 #define RK3399_PULL_PMU_OFFSET          0x40
1887 #define RK3399_DRV_3BITS_PER_PIN        3
1888
1889 static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1890                                         int pin_num, struct regmap **regmap,
1891                                         int *reg, u8 *bit)
1892 {
1893         struct rockchip_pinctrl *info = bank->drvdata;
1894
1895         /* The bank0:16 and bank1:32 pins are located in PMU */
1896         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1897                 *regmap = info->regmap_pmu;
1898                 *reg = RK3399_PULL_PMU_OFFSET;
1899
1900                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1901
1902                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1903                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1904                 *bit *= RK3188_PULL_BITS_PER_PIN;
1905         } else {
1906                 *regmap = info->regmap_base;
1907                 *reg = RK3399_PULL_GRF_OFFSET;
1908
1909                 /* correct the offset, as we're starting with the 3rd bank */
1910                 *reg -= 0x20;
1911                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1912                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1913
1914                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1915                 *bit *= RK3188_PULL_BITS_PER_PIN;
1916         }
1917
1918         return 0;
1919 }
1920
1921 static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1922                                        int pin_num, struct regmap **regmap,
1923                                        int *reg, u8 *bit)
1924 {
1925         struct rockchip_pinctrl *info = bank->drvdata;
1926         int drv_num = (pin_num / 8);
1927
1928         /*  The bank0:16 and bank1:32 pins are located in PMU */
1929         if ((bank->bank_num == 0) || (bank->bank_num == 1))
1930                 *regmap = info->regmap_pmu;
1931         else
1932                 *regmap = info->regmap_base;
1933
1934         *reg = bank->drv[drv_num].offset;
1935         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1936             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1937                 *bit = (pin_num % 8) * 3;
1938         else
1939                 *bit = (pin_num % 8) * 2;
1940
1941         return 0;
1942 }
1943
1944 #define RK3568_PULL_PMU_OFFSET          0x20
1945 #define RK3568_PULL_GRF_OFFSET          0x80
1946 #define RK3568_PULL_BITS_PER_PIN        2
1947 #define RK3568_PULL_PINS_PER_REG        8
1948 #define RK3568_PULL_BANK_STRIDE         0x10
1949
1950 static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1951                                         int pin_num, struct regmap **regmap,
1952                                         int *reg, u8 *bit)
1953 {
1954         struct rockchip_pinctrl *info = bank->drvdata;
1955
1956         if (bank->bank_num == 0) {
1957                 *regmap = info->regmap_pmu;
1958                 *reg = RK3568_PULL_PMU_OFFSET;
1959                 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
1960                 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1961
1962                 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
1963                 *bit *= RK3568_PULL_BITS_PER_PIN;
1964         } else {
1965                 *regmap = info->regmap_base;
1966                 *reg = RK3568_PULL_GRF_OFFSET;
1967                 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
1968                 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1969
1970                 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
1971                 *bit *= RK3568_PULL_BITS_PER_PIN;
1972         }
1973
1974         return 0;
1975 }
1976
1977 #define RK3568_DRV_PMU_OFFSET           0x70
1978 #define RK3568_DRV_GRF_OFFSET           0x200
1979 #define RK3568_DRV_BITS_PER_PIN         8
1980 #define RK3568_DRV_PINS_PER_REG         2
1981 #define RK3568_DRV_BANK_STRIDE          0x40
1982
1983 static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1984                                        int pin_num, struct regmap **regmap,
1985                                        int *reg, u8 *bit)
1986 {
1987         struct rockchip_pinctrl *info = bank->drvdata;
1988
1989         /* The first 32 pins of the first bank are located in PMU */
1990         if (bank->bank_num == 0) {
1991                 *regmap = info->regmap_pmu;
1992                 *reg = RK3568_DRV_PMU_OFFSET;
1993                 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1994
1995                 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
1996                 *bit *= RK3568_DRV_BITS_PER_PIN;
1997         } else {
1998                 *regmap = info->regmap_base;
1999                 *reg = RK3568_DRV_GRF_OFFSET;
2000                 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
2001                 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2002
2003                 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
2004                 *bit *= RK3568_DRV_BITS_PER_PIN;
2005         }
2006
2007         return 0;
2008 }
2009
2010 #define RK3588_PMU1_IOC_REG             (0x0000)
2011 #define RK3588_PMU2_IOC_REG             (0x4000)
2012 #define RK3588_BUS_IOC_REG              (0x8000)
2013 #define RK3588_VCCIO1_4_IOC_REG         (0x9000)
2014 #define RK3588_VCCIO3_5_IOC_REG         (0xA000)
2015 #define RK3588_VCCIO2_IOC_REG           (0xB000)
2016 #define RK3588_VCCIO6_IOC_REG           (0xC000)
2017 #define RK3588_EMMC_IOC_REG             (0xD000)
2018
2019 static const u32 rk3588_ds_regs[][2] = {
2020         {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
2021         {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
2022         {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
2023         {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
2024         {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
2025         {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
2026         {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
2027         {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
2028         {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
2029         {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
2030         {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
2031         {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
2032         {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
2033         {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
2034         {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
2035         {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
2036         {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
2037         {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
2038         {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
2039         {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
2040         {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
2041         {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
2042         {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
2043         {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
2044         {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
2045         {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
2046         {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
2047         {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
2048         {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
2049         {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
2050         {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
2051         {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
2052         {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
2053         {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
2054         {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
2055         {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
2056         {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
2057         {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
2058         {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
2059         {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
2060         {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C},
2061 };
2062
2063 static const u32 rk3588_p_regs[][2] = {
2064         {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
2065         {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
2066         {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
2067         {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
2068         {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
2069         {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
2070         {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
2071         {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
2072         {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
2073         {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
2074         {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120},
2075         {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
2076         {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
2077         {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
2078         {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
2079         {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
2080         {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
2081         {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
2082         {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
2083         {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
2084         {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
2085         {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
2086         {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
2087 };
2088
2089 static const u32 rk3588_smt_regs[][2] = {
2090         {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
2091         {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
2092         {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
2093         {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
2094         {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
2095         {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
2096         {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
2097         {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
2098         {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
2099         {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
2100         {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220},
2101         {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
2102         {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
2103         {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
2104         {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
2105         {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
2106         {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
2107         {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
2108         {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
2109         {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
2110         {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
2111         {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
2112         {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
2113 };
2114
2115 #define RK3588_PULL_BITS_PER_PIN                2
2116 #define RK3588_PULL_PINS_PER_REG                8
2117
2118 static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2119                                         int pin_num, struct regmap **regmap,
2120                                         int *reg, u8 *bit)
2121 {
2122         struct rockchip_pinctrl *info = bank->drvdata;
2123         u8 bank_num = bank->bank_num;
2124         u32 pin = bank_num * 32 + pin_num;
2125         int i;
2126
2127         for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
2128                 if (pin >= rk3588_p_regs[i][0]) {
2129                         *reg = rk3588_p_regs[i][1];
2130                         *regmap = info->regmap_base;
2131                         *bit = pin_num % RK3588_PULL_PINS_PER_REG;
2132                         *bit *= RK3588_PULL_BITS_PER_PIN;
2133                         return 0;
2134                 }
2135         }
2136
2137         return -EINVAL;
2138 }
2139
2140 #define RK3588_DRV_BITS_PER_PIN         4
2141 #define RK3588_DRV_PINS_PER_REG         4
2142
2143 static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2144                                        int pin_num, struct regmap **regmap,
2145                                        int *reg, u8 *bit)
2146 {
2147         struct rockchip_pinctrl *info = bank->drvdata;
2148         u8 bank_num = bank->bank_num;
2149         u32 pin = bank_num * 32 + pin_num;
2150         int i;
2151
2152         for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
2153                 if (pin >= rk3588_ds_regs[i][0]) {
2154                         *reg = rk3588_ds_regs[i][1];
2155                         *regmap = info->regmap_base;
2156                         *bit = pin_num % RK3588_DRV_PINS_PER_REG;
2157                         *bit *= RK3588_DRV_BITS_PER_PIN;
2158                         return 0;
2159                 }
2160         }
2161
2162         return -EINVAL;
2163 }
2164
2165 #define RK3588_SMT_BITS_PER_PIN         1
2166 #define RK3588_SMT_PINS_PER_REG         8
2167
2168 static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2169                                            int pin_num,
2170                                            struct regmap **regmap,
2171                                            int *reg, u8 *bit)
2172 {
2173         struct rockchip_pinctrl *info = bank->drvdata;
2174         u8 bank_num = bank->bank_num;
2175         u32 pin = bank_num * 32 + pin_num;
2176         int i;
2177
2178         for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
2179                 if (pin >= rk3588_smt_regs[i][0]) {
2180                         *reg = rk3588_smt_regs[i][1];
2181                         *regmap = info->regmap_base;
2182                         *bit = pin_num % RK3588_SMT_PINS_PER_REG;
2183                         *bit *= RK3588_SMT_BITS_PER_PIN;
2184                         return 0;
2185                 }
2186         }
2187
2188         return -EINVAL;
2189 }
2190
2191 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
2192         { 2, 4, 8, 12, -1, -1, -1, -1 },
2193         { 3, 6, 9, 12, -1, -1, -1, -1 },
2194         { 5, 10, 15, 20, -1, -1, -1, -1 },
2195         { 4, 6, 8, 10, 12, 14, 16, 18 },
2196         { 4, 7, 10, 13, 16, 19, 22, 26 }
2197 };
2198
2199 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
2200                                      int pin_num)
2201 {
2202         struct rockchip_pinctrl *info = bank->drvdata;
2203         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2204         struct device *dev = info->dev;
2205         struct regmap *regmap;
2206         int reg, ret;
2207         u32 data, temp, rmask_bits;
2208         u8 bit;
2209         int drv_type = bank->drv[pin_num / 8].drv_type;
2210
2211         ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2212         if (ret)
2213                 return ret;
2214
2215         switch (drv_type) {
2216         case DRV_TYPE_IO_1V8_3V0_AUTO:
2217         case DRV_TYPE_IO_3V3_ONLY:
2218                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2219                 switch (bit) {
2220                 case 0 ... 12:
2221                         /* regular case, nothing to do */
2222                         break;
2223                 case 15:
2224                         /*
2225                          * drive-strength offset is special, as it is
2226                          * spread over 2 registers
2227                          */
2228                         ret = regmap_read(regmap, reg, &data);
2229                         if (ret)
2230                                 return ret;
2231
2232                         ret = regmap_read(regmap, reg + 0x4, &temp);
2233                         if (ret)
2234                                 return ret;
2235
2236                         /*
2237                          * the bit data[15] contains bit 0 of the value
2238                          * while temp[1:0] contains bits 2 and 1
2239                          */
2240                         data >>= 15;
2241                         temp &= 0x3;
2242                         temp <<= 1;
2243                         data |= temp;
2244
2245                         return rockchip_perpin_drv_list[drv_type][data];
2246                 case 18 ... 21:
2247                         /* setting fully enclosed in the second register */
2248                         reg += 4;
2249                         bit -= 16;
2250                         break;
2251                 default:
2252                         dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2253                                 bit, drv_type);
2254                         return -EINVAL;
2255                 }
2256
2257                 break;
2258         case DRV_TYPE_IO_DEFAULT:
2259         case DRV_TYPE_IO_1V8_OR_3V0:
2260         case DRV_TYPE_IO_1V8_ONLY:
2261                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2262                 break;
2263         default:
2264                 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2265                 return -EINVAL;
2266         }
2267
2268         ret = regmap_read(regmap, reg, &data);
2269         if (ret)
2270                 return ret;
2271
2272         data >>= bit;
2273         data &= (1 << rmask_bits) - 1;
2274
2275         return rockchip_perpin_drv_list[drv_type][data];
2276 }
2277
2278 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
2279                                      int pin_num, int strength)
2280 {
2281         struct rockchip_pinctrl *info = bank->drvdata;
2282         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2283         struct device *dev = info->dev;
2284         struct regmap *regmap;
2285         int reg, ret, i;
2286         u32 data, rmask, rmask_bits, temp;
2287         u8 bit;
2288         int drv_type = bank->drv[pin_num / 8].drv_type;
2289
2290         dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
2291                 bank->bank_num, pin_num, strength);
2292
2293         ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2294         if (ret)
2295                 return ret;
2296         if (ctrl->type == RK3588) {
2297                 rmask_bits = RK3588_DRV_BITS_PER_PIN;
2298                 ret = strength;
2299                 goto config;
2300         } else if (ctrl->type == RK3568) {
2301                 rmask_bits = RK3568_DRV_BITS_PER_PIN;
2302                 ret = (1 << (strength + 1)) - 1;
2303                 goto config;
2304         }
2305
2306         if (ctrl->type == RV1126) {
2307                 rmask_bits = RV1126_DRV_BITS_PER_PIN;
2308                 ret = strength;
2309                 goto config;
2310         }
2311
2312         ret = -EINVAL;
2313         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
2314                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
2315                         ret = i;
2316                         break;
2317                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
2318                         ret = rockchip_perpin_drv_list[drv_type][i];
2319                         break;
2320                 }
2321         }
2322
2323         if (ret < 0) {
2324                 dev_err(dev, "unsupported driver strength %d\n", strength);
2325                 return ret;
2326         }
2327
2328         switch (drv_type) {
2329         case DRV_TYPE_IO_1V8_3V0_AUTO:
2330         case DRV_TYPE_IO_3V3_ONLY:
2331                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2332                 switch (bit) {
2333                 case 0 ... 12:
2334                         /* regular case, nothing to do */
2335                         break;
2336                 case 15:
2337                         /*
2338                          * drive-strength offset is special, as it is spread
2339                          * over 2 registers, the bit data[15] contains bit 0
2340                          * of the value while temp[1:0] contains bits 2 and 1
2341                          */
2342                         data = (ret & 0x1) << 15;
2343                         temp = (ret >> 0x1) & 0x3;
2344
2345                         rmask = BIT(15) | BIT(31);
2346                         data |= BIT(31);
2347                         ret = regmap_update_bits(regmap, reg, rmask, data);
2348                         if (ret)
2349                                 return ret;
2350
2351                         rmask = 0x3 | (0x3 << 16);
2352                         temp |= (0x3 << 16);
2353                         reg += 0x4;
2354                         ret = regmap_update_bits(regmap, reg, rmask, temp);
2355
2356                         return ret;
2357                 case 18 ... 21:
2358                         /* setting fully enclosed in the second register */
2359                         reg += 4;
2360                         bit -= 16;
2361                         break;
2362                 default:
2363                         dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2364                                 bit, drv_type);
2365                         return -EINVAL;
2366                 }
2367                 break;
2368         case DRV_TYPE_IO_DEFAULT:
2369         case DRV_TYPE_IO_1V8_OR_3V0:
2370         case DRV_TYPE_IO_1V8_ONLY:
2371                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2372                 break;
2373         default:
2374                 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2375                 return -EINVAL;
2376         }
2377
2378 config:
2379         /* enable the write to the equivalent lower bits */
2380         data = ((1 << rmask_bits) - 1) << (bit + 16);
2381         rmask = data | (data >> 16);
2382         data |= (ret << bit);
2383
2384         ret = regmap_update_bits(regmap, reg, rmask, data);
2385
2386         return ret;
2387 }
2388
2389 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
2390         {
2391                 PIN_CONFIG_BIAS_DISABLE,
2392                 PIN_CONFIG_BIAS_PULL_UP,
2393                 PIN_CONFIG_BIAS_PULL_DOWN,
2394                 PIN_CONFIG_BIAS_BUS_HOLD
2395         },
2396         {
2397                 PIN_CONFIG_BIAS_DISABLE,
2398                 PIN_CONFIG_BIAS_PULL_DOWN,
2399                 PIN_CONFIG_BIAS_DISABLE,
2400                 PIN_CONFIG_BIAS_PULL_UP
2401         },
2402 };
2403
2404 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
2405 {
2406         struct rockchip_pinctrl *info = bank->drvdata;
2407         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2408         struct device *dev = info->dev;
2409         struct regmap *regmap;
2410         int reg, ret, pull_type;
2411         u8 bit;
2412         u32 data;
2413
2414         /* rk3066b does support any pulls */
2415         if (ctrl->type == RK3066B)
2416                 return PIN_CONFIG_BIAS_DISABLE;
2417
2418         ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2419         if (ret)
2420                 return ret;
2421
2422         ret = regmap_read(regmap, reg, &data);
2423         if (ret)
2424                 return ret;
2425
2426         switch (ctrl->type) {
2427         case RK2928:
2428         case RK3128:
2429                 return !(data & BIT(bit))
2430                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
2431                                 : PIN_CONFIG_BIAS_DISABLE;
2432         case PX30:
2433         case RV1108:
2434         case RK3188:
2435         case RK3288:
2436         case RK3308:
2437         case RK3368:
2438         case RK3399:
2439         case RK3568:
2440         case RK3588:
2441                 pull_type = bank->pull_type[pin_num / 8];
2442                 data >>= bit;
2443                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2444                 /*
2445                  * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2446                  * where that pull up value becomes 3.
2447                  */
2448                 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2449                         if (data == 3)
2450                                 data = 1;
2451                 }
2452
2453                 return rockchip_pull_list[pull_type][data];
2454         default:
2455                 dev_err(dev, "unsupported pinctrl type\n");
2456                 return -EINVAL;
2457         };
2458 }
2459
2460 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2461                                         int pin_num, int pull)
2462 {
2463         struct rockchip_pinctrl *info = bank->drvdata;
2464         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2465         struct device *dev = info->dev;
2466         struct regmap *regmap;
2467         int reg, ret, i, pull_type;
2468         u8 bit;
2469         u32 data, rmask;
2470
2471         dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
2472
2473         /* rk3066b does support any pulls */
2474         if (ctrl->type == RK3066B)
2475                 return pull ? -EINVAL : 0;
2476
2477         ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2478         if (ret)
2479                 return ret;
2480
2481         switch (ctrl->type) {
2482         case RK2928:
2483         case RK3128:
2484                 data = BIT(bit + 16);
2485                 if (pull == PIN_CONFIG_BIAS_DISABLE)
2486                         data |= BIT(bit);
2487                 ret = regmap_write(regmap, reg, data);
2488                 break;
2489         case PX30:
2490         case RV1108:
2491         case RV1126:
2492         case RK3188:
2493         case RK3288:
2494         case RK3308:
2495         case RK3368:
2496         case RK3399:
2497         case RK3568:
2498         case RK3588:
2499                 pull_type = bank->pull_type[pin_num / 8];
2500                 ret = -EINVAL;
2501                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2502                         i++) {
2503                         if (rockchip_pull_list[pull_type][i] == pull) {
2504                                 ret = i;
2505                                 break;
2506                         }
2507                 }
2508                 /*
2509                  * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2510                  * where that pull up value becomes 3.
2511                  */
2512                 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2513                         if (ret == 1)
2514                                 ret = 3;
2515                 }
2516
2517                 if (ret < 0) {
2518                         dev_err(dev, "unsupported pull setting %d\n", pull);
2519                         return ret;
2520                 }
2521
2522                 /* enable the write to the equivalent lower bits */
2523                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2524                 rmask = data | (data >> 16);
2525                 data |= (ret << bit);
2526
2527                 ret = regmap_update_bits(regmap, reg, rmask, data);
2528                 break;
2529         default:
2530                 dev_err(dev, "unsupported pinctrl type\n");
2531                 return -EINVAL;
2532         }
2533
2534         return ret;
2535 }
2536
2537 #define RK3328_SCHMITT_BITS_PER_PIN             1
2538 #define RK3328_SCHMITT_PINS_PER_REG             16
2539 #define RK3328_SCHMITT_BANK_STRIDE              8
2540 #define RK3328_SCHMITT_GRF_OFFSET               0x380
2541
2542 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2543                                            int pin_num,
2544                                            struct regmap **regmap,
2545                                            int *reg, u8 *bit)
2546 {
2547         struct rockchip_pinctrl *info = bank->drvdata;
2548
2549         *regmap = info->regmap_base;
2550         *reg = RK3328_SCHMITT_GRF_OFFSET;
2551
2552         *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2553         *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2554         *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2555
2556         return 0;
2557 }
2558
2559 #define RK3568_SCHMITT_BITS_PER_PIN             2
2560 #define RK3568_SCHMITT_PINS_PER_REG             8
2561 #define RK3568_SCHMITT_BANK_STRIDE              0x10
2562 #define RK3568_SCHMITT_GRF_OFFSET               0xc0
2563 #define RK3568_SCHMITT_PMUGRF_OFFSET            0x30
2564
2565 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2566                                            int pin_num,
2567                                            struct regmap **regmap,
2568                                            int *reg, u8 *bit)
2569 {
2570         struct rockchip_pinctrl *info = bank->drvdata;
2571
2572         if (bank->bank_num == 0) {
2573                 *regmap = info->regmap_pmu;
2574                 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
2575         } else {
2576                 *regmap = info->regmap_base;
2577                 *reg = RK3568_SCHMITT_GRF_OFFSET;
2578                 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
2579         }
2580
2581         *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
2582         *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
2583         *bit *= RK3568_SCHMITT_BITS_PER_PIN;
2584
2585         return 0;
2586 }
2587
2588 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2589 {
2590         struct rockchip_pinctrl *info = bank->drvdata;
2591         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2592         struct regmap *regmap;
2593         int reg, ret;
2594         u8 bit;
2595         u32 data;
2596
2597         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2598         if (ret)
2599                 return ret;
2600
2601         ret = regmap_read(regmap, reg, &data);
2602         if (ret)
2603                 return ret;
2604
2605         data >>= bit;
2606         switch (ctrl->type) {
2607         case RK3568:
2608                 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
2609         default:
2610                 break;
2611         }
2612
2613         return data & 0x1;
2614 }
2615
2616 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2617                                 int pin_num, int enable)
2618 {
2619         struct rockchip_pinctrl *info = bank->drvdata;
2620         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2621         struct device *dev = info->dev;
2622         struct regmap *regmap;
2623         int reg, ret;
2624         u8 bit;
2625         u32 data, rmask;
2626
2627         dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
2628                 bank->bank_num, pin_num, enable);
2629
2630         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2631         if (ret)
2632                 return ret;
2633
2634         /* enable the write to the equivalent lower bits */
2635         switch (ctrl->type) {
2636         case RK3568:
2637                 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
2638                 rmask = data | (data >> 16);
2639                 data |= ((enable ? 0x2 : 0x1) << bit);
2640                 break;
2641         default:
2642                 data = BIT(bit + 16) | (enable << bit);
2643                 rmask = BIT(bit + 16) | BIT(bit);
2644                 break;
2645         }
2646
2647         return regmap_update_bits(regmap, reg, rmask, data);
2648 }
2649
2650 /*
2651  * Pinmux_ops handling
2652  */
2653
2654 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2655 {
2656         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2657
2658         return info->nfunctions;
2659 }
2660
2661 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2662                                           unsigned selector)
2663 {
2664         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2665
2666         return info->functions[selector].name;
2667 }
2668
2669 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2670                                 unsigned selector, const char * const **groups,
2671                                 unsigned * const num_groups)
2672 {
2673         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2674
2675         *groups = info->functions[selector].groups;
2676         *num_groups = info->functions[selector].ngroups;
2677
2678         return 0;
2679 }
2680
2681 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2682                             unsigned group)
2683 {
2684         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2685         const unsigned int *pins = info->groups[group].pins;
2686         const struct rockchip_pin_config *data = info->groups[group].data;
2687         struct device *dev = info->dev;
2688         struct rockchip_pin_bank *bank;
2689         int cnt, ret = 0;
2690
2691         dev_dbg(dev, "enable function %s group %s\n",
2692                 info->functions[selector].name, info->groups[group].name);
2693
2694         /*
2695          * for each pin in the pin group selected, program the corresponding
2696          * pin function number in the config register.
2697          */
2698         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2699                 bank = pin_to_bank(info, pins[cnt]);
2700                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2701                                        data[cnt].func);
2702                 if (ret)
2703                         break;
2704         }
2705
2706         if (ret) {
2707                 /* revert the already done pin settings */
2708                 for (cnt--; cnt >= 0; cnt--)
2709                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2710
2711                 return ret;
2712         }
2713
2714         return 0;
2715 }
2716
2717 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2718                                            struct pinctrl_gpio_range *range,
2719                                            unsigned offset,
2720                                            bool input)
2721 {
2722         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2723         struct rockchip_pin_bank *bank;
2724
2725         bank = pin_to_bank(info, offset);
2726         return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO);
2727 }
2728
2729 static const struct pinmux_ops rockchip_pmx_ops = {
2730         .get_functions_count    = rockchip_pmx_get_funcs_count,
2731         .get_function_name      = rockchip_pmx_get_func_name,
2732         .get_function_groups    = rockchip_pmx_get_groups,
2733         .set_mux                = rockchip_pmx_set,
2734         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
2735 };
2736
2737 /*
2738  * Pinconf_ops handling
2739  */
2740
2741 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2742                                         enum pin_config_param pull)
2743 {
2744         switch (ctrl->type) {
2745         case RK2928:
2746         case RK3128:
2747                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2748                                         pull == PIN_CONFIG_BIAS_DISABLE);
2749         case RK3066B:
2750                 return pull ? false : true;
2751         case PX30:
2752         case RV1108:
2753         case RV1126:
2754         case RK3188:
2755         case RK3288:
2756         case RK3308:
2757         case RK3368:
2758         case RK3399:
2759         case RK3568:
2760         case RK3588:
2761                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2762         }
2763
2764         return false;
2765 }
2766
2767 static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
2768                                          unsigned int pin, u32 param, u32 arg)
2769 {
2770         struct rockchip_pin_deferred *cfg;
2771
2772         cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
2773         if (!cfg)
2774                 return -ENOMEM;
2775
2776         cfg->pin = pin;
2777         cfg->param = param;
2778         cfg->arg = arg;
2779
2780         list_add_tail(&cfg->head, &bank->deferred_pins);
2781
2782         return 0;
2783 }
2784
2785 /* set the pin config settings for a specified pin */
2786 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2787                                 unsigned long *configs, unsigned num_configs)
2788 {
2789         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2790         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2791         struct gpio_chip *gpio = &bank->gpio_chip;
2792         enum pin_config_param param;
2793         u32 arg;
2794         int i;
2795         int rc;
2796
2797         for (i = 0; i < num_configs; i++) {
2798                 param = pinconf_to_config_param(configs[i]);
2799                 arg = pinconf_to_config_argument(configs[i]);
2800
2801                 if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
2802                         /*
2803                          * Check for gpio driver not being probed yet.
2804                          * The lock makes sure that either gpio-probe has completed
2805                          * or the gpio driver hasn't probed yet.
2806                          */
2807                         mutex_lock(&bank->deferred_lock);
2808                         if (!gpio || !gpio->direction_output) {
2809                                 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
2810                                                                 arg);
2811                                 mutex_unlock(&bank->deferred_lock);
2812                                 if (rc)
2813                                         return rc;
2814
2815                                 break;
2816                         }
2817                         mutex_unlock(&bank->deferred_lock);
2818                 }
2819
2820                 switch (param) {
2821                 case PIN_CONFIG_BIAS_DISABLE:
2822                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
2823                                 param);
2824                         if (rc)
2825                                 return rc;
2826                         break;
2827                 case PIN_CONFIG_BIAS_PULL_UP:
2828                 case PIN_CONFIG_BIAS_PULL_DOWN:
2829                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2830                 case PIN_CONFIG_BIAS_BUS_HOLD:
2831                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2832                                 return -ENOTSUPP;
2833
2834                         if (!arg)
2835                                 return -EINVAL;
2836
2837                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
2838                                 param);
2839                         if (rc)
2840                                 return rc;
2841                         break;
2842                 case PIN_CONFIG_OUTPUT:
2843                         rc = rockchip_set_mux(bank, pin - bank->pin_base,
2844                                               RK_FUNC_GPIO);
2845                         if (rc != RK_FUNC_GPIO)
2846                                 return -EINVAL;
2847
2848                         rc = gpio->direction_output(gpio, pin - bank->pin_base,
2849                                                     arg);
2850                         if (rc)
2851                                 return rc;
2852                         break;
2853                 case PIN_CONFIG_INPUT_ENABLE:
2854                         rc = rockchip_set_mux(bank, pin - bank->pin_base,
2855                                               RK_FUNC_GPIO);
2856                         if (rc != RK_FUNC_GPIO)
2857                                 return -EINVAL;
2858
2859                         rc = gpio->direction_input(gpio, pin - bank->pin_base);
2860                         if (rc)
2861                                 return rc;
2862                         break;
2863                 case PIN_CONFIG_DRIVE_STRENGTH:
2864                         /* rk3288 is the first with per-pin drive-strength */
2865                         if (!info->ctrl->drv_calc_reg)
2866                                 return -ENOTSUPP;
2867
2868                         rc = rockchip_set_drive_perpin(bank,
2869                                                 pin - bank->pin_base, arg);
2870                         if (rc < 0)
2871                                 return rc;
2872                         break;
2873                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2874                         if (!info->ctrl->schmitt_calc_reg)
2875                                 return -ENOTSUPP;
2876
2877                         rc = rockchip_set_schmitt(bank,
2878                                                   pin - bank->pin_base, arg);
2879                         if (rc < 0)
2880                                 return rc;
2881                         break;
2882                 default:
2883                         return -ENOTSUPP;
2884                         break;
2885                 }
2886         } /* for each config */
2887
2888         return 0;
2889 }
2890
2891 /* get the pin config settings for a specified pin */
2892 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2893                                                         unsigned long *config)
2894 {
2895         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2896         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2897         struct gpio_chip *gpio = &bank->gpio_chip;
2898         enum pin_config_param param = pinconf_to_config_param(*config);
2899         u16 arg;
2900         int rc;
2901
2902         switch (param) {
2903         case PIN_CONFIG_BIAS_DISABLE:
2904                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2905                         return -EINVAL;
2906
2907                 arg = 0;
2908                 break;
2909         case PIN_CONFIG_BIAS_PULL_UP:
2910         case PIN_CONFIG_BIAS_PULL_DOWN:
2911         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2912         case PIN_CONFIG_BIAS_BUS_HOLD:
2913                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2914                         return -ENOTSUPP;
2915
2916                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2917                         return -EINVAL;
2918
2919                 arg = 1;
2920                 break;
2921         case PIN_CONFIG_OUTPUT:
2922                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2923                 if (rc != RK_FUNC_GPIO)
2924                         return -EINVAL;
2925
2926                 if (!gpio || !gpio->get) {
2927                         arg = 0;
2928                         break;
2929                 }
2930
2931                 rc = gpio->get(gpio, pin - bank->pin_base);
2932                 if (rc < 0)
2933                         return rc;
2934
2935                 arg = rc ? 1 : 0;
2936                 break;
2937         case PIN_CONFIG_DRIVE_STRENGTH:
2938                 /* rk3288 is the first with per-pin drive-strength */
2939                 if (!info->ctrl->drv_calc_reg)
2940                         return -ENOTSUPP;
2941
2942                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
2943                 if (rc < 0)
2944                         return rc;
2945
2946                 arg = rc;
2947                 break;
2948         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2949                 if (!info->ctrl->schmitt_calc_reg)
2950                         return -ENOTSUPP;
2951
2952                 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2953                 if (rc < 0)
2954                         return rc;
2955
2956                 arg = rc;
2957                 break;
2958         default:
2959                 return -ENOTSUPP;
2960                 break;
2961         }
2962
2963         *config = pinconf_to_config_packed(param, arg);
2964
2965         return 0;
2966 }
2967
2968 static const struct pinconf_ops rockchip_pinconf_ops = {
2969         .pin_config_get                 = rockchip_pinconf_get,
2970         .pin_config_set                 = rockchip_pinconf_set,
2971         .is_generic                     = true,
2972 };
2973
2974 static const struct of_device_id rockchip_bank_match[] = {
2975         { .compatible = "rockchip,gpio-bank" },
2976         { .compatible = "rockchip,rk3188-gpio-bank0" },
2977         {},
2978 };
2979
2980 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2981                                                 struct device_node *np)
2982 {
2983         struct device_node *child;
2984
2985         for_each_child_of_node(np, child) {
2986                 if (of_match_node(rockchip_bank_match, child))
2987                         continue;
2988
2989                 info->nfunctions++;
2990                 info->ngroups += of_get_child_count(child);
2991         }
2992 }
2993
2994 static int rockchip_pinctrl_parse_groups(struct device_node *np,
2995                                               struct rockchip_pin_group *grp,
2996                                               struct rockchip_pinctrl *info,
2997                                               u32 index)
2998 {
2999         struct device *dev = info->dev;
3000         struct rockchip_pin_bank *bank;
3001         int size;
3002         const __be32 *list;
3003         int num;
3004         int i, j;
3005         int ret;
3006
3007         dev_dbg(dev, "group(%d): %pOFn\n", index, np);
3008
3009         /* Initialise group */
3010         grp->name = np->name;
3011
3012         /*
3013          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
3014          * do sanity check and calculate pins number
3015          */
3016         list = of_get_property(np, "rockchip,pins", &size);
3017         /* we do not check return since it's safe node passed down */
3018         size /= sizeof(*list);
3019         if (!size || size % 4)
3020                 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n");
3021
3022         grp->npins = size / 4;
3023
3024         grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
3025         grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
3026         if (!grp->pins || !grp->data)
3027                 return -ENOMEM;
3028
3029         for (i = 0, j = 0; i < size; i += 4, j++) {
3030                 const __be32 *phandle;
3031                 struct device_node *np_config;
3032
3033                 num = be32_to_cpu(*list++);
3034                 bank = bank_num_to_bank(info, num);
3035                 if (IS_ERR(bank))
3036                         return PTR_ERR(bank);
3037
3038                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
3039                 grp->data[j].func = be32_to_cpu(*list++);
3040
3041                 phandle = list++;
3042                 if (!phandle)
3043                         return -EINVAL;
3044
3045                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
3046                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
3047                                 &grp->data[j].configs, &grp->data[j].nconfigs);
3048                 of_node_put(np_config);
3049                 if (ret)
3050                         return ret;
3051         }
3052
3053         return 0;
3054 }
3055
3056 static int rockchip_pinctrl_parse_functions(struct device_node *np,
3057                                                 struct rockchip_pinctrl *info,
3058                                                 u32 index)
3059 {
3060         struct device *dev = info->dev;
3061         struct device_node *child;
3062         struct rockchip_pmx_func *func;
3063         struct rockchip_pin_group *grp;
3064         int ret;
3065         static u32 grp_index;
3066         u32 i = 0;
3067
3068         dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
3069
3070         func = &info->functions[index];
3071
3072         /* Initialise function */
3073         func->name = np->name;
3074         func->ngroups = of_get_child_count(np);
3075         if (func->ngroups <= 0)
3076                 return 0;
3077
3078         func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
3079         if (!func->groups)
3080                 return -ENOMEM;
3081
3082         for_each_child_of_node(np, child) {
3083                 func->groups[i] = child->name;
3084                 grp = &info->groups[grp_index++];
3085                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
3086                 if (ret) {
3087                         of_node_put(child);
3088                         return ret;
3089                 }
3090         }
3091
3092         return 0;
3093 }
3094
3095 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
3096                                               struct rockchip_pinctrl *info)
3097 {
3098         struct device *dev = &pdev->dev;
3099         struct device_node *np = dev->of_node;
3100         struct device_node *child;
3101         int ret;
3102         int i;
3103
3104         rockchip_pinctrl_child_count(info, np);
3105
3106         dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
3107         dev_dbg(dev, "ngroups = %d\n", info->ngroups);
3108
3109         info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
3110         if (!info->functions)
3111                 return -ENOMEM;
3112
3113         info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
3114         if (!info->groups)
3115                 return -ENOMEM;
3116
3117         i = 0;
3118
3119         for_each_child_of_node(np, child) {
3120                 if (of_match_node(rockchip_bank_match, child))
3121                         continue;
3122
3123                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
3124                 if (ret) {
3125                         dev_err(dev, "failed to parse function\n");
3126                         of_node_put(child);
3127                         return ret;
3128                 }
3129         }
3130
3131         return 0;
3132 }
3133
3134 static int rockchip_pinctrl_register(struct platform_device *pdev,
3135                                         struct rockchip_pinctrl *info)
3136 {
3137         struct pinctrl_desc *ctrldesc = &info->pctl;
3138         struct pinctrl_pin_desc *pindesc, *pdesc;
3139         struct rockchip_pin_bank *pin_bank;
3140         struct device *dev = &pdev->dev;
3141         char **pin_names;
3142         int pin, bank, ret;
3143         int k;
3144
3145         ctrldesc->name = "rockchip-pinctrl";
3146         ctrldesc->owner = THIS_MODULE;
3147         ctrldesc->pctlops = &rockchip_pctrl_ops;
3148         ctrldesc->pmxops = &rockchip_pmx_ops;
3149         ctrldesc->confops = &rockchip_pinconf_ops;
3150
3151         pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
3152         if (!pindesc)
3153                 return -ENOMEM;
3154
3155         ctrldesc->pins = pindesc;
3156         ctrldesc->npins = info->ctrl->nr_pins;
3157
3158         pdesc = pindesc;
3159         for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
3160                 pin_bank = &info->ctrl->pin_banks[bank];
3161
3162                 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins);
3163                 if (IS_ERR(pin_names))
3164                         return PTR_ERR(pin_names);
3165
3166                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
3167                         pdesc->number = k;
3168                         pdesc->name = pin_names[pin];
3169                         pdesc++;
3170                 }
3171
3172                 INIT_LIST_HEAD(&pin_bank->deferred_pins);
3173                 mutex_init(&pin_bank->deferred_lock);
3174         }
3175
3176         ret = rockchip_pinctrl_parse_dt(pdev, info);
3177         if (ret)
3178                 return ret;
3179
3180         info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
3181         if (IS_ERR(info->pctl_dev))
3182                 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
3183
3184         return 0;
3185 }
3186
3187 static const struct of_device_id rockchip_pinctrl_dt_match[];
3188
3189 /* retrieve the soc specific data */
3190 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3191                                                 struct rockchip_pinctrl *d,
3192                                                 struct platform_device *pdev)
3193 {
3194         struct device *dev = &pdev->dev;
3195         struct device_node *node = dev->of_node;
3196         const struct of_device_id *match;
3197         struct rockchip_pin_ctrl *ctrl;
3198         struct rockchip_pin_bank *bank;
3199         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3200
3201         match = of_match_node(rockchip_pinctrl_dt_match, node);
3202         ctrl = (struct rockchip_pin_ctrl *)match->data;
3203
3204         grf_offs = ctrl->grf_mux_offset;
3205         pmu_offs = ctrl->pmu_mux_offset;
3206         drv_pmu_offs = ctrl->pmu_drv_offset;
3207         drv_grf_offs = ctrl->grf_drv_offset;
3208         bank = ctrl->pin_banks;
3209         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3210                 int bank_pins = 0;
3211
3212                 raw_spin_lock_init(&bank->slock);
3213                 bank->drvdata = d;
3214                 bank->pin_base = ctrl->nr_pins;
3215                 ctrl->nr_pins += bank->nr_pins;
3216
3217                 /* calculate iomux and drv offsets */
3218                 for (j = 0; j < 4; j++) {
3219                         struct rockchip_iomux *iom = &bank->iomux[j];
3220                         struct rockchip_drv *drv = &bank->drv[j];
3221                         int inc;
3222
3223                         if (bank_pins >= bank->nr_pins)
3224                                 break;
3225
3226                         /* preset iomux offset value, set new start value */
3227                         if (iom->offset >= 0) {
3228                                 if ((iom->type & IOMUX_SOURCE_PMU) ||
3229                                     (iom->type & IOMUX_L_SOURCE_PMU))
3230                                         pmu_offs = iom->offset;
3231                                 else
3232                                         grf_offs = iom->offset;
3233                         } else { /* set current iomux offset */
3234                                 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
3235                                                (iom->type & IOMUX_L_SOURCE_PMU)) ?
3236                                                         pmu_offs : grf_offs;
3237                         }
3238
3239                         /* preset drv offset value, set new start value */
3240                         if (drv->offset >= 0) {
3241                                 if (iom->type & IOMUX_SOURCE_PMU)
3242                                         drv_pmu_offs = drv->offset;
3243                                 else
3244                                         drv_grf_offs = drv->offset;
3245                         } else { /* set current drv offset */
3246                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3247                                                 drv_pmu_offs : drv_grf_offs;
3248                         }
3249
3250                         dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3251                                 i, j, iom->offset, drv->offset);
3252
3253                         /*
3254                          * Increase offset according to iomux width.
3255                          * 4bit iomux'es are spread over two registers.
3256                          */
3257                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
3258                                             IOMUX_WIDTH_3BIT |
3259                                             IOMUX_WIDTH_2BIT)) ? 8 : 4;
3260                         if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
3261                                 pmu_offs += inc;
3262                         else
3263                                 grf_offs += inc;
3264
3265                         /*
3266                          * Increase offset according to drv width.
3267                          * 3bit drive-strenth'es are spread over two registers.
3268                          */
3269                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3270                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3271                                 inc = 8;
3272                         else
3273                                 inc = 4;
3274
3275                         if (iom->type & IOMUX_SOURCE_PMU)
3276                                 drv_pmu_offs += inc;
3277                         else
3278                                 drv_grf_offs += inc;
3279
3280                         bank_pins += 8;
3281                 }
3282
3283                 /* calculate the per-bank recalced_mask */
3284                 for (j = 0; j < ctrl->niomux_recalced; j++) {
3285                         int pin = 0;
3286
3287                         if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3288                                 pin = ctrl->iomux_recalced[j].pin;
3289                                 bank->recalced_mask |= BIT(pin);
3290                         }
3291                 }
3292
3293                 /* calculate the per-bank route_mask */
3294                 for (j = 0; j < ctrl->niomux_routes; j++) {
3295                         int pin = 0;
3296
3297                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3298                                 pin = ctrl->iomux_routes[j].pin;
3299                                 bank->route_mask |= BIT(pin);
3300                         }
3301                 }
3302         }
3303
3304         return ctrl;
3305 }
3306
3307 #define RK3288_GRF_GPIO6C_IOMUX         0x64
3308 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
3309
3310 static u32 rk3288_grf_gpio6c_iomux;
3311
3312 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3313 {
3314         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3315         int ret = pinctrl_force_sleep(info->pctl_dev);
3316
3317         if (ret)
3318                 return ret;
3319
3320         /*
3321          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3322          * the setting here, and restore it at resume.
3323          */
3324         if (info->ctrl->type == RK3288) {
3325                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3326                                   &rk3288_grf_gpio6c_iomux);
3327                 if (ret) {
3328                         pinctrl_force_default(info->pctl_dev);
3329                         return ret;
3330                 }
3331         }
3332
3333         return 0;
3334 }
3335
3336 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3337 {
3338         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3339         int ret;
3340
3341         if (info->ctrl->type == RK3288) {
3342                 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3343                                    rk3288_grf_gpio6c_iomux |
3344                                    GPIO6C6_SEL_WRITE_ENABLE);
3345                 if (ret)
3346                         return ret;
3347         }
3348
3349         return pinctrl_force_default(info->pctl_dev);
3350 }
3351
3352 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3353                          rockchip_pinctrl_resume);
3354
3355 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3356 {
3357         struct rockchip_pinctrl *info;
3358         struct device *dev = &pdev->dev;
3359         struct device_node *np = dev->of_node, *node;
3360         struct rockchip_pin_ctrl *ctrl;
3361         struct resource *res;
3362         void __iomem *base;
3363         int ret;
3364
3365         if (!dev->of_node)
3366                 return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
3367
3368         info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3369         if (!info)
3370                 return -ENOMEM;
3371
3372         info->dev = dev;
3373
3374         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3375         if (!ctrl)
3376                 return dev_err_probe(dev, -EINVAL, "driver data not available\n");
3377         info->ctrl = ctrl;
3378
3379         node = of_parse_phandle(np, "rockchip,grf", 0);
3380         if (node) {
3381                 info->regmap_base = syscon_node_to_regmap(node);
3382                 of_node_put(node);
3383                 if (IS_ERR(info->regmap_base))
3384                         return PTR_ERR(info->regmap_base);
3385         } else {
3386                 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
3387                 if (IS_ERR(base))
3388                         return PTR_ERR(base);
3389
3390                 rockchip_regmap_config.max_register = resource_size(res) - 4;
3391                 rockchip_regmap_config.name = "rockchip,pinctrl";
3392                 info->regmap_base =
3393                         devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3394
3395                 /* to check for the old dt-bindings */
3396                 info->reg_size = resource_size(res);
3397
3398                 /* Honor the old binding, with pull registers as 2nd resource */
3399                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3400                         base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
3401                         if (IS_ERR(base))
3402                                 return PTR_ERR(base);
3403
3404                         rockchip_regmap_config.max_register = resource_size(res) - 4;
3405                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3406                         info->regmap_pull =
3407                                 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3408                 }
3409         }
3410
3411         /* try to find the optional reference to the pmu syscon */
3412         node = of_parse_phandle(np, "rockchip,pmu", 0);
3413         if (node) {
3414                 info->regmap_pmu = syscon_node_to_regmap(node);
3415                 of_node_put(node);
3416                 if (IS_ERR(info->regmap_pmu))
3417                         return PTR_ERR(info->regmap_pmu);
3418         }
3419
3420         ret = rockchip_pinctrl_register(pdev, info);
3421         if (ret)
3422                 return ret;
3423
3424         platform_set_drvdata(pdev, info);
3425
3426         ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
3427         if (ret)
3428                 return dev_err_probe(dev, ret, "failed to register gpio device\n");
3429
3430         return 0;
3431 }
3432
3433 static int rockchip_pinctrl_remove(struct platform_device *pdev)
3434 {
3435         struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
3436         struct rockchip_pin_bank *bank;
3437         struct rockchip_pin_deferred *cfg;
3438         int i;
3439
3440         of_platform_depopulate(&pdev->dev);
3441
3442         for (i = 0; i < info->ctrl->nr_banks; i++) {
3443                 bank = &info->ctrl->pin_banks[i];
3444
3445                 mutex_lock(&bank->deferred_lock);
3446                 while (!list_empty(&bank->deferred_pins)) {
3447                         cfg = list_first_entry(&bank->deferred_pins,
3448                                                struct rockchip_pin_deferred, head);
3449                         list_del(&cfg->head);
3450                         kfree(cfg);
3451                 }
3452                 mutex_unlock(&bank->deferred_lock);
3453         }
3454
3455         return 0;
3456 }
3457
3458 static struct rockchip_pin_bank px30_pin_banks[] = {
3459         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3460                                              IOMUX_SOURCE_PMU,
3461                                              IOMUX_SOURCE_PMU,
3462                                              IOMUX_SOURCE_PMU
3463                             ),
3464         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3465                                              IOMUX_WIDTH_4BIT,
3466                                              IOMUX_WIDTH_4BIT,
3467                                              IOMUX_WIDTH_4BIT
3468                             ),
3469         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3470                                              IOMUX_WIDTH_4BIT,
3471                                              IOMUX_WIDTH_4BIT,
3472                                              IOMUX_WIDTH_4BIT
3473                             ),
3474         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3475                                              IOMUX_WIDTH_4BIT,
3476                                              IOMUX_WIDTH_4BIT,
3477                                              IOMUX_WIDTH_4BIT
3478                             ),
3479 };
3480
3481 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3482                 .pin_banks              = px30_pin_banks,
3483                 .nr_banks               = ARRAY_SIZE(px30_pin_banks),
3484                 .label                  = "PX30-GPIO",
3485                 .type                   = PX30,
3486                 .grf_mux_offset         = 0x0,
3487                 .pmu_mux_offset         = 0x0,
3488                 .iomux_routes           = px30_mux_route_data,
3489                 .niomux_routes          = ARRAY_SIZE(px30_mux_route_data),
3490                 .pull_calc_reg          = px30_calc_pull_reg_and_bit,
3491                 .drv_calc_reg           = px30_calc_drv_reg_and_bit,
3492                 .schmitt_calc_reg       = px30_calc_schmitt_reg_and_bit,
3493 };
3494
3495 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3496         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3497                                              IOMUX_SOURCE_PMU,
3498                                              IOMUX_SOURCE_PMU,
3499                                              IOMUX_SOURCE_PMU),
3500         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3501         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3502         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3503 };
3504
3505 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3506         .pin_banks              = rv1108_pin_banks,
3507         .nr_banks               = ARRAY_SIZE(rv1108_pin_banks),
3508         .label                  = "RV1108-GPIO",
3509         .type                   = RV1108,
3510         .grf_mux_offset         = 0x10,
3511         .pmu_mux_offset         = 0x0,
3512         .iomux_recalced         = rv1108_mux_recalced_data,
3513         .niomux_recalced        = ARRAY_SIZE(rv1108_mux_recalced_data),
3514         .pull_calc_reg          = rv1108_calc_pull_reg_and_bit,
3515         .drv_calc_reg           = rv1108_calc_drv_reg_and_bit,
3516         .schmitt_calc_reg       = rv1108_calc_schmitt_reg_and_bit,
3517 };
3518
3519 static struct rockchip_pin_bank rv1126_pin_banks[] = {
3520         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
3521                              IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
3522                              IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
3523                              IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
3524                              IOMUX_WIDTH_4BIT),
3525         PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
3526                                     IOMUX_WIDTH_4BIT,
3527                                     IOMUX_WIDTH_4BIT,
3528                                     IOMUX_WIDTH_4BIT,
3529                                     IOMUX_WIDTH_4BIT,
3530                                     0x10010, 0x10018, 0x10020, 0x10028),
3531         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
3532                              IOMUX_WIDTH_4BIT,
3533                              IOMUX_WIDTH_4BIT,
3534                              IOMUX_WIDTH_4BIT,
3535                              IOMUX_WIDTH_4BIT),
3536         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3537                              IOMUX_WIDTH_4BIT,
3538                              IOMUX_WIDTH_4BIT,
3539                              IOMUX_WIDTH_4BIT,
3540                              IOMUX_WIDTH_4BIT),
3541         PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
3542                              IOMUX_WIDTH_4BIT, 0, 0, 0),
3543 };
3544
3545 static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
3546         .pin_banks              = rv1126_pin_banks,
3547         .nr_banks               = ARRAY_SIZE(rv1126_pin_banks),
3548         .label                  = "RV1126-GPIO",
3549         .type                   = RV1126,
3550         .grf_mux_offset         = 0x10004, /* mux offset from GPIO0_D0 */
3551         .pmu_mux_offset         = 0x0,
3552         .iomux_routes           = rv1126_mux_route_data,
3553         .niomux_routes          = ARRAY_SIZE(rv1126_mux_route_data),
3554         .iomux_recalced         = rv1126_mux_recalced_data,
3555         .niomux_recalced        = ARRAY_SIZE(rv1126_mux_recalced_data),
3556         .pull_calc_reg          = rv1126_calc_pull_reg_and_bit,
3557         .drv_calc_reg           = rv1126_calc_drv_reg_and_bit,
3558         .schmitt_calc_reg       = rv1126_calc_schmitt_reg_and_bit,
3559 };
3560
3561 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3562         PIN_BANK(0, 32, "gpio0"),
3563         PIN_BANK(1, 32, "gpio1"),
3564         PIN_BANK(2, 32, "gpio2"),
3565         PIN_BANK(3, 32, "gpio3"),
3566 };
3567
3568 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3569                 .pin_banks              = rk2928_pin_banks,
3570                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
3571                 .label                  = "RK2928-GPIO",
3572                 .type                   = RK2928,
3573                 .grf_mux_offset         = 0xa8,
3574                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3575 };
3576
3577 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3578         PIN_BANK(0, 32, "gpio0"),
3579         PIN_BANK(1, 32, "gpio1"),
3580         PIN_BANK(2, 32, "gpio2"),
3581 };
3582
3583 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3584                 .pin_banks              = rk3036_pin_banks,
3585                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
3586                 .label                  = "RK3036-GPIO",
3587                 .type                   = RK2928,
3588                 .grf_mux_offset         = 0xa8,
3589                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3590 };
3591
3592 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3593         PIN_BANK(0, 32, "gpio0"),
3594         PIN_BANK(1, 32, "gpio1"),
3595         PIN_BANK(2, 32, "gpio2"),
3596         PIN_BANK(3, 32, "gpio3"),
3597         PIN_BANK(4, 32, "gpio4"),
3598         PIN_BANK(6, 16, "gpio6"),
3599 };
3600
3601 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3602                 .pin_banks              = rk3066a_pin_banks,
3603                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
3604                 .label                  = "RK3066a-GPIO",
3605                 .type                   = RK2928,
3606                 .grf_mux_offset         = 0xa8,
3607                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3608 };
3609
3610 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3611         PIN_BANK(0, 32, "gpio0"),
3612         PIN_BANK(1, 32, "gpio1"),
3613         PIN_BANK(2, 32, "gpio2"),
3614         PIN_BANK(3, 32, "gpio3"),
3615 };
3616
3617 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3618                 .pin_banks      = rk3066b_pin_banks,
3619                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
3620                 .label          = "RK3066b-GPIO",
3621                 .type           = RK3066B,
3622                 .grf_mux_offset = 0x60,
3623 };
3624
3625 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3626         PIN_BANK(0, 32, "gpio0"),
3627         PIN_BANK(1, 32, "gpio1"),
3628         PIN_BANK(2, 32, "gpio2"),
3629         PIN_BANK(3, 32, "gpio3"),
3630 };
3631
3632 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3633                 .pin_banks              = rk3128_pin_banks,
3634                 .nr_banks               = ARRAY_SIZE(rk3128_pin_banks),
3635                 .label                  = "RK3128-GPIO",
3636                 .type                   = RK3128,
3637                 .grf_mux_offset         = 0xa8,
3638                 .iomux_recalced         = rk3128_mux_recalced_data,
3639                 .niomux_recalced        = ARRAY_SIZE(rk3128_mux_recalced_data),
3640                 .iomux_routes           = rk3128_mux_route_data,
3641                 .niomux_routes          = ARRAY_SIZE(rk3128_mux_route_data),
3642                 .pull_calc_reg          = rk3128_calc_pull_reg_and_bit,
3643 };
3644
3645 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3646         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3647         PIN_BANK(1, 32, "gpio1"),
3648         PIN_BANK(2, 32, "gpio2"),
3649         PIN_BANK(3, 32, "gpio3"),
3650 };
3651
3652 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3653                 .pin_banks              = rk3188_pin_banks,
3654                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
3655                 .label                  = "RK3188-GPIO",
3656                 .type                   = RK3188,
3657                 .grf_mux_offset         = 0x60,
3658                 .iomux_routes           = rk3188_mux_route_data,
3659                 .niomux_routes          = ARRAY_SIZE(rk3188_mux_route_data),
3660                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
3661 };
3662
3663 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3664         PIN_BANK(0, 32, "gpio0"),
3665         PIN_BANK(1, 32, "gpio1"),
3666         PIN_BANK(2, 32, "gpio2"),
3667         PIN_BANK(3, 32, "gpio3"),
3668 };
3669
3670 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3671                 .pin_banks              = rk3228_pin_banks,
3672                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
3673                 .label                  = "RK3228-GPIO",
3674                 .type                   = RK3288,
3675                 .grf_mux_offset         = 0x0,
3676                 .iomux_routes           = rk3228_mux_route_data,
3677                 .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
3678                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3679                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3680 };
3681
3682 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3683         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3684                                              IOMUX_SOURCE_PMU,
3685                                              IOMUX_SOURCE_PMU,
3686                                              IOMUX_UNROUTED
3687                             ),
3688         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3689                                              IOMUX_UNROUTED,
3690                                              IOMUX_UNROUTED,
3691                                              0
3692                             ),
3693         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3694         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3695         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3696                                              IOMUX_WIDTH_4BIT,
3697                                              0,
3698                                              0
3699                             ),
3700         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3701                                              0,
3702                                              0,
3703                                              IOMUX_UNROUTED
3704                             ),
3705         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3706         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3707                                              0,
3708                                              IOMUX_WIDTH_4BIT,
3709                                              IOMUX_UNROUTED
3710                             ),
3711         PIN_BANK(8, 16, "gpio8"),
3712 };
3713
3714 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3715                 .pin_banks              = rk3288_pin_banks,
3716                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
3717                 .label                  = "RK3288-GPIO",
3718                 .type                   = RK3288,
3719                 .grf_mux_offset         = 0x0,
3720                 .pmu_mux_offset         = 0x84,
3721                 .iomux_routes           = rk3288_mux_route_data,
3722                 .niomux_routes          = ARRAY_SIZE(rk3288_mux_route_data),
3723                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
3724                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
3725 };
3726
3727 static struct rockchip_pin_bank rk3308_pin_banks[] = {
3728         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3729                                              IOMUX_WIDTH_2BIT,
3730                                              IOMUX_WIDTH_2BIT,
3731                                              IOMUX_WIDTH_2BIT),
3732         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
3733                                              IOMUX_WIDTH_2BIT,
3734                                              IOMUX_WIDTH_2BIT,
3735                                              IOMUX_WIDTH_2BIT),
3736         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
3737                                              IOMUX_WIDTH_2BIT,
3738                                              IOMUX_WIDTH_2BIT,
3739                                              IOMUX_WIDTH_2BIT),
3740         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
3741                                              IOMUX_WIDTH_2BIT,
3742                                              IOMUX_WIDTH_2BIT,
3743                                              IOMUX_WIDTH_2BIT),
3744         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
3745                                              IOMUX_WIDTH_2BIT,
3746                                              IOMUX_WIDTH_2BIT,
3747                                              IOMUX_WIDTH_2BIT),
3748 };
3749
3750 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
3751                 .pin_banks              = rk3308_pin_banks,
3752                 .nr_banks               = ARRAY_SIZE(rk3308_pin_banks),
3753                 .label                  = "RK3308-GPIO",
3754                 .type                   = RK3308,
3755                 .grf_mux_offset         = 0x0,
3756                 .iomux_recalced         = rk3308_mux_recalced_data,
3757                 .niomux_recalced        = ARRAY_SIZE(rk3308_mux_recalced_data),
3758                 .iomux_routes           = rk3308_mux_route_data,
3759                 .niomux_routes          = ARRAY_SIZE(rk3308_mux_route_data),
3760                 .pull_calc_reg          = rk3308_calc_pull_reg_and_bit,
3761                 .drv_calc_reg           = rk3308_calc_drv_reg_and_bit,
3762                 .schmitt_calc_reg       = rk3308_calc_schmitt_reg_and_bit,
3763 };
3764
3765 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3766         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3767         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3768         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3769                              IOMUX_WIDTH_3BIT,
3770                              IOMUX_WIDTH_3BIT,
3771                              0),
3772         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3773                              IOMUX_WIDTH_3BIT,
3774                              IOMUX_WIDTH_3BIT,
3775                              0,
3776                              0),
3777 };
3778
3779 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3780                 .pin_banks              = rk3328_pin_banks,
3781                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
3782                 .label                  = "RK3328-GPIO",
3783                 .type                   = RK3288,
3784                 .grf_mux_offset         = 0x0,
3785                 .iomux_recalced         = rk3328_mux_recalced_data,
3786                 .niomux_recalced        = ARRAY_SIZE(rk3328_mux_recalced_data),
3787                 .iomux_routes           = rk3328_mux_route_data,
3788                 .niomux_routes          = ARRAY_SIZE(rk3328_mux_route_data),
3789                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3790                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3791                 .schmitt_calc_reg       = rk3328_calc_schmitt_reg_and_bit,
3792 };
3793
3794 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3795         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3796                                              IOMUX_SOURCE_PMU,
3797                                              IOMUX_SOURCE_PMU,
3798                                              IOMUX_SOURCE_PMU
3799                             ),
3800         PIN_BANK(1, 32, "gpio1"),
3801         PIN_BANK(2, 32, "gpio2"),
3802         PIN_BANK(3, 32, "gpio3"),
3803 };
3804
3805 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3806                 .pin_banks              = rk3368_pin_banks,
3807                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
3808                 .label                  = "RK3368-GPIO",
3809                 .type                   = RK3368,
3810                 .grf_mux_offset         = 0x0,
3811                 .pmu_mux_offset         = 0x0,
3812                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
3813                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
3814 };
3815
3816 static struct rockchip_pin_bank rk3399_pin_banks[] = {
3817         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3818                                                          IOMUX_SOURCE_PMU,
3819                                                          IOMUX_SOURCE_PMU,
3820                                                          IOMUX_SOURCE_PMU,
3821                                                          IOMUX_SOURCE_PMU,
3822                                                          DRV_TYPE_IO_1V8_ONLY,
3823                                                          DRV_TYPE_IO_1V8_ONLY,
3824                                                          DRV_TYPE_IO_DEFAULT,
3825                                                          DRV_TYPE_IO_DEFAULT,
3826                                                          0x80,
3827                                                          0x88,
3828                                                          -1,
3829                                                          -1,
3830                                                          PULL_TYPE_IO_1V8_ONLY,
3831                                                          PULL_TYPE_IO_1V8_ONLY,
3832                                                          PULL_TYPE_IO_DEFAULT,
3833                                                          PULL_TYPE_IO_DEFAULT
3834                                                         ),
3835         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3836                                         IOMUX_SOURCE_PMU,
3837                                         IOMUX_SOURCE_PMU,
3838                                         IOMUX_SOURCE_PMU,
3839                                         DRV_TYPE_IO_1V8_OR_3V0,
3840                                         DRV_TYPE_IO_1V8_OR_3V0,
3841                                         DRV_TYPE_IO_1V8_OR_3V0,
3842                                         DRV_TYPE_IO_1V8_OR_3V0,
3843                                         0xa0,
3844                                         0xa8,
3845                                         0xb0,
3846                                         0xb8
3847                                         ),
3848         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3849                                       DRV_TYPE_IO_1V8_OR_3V0,
3850                                       DRV_TYPE_IO_1V8_ONLY,
3851                                       DRV_TYPE_IO_1V8_ONLY,
3852                                       PULL_TYPE_IO_DEFAULT,
3853                                       PULL_TYPE_IO_DEFAULT,
3854                                       PULL_TYPE_IO_1V8_ONLY,
3855                                       PULL_TYPE_IO_1V8_ONLY
3856                                       ),
3857         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3858                            DRV_TYPE_IO_3V3_ONLY,
3859                            DRV_TYPE_IO_3V3_ONLY,
3860                            DRV_TYPE_IO_1V8_OR_3V0
3861                            ),
3862         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3863                            DRV_TYPE_IO_1V8_3V0_AUTO,
3864                            DRV_TYPE_IO_1V8_OR_3V0,
3865                            DRV_TYPE_IO_1V8_OR_3V0
3866                            ),
3867 };
3868
3869 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3870                 .pin_banks              = rk3399_pin_banks,
3871                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
3872                 .label                  = "RK3399-GPIO",
3873                 .type                   = RK3399,
3874                 .grf_mux_offset         = 0xe000,
3875                 .pmu_mux_offset         = 0x0,
3876                 .grf_drv_offset         = 0xe100,
3877                 .pmu_drv_offset         = 0x80,
3878                 .iomux_routes           = rk3399_mux_route_data,
3879                 .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
3880                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
3881                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
3882 };
3883
3884 static struct rockchip_pin_bank rk3568_pin_banks[] = {
3885         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3886                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3887                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3888                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
3889         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3890                                              IOMUX_WIDTH_4BIT,
3891                                              IOMUX_WIDTH_4BIT,
3892                                              IOMUX_WIDTH_4BIT),
3893         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3894                                              IOMUX_WIDTH_4BIT,
3895                                              IOMUX_WIDTH_4BIT,
3896                                              IOMUX_WIDTH_4BIT),
3897         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3898                                              IOMUX_WIDTH_4BIT,
3899                                              IOMUX_WIDTH_4BIT,
3900                                              IOMUX_WIDTH_4BIT),
3901         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3902                                              IOMUX_WIDTH_4BIT,
3903                                              IOMUX_WIDTH_4BIT,
3904                                              IOMUX_WIDTH_4BIT),
3905 };
3906
3907 static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
3908         .pin_banks              = rk3568_pin_banks,
3909         .nr_banks               = ARRAY_SIZE(rk3568_pin_banks),
3910         .label                  = "RK3568-GPIO",
3911         .type                   = RK3568,
3912         .grf_mux_offset         = 0x0,
3913         .pmu_mux_offset         = 0x0,
3914         .grf_drv_offset         = 0x0200,
3915         .pmu_drv_offset         = 0x0070,
3916         .iomux_routes           = rk3568_mux_route_data,
3917         .niomux_routes          = ARRAY_SIZE(rk3568_mux_route_data),
3918         .pull_calc_reg          = rk3568_calc_pull_reg_and_bit,
3919         .drv_calc_reg           = rk3568_calc_drv_reg_and_bit,
3920         .schmitt_calc_reg       = rk3568_calc_schmitt_reg_and_bit,
3921 };
3922
3923 static struct rockchip_pin_bank rk3588_pin_banks[] = {
3924         RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
3925                               IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
3926         RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
3927                               IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
3928         RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
3929                               IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
3930         RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
3931                               IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
3932         RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
3933                               IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
3934 };
3935
3936 static struct rockchip_pin_ctrl rk3588_pin_ctrl = {
3937         .pin_banks              = rk3588_pin_banks,
3938         .nr_banks               = ARRAY_SIZE(rk3588_pin_banks),
3939         .label                  = "RK3588-GPIO",
3940         .type                   = RK3588,
3941         .pull_calc_reg          = rk3588_calc_pull_reg_and_bit,
3942         .drv_calc_reg           = rk3588_calc_drv_reg_and_bit,
3943         .schmitt_calc_reg       = rk3588_calc_schmitt_reg_and_bit,
3944 };
3945
3946 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3947         { .compatible = "rockchip,px30-pinctrl",
3948                 .data = &px30_pin_ctrl },
3949         { .compatible = "rockchip,rv1108-pinctrl",
3950                 .data = &rv1108_pin_ctrl },
3951         { .compatible = "rockchip,rv1126-pinctrl",
3952                 .data = &rv1126_pin_ctrl },
3953         { .compatible = "rockchip,rk2928-pinctrl",
3954                 .data = &rk2928_pin_ctrl },
3955         { .compatible = "rockchip,rk3036-pinctrl",
3956                 .data = &rk3036_pin_ctrl },
3957         { .compatible = "rockchip,rk3066a-pinctrl",
3958                 .data = &rk3066a_pin_ctrl },
3959         { .compatible = "rockchip,rk3066b-pinctrl",
3960                 .data = &rk3066b_pin_ctrl },
3961         { .compatible = "rockchip,rk3128-pinctrl",
3962                 .data = (void *)&rk3128_pin_ctrl },
3963         { .compatible = "rockchip,rk3188-pinctrl",
3964                 .data = &rk3188_pin_ctrl },
3965         { .compatible = "rockchip,rk3228-pinctrl",
3966                 .data = &rk3228_pin_ctrl },
3967         { .compatible = "rockchip,rk3288-pinctrl",
3968                 .data = &rk3288_pin_ctrl },
3969         { .compatible = "rockchip,rk3308-pinctrl",
3970                 .data = &rk3308_pin_ctrl },
3971         { .compatible = "rockchip,rk3328-pinctrl",
3972                 .data = &rk3328_pin_ctrl },
3973         { .compatible = "rockchip,rk3368-pinctrl",
3974                 .data = &rk3368_pin_ctrl },
3975         { .compatible = "rockchip,rk3399-pinctrl",
3976                 .data = &rk3399_pin_ctrl },
3977         { .compatible = "rockchip,rk3568-pinctrl",
3978                 .data = &rk3568_pin_ctrl },
3979         { .compatible = "rockchip,rk3588-pinctrl",
3980                 .data = &rk3588_pin_ctrl },
3981         {},
3982 };
3983
3984 static struct platform_driver rockchip_pinctrl_driver = {
3985         .probe          = rockchip_pinctrl_probe,
3986         .remove         = rockchip_pinctrl_remove,
3987         .driver = {
3988                 .name   = "rockchip-pinctrl",
3989                 .pm = &rockchip_pinctrl_dev_pm_ops,
3990                 .of_match_table = rockchip_pinctrl_dt_match,
3991         },
3992 };
3993
3994 static int __init rockchip_pinctrl_drv_register(void)
3995 {
3996         return platform_driver_register(&rockchip_pinctrl_driver);
3997 }
3998 postcore_initcall(rockchip_pinctrl_drv_register);
3999
4000 static void __exit rockchip_pinctrl_drv_unregister(void)
4001 {
4002         platform_driver_unregister(&rockchip_pinctrl_driver);
4003 }
4004 module_exit(rockchip_pinctrl_drv_unregister);
4005
4006 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
4007 MODULE_LICENSE("GPL");
4008 MODULE_ALIAS("platform:pinctrl-rockchip");
4009 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);