drivers/pinctrl/pinctrl-palmas.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * pinctrl-palmas.c -- TI PALMAS series pin control driver.
   4  *
   5  * Copyright (c) 2013, NVIDIA Corporation.
   6  *
   7  * Author: Laxman Dewangan <ldewangan@nvidia.com>
   8  */
   9
  10 #include <linux/delay.h>
  11 #include <linux/module.h>
  12 #include <linux/mfd/palmas.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pinctrl/machine.h>
  17 #include <linux/pinctrl/pinctrl.h>
  18 #include <linux/pinctrl/pinconf-generic.h>
  19 #include <linux/pinctrl/pinconf.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/pm.h>
  22 #include <linux/slab.h>
  23
  24 #include "core.h"
  25 #include "pinconf.h"
  26 #include "pinctrl-utils.h"
  27
  28 #define PALMAS_PIN_GPIO0_ID                             0
  29 #define PALMAS_PIN_GPIO1_VBUS_LED1_PWM1                 1
  30 #define PALMAS_PIN_GPIO2_REGEN_LED2_PWM2                2
  31 #define PALMAS_PIN_GPIO3_CHRG_DET                       3
  32 #define PALMAS_PIN_GPIO4_SYSEN1                         4
  33 #define PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL          5
  34 #define PALMAS_PIN_GPIO6_SYSEN2                         6
  35 #define PALMAS_PIN_GPIO7_MSECURE_PWRHOLD                7
  36 #define PALMAS_PIN_GPIO8_SIM1RSTI                       8
  37 #define PALMAS_PIN_GPIO9_LOW_VBAT                       9
  38 #define PALMAS_PIN_GPIO10_WIRELESS_CHRG1                10
  39 #define PALMAS_PIN_GPIO11_RCM                           11
  40 #define PALMAS_PIN_GPIO12_SIM2RSTO                      12
  41 #define PALMAS_PIN_GPIO13                               13
  42 #define PALMAS_PIN_GPIO14                               14
  43 #define PALMAS_PIN_GPIO15_SIM2RSTI                      15
  44 #define PALMAS_PIN_VAC                                  16
  45 #define PALMAS_PIN_POWERGOOD_USB_PSEL                   17
  46 #define PALMAS_PIN_NRESWARM                             18
  47 #define PALMAS_PIN_PWRDOWN                              19
  48 #define PALMAS_PIN_GPADC_START                          20
  49 #define PALMAS_PIN_RESET_IN                             21
  50 #define PALMAS_PIN_NSLEEP                               22
  51 #define PALMAS_PIN_ENABLE1                              23
  52 #define PALMAS_PIN_ENABLE2                              24
  53 #define PALMAS_PIN_INT                                  25
  54 #define PALMAS_PIN_NUM                                  (PALMAS_PIN_INT + 1)
  55
  56 struct palmas_pin_function {
  57         const char *name;
  58         const char * const *groups;
  59         unsigned ngroups;
  60 };
  61
  62 struct palmas_pctrl_chip_info {
  63         struct device *dev;
  64         struct pinctrl_dev *pctl;
  65         struct palmas *palmas;
  66         int pins_current_opt[PALMAS_PIN_NUM];
  67         const struct palmas_pin_function *functions;
  68         unsigned num_functions;
  69         const struct palmas_pingroup *pin_groups;
  70         int num_pin_groups;
  71         const struct pinctrl_pin_desc *pins;
  72         unsigned num_pins;
  73 };
  74
  75 static const struct pinctrl_pin_desc palmas_pins_desc[] = {
  76         PINCTRL_PIN(PALMAS_PIN_GPIO0_ID, "gpio0"),
  77         PINCTRL_PIN(PALMAS_PIN_GPIO1_VBUS_LED1_PWM1, "gpio1"),
  78         PINCTRL_PIN(PALMAS_PIN_GPIO2_REGEN_LED2_PWM2, "gpio2"),
  79         PINCTRL_PIN(PALMAS_PIN_GPIO3_CHRG_DET, "gpio3"),
  80         PINCTRL_PIN(PALMAS_PIN_GPIO4_SYSEN1, "gpio4"),
  81         PINCTRL_PIN(PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL, "gpio5"),
  82         PINCTRL_PIN(PALMAS_PIN_GPIO6_SYSEN2, "gpio6"),
  83         PINCTRL_PIN(PALMAS_PIN_GPIO7_MSECURE_PWRHOLD, "gpio7"),
  84         PINCTRL_PIN(PALMAS_PIN_GPIO8_SIM1RSTI, "gpio8"),
  85         PINCTRL_PIN(PALMAS_PIN_GPIO9_LOW_VBAT, "gpio9"),
  86         PINCTRL_PIN(PALMAS_PIN_GPIO10_WIRELESS_CHRG1, "gpio10"),
  87         PINCTRL_PIN(PALMAS_PIN_GPIO11_RCM, "gpio11"),
  88         PINCTRL_PIN(PALMAS_PIN_GPIO12_SIM2RSTO, "gpio12"),
  89         PINCTRL_PIN(PALMAS_PIN_GPIO13, "gpio13"),
  90         PINCTRL_PIN(PALMAS_PIN_GPIO14, "gpio14"),
  91         PINCTRL_PIN(PALMAS_PIN_GPIO15_SIM2RSTI, "gpio15"),
  92         PINCTRL_PIN(PALMAS_PIN_VAC, "vac"),
  93         PINCTRL_PIN(PALMAS_PIN_POWERGOOD_USB_PSEL, "powergood"),
  94         PINCTRL_PIN(PALMAS_PIN_NRESWARM, "nreswarm"),
  95         PINCTRL_PIN(PALMAS_PIN_PWRDOWN, "pwrdown"),
  96         PINCTRL_PIN(PALMAS_PIN_GPADC_START, "gpadc_start"),
  97         PINCTRL_PIN(PALMAS_PIN_RESET_IN, "reset_in"),
  98         PINCTRL_PIN(PALMAS_PIN_NSLEEP, "nsleep"),
  99         PINCTRL_PIN(PALMAS_PIN_ENABLE1, "enable1"),
 100         PINCTRL_PIN(PALMAS_PIN_ENABLE2, "enable2"),
 101         PINCTRL_PIN(PALMAS_PIN_INT, "int"),
 102 };
 103
 104 static const char * const opt0_groups[] = {
 105         "gpio0",
 106         "gpio1",
 107         "gpio2",
 108         "gpio3",
 109         "gpio4",
 110         "gpio5",
 111         "gpio6",
 112         "gpio7",
 113         "gpio8",
 114         "gpio9",
 115         "gpio10",
 116         "gpio11",
 117         "gpio12",
 118         "gpio13",
 119         "gpio14",
 120         "gpio15",
 121         "vac",
 122         "powergood",
 123         "nreswarm",
 124         "pwrdown",
 125         "gpadc_start",
 126         "reset_in",
 127         "nsleep",
 128         "enable1",
 129         "enable2",
 130         "int",
 131 };
 132
 133 static const char * const opt1_groups[] = {
 134         "gpio0",
 135         "gpio1",
 136         "gpio2",
 137         "gpio3",
 138         "gpio4",
 139         "gpio5",
 140         "gpio6",
 141         "gpio7",
 142         "gpio8",
 143         "gpio9",
 144         "gpio10",
 145         "gpio11",
 146         "gpio12",
 147         "gpio15",
 148         "vac",
 149         "powergood",
 150 };
 151
 152 static const char * const opt2_groups[] = {
 153         "gpio1",
 154         "gpio2",
 155         "gpio5",
 156         "gpio7",
 157 };
 158
 159 static const char * const opt3_groups[] = {
 160         "gpio1",
 161         "gpio2",
 162 };
 163
 164 static const char * const gpio_groups[] = {
 165         "gpio0",
 166         "gpio1",
 167         "gpio2",
 168         "gpio3",
 169         "gpio4",
 170         "gpio5",
 171         "gpio6",
 172         "gpio7",
 173         "gpio8",
 174         "gpio9",
 175         "gpio10",
 176         "gpio11",
 177         "gpio12",
 178         "gpio13",
 179         "gpio14",
 180         "gpio15",
 181 };
 182
 183 static const char * const led_groups[] = {
 184         "gpio1",
 185         "gpio2",
 186 };
 187
 188 static const char * const pwm_groups[] = {
 189         "gpio1",
 190         "gpio2",
 191 };
 192
 193 static const char * const regen_groups[] = {
 194         "gpio2",
 195 };
 196
 197 static const char * const sysen_groups[] = {
 198         "gpio4",
 199         "gpio6",
 200 };
 201
 202 static const char * const clk32kgaudio_groups[] = {
 203         "gpio5",
 204 };
 205
 206 static const char * const id_groups[] = {
 207         "gpio0",
 208 };
 209
 210 static const char * const vbus_det_groups[] = {
 211         "gpio1",
 212 };
 213
 214 static const char * const chrg_det_groups[] = {
 215         "gpio3",
 216 };
 217
 218 static const char * const vac_groups[] = {
 219         "vac",
 220 };
 221
 222 static const char * const vacok_groups[] = {
 223         "vac",
 224 };
 225
 226 static const char * const powergood_groups[] = {
 227         "powergood",
 228 };
 229
 230 static const char * const usb_psel_groups[] = {
 231         "gpio5",
 232         "powergood",
 233 };
 234
 235 static const char * const msecure_groups[] = {
 236         "gpio7",
 237 };
 238
 239 static const char * const pwrhold_groups[] = {
 240         "gpio7",
 241 };
 242
 243 static const char * const int_groups[] = {
 244         "int",
 245 };
 246
 247 static const char * const nreswarm_groups[] = {
 248         "nreswarm",
 249 };
 250
 251 static const char * const simrsto_groups[] = {
 252         "gpio12",
 253 };
 254
 255 static const char * const simrsti_groups[] = {
 256         "gpio8",
 257         "gpio15",
 258 };
 259
 260 static const char * const low_vbat_groups[] = {
 261         "gpio9",
 262 };
 263
 264 static const char * const wireless_chrg1_groups[] = {
 265         "gpio10",
 266 };
 267
 268 static const char * const rcm_groups[] = {
 269         "gpio11",
 270 };
 271
 272 static const char * const pwrdown_groups[] = {
 273         "pwrdown",
 274 };
 275
 276 static const char * const gpadc_start_groups[] = {
 277         "gpadc_start",
 278 };
 279
 280 static const char * const reset_in_groups[] = {
 281         "reset_in",
 282 };
 283
 284 static const char * const nsleep_groups[] = {
 285         "nsleep",
 286 };
 287
 288 static const char * const enable_groups[] = {
 289         "enable1",
 290         "enable2",
 291 };
 292
 293 #define FUNCTION_GROUPS                                 \
 294         FUNCTION_GROUP(opt0, OPTION0),                  \
 295         FUNCTION_GROUP(opt1, OPTION1),                  \
 296         FUNCTION_GROUP(opt2, OPTION2),                  \
 297         FUNCTION_GROUP(opt3, OPTION3),                  \
 298         FUNCTION_GROUP(gpio, GPIO),                     \
 299         FUNCTION_GROUP(led, LED),                       \
 300         FUNCTION_GROUP(pwm, PWM),                       \
 301         FUNCTION_GROUP(regen, REGEN),                   \
 302         FUNCTION_GROUP(sysen, SYSEN),                   \
 303         FUNCTION_GROUP(clk32kgaudio, CLK32KGAUDIO),     \
 304         FUNCTION_GROUP(id, ID),                         \
 305         FUNCTION_GROUP(vbus_det, VBUS_DET),             \
 306         FUNCTION_GROUP(chrg_det, CHRG_DET),             \
 307         FUNCTION_GROUP(vac, VAC),                       \
 308         FUNCTION_GROUP(vacok, VACOK),                   \
 309         FUNCTION_GROUP(powergood, POWERGOOD),           \
 310         FUNCTION_GROUP(usb_psel, USB_PSEL),             \
 311         FUNCTION_GROUP(msecure, MSECURE),               \
 312         FUNCTION_GROUP(pwrhold, PWRHOLD),               \
 313         FUNCTION_GROUP(int, INT),                       \
 314         FUNCTION_GROUP(nreswarm, NRESWARM),             \
 315         FUNCTION_GROUP(simrsto, SIMRSTO),               \
 316         FUNCTION_GROUP(simrsti, SIMRSTI),               \
 317         FUNCTION_GROUP(low_vbat, LOW_VBAT),             \
 318         FUNCTION_GROUP(wireless_chrg1, WIRELESS_CHRG1), \
 319         FUNCTION_GROUP(rcm, RCM),                       \
 320         FUNCTION_GROUP(pwrdown, PWRDOWN),               \
 321         FUNCTION_GROUP(gpadc_start, GPADC_START),       \
 322         FUNCTION_GROUP(reset_in, RESET_IN),             \
 323         FUNCTION_GROUP(nsleep, NSLEEP),                 \
 324         FUNCTION_GROUP(enable, ENABLE)
 325
 326 static const struct palmas_pin_function palmas_pin_function[] = {
 327 #undef FUNCTION_GROUP
 328 #define FUNCTION_GROUP(fname, mux)                      \
 329         {                                               \
 330                 .name = #fname,                         \
 331                 .groups = fname##_groups,               \
 332                 .ngroups = ARRAY_SIZE(fname##_groups),  \
 333         }
 334
 335         FUNCTION_GROUPS,
 336 };
 337
 338 enum palmas_pinmux {
 339 #undef FUNCTION_GROUP
 340 #define FUNCTION_GROUP(fname, mux)      PALMAS_PINMUX_##mux
 341         FUNCTION_GROUPS,
 342         PALMAS_PINMUX_NA = 0xFFFF,
 343 };
 344
 345 struct palmas_pins_pullup_dn_info {
 346         int pullup_dn_reg_base;
 347         int pullup_dn_reg_add;
 348         int pullup_dn_mask;
 349         int normal_val;
 350         int pull_up_val;
 351         int pull_dn_val;
 352 };
 353
 354 struct palmas_pins_od_info {
 355         int od_reg_base;
 356         int od_reg_add;
 357         int od_mask;
 358         int od_enable;
 359         int od_disable;
 360 };
 361
 362 struct palmas_pin_info {
 363         enum palmas_pinmux mux_opt;
 364         const struct palmas_pins_pullup_dn_info *pud_info;
 365         const struct palmas_pins_od_info *od_info;
 366 };
 367
 368 struct palmas_pingroup {
 369         const char *name;
 370         const unsigned pins[1];
 371         unsigned npins;
 372         unsigned mux_reg_base;
 373         unsigned mux_reg_add;
 374         unsigned mux_reg_mask;
 375         unsigned mux_bit_shift;
 376         const struct palmas_pin_info *opt[4];
 377 };
 378
 379 #define PULL_UP_DN(_name, _rbase, _add, _mask, _nv, _uv, _dv)           \
 380 static const struct palmas_pins_pullup_dn_info pud_##_name##_info = {   \
 381         .pullup_dn_reg_base = PALMAS_##_rbase##_BASE,                   \
 382         .pullup_dn_reg_add = _add,                                      \
 383         .pullup_dn_mask = _mask,                                        \
 384         .normal_val = _nv,                                              \
 385         .pull_up_val = _uv,                                             \
 386         .pull_dn_val = _dv,                                             \
 387 }
 388
 389 PULL_UP_DN(nreswarm,    PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL1,       0x2,    0x0,    0x2,    -1);
 390 PULL_UP_DN(pwrdown,     PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL1,       0x4,    0x0,    -1,     0x4);
 391 PULL_UP_DN(gpadc_start, PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL1,       0x30,   0x0,    0x20,   0x10);
 392 PULL_UP_DN(reset_in,    PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL1,       0x40,   0x0,    -1,     0x40);
 393 PULL_UP_DN(nsleep,      PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL2,       0x3,    0x0,    0x2,    0x1);
 394 PULL_UP_DN(enable1,     PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL2,       0xC,    0x0,    0x8,    0x4);
 395 PULL_UP_DN(enable2,     PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL2,       0x30,   0x0,    0x20,   0x10);
 396 PULL_UP_DN(vacok,       PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL3,       0x40,   0x0,    -1,     0x40);
 397 PULL_UP_DN(chrg_det,    PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL3,       0x10,   0x0,    -1,     0x10);
 398 PULL_UP_DN(pwrhold,     PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL3,       0x4,    0x0,    -1,     0x4);
 399 PULL_UP_DN(msecure,     PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL3,       0x1,    0x0,    -1,     0x1);
 400 PULL_UP_DN(id,          USB_OTG,        PALMAS_USB_ID_CTRL_SET,         0x40,   0x0,    0x40,   -1);
 401 PULL_UP_DN(gpio0,       GPIO,           PALMAS_PU_PD_GPIO_CTRL1,        0x04,   0,      -1,     1);
 402 PULL_UP_DN(gpio1,       GPIO,           PALMAS_PU_PD_GPIO_CTRL1,        0x0C,   0,      0x8,    0x4);
 403 PULL_UP_DN(gpio2,       GPIO,           PALMAS_PU_PD_GPIO_CTRL1,        0x30,   0x0,    0x20,   0x10);
 404 PULL_UP_DN(gpio3,       GPIO,           PALMAS_PU_PD_GPIO_CTRL1,        0x40,   0x0,    -1,     0x40);
 405 PULL_UP_DN(gpio4,       GPIO,           PALMAS_PU_PD_GPIO_CTRL2,        0x03,   0x0,    0x2,    0x1);
 406 PULL_UP_DN(gpio5,       GPIO,           PALMAS_PU_PD_GPIO_CTRL2,        0x0c,   0x0,    0x8,    0x4);
 407 PULL_UP_DN(gpio6,       GPIO,           PALMAS_PU_PD_GPIO_CTRL2,        0x30,   0x0,    0x20,   0x10);
 408 PULL_UP_DN(gpio7,       GPIO,           PALMAS_PU_PD_GPIO_CTRL2,        0x40,   0x0,    -1,     0x40);
 409 PULL_UP_DN(gpio9,       GPIO,           PALMAS_PU_PD_GPIO_CTRL3,        0x0C,   0x0,    0x8,    0x4);
 410 PULL_UP_DN(gpio10,      GPIO,           PALMAS_PU_PD_GPIO_CTRL3,        0x30,   0x0,    0x20,   0x10);
 411 PULL_UP_DN(gpio11,      GPIO,           PALMAS_PU_PD_GPIO_CTRL3,        0xC0,   0x0,    0x80,   0x40);
 412 PULL_UP_DN(gpio13,      GPIO,           PALMAS_PU_PD_GPIO_CTRL4,        0x04,   0x0,    -1,     0x04);
 413 PULL_UP_DN(gpio14,      GPIO,           PALMAS_PU_PD_GPIO_CTRL4,        0x30,   0x0,    0x20,   0x10);
 414
 415 #define OD_INFO(_name, _rbase, _add, _mask, _ev, _dv)           \
 416 static const struct palmas_pins_od_info od_##_name##_info = {   \
 417         .od_reg_base = PALMAS_##_rbase##_BASE,                  \
 418         .od_reg_add = _add,                                     \
 419         .od_mask = _mask,                                       \
 420         .od_enable = _ev,                                       \
 421         .od_disable = _dv,                                      \
 422 }
 423
 424 OD_INFO(gpio1,  GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL,     0x1,    0x1,    0x0);
 425 OD_INFO(gpio2,  GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL,     0x2,    0x2,    0x0);
 426 OD_INFO(gpio5,  GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL,     0x20,   0x20,   0x0);
 427 OD_INFO(gpio10, GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL2,    0x04,   0x04,   0x0);
 428 OD_INFO(gpio13, GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL2,    0x20,   0x20,   0x0);
 429 OD_INFO(int,            PU_PD_OD,       PALMAS_OD_OUTPUT_CTRL,  0x8,    0x8,    0x0);
 430 OD_INFO(pwm1,           PU_PD_OD,       PALMAS_OD_OUTPUT_CTRL,  0x20,   0x20,   0x0);
 431 OD_INFO(pwm2,           PU_PD_OD,       PALMAS_OD_OUTPUT_CTRL,  0x80,   0x80,   0x0);
 432 OD_INFO(vbus_det,       PU_PD_OD,       PALMAS_OD_OUTPUT_CTRL,  0x40,   0x40,   0x0);
 433
 434 #define PIN_INFO(_name, _id, _pud_info, _od_info)               \
 435 static const struct palmas_pin_info pin_##_name##_info = {      \
 436         .mux_opt = PALMAS_PINMUX_##_id,                         \
 437         .pud_info = _pud_info,                                  \
 438         .od_info = _od_info                                     \
 439 }
 440
 441 PIN_INFO(gpio0,         GPIO,           &pud_gpio0_info,        NULL);
 442 PIN_INFO(gpio1,         GPIO,           &pud_gpio1_info,        &od_gpio1_info);
 443 PIN_INFO(gpio2,         GPIO,           &pud_gpio2_info,        &od_gpio2_info);
 444 PIN_INFO(gpio3,         GPIO,           &pud_gpio3_info,        NULL);
 445 PIN_INFO(gpio4,         GPIO,           &pud_gpio4_info,        NULL);
 446 PIN_INFO(gpio5,         GPIO,           &pud_gpio5_info,        &od_gpio5_info);
 447 PIN_INFO(gpio6,         GPIO,           &pud_gpio6_info,        NULL);
 448 PIN_INFO(gpio7,         GPIO,           &pud_gpio7_info,        NULL);
 449 PIN_INFO(gpio8,         GPIO,           NULL,                   NULL);
 450 PIN_INFO(gpio9,         GPIO,           &pud_gpio9_info,        NULL);
 451 PIN_INFO(gpio10,        GPIO,           &pud_gpio10_info,       &od_gpio10_info);
 452 PIN_INFO(gpio11,        GPIO,           &pud_gpio11_info,       NULL);
 453 PIN_INFO(gpio12,        GPIO,           NULL,                   NULL);
 454 PIN_INFO(gpio13,        GPIO,           &pud_gpio13_info,       &od_gpio13_info);
 455 PIN_INFO(gpio14,        GPIO,           &pud_gpio14_info,       NULL);
 456 PIN_INFO(gpio15,        GPIO,           NULL,                   NULL);
 457 PIN_INFO(id,            ID,             &pud_id_info,           NULL);
 458 PIN_INFO(led1,          LED,            NULL,                   NULL);
 459 PIN_INFO(led2,          LED,            NULL,                   NULL);
 460 PIN_INFO(regen,         REGEN,          NULL,                   NULL);
 461 PIN_INFO(sysen1,        SYSEN,          NULL,                   NULL);
 462 PIN_INFO(sysen2,        SYSEN,          NULL,                   NULL);
 463 PIN_INFO(int,           INT,            NULL,                   &od_int_info);
 464 PIN_INFO(pwm1,          PWM,            NULL,                   &od_pwm1_info);
 465 PIN_INFO(pwm2,          PWM,            NULL,                   &od_pwm2_info);
 466 PIN_INFO(vacok,         VACOK,          &pud_vacok_info,        NULL);
 467 PIN_INFO(chrg_det,      CHRG_DET,       &pud_chrg_det_info,     NULL);
 468 PIN_INFO(pwrhold,       PWRHOLD,        &pud_pwrhold_info,      NULL);
 469 PIN_INFO(msecure,       MSECURE,        &pud_msecure_info,      NULL);
 470 PIN_INFO(nreswarm,      NA,             &pud_nreswarm_info,     NULL);
 471 PIN_INFO(pwrdown,       NA,             &pud_pwrdown_info,      NULL);
 472 PIN_INFO(gpadc_start,   NA,             &pud_gpadc_start_info,  NULL);
 473 PIN_INFO(reset_in,      NA,             &pud_reset_in_info,     NULL);
 474 PIN_INFO(nsleep,        NA,             &pud_nsleep_info,       NULL);
 475 PIN_INFO(enable1,       NA,             &pud_enable1_info,      NULL);
 476 PIN_INFO(enable2,       NA,             &pud_enable2_info,      NULL);
 477 PIN_INFO(clk32kgaudio,  CLK32KGAUDIO,   NULL,                   NULL);
 478 PIN_INFO(usb_psel,      USB_PSEL,       NULL,                   NULL);
 479 PIN_INFO(vac,           VAC,            NULL,                   NULL);
 480 PIN_INFO(powergood,     POWERGOOD,      NULL,                   NULL);
 481 PIN_INFO(vbus_det,      VBUS_DET,       NULL,                   &od_vbus_det_info);
 482 PIN_INFO(sim1rsti,      SIMRSTI,        NULL,                   NULL);
 483 PIN_INFO(low_vbat,      LOW_VBAT,       NULL,                   NULL);
 484 PIN_INFO(rcm,           RCM,            NULL,                   NULL);
 485 PIN_INFO(sim2rsto,      SIMRSTO,        NULL,                   NULL);
 486 PIN_INFO(sim2rsti,      SIMRSTI,        NULL,                   NULL);
 487 PIN_INFO(wireless_chrg1,        WIRELESS_CHRG1, NULL,           NULL);
 488
 489 #define PALMAS_PRIMARY_SECONDARY_NONE   0
 490 #define PALMAS_NONE_BASE                0
 491 #define PALMAS_PRIMARY_SECONDARY_INPUT3 PALMAS_PU_PD_INPUT_CTRL3
 492
 493 #define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3)  \
 494         {                                                               \
 495                 .name = #pg_name,                                       \
 496                 .pins = {PALMAS_PIN_##pin_id},                          \
 497                 .npins = 1,                                             \
 498                 .mux_reg_base = PALMAS_##base##_BASE,                   \
 499                 .mux_reg_add = PALMAS_PRIMARY_SECONDARY_##reg,          \
 500                 .mux_reg_mask = _mask,                                  \
 501                 .mux_bit_shift = _bshift,                               \
 502                 .opt = {                                                \
 503                         o0,                                             \
 504                         o1,                                             \
 505                         o2,                                             \
 506                         o3,                                             \
 507                 },                                                      \
 508         }
 509
 510 static const struct palmas_pingroup tps65913_pingroups[] = {
 511         PALMAS_PINGROUP(gpio0,  GPIO0_ID,                       PU_PD_OD,       PAD1,   0x4,    0x2,    &pin_gpio0_info,        &pin_id_info,           NULL,           NULL),
 512         PALMAS_PINGROUP(gpio1,  GPIO1_VBUS_LED1_PWM1,           PU_PD_OD,       PAD1,   0x18,   0x3,    &pin_gpio1_info,        &pin_vbus_det_info,     &pin_led1_info, &pin_pwm1_info),
 513         PALMAS_PINGROUP(gpio2,  GPIO2_REGEN_LED2_PWM2,          PU_PD_OD,       PAD1,   0x60,   0x5,    &pin_gpio2_info,        &pin_regen_info,        &pin_led2_info, &pin_pwm2_info),
 514         PALMAS_PINGROUP(gpio3,  GPIO3_CHRG_DET,                 PU_PD_OD,       PAD1,   0x80,   0x7,    &pin_gpio3_info,        &pin_chrg_det_info,     NULL,           NULL),
 515         PALMAS_PINGROUP(gpio4,  GPIO4_SYSEN1,                   PU_PD_OD,       PAD1,   0x01,   0x0,    &pin_gpio4_info,        &pin_sysen1_info,       NULL,           NULL),
 516         PALMAS_PINGROUP(gpio5,  GPIO5_CLK32KGAUDIO_USB_PSEL,    PU_PD_OD,       PAD2,   0x6,    0x1,    &pin_gpio5_info,        &pin_clk32kgaudio_info, &pin_usb_psel_info,     NULL),
 517         PALMAS_PINGROUP(gpio6,  GPIO6_SYSEN2,                   PU_PD_OD,       PAD2,   0x08,   0x3,    &pin_gpio6_info,        &pin_sysen2_info,       NULL,           NULL),
 518         PALMAS_PINGROUP(gpio7,  GPIO7_MSECURE_PWRHOLD,          PU_PD_OD,       PAD2,   0x30,   0x4,    &pin_gpio7_info,        &pin_msecure_info,      &pin_pwrhold_info,      NULL),
 519         PALMAS_PINGROUP(vac,    VAC,                            PU_PD_OD,       PAD1,   0x02,   0x1,    &pin_vac_info,          &pin_vacok_info,        NULL,           NULL),
 520         PALMAS_PINGROUP(powergood,      POWERGOOD_USB_PSEL,     PU_PD_OD,       PAD1,   0x01,   0x0,    &pin_powergood_info,    &pin_usb_psel_info,     NULL,   NULL),
 521         PALMAS_PINGROUP(nreswarm,       NRESWARM,               NONE,           NONE,   0x0,    0x0,    &pin_nreswarm_info,     NULL,                   NULL,           NULL),
 522         PALMAS_PINGROUP(pwrdown,        PWRDOWN,                NONE,           NONE,   0x0,    0x0,    &pin_pwrdown_info,      NULL,                   NULL,           NULL),
 523         PALMAS_PINGROUP(gpadc_start,    GPADC_START,            NONE,           NONE,   0x0,    0x0,    &pin_gpadc_start_info,  NULL,                   NULL,           NULL),
 524         PALMAS_PINGROUP(reset_in,       RESET_IN,               NONE,           NONE,   0x0,    0x0,    &pin_reset_in_info,     NULL,                   NULL,           NULL),
 525         PALMAS_PINGROUP(nsleep,         NSLEEP,                 NONE,           NONE,   0x0,    0x0,    &pin_nsleep_info,       NULL,                   NULL,           NULL),
 526         PALMAS_PINGROUP(enable1,        ENABLE1,                NONE,           NONE,   0x0,    0x0,    &pin_enable1_info,      NULL,                   NULL,           NULL),
 527         PALMAS_PINGROUP(enable2,        ENABLE2,                NONE,           NONE,   0x0,    0x0,    &pin_enable2_info,      NULL,                   NULL,           NULL),
 528         PALMAS_PINGROUP(int,            INT,                    NONE,           NONE,   0x0,    0x0,    &pin_int_info,          NULL,                   NULL,           NULL),
 529 };
 530
 531 static const struct palmas_pingroup tps80036_pingroups[] = {
 532         PALMAS_PINGROUP(gpio0,  GPIO0_ID,                       PU_PD_OD,       PAD1,   0x4,    0x2,    &pin_gpio0_info,        &pin_id_info,           NULL,           NULL),
 533         PALMAS_PINGROUP(gpio1,  GPIO1_VBUS_LED1_PWM1,           PU_PD_OD,       PAD1,   0x18,   0x3,    &pin_gpio1_info,        &pin_vbus_det_info,     &pin_led1_info, &pin_pwm1_info),
 534         PALMAS_PINGROUP(gpio2,  GPIO2_REGEN_LED2_PWM2,          PU_PD_OD,       PAD1,   0x60,   0x5,    &pin_gpio2_info,        &pin_regen_info,        &pin_led2_info, &pin_pwm2_info),
 535         PALMAS_PINGROUP(gpio3,  GPIO3_CHRG_DET,                 PU_PD_OD,       PAD1,   0x80,   0x7,    &pin_gpio3_info,        &pin_chrg_det_info,     NULL,           NULL),
 536         PALMAS_PINGROUP(gpio4,  GPIO4_SYSEN1,                   PU_PD_OD,       PAD1,   0x01,   0x0,    &pin_gpio4_info,        &pin_sysen1_info,       NULL,           NULL),
 537         PALMAS_PINGROUP(gpio5,  GPIO5_CLK32KGAUDIO_USB_PSEL,    PU_PD_OD,       PAD2,   0x6,    0x1,    &pin_gpio5_info,        &pin_clk32kgaudio_info, &pin_usb_psel_info,     NULL),
 538         PALMAS_PINGROUP(gpio6,  GPIO6_SYSEN2,                   PU_PD_OD,       PAD2,   0x08,   0x3,    &pin_gpio6_info,        &pin_sysen2_info,       NULL,           NULL),
 539         PALMAS_PINGROUP(gpio7,  GPIO7_MSECURE_PWRHOLD,          PU_PD_OD,       PAD2,   0x30,   0x4,    &pin_gpio7_info,        &pin_msecure_info,      &pin_pwrhold_info,      NULL),
 540         PALMAS_PINGROUP(gpio8,  GPIO8_SIM1RSTI,                 PU_PD_OD,       PAD4,   0x01,   0x0,    &pin_gpio8_info,        &pin_sim1rsti_info,     NULL,           NULL),
 541         PALMAS_PINGROUP(gpio9,  GPIO9_LOW_VBAT,                 PU_PD_OD,       PAD4,   0x02,   0x1,    &pin_gpio9_info,        &pin_low_vbat_info,     NULL,           NULL),
 542         PALMAS_PINGROUP(gpio10, GPIO10_WIRELESS_CHRG1,          PU_PD_OD,       PAD4,   0x04,   0x2,    &pin_gpio10_info,       &pin_wireless_chrg1_info,       NULL,   NULL),
 543         PALMAS_PINGROUP(gpio11, GPIO11_RCM,                     PU_PD_OD,       PAD4,   0x08,   0x3,    &pin_gpio11_info,       &pin_rcm_info,          NULL,           NULL),
 544         PALMAS_PINGROUP(gpio12, GPIO12_SIM2RSTO,                PU_PD_OD,       PAD4,   0x10,   0x4,    &pin_gpio12_info,       &pin_sim2rsto_info,     NULL,           NULL),
 545         PALMAS_PINGROUP(gpio13, GPIO13,                         NONE,           NONE,   0x00,   0x0,    &pin_gpio13_info,       NULL,                   NULL,           NULL),
 546         PALMAS_PINGROUP(gpio14, GPIO14,                         NONE,           NONE,   0x00,   0x0,    &pin_gpio14_info,       NULL,                   NULL,           NULL),
 547         PALMAS_PINGROUP(gpio15, GPIO15_SIM2RSTI,                PU_PD_OD,       PAD4,   0x80,   0x7,    &pin_gpio15_info,       &pin_sim2rsti_info,     NULL,           NULL),
 548         PALMAS_PINGROUP(vac,    VAC,                            PU_PD_OD,       PAD1,   0x02,   0x1,    &pin_vac_info,          &pin_vacok_info,        NULL,           NULL),
 549         PALMAS_PINGROUP(powergood,      POWERGOOD_USB_PSEL,     PU_PD_OD,       PAD1,   0x01,   0x0,    &pin_powergood_info,    &pin_usb_psel_info,     NULL,   NULL),
 550         PALMAS_PINGROUP(nreswarm,       NRESWARM,               NONE,           NONE,   0x0,    0x0,    &pin_nreswarm_info,     NULL,                   NULL,           NULL),
 551         PALMAS_PINGROUP(pwrdown,        PWRDOWN,                NONE,           NONE,   0x0,    0x0,    &pin_pwrdown_info,      NULL,                   NULL,           NULL),
 552         PALMAS_PINGROUP(gpadc_start,    GPADC_START,            NONE,           NONE,   0x0,    0x0,    &pin_gpadc_start_info,  NULL,                   NULL,           NULL),
 553         PALMAS_PINGROUP(reset_in,       RESET_IN,               NONE,           NONE,   0x0,    0x0,    &pin_reset_in_info,     NULL,                   NULL,           NULL),
 554         PALMAS_PINGROUP(nsleep,         NSLEEP,                 NONE,           NONE,   0x0,    0x0,    &pin_nsleep_info,       NULL,                   NULL,           NULL),
 555         PALMAS_PINGROUP(enable1,        ENABLE1,                NONE,           NONE,   0x0,    0x0,    &pin_enable1_info,      NULL,                   NULL,           NULL),
 556         PALMAS_PINGROUP(enable2,        ENABLE2,                NONE,           NONE,   0x0,    0x0,    &pin_enable2_info,      NULL,                   NULL,           NULL),
 557         PALMAS_PINGROUP(int,            INT,                    NONE,           NONE,   0x0,    0x0,    &pin_int_info,          NULL,                   NULL,           NULL),
 558 };
 559
 560 static int palmas_pinctrl_get_pin_mux(struct palmas_pctrl_chip_info *pci)
 561 {
 562         const struct palmas_pingroup *g;
 563         unsigned int val;
 564         int ret;
 565         int i;
 566
 567         for (i = 0; i < pci->num_pin_groups; ++i) {
 568                 g = &pci->pin_groups[i];
 569                 if (g->mux_reg_base == PALMAS_NONE_BASE) {
 570                         pci->pins_current_opt[i] = 0;
 571                         continue;
 572                 }
 573                 ret = palmas_read(pci->palmas, g->mux_reg_base,
 574                                 g->mux_reg_add, &val);
 575                 if (ret < 0) {
 576                         dev_err(pci->dev, "mux_reg 0x%02x read failed: %d\n",
 577                                         g->mux_reg_add, ret);
 578                         return ret;
 579                 }
 580                 val &= g->mux_reg_mask;
 581                 pci->pins_current_opt[i] = val >> g->mux_bit_shift;
 582         }
 583         return 0;
 584 }
 585
 586 static int palmas_pinctrl_set_dvfs1(struct palmas_pctrl_chip_info *pci,
 587                 bool enable)
 588 {
 589         int ret;
 590         int val;
 591
 592         val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 : 0;
 593         ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
 594                         PALMAS_PRIMARY_SECONDARY_PAD3,
 595                         PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1, val);
 596         if (ret < 0)
 597                 dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
 598         return ret;
 599 }
 600
 601 static int palmas_pinctrl_set_dvfs2(struct palmas_pctrl_chip_info *pci,
 602                 bool enable)
 603 {
 604         int ret;
 605         int val;
 606
 607         val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 : 0;
 608         ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
 609                         PALMAS_PRIMARY_SECONDARY_PAD3,
 610                         PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2, val);
 611         if (ret < 0)
 612                 dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
 613         return ret;
 614 }
 615
 616 static int palmas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 617 {
 618         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 619
 620         return pci->num_pin_groups;
 621 }
 622
 623 static const char *palmas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 624                 unsigned group)
 625 {
 626         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 627
 628         return pci->pin_groups[group].name;
 629 }
 630
 631 static int palmas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 632                 unsigned group, const unsigned **pins, unsigned *num_pins)
 633 {
 634         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 635
 636         *pins = pci->pin_groups[group].pins;
 637         *num_pins = pci->pin_groups[group].npins;
 638         return 0;
 639 }
 640
 641 static const struct pinctrl_ops palmas_pinctrl_ops = {
 642         .get_groups_count = palmas_pinctrl_get_groups_count,
 643         .get_group_name = palmas_pinctrl_get_group_name,
 644         .get_group_pins = palmas_pinctrl_get_group_pins,
 645         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 646         .dt_free_map = pinctrl_utils_free_map,
 647 };
 648
 649 static int palmas_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 650 {
 651         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 652
 653         return pci->num_functions;
 654 }
 655
 656 static const char *palmas_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 657                         unsigned function)
 658 {
 659         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 660
 661         return pci->functions[function].name;
 662 }
 663
 664 static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 665                 unsigned function, const char * const **groups,
 666                 unsigned * const num_groups)
 667 {
 668         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 669
 670         *groups = pci->functions[function].groups;
 671         *num_groups = pci->functions[function].ngroups;
 672         return 0;
 673 }
 674
 675 static int palmas_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 676                 unsigned function,
 677                 unsigned group)
 678 {
 679         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 680         const struct palmas_pingroup *g;
 681         int i;
 682         int ret;
 683
 684         g = &pci->pin_groups[group];
 685
 686         /* If direct option is provided here */
 687         if (function <= PALMAS_PINMUX_OPTION3) {
 688                 if (!g->opt[function]) {
 689                         dev_err(pci->dev, "Pin %s does not support option %d\n",
 690                                 g->name, function);
 691                         return -EINVAL;
 692                 }
 693                 i = function;
 694         } else {
 695                 for (i = 0; i < ARRAY_SIZE(g->opt); i++) {
 696                         if (!g->opt[i])
 697                                 continue;
 698                         if (g->opt[i]->mux_opt == function)
 699                                 break;
 700                 }
 701                 if (WARN_ON(i == ARRAY_SIZE(g->opt))) {
 702                         dev_err(pci->dev, "Pin %s does not support option %d\n",
 703                                 g->name, function);
 704                         return -EINVAL;
 705                 }
 706         }
 707
 708         if (g->mux_reg_base == PALMAS_NONE_BASE) {
 709                 if (WARN_ON(i != 0))
 710                         return -EINVAL;
 711                 return 0;
 712         }
 713
 714         dev_dbg(pci->dev, "%s(): Base0x%02x:0x%02x:0x%02x:0x%02x\n",
 715                         __func__, g->mux_reg_base, g->mux_reg_add,
 716                         g->mux_reg_mask, i << g->mux_bit_shift);
 717
 718         ret = palmas_update_bits(pci->palmas, g->mux_reg_base, g->mux_reg_add,
 719                         g->mux_reg_mask, i << g->mux_bit_shift);
 720         if (ret < 0) {
 721                 dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
 722                                 g->mux_reg_add, ret);
 723                 return ret;
 724         }
 725         pci->pins_current_opt[group] = i;
 726         return 0;
 727 }
 728
 729 static const struct pinmux_ops palmas_pinmux_ops = {
 730         .get_functions_count = palmas_pinctrl_get_funcs_count,
 731         .get_function_name = palmas_pinctrl_get_func_name,
 732         .get_function_groups = palmas_pinctrl_get_func_groups,
 733         .set_mux = palmas_pinctrl_set_mux,
 734 };
 735
 736 static int palmas_pinconf_get(struct pinctrl_dev *pctldev,
 737                         unsigned pin, unsigned long *config)
 738 {
 739         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 740         enum pin_config_param param = pinconf_to_config_param(*config);
 741         const struct palmas_pingroup *g;
 742         const struct palmas_pin_info *opt;
 743         unsigned int val;
 744         int ret;
 745         int base, add;
 746         int rval;
 747         int arg;
 748         int group_nr;
 749
 750         for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
 751                 if (pci->pin_groups[group_nr].pins[0] == pin)
 752                         break;
 753         }
 754
 755         if (group_nr == pci->num_pin_groups) {
 756                 dev_err(pci->dev,
 757                         "Pinconf is not supported for pin-id %d\n", pin);
 758                 return -ENOTSUPP;
 759         }
 760
 761         g = &pci->pin_groups[group_nr];
 762         opt = g->opt[pci->pins_current_opt[group_nr]];
 763         if (!opt) {
 764                 dev_err(pci->dev,
 765                         "Pinconf is not supported for pin %s\n", g->name);
 766                 return -ENOTSUPP;
 767         }
 768
 769         switch (param) {
 770         case PIN_CONFIG_BIAS_DISABLE:
 771         case PIN_CONFIG_BIAS_PULL_UP:
 772         case PIN_CONFIG_BIAS_PULL_DOWN:
 773                 if (!opt->pud_info) {
 774                         dev_err(pci->dev,
 775                                 "PULL control not supported for pin %s\n",
 776                                 g->name);
 777                         return -ENOTSUPP;
 778                 }
 779                 base = opt->pud_info->pullup_dn_reg_base;
 780                 add = opt->pud_info->pullup_dn_reg_add;
 781                 ret = palmas_read(pci->palmas, base, add, &val);
 782                 if (ret < 0) {
 783                         dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
 784                                 add, ret);
 785                         return ret;
 786                 }
 787
 788                 rval = val & opt->pud_info->pullup_dn_mask;
 789                 arg = 0;
 790                 if ((opt->pud_info->normal_val >= 0) &&
 791                                 (opt->pud_info->normal_val == rval) &&
 792                                 (param == PIN_CONFIG_BIAS_DISABLE))
 793                         arg = 1;
 794                 else if ((opt->pud_info->pull_up_val >= 0) &&
 795                                 (opt->pud_info->pull_up_val == rval) &&
 796                                 (param == PIN_CONFIG_BIAS_PULL_UP))
 797                         arg = 1;
 798                 else if ((opt->pud_info->pull_dn_val >= 0) &&
 799                                 (opt->pud_info->pull_dn_val == rval) &&
 800                                 (param == PIN_CONFIG_BIAS_PULL_DOWN))
 801                         arg = 1;
 802                 break;
 803
 804         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 805                 if (!opt->od_info) {
 806                         dev_err(pci->dev,
 807                                 "OD control not supported for pin %s\n",
 808                                 g->name);
 809                         return -ENOTSUPP;
 810                 }
 811                 base = opt->od_info->od_reg_base;
 812                 add = opt->od_info->od_reg_add;
 813                 ret = palmas_read(pci->palmas, base, add, &val);
 814                 if (ret < 0) {
 815                         dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
 816                                 add, ret);
 817                         return ret;
 818                 }
 819                 rval = val & opt->od_info->od_mask;
 820                 arg = -1;
 821                 if ((opt->od_info->od_disable >= 0) &&
 822                                 (opt->od_info->od_disable == rval))
 823                         arg = 0;
 824                 else if ((opt->od_info->od_enable >= 0) &&
 825                                         (opt->od_info->od_enable == rval))
 826                         arg = 1;
 827                 if (arg < 0) {
 828                         dev_err(pci->dev,
 829                                 "OD control not supported for pin %s\n",
 830                                 g->name);
 831                         return -ENOTSUPP;
 832                 }
 833                 break;
 834
 835         default:
 836                 dev_err(pci->dev, "Properties not supported\n");
 837                 return -ENOTSUPP;
 838         }
 839
 840         *config = pinconf_to_config_packed(param, (u16)arg);
 841         return 0;
 842 }
 843
 844 static int palmas_pinconf_set(struct pinctrl_dev *pctldev,
 845                         unsigned pin, unsigned long *configs,
 846                         unsigned num_configs)
 847 {
 848         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 849         enum pin_config_param param;
 850         u32 param_val;
 851         const struct palmas_pingroup *g;
 852         const struct palmas_pin_info *opt;
 853         int ret;
 854         int base, add, mask;
 855         int rval;
 856         int group_nr;
 857         int i;
 858
 859         for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
 860                 if (pci->pin_groups[group_nr].pins[0] == pin)
 861                         break;
 862         }
 863
 864         if (group_nr == pci->num_pin_groups) {
 865                 dev_err(pci->dev,
 866                         "Pinconf is not supported for pin-id %d\n", pin);
 867                 return -ENOTSUPP;
 868         }
 869
 870         g = &pci->pin_groups[group_nr];
 871         opt = g->opt[pci->pins_current_opt[group_nr]];
 872         if (!opt) {
 873                 dev_err(pci->dev,
 874                         "Pinconf is not supported for pin %s\n", g->name);
 875                 return -ENOTSUPP;
 876         }
 877
 878         for (i = 0; i < num_configs; i++) {
 879                 param = pinconf_to_config_param(configs[i]);
 880                 param_val = pinconf_to_config_argument(configs[i]);
 881
 882                 switch (param) {
 883                 case PIN_CONFIG_BIAS_DISABLE:
 884                 case PIN_CONFIG_BIAS_PULL_UP:
 885                 case PIN_CONFIG_BIAS_PULL_DOWN:
 886                         if (!opt->pud_info) {
 887                                 dev_err(pci->dev,
 888                                         "PULL control not supported for pin %s\n",
 889                                         g->name);
 890                                 return -ENOTSUPP;
 891                         }
 892                         base = opt->pud_info->pullup_dn_reg_base;
 893                         add = opt->pud_info->pullup_dn_reg_add;
 894                         mask = opt->pud_info->pullup_dn_mask;
 895
 896                         if (param == PIN_CONFIG_BIAS_DISABLE)
 897                                 rval = opt->pud_info->normal_val;
 898                         else if (param == PIN_CONFIG_BIAS_PULL_UP)
 899                                 rval = opt->pud_info->pull_up_val;
 900                         else
 901                                 rval = opt->pud_info->pull_dn_val;
 902
 903                         if (rval < 0) {
 904                                 dev_err(pci->dev,
 905                                         "PULL control not supported for pin %s\n",
 906                                         g->name);
 907                                 return -ENOTSUPP;
 908                         }
 909                         break;
 910
 911                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 912                         if (!opt->od_info) {
 913                                 dev_err(pci->dev,
 914                                         "OD control not supported for pin %s\n",
 915                                         g->name);
 916                                 return -ENOTSUPP;
 917                         }
 918                         base = opt->od_info->od_reg_base;
 919                         add = opt->od_info->od_reg_add;
 920                         mask = opt->od_info->od_mask;
 921                         if (param_val == 0)
 922                                 rval = opt->od_info->od_disable;
 923                         else
 924                                 rval = opt->od_info->od_enable;
 925                         if (rval < 0) {
 926                                 dev_err(pci->dev,
 927                                         "OD control not supported for pin %s\n",
 928                                         g->name);
 929                                 return -ENOTSUPP;
 930                         }
 931                         break;
 932                 default:
 933                         dev_err(pci->dev, "Properties not supported\n");
 934                         return -ENOTSUPP;
 935                 }
 936
 937                 dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n",
 938                                 __func__, base, add, mask, rval);
 939                 ret = palmas_update_bits(pci->palmas, base, add, mask, rval);
 940                 if (ret < 0) {
 941                         dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
 942                                 add, ret);
 943                         return ret;
 944                 }
 945         } /* for each config */
 946
 947         return 0;
 948 }
 949
 950 static const struct pinconf_ops palmas_pinconf_ops = {
 951         .pin_config_get = palmas_pinconf_get,
 952         .pin_config_set = palmas_pinconf_set,
 953 };
 954
 955 static struct pinctrl_desc palmas_pinctrl_desc = {
 956         .pctlops = &palmas_pinctrl_ops,
 957         .pmxops = &palmas_pinmux_ops,
 958         .confops = &palmas_pinconf_ops,
 959         .owner = THIS_MODULE,
 960 };
 961
 962 struct palmas_pinctrl_data {
 963         const struct palmas_pingroup *pin_groups;
 964         int num_pin_groups;
 965 };
 966
 967 static struct palmas_pinctrl_data tps65913_pinctrl_data = {
 968         .pin_groups = tps65913_pingroups,
 969         .num_pin_groups = ARRAY_SIZE(tps65913_pingroups),
 970 };
 971
 972 static struct palmas_pinctrl_data tps80036_pinctrl_data = {
 973         .pin_groups = tps80036_pingroups,
 974         .num_pin_groups = ARRAY_SIZE(tps80036_pingroups),
 975 };
 976
 977 static const struct of_device_id palmas_pinctrl_of_match[] = {
 978         { .compatible = "ti,palmas-pinctrl", .data = &tps65913_pinctrl_data},
 979         { .compatible = "ti,tps65913-pinctrl", .data = &tps65913_pinctrl_data},
 980         { .compatible = "ti,tps80036-pinctrl", .data = &tps80036_pinctrl_data},
 981         { },
 982 };
 983 MODULE_DEVICE_TABLE(of, palmas_pinctrl_of_match);
 984
 985 static int palmas_pinctrl_probe(struct platform_device *pdev)
 986 {
 987         struct palmas_pctrl_chip_info *pci;
 988         const struct palmas_pinctrl_data *pinctrl_data = &tps65913_pinctrl_data;
 989         int ret;
 990         bool enable_dvfs1 = false;
 991         bool enable_dvfs2 = false;
 992
 993         if (pdev->dev.of_node) {
 994                 pinctrl_data = of_device_get_match_data(&pdev->dev);
 995                 enable_dvfs1 = of_property_read_bool(pdev->dev.of_node,
 996                                         "ti,palmas-enable-dvfs1");
 997                 enable_dvfs2 = of_property_read_bool(pdev->dev.of_node,
 998                                         "ti,palmas-enable-dvfs2");
 999         }
1000
1001         pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
1002         if (!pci)
1003                 return -ENOMEM;
1004
1005         pci->dev = &pdev->dev;
1006         pci->palmas = dev_get_drvdata(pdev->dev.parent);
1007
1008         pci->pins = palmas_pins_desc;
1009         pci->num_pins = ARRAY_SIZE(palmas_pins_desc);
1010         pci->functions = palmas_pin_function;
1011         pci->num_functions = ARRAY_SIZE(palmas_pin_function);
1012         pci->pin_groups = pinctrl_data->pin_groups;
1013         pci->num_pin_groups = pinctrl_data->num_pin_groups;
1014
1015         platform_set_drvdata(pdev, pci);
1016
1017         palmas_pinctrl_set_dvfs1(pci, enable_dvfs1);
1018         palmas_pinctrl_set_dvfs2(pci, enable_dvfs2);
1019         ret = palmas_pinctrl_get_pin_mux(pci);
1020         if (ret < 0) {
1021                 dev_err(&pdev->dev,
1022                         "Reading pinctrol option register failed: %d\n", ret);
1023                 return ret;
1024         }
1025
1026         palmas_pinctrl_desc.name = dev_name(&pdev->dev);
1027         palmas_pinctrl_desc.pins = palmas_pins_desc;
1028         palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc);
1029         pci->pctl = devm_pinctrl_register(&pdev->dev, &palmas_pinctrl_desc,
1030                                           pci);
1031         if (IS_ERR(pci->pctl)) {
1032                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1033                 return PTR_ERR(pci->pctl);
1034         }
1035         return 0;
1036 }
1037
1038 static struct platform_driver palmas_pinctrl_driver = {
1039         .driver = {
1040                 .name = "palmas-pinctrl",
1041                 .of_match_table = palmas_pinctrl_of_match,
1042         },
1043         .probe = palmas_pinctrl_probe,
1044 };
1045
1046 module_platform_driver(palmas_pinctrl_driver);
1047
1048 MODULE_DESCRIPTION("Palmas pin control driver");
1049 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
1050 MODULE_ALIAS("platform:palmas-pinctrl");
1051 MODULE_LICENSE("GPL v2");