drivers/pinctrl/pinctrl-max77620.c

   1 /*
   2  * MAX77620 pin control driver.
   3  *
   4  * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * Author:
   7  *      Chaitanya Bandi <bandik@nvidia.com>
   8  *      Laxman Dewangan <ldewangan@nvidia.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms and conditions of the GNU General Public License,
  12  * version 2, as published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/mfd/max77620.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/pinctrl/pinctrl.h>
  19 #include <linux/pinctrl/pinconf-generic.h>
  20 #include <linux/pinctrl/pinconf.h>
  21 #include <linux/pinctrl/pinmux.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regmap.h>
  24
  25 #include "core.h"
  26 #include "pinconf.h"
  27 #include "pinctrl-utils.h"
  28
  29 #define MAX77620_PIN_NUM 8
  30
  31 enum max77620_pin_ppdrv {
  32         MAX77620_PIN_UNCONFIG_DRV,
  33         MAX77620_PIN_OD_DRV,
  34         MAX77620_PIN_PP_DRV,
  35 };
  36
  37 enum max77620_pinconf_param {
  38         MAX77620_ACTIVE_FPS_SOURCE = PIN_CONFIG_END + 1,
  39         MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
  40         MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
  41         MAX77620_SUSPEND_FPS_SOURCE,
  42         MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
  43         MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
  44 };
  45
  46 struct max77620_pin_function {
  47         const char *name;
  48         const char * const *groups;
  49         unsigned int ngroups;
  50         int mux_option;
  51 };
  52
  53 static const struct pinconf_generic_params max77620_cfg_params[] = {
  54         {
  55                 .property = "maxim,active-fps-source",
  56                 .param = MAX77620_ACTIVE_FPS_SOURCE,
  57         }, {
  58                 .property = "maxim,active-fps-power-up-slot",
  59                 .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
  60         }, {
  61                 .property = "maxim,active-fps-power-down-slot",
  62                 .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
  63         }, {
  64                 .property = "maxim,suspend-fps-source",
  65                 .param = MAX77620_SUSPEND_FPS_SOURCE,
  66         }, {
  67                 .property = "maxim,suspend-fps-power-up-slot",
  68                 .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
  69         }, {
  70                 .property = "maxim,suspend-fps-power-down-slot",
  71                 .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
  72         },
  73 };
  74
  75 enum max77620_alternate_pinmux_option {
  76         MAX77620_PINMUX_GPIO                            = 0,
  77         MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN       = 1,
  78         MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT    = 2,
  79         MAX77620_PINMUX_32K_OUT1                        = 3,
  80         MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN  = 4,
  81         MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN  = 5,
  82         MAX77620_PINMUX_REFERENCE_OUT                   = 6,
  83 };
  84
  85 struct max77620_pingroup {
  86         const char *name;
  87         const unsigned int pins[1];
  88         unsigned int npins;
  89         enum max77620_alternate_pinmux_option alt_option;
  90 };
  91
  92 struct max77620_pin_info {
  93         enum max77620_pin_ppdrv drv_type;
  94         int pull_config;
  95 };
  96
  97 struct max77620_fps_config {
  98         int active_fps_src;
  99         int active_power_up_slots;
 100         int active_power_down_slots;
 101         int suspend_fps_src;
 102         int suspend_power_up_slots;
 103         int suspend_power_down_slots;
 104 };
 105
 106 struct max77620_pctrl_info {
 107         struct device *dev;
 108         struct pinctrl_dev *pctl;
 109         struct regmap *rmap;
 110         int pins_current_opt[MAX77620_GPIO_NR];
 111         const struct max77620_pin_function *functions;
 112         unsigned int num_functions;
 113         const struct max77620_pingroup *pin_groups;
 114         int num_pin_groups;
 115         const struct pinctrl_pin_desc *pins;
 116         unsigned int num_pins;
 117         struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
 118         struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
 119 };
 120
 121 static const struct pinctrl_pin_desc max77620_pins_desc[] = {
 122         PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
 123         PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
 124         PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
 125         PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
 126         PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
 127         PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
 128         PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
 129         PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
 130 };
 131
 132 static const char * const gpio_groups[] = {
 133         "gpio0",
 134         "gpio1",
 135         "gpio2",
 136         "gpio3",
 137         "gpio4",
 138         "gpio5",
 139         "gpio6",
 140         "gpio7",
 141 };
 142
 143 #define FUNCTION_GROUP(fname, mux)                      \
 144         {                                               \
 145                 .name = fname,                          \
 146                 .groups = gpio_groups,                  \
 147                 .ngroups = ARRAY_SIZE(gpio_groups),     \
 148                 .mux_option = MAX77620_PINMUX_##mux,    \
 149         }
 150
 151 static const struct max77620_pin_function max77620_pin_function[] = {
 152         FUNCTION_GROUP("gpio", GPIO),
 153         FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
 154         FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
 155         FUNCTION_GROUP("32k-out1", 32K_OUT1),
 156         FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
 157         FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
 158         FUNCTION_GROUP("reference-out", REFERENCE_OUT),
 159 };
 160
 161 #define MAX77620_PINGROUP(pg_name, pin_id, option) \
 162         {                                                               \
 163                 .name = #pg_name,                                       \
 164                 .pins = {MAX77620_##pin_id},                            \
 165                 .npins = 1,                                             \
 166                 .alt_option = MAX77620_PINMUX_##option,                 \
 167         }
 168
 169 static const struct max77620_pingroup max77620_pingroups[] = {
 170         MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
 171         MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
 172         MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
 173         MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
 174         MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
 175         MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
 176         MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
 177         MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
 178 };
 179
 180 static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 181 {
 182         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 183
 184         return mpci->num_pin_groups;
 185 }
 186
 187 static const char *max77620_pinctrl_get_group_name(
 188                 struct pinctrl_dev *pctldev, unsigned int group)
 189 {
 190         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 191
 192         return mpci->pin_groups[group].name;
 193 }
 194
 195 static int max77620_pinctrl_get_group_pins(
 196                 struct pinctrl_dev *pctldev, unsigned int group,
 197                 const unsigned int **pins, unsigned int *num_pins)
 198 {
 199         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 200
 201         *pins = mpci->pin_groups[group].pins;
 202         *num_pins = mpci->pin_groups[group].npins;
 203
 204         return 0;
 205 }
 206
 207 static const struct pinctrl_ops max77620_pinctrl_ops = {
 208         .get_groups_count = max77620_pinctrl_get_groups_count,
 209         .get_group_name = max77620_pinctrl_get_group_name,
 210         .get_group_pins = max77620_pinctrl_get_group_pins,
 211         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 212         .dt_free_map = pinctrl_utils_free_map,
 213 };
 214
 215 static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 216 {
 217         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 218
 219         return mpci->num_functions;
 220 }
 221
 222 static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 223                                                   unsigned int function)
 224 {
 225         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 226
 227         return mpci->functions[function].name;
 228 }
 229
 230 static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 231                                             unsigned int function,
 232                                             const char * const **groups,
 233                                             unsigned int * const num_groups)
 234 {
 235         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 236
 237         *groups = mpci->functions[function].groups;
 238         *num_groups = mpci->functions[function].ngroups;
 239
 240         return 0;
 241 }
 242
 243 static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev,
 244                                    unsigned int function, unsigned int group)
 245 {
 246         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 247         u8 val;
 248         int ret;
 249
 250         if (function == MAX77620_PINMUX_GPIO) {
 251                 val = 0;
 252         } else if (function == mpci->pin_groups[group].alt_option) {
 253                 val = 1 << group;
 254         } else {
 255                 dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
 256                         group, function);
 257                 return -EINVAL;
 258         }
 259         ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO,
 260                                  BIT(group), val);
 261         if (ret < 0)
 262                 dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
 263
 264         return ret;
 265 }
 266
 267 static const struct pinmux_ops max77620_pinmux_ops = {
 268         .get_functions_count    = max77620_pinctrl_get_funcs_count,
 269         .get_function_name      = max77620_pinctrl_get_func_name,
 270         .get_function_groups    = max77620_pinctrl_get_func_groups,
 271         .set_mux                = max77620_pinctrl_enable,
 272 };
 273
 274 static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
 275                                 unsigned int pin, unsigned long *config)
 276 {
 277         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 278         struct device *dev = mpci->dev;
 279         enum pin_config_param param = pinconf_to_config_param(*config);
 280         unsigned int val;
 281         int arg = 0;
 282         int ret;
 283
 284         switch (param) {
 285         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 286                 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
 287                         arg = 1;
 288                 break;
 289
 290         case PIN_CONFIG_DRIVE_PUSH_PULL:
 291                 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
 292                         arg = 1;
 293                 break;
 294
 295         case PIN_CONFIG_BIAS_PULL_UP:
 296                 ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val);
 297                 if (ret < 0) {
 298                         dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
 299                         return ret;
 300                 }
 301                 if (val & BIT(pin))
 302                         arg = 1;
 303                 break;
 304
 305         case PIN_CONFIG_BIAS_PULL_DOWN:
 306                 ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val);
 307                 if (ret < 0) {
 308                         dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
 309                         return ret;
 310                 }
 311                 if (val & BIT(pin))
 312                         arg = 1;
 313                 break;
 314
 315         default:
 316                 dev_err(dev, "Properties not supported\n");
 317                 return -ENOTSUPP;
 318         }
 319
 320         *config = pinconf_to_config_packed(param, (u16)arg);
 321
 322         return 0;
 323 }
 324
 325 static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
 326                                     int addr, int *fps)
 327 {
 328         unsigned int val;
 329         int ret;
 330
 331         ret = regmap_read(mpci->rmap, addr, &val);
 332         if (ret < 0) {
 333                 dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
 334                 return ret;
 335         }
 336         *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
 337
 338         return 0;
 339 }
 340
 341 static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
 342                                   int pin, int param)
 343 {
 344         struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
 345         int addr, ret;
 346         int param_val;
 347         int mask, shift;
 348
 349         if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
 350                 return 0;
 351
 352         addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
 353         switch (param) {
 354         case MAX77620_ACTIVE_FPS_SOURCE:
 355         case MAX77620_SUSPEND_FPS_SOURCE:
 356                 mask = MAX77620_FPS_SRC_MASK;
 357                 shift = MAX77620_FPS_SRC_SHIFT;
 358                 param_val = fps_config->active_fps_src;
 359                 if (param == MAX77620_SUSPEND_FPS_SOURCE)
 360                         param_val = fps_config->suspend_fps_src;
 361                 break;
 362
 363         case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
 364         case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
 365                 mask = MAX77620_FPS_PU_PERIOD_MASK;
 366                 shift = MAX77620_FPS_PU_PERIOD_SHIFT;
 367                 param_val = fps_config->active_power_up_slots;
 368                 if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
 369                         param_val = fps_config->suspend_power_up_slots;
 370                 break;
 371
 372         case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
 373         case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
 374                 mask = MAX77620_FPS_PD_PERIOD_MASK;
 375                 shift = MAX77620_FPS_PD_PERIOD_SHIFT;
 376                 param_val = fps_config->active_power_down_slots;
 377                 if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
 378                         param_val = fps_config->suspend_power_down_slots;
 379                 break;
 380
 381         default:
 382                 dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
 383                         param, pin);
 384                 return -EINVAL;
 385         }
 386
 387         if (param_val < 0)
 388                 return 0;
 389
 390         ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
 391         if (ret < 0)
 392                 dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
 393
 394         return ret;
 395 }
 396
 397 static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
 398                                 unsigned int pin, unsigned long *configs,
 399                                 unsigned int num_configs)
 400 {
 401         struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
 402         struct device *dev = mpci->dev;
 403         struct max77620_fps_config *fps_config;
 404         int param;
 405         u32 param_val;
 406         unsigned int val;
 407         unsigned int pu_val;
 408         unsigned int pd_val;
 409         int addr, ret;
 410         int i;
 411
 412         for (i = 0; i < num_configs; i++) {
 413                 param = pinconf_to_config_param(configs[i]);
 414                 param_val = pinconf_to_config_argument(configs[i]);
 415
 416                 switch (param) {
 417                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 418                         val = param_val ? 0 : 1;
 419                         ret = regmap_update_bits(mpci->rmap,
 420                                                  MAX77620_REG_GPIO0 + pin,
 421                                                  MAX77620_CNFG_GPIO_DRV_MASK,
 422                                                  val);
 423                         if (ret)
 424                                 goto report_update_failure;
 425
 426                         mpci->pin_info[pin].drv_type = val ?
 427                                 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
 428                         break;
 429
 430                 case PIN_CONFIG_DRIVE_PUSH_PULL:
 431                         val = param_val ? 1 : 0;
 432                         ret = regmap_update_bits(mpci->rmap,
 433                                                  MAX77620_REG_GPIO0 + pin,
 434                                                  MAX77620_CNFG_GPIO_DRV_MASK,
 435                                                  val);
 436                         if (ret)
 437                                 goto report_update_failure;
 438
 439                         mpci->pin_info[pin].drv_type = val ?
 440                                 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
 441                         break;
 442
 443                 case MAX77620_ACTIVE_FPS_SOURCE:
 444                 case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
 445                 case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
 446                         if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
 447                                 return -EINVAL;
 448
 449                         fps_config = &mpci->fps_config[pin];
 450
 451                         if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
 452                             (param_val == MAX77620_FPS_SRC_DEF)) {
 453                                 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
 454                                 ret = max77620_get_default_fps(
 455                                                 mpci, addr,
 456                                                 &fps_config->active_fps_src);
 457                                 if (ret < 0)
 458                                         return ret;
 459                                 break;
 460                         }
 461
 462                         if (param == MAX77620_ACTIVE_FPS_SOURCE)
 463                                 fps_config->active_fps_src = param_val;
 464                         else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
 465                                 fps_config->active_power_up_slots = param_val;
 466                         else
 467                                 fps_config->active_power_down_slots = param_val;
 468
 469                         ret = max77620_set_fps_param(mpci, pin, param);
 470                         if (ret < 0)
 471                                 return ret;
 472                         break;
 473
 474                 case MAX77620_SUSPEND_FPS_SOURCE:
 475                 case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
 476                 case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
 477                         if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
 478                                 return -EINVAL;
 479
 480                         fps_config = &mpci->fps_config[pin];
 481
 482                         if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
 483                             (param_val == MAX77620_FPS_SRC_DEF)) {
 484                                 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
 485                                 ret = max77620_get_default_fps(
 486                                                 mpci, addr,
 487                                                 &fps_config->suspend_fps_src);
 488                                 if (ret < 0)
 489                                         return ret;
 490                                 break;
 491                         }
 492
 493                         if (param == MAX77620_SUSPEND_FPS_SOURCE)
 494                                 fps_config->suspend_fps_src = param_val;
 495                         else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
 496                                 fps_config->suspend_power_up_slots = param_val;
 497                         else
 498                                 fps_config->suspend_power_down_slots =
 499                                                                 param_val;
 500                         break;
 501
 502                 case PIN_CONFIG_BIAS_PULL_UP:
 503                 case PIN_CONFIG_BIAS_PULL_DOWN:
 504                         pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
 505                                                         BIT(pin) : 0;
 506                         pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
 507                                                         BIT(pin) : 0;
 508
 509                         ret = regmap_update_bits(mpci->rmap,
 510                                                  MAX77620_REG_PUE_GPIO,
 511                                                  BIT(pin), pu_val);
 512                         if (ret < 0) {
 513                                 dev_err(dev, "PUE_GPIO update failed: %d\n",
 514                                         ret);
 515                                 return ret;
 516                         }
 517
 518                         ret = regmap_update_bits(mpci->rmap,
 519                                                  MAX77620_REG_PDE_GPIO,
 520                                                  BIT(pin), pd_val);
 521                         if (ret < 0) {
 522                                 dev_err(dev, "PDE_GPIO update failed: %d\n",
 523                                         ret);
 524                                 return ret;
 525                         }
 526                         break;
 527
 528                 default:
 529                         dev_err(dev, "Properties not supported\n");
 530                         return -ENOTSUPP;
 531                 }
 532         }
 533
 534         return 0;
 535
 536 report_update_failure:
 537         dev_err(dev, "Reg 0x%02x update failed %d\n",
 538                 MAX77620_REG_GPIO0 + pin, ret);
 539         return ret;
 540 }
 541
 542 static const struct pinconf_ops max77620_pinconf_ops = {
 543         .pin_config_get = max77620_pinconf_get,
 544         .pin_config_set = max77620_pinconf_set,
 545 };
 546
 547 static struct pinctrl_desc max77620_pinctrl_desc = {
 548         .pctlops = &max77620_pinctrl_ops,
 549         .pmxops = &max77620_pinmux_ops,
 550         .confops = &max77620_pinconf_ops,
 551 };
 552
 553 static int max77620_pinctrl_probe(struct platform_device *pdev)
 554 {
 555         struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
 556         struct max77620_pctrl_info *mpci;
 557         int i;
 558
 559         mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
 560         if (!mpci)
 561                 return -ENOMEM;
 562
 563         mpci->dev = &pdev->dev;
 564         mpci->dev->of_node = pdev->dev.parent->of_node;
 565         mpci->rmap = max77620->rmap;
 566
 567         mpci->pins = max77620_pins_desc;
 568         mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
 569         mpci->functions = max77620_pin_function;
 570         mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
 571         mpci->pin_groups = max77620_pingroups;
 572         mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
 573         platform_set_drvdata(pdev, mpci);
 574
 575         max77620_pinctrl_desc.name = dev_name(&pdev->dev);
 576         max77620_pinctrl_desc.pins = max77620_pins_desc;
 577         max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
 578         max77620_pinctrl_desc.num_custom_params =
 579                                 ARRAY_SIZE(max77620_cfg_params);
 580         max77620_pinctrl_desc.custom_params = max77620_cfg_params;
 581
 582         for (i = 0; i < MAX77620_PIN_NUM; ++i) {
 583                 mpci->fps_config[i].active_fps_src = -1;
 584                 mpci->fps_config[i].active_power_up_slots = -1;
 585                 mpci->fps_config[i].active_power_down_slots = -1;
 586                 mpci->fps_config[i].suspend_fps_src = -1;
 587                 mpci->fps_config[i].suspend_power_up_slots = -1;
 588                 mpci->fps_config[i].suspend_power_down_slots = -1;
 589         }
 590
 591         mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc,
 592                                            mpci);
 593         if (IS_ERR(mpci->pctl)) {
 594                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 595                 return PTR_ERR(mpci->pctl);
 596         }
 597
 598         return 0;
 599 }
 600
 601 #ifdef CONFIG_PM_SLEEP
 602 static int max77620_suspend_fps_param[] = {
 603         MAX77620_SUSPEND_FPS_SOURCE,
 604         MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
 605         MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
 606 };
 607
 608 static int max77620_active_fps_param[] = {
 609         MAX77620_ACTIVE_FPS_SOURCE,
 610         MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
 611         MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
 612 };
 613
 614 static int max77620_pinctrl_suspend(struct device *dev)
 615 {
 616         struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
 617         int pin, p;
 618
 619         for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
 620                 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
 621                         continue;
 622                 for (p = 0; p < 3; ++p)
 623                         max77620_set_fps_param(
 624                                 mpci, pin, max77620_suspend_fps_param[p]);
 625         }
 626
 627         return 0;
 628 };
 629
 630 static int max77620_pinctrl_resume(struct device *dev)
 631 {
 632         struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
 633         int pin, p;
 634
 635         for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
 636                 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
 637                         continue;
 638                 for (p = 0; p < 3; ++p)
 639                         max77620_set_fps_param(
 640                                 mpci, pin, max77620_active_fps_param[p]);
 641         }
 642
 643         return 0;
 644 }
 645 #endif
 646
 647 static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
 648         SET_SYSTEM_SLEEP_PM_OPS(
 649                 max77620_pinctrl_suspend, max77620_pinctrl_resume)
 650 };
 651
 652 static const struct platform_device_id max77620_pinctrl_devtype[] = {
 653         { .name = "max77620-pinctrl", },
 654         { .name = "max20024-pinctrl", },
 655         {},
 656 };
 657 MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
 658
 659 static struct platform_driver max77620_pinctrl_driver = {
 660         .driver = {
 661                 .name = "max77620-pinctrl",
 662                 .pm = &max77620_pinctrl_pm_ops,
 663         },
 664         .probe = max77620_pinctrl_probe,
 665         .id_table = max77620_pinctrl_devtype,
 666 };
 667
 668 module_platform_driver(max77620_pinctrl_driver);
 669
 670 MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
 671 MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
 672 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
 673 MODULE_ALIAS("platform:max77620-pinctrl");
 674 MODULE_LICENSE("GPL v2");