drivers/pinctrl/pinctrl-ingenic.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Ingenic SoCs pinctrl driver
   4  *
   5  * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
   6  * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
   7  * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk>
   8  */
   9
  10 #include <linux/compiler.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_irq.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/pinctrl/pinctrl.h>
  18 #include <linux/pinctrl/pinmux.h>
  19 #include <linux/pinctrl/pinconf.h>
  20 #include <linux/pinctrl/pinconf-generic.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/regmap.h>
  23 #include <linux/slab.h>
  24
  25 #include "core.h"
  26 #include "pinconf.h"
  27 #include "pinmux.h"
  28
  29 #define GPIO_PIN        0x00
  30 #define GPIO_MSK        0x20
  31
  32 #define JZ4740_GPIO_DATA        0x10
  33 #define JZ4740_GPIO_PULL_DIS    0x30
  34 #define JZ4740_GPIO_FUNC        0x40
  35 #define JZ4740_GPIO_SELECT      0x50
  36 #define JZ4740_GPIO_DIR         0x60
  37 #define JZ4740_GPIO_TRIG        0x70
  38 #define JZ4740_GPIO_FLAG        0x80
  39
  40 #define JZ4770_GPIO_INT         0x10
  41 #define JZ4770_GPIO_PAT1        0x30
  42 #define JZ4770_GPIO_PAT0        0x40
  43 #define JZ4770_GPIO_FLAG        0x50
  44 #define JZ4770_GPIO_PEN         0x70
  45
  46 #define X1830_GPIO_PEL                  0x110
  47 #define X1830_GPIO_PEH                  0x120
  48
  49 #define REG_SET(x) ((x) + 0x4)
  50 #define REG_CLEAR(x) ((x) + 0x8)
  51
  52 #define REG_PZ_BASE(x) ((x) * 7)
  53 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0)
  54
  55 #define GPIO_PULL_DIS   0
  56 #define GPIO_PULL_UP    1
  57 #define GPIO_PULL_DOWN  2
  58
  59 #define PINS_PER_GPIO_CHIP 32
  60
  61 enum jz_version {
  62         ID_JZ4740,
  63         ID_JZ4725B,
  64         ID_JZ4760,
  65         ID_JZ4770,
  66         ID_JZ4780,
  67         ID_X1000,
  68         ID_X1500,
  69         ID_X1830,
  70 };
  71
  72 struct ingenic_chip_info {
  73         unsigned int num_chips;
  74         unsigned int reg_offset;
  75         enum jz_version version;
  76
  77         const struct group_desc *groups;
  78         unsigned int num_groups;
  79
  80         const struct function_desc *functions;
  81         unsigned int num_functions;
  82
  83         const u32 *pull_ups, *pull_downs;
  84 };
  85
  86 struct ingenic_pinctrl {
  87         struct device *dev;
  88         struct regmap *map;
  89         struct pinctrl_dev *pctl;
  90         struct pinctrl_pin_desc *pdesc;
  91
  92         const struct ingenic_chip_info *info;
  93 };
  94
  95 struct ingenic_gpio_chip {
  96         struct ingenic_pinctrl *jzpc;
  97         struct gpio_chip gc;
  98         struct irq_chip irq_chip;
  99         unsigned int irq, reg_base;
 100 };
 101
 102 static const u32 jz4740_pull_ups[4] = {
 103         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 104 };
 105
 106 static const u32 jz4740_pull_downs[4] = {
 107         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 108 };
 109
 110 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
 111 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
 112 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
 113 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
 114 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
 115 static int jz4740_lcd_8bit_pins[] = {
 116         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54,
 117 };
 118 static int jz4740_lcd_16bit_pins[] = {
 119         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55,
 120 };
 121 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
 122 static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, };
 123 static int jz4740_nand_cs1_pins[] = { 0x39, };
 124 static int jz4740_nand_cs2_pins[] = { 0x3a, };
 125 static int jz4740_nand_cs3_pins[] = { 0x3b, };
 126 static int jz4740_nand_cs4_pins[] = { 0x3c, };
 127 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
 128 static int jz4740_pwm_pwm0_pins[] = { 0x77, };
 129 static int jz4740_pwm_pwm1_pins[] = { 0x78, };
 130 static int jz4740_pwm_pwm2_pins[] = { 0x79, };
 131 static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
 132 static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
 133 static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
 134 static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
 135 static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
 136
 137
 138 #define INGENIC_PIN_GROUP_FUNCS(name, id, funcs)                \
 139         {                                               \
 140                 name,                                   \
 141                 id##_pins,                              \
 142                 ARRAY_SIZE(id##_pins),                  \
 143                 funcs,                                  \
 144         }
 145
 146 #define INGENIC_PIN_GROUP(name, id, func)               \
 147         INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func))
 148
 149 static const struct group_desc jz4740_groups[] = {
 150         INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
 151         INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
 152         INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),
 153         INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),
 154         INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),
 155         INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
 156         INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
 157         INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
 158         INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft, 0),
 159         { "lcd-no-pins", },
 160         INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
 161         INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
 162         INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
 163         INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),
 164         INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),
 165         INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0),
 166         INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0),
 167         INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0),
 168         INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0),
 169         INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0),
 170         INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0),
 171         INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0),
 172         INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0),
 173 };
 174
 175 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
 176 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 177 static const char *jz4740_uart1_groups[] = { "uart1-data", };
 178 static const char *jz4740_lcd_groups[] = {
 179         "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
 180 };
 181 static const char *jz4740_nand_groups[] = {
 182         "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
 183 };
 184 static const char *jz4740_pwm0_groups[] = { "pwm0", };
 185 static const char *jz4740_pwm1_groups[] = { "pwm1", };
 186 static const char *jz4740_pwm2_groups[] = { "pwm2", };
 187 static const char *jz4740_pwm3_groups[] = { "pwm3", };
 188 static const char *jz4740_pwm4_groups[] = { "pwm4", };
 189 static const char *jz4740_pwm5_groups[] = { "pwm5", };
 190 static const char *jz4740_pwm6_groups[] = { "pwm6", };
 191 static const char *jz4740_pwm7_groups[] = { "pwm7", };
 192
 193 static const struct function_desc jz4740_functions[] = {
 194         { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
 195         { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
 196         { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
 197         { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
 198         { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
 199         { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
 200         { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
 201         { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
 202         { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
 203         { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
 204         { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
 205         { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
 206         { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
 207 };
 208
 209 static const struct ingenic_chip_info jz4740_chip_info = {
 210         .num_chips = 4,
 211         .reg_offset = 0x100,
 212         .version = ID_JZ4740,
 213         .groups = jz4740_groups,
 214         .num_groups = ARRAY_SIZE(jz4740_groups),
 215         .functions = jz4740_functions,
 216         .num_functions = ARRAY_SIZE(jz4740_functions),
 217         .pull_ups = jz4740_pull_ups,
 218         .pull_downs = jz4740_pull_downs,
 219 };
 220
 221 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
 222 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
 223 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
 224 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
 225 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
 226 static int jz4725b_nand_cs1_pins[] = { 0x55, };
 227 static int jz4725b_nand_cs2_pins[] = { 0x56, };
 228 static int jz4725b_nand_cs3_pins[] = { 0x57, };
 229 static int jz4725b_nand_cs4_pins[] = { 0x58, };
 230 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
 231 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
 232 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
 233 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
 234 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
 235 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
 236 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
 237 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
 238 static int jz4725b_lcd_8bit_pins[] = {
 239         0x72, 0x73, 0x74,
 240         0x60, 0x61, 0x62, 0x63,
 241         0x64, 0x65, 0x66, 0x67,
 242 };
 243 static int jz4725b_lcd_16bit_pins[] = {
 244         0x68, 0x69, 0x6a, 0x6b,
 245         0x6c, 0x6d, 0x6e, 0x6f,
 246 };
 247 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
 248 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
 249 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
 250 static int jz4725b_lcd_generic_pins[] = { 0x75, };
 251
 252 static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
 253
 254 static const struct group_desc jz4725b_groups[] = {
 255         INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),
 256         INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,
 257                                 jz4725b_mmc0_4bit_funcs),
 258         INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),
 259         INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),
 260         INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),
 261         INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),
 262         INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),
 263         INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),
 264         INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),
 265         INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),
 266         INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),
 267         INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0),
 268         INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0),
 269         INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0),
 270         INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0),
 271         INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0),
 272         INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0),
 273         INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),
 274         INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),
 275         INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),
 276         INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),
 277         INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),
 278         INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),
 279 };
 280
 281 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
 282 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
 283 static const char *jz4725b_uart_groups[] = { "uart-data", };
 284 static const char *jz4725b_nand_groups[] = {
 285         "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
 286         "nand-cle-ale", "nand-fre-fwe",
 287 };
 288 static const char *jz4725b_pwm0_groups[] = { "pwm0", };
 289 static const char *jz4725b_pwm1_groups[] = { "pwm1", };
 290 static const char *jz4725b_pwm2_groups[] = { "pwm2", };
 291 static const char *jz4725b_pwm3_groups[] = { "pwm3", };
 292 static const char *jz4725b_pwm4_groups[] = { "pwm4", };
 293 static const char *jz4725b_pwm5_groups[] = { "pwm5", };
 294 static const char *jz4725b_lcd_groups[] = {
 295         "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
 296         "lcd-special", "lcd-generic",
 297 };
 298
 299 static const struct function_desc jz4725b_functions[] = {
 300         { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
 301         { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
 302         { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
 303         { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
 304         { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
 305         { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
 306         { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
 307         { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
 308         { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
 309         { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
 310         { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
 311 };
 312
 313 static const struct ingenic_chip_info jz4725b_chip_info = {
 314         .num_chips = 4,
 315         .reg_offset = 0x100,
 316         .version = ID_JZ4725B,
 317         .groups = jz4725b_groups,
 318         .num_groups = ARRAY_SIZE(jz4725b_groups),
 319         .functions = jz4725b_functions,
 320         .num_functions = ARRAY_SIZE(jz4725b_functions),
 321         .pull_ups = jz4740_pull_ups,
 322         .pull_downs = jz4740_pull_downs,
 323 };
 324
 325 static const u32 jz4760_pull_ups[6] = {
 326         0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f,
 327 };
 328
 329 static const u32 jz4760_pull_downs[6] = {
 330         0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
 331 };
 332
 333 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
 334 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
 335 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
 336 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
 337 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
 338 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
 339 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
 340 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
 341 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
 342 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
 343 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 344 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 345 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 346 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
 347 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
 348 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 349 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 350 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 351 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
 352 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
 353 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 354 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 355 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 356 static int jz4760_nemc_8bit_data_pins[] = {
 357         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 358 };
 359 static int jz4760_nemc_16bit_data_pins[] = {
 360         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
 361 };
 362 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
 363 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
 364 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
 365 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
 366 static int jz4760_nemc_wait_pins[] = { 0x1b, };
 367 static int jz4760_nemc_cs1_pins[] = { 0x15, };
 368 static int jz4760_nemc_cs2_pins[] = { 0x16, };
 369 static int jz4760_nemc_cs3_pins[] = { 0x17, };
 370 static int jz4760_nemc_cs4_pins[] = { 0x18, };
 371 static int jz4760_nemc_cs5_pins[] = { 0x19, };
 372 static int jz4760_nemc_cs6_pins[] = { 0x1a, };
 373 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
 374 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
 375 static int jz4760_cim_pins[] = {
 376         0x26, 0x27, 0x28, 0x29,
 377         0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
 378 };
 379 static int jz4760_lcd_8bit_pins[] = {
 380         0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c,
 381         0x4d, 0x52, 0x53,
 382 };
 383 static int jz4760_lcd_16bit_pins[] = {
 384         0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
 385 };
 386 static int jz4760_lcd_18bit_pins[] = {
 387         0x5a, 0x5b,
 388 };
 389 static int jz4760_lcd_24bit_pins[] = {
 390         0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
 391 };
 392 static int jz4760_lcd_special_pins[] = { 0x40, 0x41, 0x4a, 0x54 };
 393 static int jz4760_lcd_generic_pins[] = { 0x49, };
 394 static int jz4760_pwm_pwm0_pins[] = { 0x80, };
 395 static int jz4760_pwm_pwm1_pins[] = { 0x81, };
 396 static int jz4760_pwm_pwm2_pins[] = { 0x82, };
 397 static int jz4760_pwm_pwm3_pins[] = { 0x83, };
 398 static int jz4760_pwm_pwm4_pins[] = { 0x84, };
 399 static int jz4760_pwm_pwm5_pins[] = { 0x85, };
 400 static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
 401 static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
 402 static int jz4760_otg_pins[] = { 0x8a, };
 403
 404 static u8 jz4760_uart3_data_funcs[] = { 0, 1, };
 405 static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
 406
 407 static const struct group_desc jz4760_groups[] = {
 408         INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),
 409         INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),
 410         INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),
 411         INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),
 412         INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),
 413         INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),
 414         INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
 415                                 jz4760_uart3_data_funcs),
 416         INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
 417         INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
 418                                 jz4760_mmc0_1bit_a_funcs),
 419         INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
 420         INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),
 421         INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),
 422         INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),
 423         INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),
 424         INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),
 425         INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),
 426         INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),
 427         INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),
 428         INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),
 429         INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),
 430         INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),
 431         INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),
 432         INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),
 433         INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),
 434         INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),
 435         INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),
 436         INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),
 437         INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),
 438         INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),
 439         INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),
 440         INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),
 441         INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),
 442         INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),
 443         INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),
 444         INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),
 445         INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),
 446         INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
 447         INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
 448         INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
 449         INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),
 450         INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),
 451         INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),
 452         INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
 453         INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),
 454         INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),
 455         INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0),
 456         INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0),
 457         INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0),
 458         INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0),
 459         INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0),
 460         INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0),
 461         INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0),
 462         INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0),
 463         INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
 464 };
 465
 466 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 467 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
 468 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
 469 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
 470 static const char *jz4760_mmc0_groups[] = {
 471         "mmc0-1bit-a", "mmc0-4bit-a",
 472         "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
 473 };
 474 static const char *jz4760_mmc1_groups[] = {
 475         "mmc1-1bit-d", "mmc1-4bit-d",
 476         "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
 477 };
 478 static const char *jz4760_mmc2_groups[] = {
 479         "mmc2-1bit-b", "mmc2-4bit-b",
 480         "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
 481 };
 482 static const char *jz4760_nemc_groups[] = {
 483         "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
 484         "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
 485 };
 486 static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
 487 static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
 488 static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
 489 static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
 490 static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
 491 static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
 492 static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
 493 static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
 494 static const char *jz4760_cim_groups[] = { "cim-data", };
 495 static const char *jz4760_lcd_groups[] = {
 496         "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
 497         "lcd-special", "lcd-generic",
 498 };
 499 static const char *jz4760_pwm0_groups[] = { "pwm0", };
 500 static const char *jz4760_pwm1_groups[] = { "pwm1", };
 501 static const char *jz4760_pwm2_groups[] = { "pwm2", };
 502 static const char *jz4760_pwm3_groups[] = { "pwm3", };
 503 static const char *jz4760_pwm4_groups[] = { "pwm4", };
 504 static const char *jz4760_pwm5_groups[] = { "pwm5", };
 505 static const char *jz4760_pwm6_groups[] = { "pwm6", };
 506 static const char *jz4760_pwm7_groups[] = { "pwm7", };
 507 static const char *jz4760_otg_groups[] = { "otg-vbus", };
 508
 509 static const struct function_desc jz4760_functions[] = {
 510         { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
 511         { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
 512         { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
 513         { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
 514         { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
 515         { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
 516         { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
 517         { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
 518         { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
 519         { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
 520         { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
 521         { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
 522         { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
 523         { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
 524         { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
 525         { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
 526         { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
 527         { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
 528         { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
 529         { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
 530         { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
 531         { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
 532         { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
 533         { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
 534         { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
 535         { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
 536         { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
 537 };
 538
 539 static const struct ingenic_chip_info jz4760_chip_info = {
 540         .num_chips = 6,
 541         .reg_offset = 0x100,
 542         .version = ID_JZ4760,
 543         .groups = jz4760_groups,
 544         .num_groups = ARRAY_SIZE(jz4760_groups),
 545         .functions = jz4760_functions,
 546         .num_functions = ARRAY_SIZE(jz4760_functions),
 547         .pull_ups = jz4760_pull_ups,
 548         .pull_downs = jz4760_pull_downs,
 549 };
 550
 551 static const u32 jz4770_pull_ups[6] = {
 552         0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f,
 553 };
 554
 555 static const u32 jz4770_pull_downs[6] = {
 556         0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
 557 };
 558
 559 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
 560 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
 561 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
 562 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
 563 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
 564 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
 565 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
 566 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
 567 static int jz4770_ssi0_dt_a_pins[] = { 0x15, };
 568 static int jz4770_ssi0_dt_b_pins[] = { 0x35, };
 569 static int jz4770_ssi0_dt_d_pins[] = { 0x75, };
 570 static int jz4770_ssi0_dt_e_pins[] = { 0x91, };
 571 static int jz4770_ssi0_dr_a_pins[] = { 0x14, };
 572 static int jz4770_ssi0_dr_b_pins[] = { 0x34, };
 573 static int jz4770_ssi0_dr_d_pins[] = { 0x74, };
 574 static int jz4770_ssi0_dr_e_pins[] = { 0x8e, };
 575 static int jz4770_ssi0_clk_a_pins[] = { 0x12, };
 576 static int jz4770_ssi0_clk_b_pins[] = { 0x3c, };
 577 static int jz4770_ssi0_clk_d_pins[] = { 0x78, };
 578 static int jz4770_ssi0_clk_e_pins[] = { 0x8f, };
 579 static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, };
 580 static int jz4770_ssi0_gpc_d_pins[] = { 0x76, };
 581 static int jz4770_ssi0_gpc_e_pins[] = { 0x93, };
 582 static int jz4770_ssi0_ce0_a_pins[] = { 0x13, };
 583 static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, };
 584 static int jz4770_ssi0_ce0_d_pins[] = { 0x79, };
 585 static int jz4770_ssi0_ce0_e_pins[] = { 0x90, };
 586 static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, };
 587 static int jz4770_ssi0_ce1_d_pins[] = { 0x77, };
 588 static int jz4770_ssi0_ce1_e_pins[] = { 0x92, };
 589 static int jz4770_ssi1_dt_b_pins[] = { 0x35, };
 590 static int jz4770_ssi1_dt_d_pins[] = { 0x75, };
 591 static int jz4770_ssi1_dt_e_pins[] = { 0x91, };
 592 static int jz4770_ssi1_dr_b_pins[] = { 0x34, };
 593 static int jz4770_ssi1_dr_d_pins[] = { 0x74, };
 594 static int jz4770_ssi1_dr_e_pins[] = { 0x8e, };
 595 static int jz4770_ssi1_clk_b_pins[] = { 0x3c, };
 596 static int jz4770_ssi1_clk_d_pins[] = { 0x78, };
 597 static int jz4770_ssi1_clk_e_pins[] = { 0x8f, };
 598 static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, };
 599 static int jz4770_ssi1_gpc_d_pins[] = { 0x76, };
 600 static int jz4770_ssi1_gpc_e_pins[] = { 0x93, };
 601 static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, };
 602 static int jz4770_ssi1_ce0_d_pins[] = { 0x79, };
 603 static int jz4770_ssi1_ce0_e_pins[] = { 0x90, };
 604 static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, };
 605 static int jz4770_ssi1_ce1_d_pins[] = { 0x77, };
 606 static int jz4770_ssi1_ce1_e_pins[] = { 0x92, };
 607 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
 608 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
 609 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 610 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 611 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 612 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
 613 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
 614 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 615 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 616 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 617 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
 618 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
 619 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 620 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 621 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 622 static int jz4770_nemc_8bit_data_pins[] = {
 623         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 624 };
 625 static int jz4770_nemc_16bit_data_pins[] = {
 626         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
 627 };
 628 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
 629 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
 630 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
 631 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
 632 static int jz4770_nemc_wait_pins[] = { 0x1b, };
 633 static int jz4770_nemc_cs1_pins[] = { 0x15, };
 634 static int jz4770_nemc_cs2_pins[] = { 0x16, };
 635 static int jz4770_nemc_cs3_pins[] = { 0x17, };
 636 static int jz4770_nemc_cs4_pins[] = { 0x18, };
 637 static int jz4770_nemc_cs5_pins[] = { 0x19, };
 638 static int jz4770_nemc_cs6_pins[] = { 0x1a, };
 639 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
 640 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
 641 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
 642 static int jz4770_cim_8bit_pins[] = {
 643         0x26, 0x27, 0x28, 0x29,
 644         0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
 645 };
 646 static int jz4770_cim_12bit_pins[] = {
 647         0x32, 0x33, 0xb0, 0xb1,
 648 };
 649 static int jz4770_lcd_8bit_pins[] = {
 650         0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
 651         0x48, 0x49, 0x52, 0x53,
 652 };
 653 static int jz4770_lcd_24bit_pins[] = {
 654         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
 655         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
 656         0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
 657         0x58, 0x59, 0x5a, 0x5b,
 658 };
 659 static int jz4770_pwm_pwm0_pins[] = { 0x80, };
 660 static int jz4770_pwm_pwm1_pins[] = { 0x81, };
 661 static int jz4770_pwm_pwm2_pins[] = { 0x82, };
 662 static int jz4770_pwm_pwm3_pins[] = { 0x83, };
 663 static int jz4770_pwm_pwm4_pins[] = { 0x84, };
 664 static int jz4770_pwm_pwm5_pins[] = { 0x85, };
 665 static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
 666 static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
 667 static int jz4770_mac_rmii_pins[] = {
 668         0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
 669 };
 670 static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
 671
 672 static const struct group_desc jz4770_groups[] = {
 673         INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
 674         INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
 675         INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
 676         INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
 677         INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),
 678         INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),
 679         INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
 680                                 jz4760_uart3_data_funcs),
 681         INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
 682         INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),
 683         INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),
 684         INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),
 685         INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
 686         INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),
 687         INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),
 688         INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),
 689         INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
 690         INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),
 691         INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),
 692         INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),
 693         INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
 694         INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),
 695         INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),
 696         INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
 697         INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),
 698         INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),
 699         INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),
 700         INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
 701         INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),
 702         INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),
 703         INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
 704         INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),
 705         INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),
 706         INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
 707         INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),
 708         INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),
 709         INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
 710         INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),
 711         INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),
 712         INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
 713         INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),
 714         INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),
 715         INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
 716         INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),
 717         INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),
 718         INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
 719         INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),
 720         INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),
 721         INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
 722         INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
 723                                 jz4760_mmc0_1bit_a_funcs),
 724         INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
 725         INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
 726         INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
 727         INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),
 728         INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
 729         INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
 730         INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
 731         INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
 732         INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),
 733         INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
 734         INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
 735         INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
 736         INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
 737         INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),
 738         INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),
 739         INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),
 740         INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
 741         INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
 742         INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
 743         INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
 744         INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
 745         INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
 746         INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
 747         INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
 748         INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
 749         INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
 750         INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
 751         INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
 752         INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
 753         INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
 754         INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),
 755         INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
 756         INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
 757         INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
 758         { "lcd-no-pins", },
 759         INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
 760         INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
 761         INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
 762         INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
 763         INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
 764         INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
 765         INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
 766         INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
 767         INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
 768         INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
 769         INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
 770 };
 771
 772 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 773 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
 774 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
 775 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
 776 static const char *jz4770_ssi0_groups[] = {
 777         "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
 778         "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
 779         "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
 780         "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
 781         "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
 782         "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
 783 };
 784 static const char *jz4770_ssi1_groups[] = {
 785         "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
 786         "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
 787         "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
 788         "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
 789         "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
 790         "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
 791 };
 792 static const char *jz4770_mmc0_groups[] = {
 793         "mmc0-1bit-a", "mmc0-4bit-a",
 794         "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
 795 };
 796 static const char *jz4770_mmc1_groups[] = {
 797         "mmc1-1bit-d", "mmc1-4bit-d",
 798         "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
 799 };
 800 static const char *jz4770_mmc2_groups[] = {
 801         "mmc2-1bit-b", "mmc2-4bit-b",
 802         "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
 803 };
 804 static const char *jz4770_nemc_groups[] = {
 805         "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
 806         "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
 807 };
 808 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
 809 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
 810 static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
 811 static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
 812 static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
 813 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
 814 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
 815 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
 816 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
 817 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
 818 static const char *jz4770_lcd_groups[] = {
 819         "lcd-8bit", "lcd-24bit", "lcd-no-pins",
 820 };
 821 static const char *jz4770_pwm0_groups[] = { "pwm0", };
 822 static const char *jz4770_pwm1_groups[] = { "pwm1", };
 823 static const char *jz4770_pwm2_groups[] = { "pwm2", };
 824 static const char *jz4770_pwm3_groups[] = { "pwm3", };
 825 static const char *jz4770_pwm4_groups[] = { "pwm4", };
 826 static const char *jz4770_pwm5_groups[] = { "pwm5", };
 827 static const char *jz4770_pwm6_groups[] = { "pwm6", };
 828 static const char *jz4770_pwm7_groups[] = { "pwm7", };
 829 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
 830
 831 static const struct function_desc jz4770_functions[] = {
 832         { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
 833         { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
 834         { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
 835         { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
 836         { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), },
 837         { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), },
 838         { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
 839         { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
 840         { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
 841         { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
 842         { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
 843         { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
 844         { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
 845         { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
 846         { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
 847         { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
 848         { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
 849         { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
 850         { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
 851         { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
 852         { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
 853         { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
 854         { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
 855         { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
 856         { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
 857         { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
 858         { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
 859         { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
 860         { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
 861         { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
 862         { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
 863 };
 864
 865 static const struct ingenic_chip_info jz4770_chip_info = {
 866         .num_chips = 6,
 867         .reg_offset = 0x100,
 868         .version = ID_JZ4770,
 869         .groups = jz4770_groups,
 870         .num_groups = ARRAY_SIZE(jz4770_groups),
 871         .functions = jz4770_functions,
 872         .num_functions = ARRAY_SIZE(jz4770_functions),
 873         .pull_ups = jz4770_pull_ups,
 874         .pull_downs = jz4770_pull_downs,
 875 };
 876
 877 static const u32 jz4780_pull_ups[6] = {
 878         0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f,
 879 };
 880
 881 static const u32 jz4780_pull_downs[6] = {
 882         0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
 883 };
 884
 885 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
 886 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
 887 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
 888 static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, };
 889 static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, };
 890 static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, };
 891 static int jz4780_ssi0_dt_b_pins[] = { 0x3d, };
 892 static int jz4780_ssi0_dt_d_pins[] = { 0x79, };
 893 static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, };
 894 static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, };
 895 static int jz4780_ssi0_dr_b_pins[] = { 0x34, };
 896 static int jz4780_ssi0_dr_d_pins[] = { 0x74, };
 897 static int jz4780_ssi0_clk_a_pins[] = { 0x12, };
 898 static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, };
 899 static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, };
 900 static int jz4780_ssi0_clk_d_pins[] = { 0x78, };
 901 static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, };
 902 static int jz4780_ssi0_gpc_d_pins[] = { 0x76, };
 903 static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, };
 904 static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, };
 905 static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, };
 906 static int jz4780_ssi0_ce0_d_pins[] = { 0x77, };
 907 static int jz4780_ssi0_ce1_b_pins[] = { 0x35, };
 908 static int jz4780_ssi0_ce1_d_pins[] = { 0x75, };
 909 static int jz4780_ssi1_dt_b_pins[] = { 0x3d, };
 910 static int jz4780_ssi1_dt_d_pins[] = { 0x79, };
 911 static int jz4780_ssi1_dr_b_pins[] = { 0x34, };
 912 static int jz4780_ssi1_dr_d_pins[] = { 0x74, };
 913 static int jz4780_ssi1_clk_b_pins[] = { 0x3c, };
 914 static int jz4780_ssi1_clk_d_pins[] = { 0x78, };
 915 static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, };
 916 static int jz4780_ssi1_gpc_d_pins[] = { 0x76, };
 917 static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, };
 918 static int jz4780_ssi1_ce0_d_pins[] = { 0x77, };
 919 static int jz4780_ssi1_ce1_b_pins[] = { 0x35, };
 920 static int jz4780_ssi1_ce1_d_pins[] = { 0x75, };
 921 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
 922 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
 923 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
 924 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
 925 static int jz4780_i2s_data_tx_pins[] = { 0x87, };
 926 static int jz4780_i2s_data_rx_pins[] = { 0x86, };
 927 static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, };
 928 static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, };
 929 static int jz4780_i2s_sysclk_pins[] = { 0x85, };
 930 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
 931
 932 static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };
 933
 934 static const struct group_desc jz4780_groups[] = {
 935         INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
 936         INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
 937         INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
 938         INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
 939         INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),
 940         INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),
 941         INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
 942                                 jz4760_uart3_data_funcs),
 943         INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
 944         INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),
 945         INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),
 946         INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),
 947         INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),
 948         INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),
 949         INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),
 950         INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
 951         INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),
 952         INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),
 953         INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),
 954         INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),
 955         INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
 956         INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),
 957         INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),
 958         INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),
 959         INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),
 960         INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
 961         INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),
 962         INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),
 963         INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
 964         INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),
 965         INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),
 966         INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),
 967         INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),
 968         INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
 969         INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),
 970         INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),
 971         INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
 972         INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),
 973         INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),
 974         INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
 975         INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),
 976         INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),
 977         INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
 978         INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),
 979         INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),
 980         INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
 981         INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),
 982         INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),
 983         INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
 984         INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),
 985         INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),
 986         INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
 987         INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),
 988         INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),
 989         INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
 990         INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
 991                                 jz4760_mmc0_1bit_a_funcs),
 992         INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
 993         INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),
 994         INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
 995         INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
 996         INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
 997         INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
 998         INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
 999         INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1000         INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1001         INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1002         INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1003         INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1004         INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),
1005         INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1006         INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1007         INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1008         INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1009         INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1010         INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1011         INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1012         INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1013         INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1014         INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1015         INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1016         INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1017         INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1018         INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1019         INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),
1020         INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),
1021         INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),
1022         INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),
1023         INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),
1024         INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,
1025                                 jz4780_i2s_clk_txrx_funcs),
1026         INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),
1027         INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),
1028         INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),
1029         INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),
1030         INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1031         INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1032         { "lcd-no-pins", },
1033         INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
1034         INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
1035         INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
1036         INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
1037         INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
1038         INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
1039         INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
1040         INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
1041 };
1042
1043 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1044 static const char *jz4780_uart4_groups[] = { "uart4-data", };
1045 static const char *jz4780_ssi0_groups[] = {
1046         "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1047         "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1048         "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
1049         "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1050         "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1051         "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1052 };
1053 static const char *jz4780_ssi1_groups[] = {
1054         "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1055         "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1056         "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1057         "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1058         "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1059         "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1060 };
1061 static const char *jz4780_mmc0_groups[] = {
1062         "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1063         "mmc0-1bit-e", "mmc0-4bit-e",
1064 };
1065 static const char *jz4780_mmc1_groups[] = {
1066         "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
1067 };
1068 static const char *jz4780_mmc2_groups[] = {
1069         "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
1070 };
1071 static const char *jz4780_nemc_groups[] = {
1072         "nemc-data", "nemc-cle-ale", "nemc-addr",
1073         "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1074 };
1075 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
1076 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
1077 static const char *jz4780_i2s_groups[] = {
1078         "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1079 };
1080 static const char *jz4780_cim_groups[] = { "cim-data", };
1081 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
1082
1083 static const struct function_desc jz4780_functions[] = {
1084         { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
1085         { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
1086         { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
1087         { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
1088         { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
1089         { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), },
1090         { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), },
1091         { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
1092         { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
1093         { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
1094         { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
1095         { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1096         { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1097         { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1098         { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1099         { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1100         { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1101         { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1102         { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1103         { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
1104         { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
1105         { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
1106         { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), },
1107         { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
1108         { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1109         { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1110         { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1111         { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1112         { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1113         { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1114         { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1115         { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1116         { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
1117         { "hdmi-ddc", jz4780_hdmi_ddc_groups,
1118                       ARRAY_SIZE(jz4780_hdmi_ddc_groups), },
1119 };
1120
1121 static const struct ingenic_chip_info jz4780_chip_info = {
1122         .num_chips = 6,
1123         .reg_offset = 0x100,
1124         .version = ID_JZ4780,
1125         .groups = jz4780_groups,
1126         .num_groups = ARRAY_SIZE(jz4780_groups),
1127         .functions = jz4780_functions,
1128         .num_functions = ARRAY_SIZE(jz4780_functions),
1129         .pull_ups = jz4780_pull_ups,
1130         .pull_downs = jz4780_pull_downs,
1131 };
1132
1133 static const u32 x1000_pull_ups[4] = {
1134         0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,
1135 };
1136
1137 static const u32 x1000_pull_downs[4] = {
1138         0x00000000, 0x02000000, 0x02000000, 0x00000000,
1139 };
1140
1141 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
1142 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1143 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
1144 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
1145 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
1146 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
1147 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
1148 static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, };
1149 static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
1150 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
1151 static int x1000_ssi_dt_d_pins[] = { 0x62, };
1152 static int x1000_ssi_dr_a_23_pins[] = { 0x17, };
1153 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };
1154 static int x1000_ssi_dr_d_pins[] = { 0x63, };
1155 static int x1000_ssi_clk_a_24_pins[] = { 0x18, };
1156 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };
1157 static int x1000_ssi_clk_d_pins[] = { 0x60, };
1158 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };
1159 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };
1160 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };
1161 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };
1162 static int x1000_ssi_ce0_d_pins[] = { 0x61, };
1163 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };
1164 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };
1165 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
1166 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
1167 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
1168 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
1169 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
1170 static int x1000_emc_8bit_data_pins[] = {
1171         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1172 };
1173 static int x1000_emc_16bit_data_pins[] = {
1174         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1175 };
1176 static int x1000_emc_addr_pins[] = {
1177         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
1178         0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
1179 };
1180 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };
1181 static int x1000_emc_wait_pins[] = { 0x34, };
1182 static int x1000_emc_cs1_pins[] = { 0x32, };
1183 static int x1000_emc_cs2_pins[] = { 0x33, };
1184 static int x1000_i2c0_pins[] = { 0x38, 0x37, };
1185 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
1186 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
1187 static int x1000_i2c2_pins[] = { 0x61, 0x60, };
1188 static int x1000_i2s_data_tx_pins[] = { 0x24, };
1189 static int x1000_i2s_data_rx_pins[] = { 0x23, };
1190 static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
1191 static int x1000_i2s_sysclk_pins[] = { 0x20, };
1192 static int x1000_cim_pins[] = {
1193         0x08, 0x09, 0x0a, 0x0b,
1194         0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
1195 };
1196 static int x1000_lcd_8bit_pins[] = {
1197         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1198         0x30, 0x31, 0x32, 0x33, 0x34,
1199 };
1200 static int x1000_lcd_16bit_pins[] = {
1201         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1202 };
1203 static int x1000_pwm_pwm0_pins[] = { 0x59, };
1204 static int x1000_pwm_pwm1_pins[] = { 0x5a, };
1205 static int x1000_pwm_pwm2_pins[] = { 0x5b, };
1206 static int x1000_pwm_pwm3_pins[] = { 0x26, };
1207 static int x1000_pwm_pwm4_pins[] = { 0x58, };
1208 static int x1000_mac_pins[] = {
1209         0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
1210 };
1211
1212 static const struct group_desc x1000_groups[] = {
1213         INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),
1214         INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),
1215         INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),
1216         INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),
1217         INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
1218         INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
1219         INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
1220         INGENIC_PIN_GROUP("sfc", x1000_sfc, 1),
1221         INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
1222         INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
1223         INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
1224         INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),
1225         INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),
1226         INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),
1227         INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),
1228         INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),
1229         INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),
1230         INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),
1231         INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),
1232         INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),
1233         INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),
1234         INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),
1235         INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),
1236         INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),
1237         INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),
1238         INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),
1239         INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),
1240         INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),
1241         INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),
1242         INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),
1243         INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),
1244         INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),
1245         INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),
1246         INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),
1247         INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),
1248         INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),
1249         INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),
1250         INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),
1251         INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),
1252         INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),
1253         INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),
1254         INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
1255         INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
1256         INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
1257         INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
1258         INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
1259         INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
1260         { "lcd-no-pins", },
1261         INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0),
1262         INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1),
1263         INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1),
1264         INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2),
1265         INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0),
1266         INGENIC_PIN_GROUP("mac", x1000_mac, 1),
1267 };
1268
1269 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1270 static const char *x1000_uart1_groups[] = {
1271         "uart1-data-a", "uart1-data-d", "uart1-hwflow",
1272 };
1273 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
1274 static const char *x1000_sfc_groups[] = { "sfc", };
1275 static const char *x1000_ssi_groups[] = {
1276         "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
1277         "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
1278         "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
1279         "ssi-gpc-a-20", "ssi-gpc-a-31",
1280         "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
1281         "ssi-ce1-a-21", "ssi-ce1-a-30",
1282 };
1283 static const char *x1000_mmc0_groups[] = {
1284         "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
1285 };
1286 static const char *x1000_mmc1_groups[] = {
1287         "mmc1-1bit", "mmc1-4bit",
1288 };
1289 static const char *x1000_emc_groups[] = {
1290         "emc-8bit-data", "emc-16bit-data",
1291         "emc-addr", "emc-rd-we", "emc-wait",
1292 };
1293 static const char *x1000_cs1_groups[] = { "emc-cs1", };
1294 static const char *x1000_cs2_groups[] = { "emc-cs2", };
1295 static const char *x1000_i2c0_groups[] = { "i2c0-data", };
1296 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1297 static const char *x1000_i2c2_groups[] = { "i2c2-data", };
1298 static const char *x1000_i2s_groups[] = {
1299         "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1300 };
1301 static const char *x1000_cim_groups[] = { "cim-data", };
1302 static const char *x1000_lcd_groups[] = {
1303         "lcd-8bit", "lcd-16bit", "lcd-no-pins",
1304 };
1305 static const char *x1000_pwm0_groups[] = { "pwm0", };
1306 static const char *x1000_pwm1_groups[] = { "pwm1", };
1307 static const char *x1000_pwm2_groups[] = { "pwm2", };
1308 static const char *x1000_pwm3_groups[] = { "pwm3", };
1309 static const char *x1000_pwm4_groups[] = { "pwm4", };
1310 static const char *x1000_mac_groups[] = { "mac", };
1311
1312 static const struct function_desc x1000_functions[] = {
1313         { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
1314         { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
1315         { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
1316         { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
1317         { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), },
1318         { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
1319         { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
1320         { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), },
1321         { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
1322         { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
1323         { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
1324         { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
1325         { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
1326         { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), },
1327         { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
1328         { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
1329         { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
1330         { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
1331         { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
1332         { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
1333         { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
1334         { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
1335 };
1336
1337 static const struct ingenic_chip_info x1000_chip_info = {
1338         .num_chips = 4,
1339         .reg_offset = 0x100,
1340         .version = ID_X1000,
1341         .groups = x1000_groups,
1342         .num_groups = ARRAY_SIZE(x1000_groups),
1343         .functions = x1000_functions,
1344         .num_functions = ARRAY_SIZE(x1000_functions),
1345         .pull_ups = x1000_pull_ups,
1346         .pull_downs = x1000_pull_downs,
1347 };
1348
1349 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
1350 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1351 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
1352 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
1353 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };
1354 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
1355 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
1356 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };
1357 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };
1358 static int x1500_i2c0_pins[] = { 0x38, 0x37, };
1359 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
1360 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
1361 static int x1500_i2c2_pins[] = { 0x61, 0x60, };
1362 static int x1500_i2s_data_tx_pins[] = { 0x24, };
1363 static int x1500_i2s_data_rx_pins[] = { 0x23, };
1364 static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
1365 static int x1500_i2s_sysclk_pins[] = { 0x20, };
1366 static int x1500_cim_pins[] = {
1367         0x08, 0x09, 0x0a, 0x0b,
1368         0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
1369 };
1370 static int x1500_pwm_pwm0_pins[] = { 0x59, };
1371 static int x1500_pwm_pwm1_pins[] = { 0x5a, };
1372 static int x1500_pwm_pwm2_pins[] = { 0x5b, };
1373 static int x1500_pwm_pwm3_pins[] = { 0x26, };
1374 static int x1500_pwm_pwm4_pins[] = { 0x58, };
1375
1376 static const struct group_desc x1500_groups[] = {
1377         INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),
1378         INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),
1379         INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),
1380         INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),
1381         INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
1382         INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
1383         INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
1384         INGENIC_PIN_GROUP("sfc", x1000_sfc, 1),
1385         INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
1386         INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
1387         INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
1388         INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),
1389         INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),
1390         INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),
1391         INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),
1392         INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
1393         INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
1394         INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
1395         INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
1396         { "lcd-no-pins", },
1397         INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0),
1398         INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1),
1399         INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1),
1400         INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2),
1401         INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0),
1402 };
1403
1404 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1405 static const char *x1500_uart1_groups[] = {
1406         "uart1-data-a", "uart1-data-d", "uart1-hwflow",
1407 };
1408 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
1409 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
1410 static const char *x1500_i2c0_groups[] = { "i2c0-data", };
1411 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1412 static const char *x1500_i2c2_groups[] = { "i2c2-data", };
1413 static const char *x1500_i2s_groups[] = {
1414         "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1415 };
1416 static const char *x1500_cim_groups[] = { "cim-data", };
1417 static const char *x1500_lcd_groups[] = { "lcd-no-pins", };
1418 static const char *x1500_pwm0_groups[] = { "pwm0", };
1419 static const char *x1500_pwm1_groups[] = { "pwm1", };
1420 static const char *x1500_pwm2_groups[] = { "pwm2", };
1421 static const char *x1500_pwm3_groups[] = { "pwm3", };
1422 static const char *x1500_pwm4_groups[] = { "pwm4", };
1423
1424 static const struct function_desc x1500_functions[] = {
1425         { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
1426         { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
1427         { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
1428         { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
1429         { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
1430         { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
1431         { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
1432         { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
1433         { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), },
1434         { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
1435         { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), },
1436         { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
1437         { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
1438         { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
1439         { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
1440         { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
1441 };
1442
1443 static const struct ingenic_chip_info x1500_chip_info = {
1444         .num_chips = 4,
1445         .reg_offset = 0x100,
1446         .version = ID_X1500,
1447         .groups = x1500_groups,
1448         .num_groups = ARRAY_SIZE(x1500_groups),
1449         .functions = x1500_functions,
1450         .num_functions = ARRAY_SIZE(x1500_functions),
1451         .pull_ups = x1000_pull_ups,
1452         .pull_downs = x1000_pull_downs,
1453 };
1454
1455 static const u32 x1830_pull_ups[4] = {
1456         0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
1457 };
1458
1459 static const u32 x1830_pull_downs[4] = {
1460         0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
1461 };
1462
1463 static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
1464 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
1465 static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
1466 static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, };
1467 static int x1830_ssi0_dt_pins[] = { 0x4c, };
1468 static int x1830_ssi0_dr_pins[] = { 0x4b, };
1469 static int x1830_ssi0_clk_pins[] = { 0x4f, };
1470 static int x1830_ssi0_gpc_pins[] = { 0x4d, };
1471 static int x1830_ssi0_ce0_pins[] = { 0x50, };
1472 static int x1830_ssi0_ce1_pins[] = { 0x4e, };
1473 static int x1830_ssi1_dt_c_pins[] = { 0x53, };
1474 static int x1830_ssi1_dr_c_pins[] = { 0x54, };
1475 static int x1830_ssi1_clk_c_pins[] = { 0x57, };
1476 static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
1477 static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
1478 static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
1479 static int x1830_ssi1_dt_d_pins[] = { 0x62, };
1480 static int x1830_ssi1_dr_d_pins[] = { 0x63, };
1481 static int x1830_ssi1_clk_d_pins[] = { 0x66, };
1482 static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
1483 static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
1484 static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
1485 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
1486 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
1487 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };
1488 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
1489 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
1490 static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
1491 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
1492 static int x1830_i2s_data_tx_pins[] = { 0x53, };
1493 static int x1830_i2s_data_rx_pins[] = { 0x54, };
1494 static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, };
1495 static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, };
1496 static int x1830_i2s_sysclk_pins[] = { 0x57, };
1497 static int x1830_lcd_rgb_18bit_pins[] = {
1498         0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
1499         0x68, 0x69, 0x6c, 0x6d, 0x6e, 0x6f,
1500         0x70, 0x71, 0x72, 0x73, 0x76, 0x77,
1501         0x78, 0x79, 0x7a, 0x7b,
1502 };
1503 static int x1830_lcd_slcd_8bit_pins[] = {
1504         0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d,
1505         0x69, 0x72, 0x73, 0x7b, 0x7a,
1506 };
1507 static int x1830_lcd_slcd_16bit_pins[] = {
1508         0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79,
1509 };
1510 static int x1830_pwm_pwm0_b_pins[] = { 0x31, };
1511 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };
1512 static int x1830_pwm_pwm1_b_pins[] = { 0x32, };
1513 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };
1514 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };
1515 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };
1516 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };
1517 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };
1518 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };
1519 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };
1520 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };
1521 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };
1522 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };
1523 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };
1524 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };
1525 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };
1526 static int x1830_mac_pins[] = {
1527         0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
1528 };
1529
1530 static const struct group_desc x1830_groups[] = {
1531         INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
1532         INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
1533         INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
1534         INGENIC_PIN_GROUP("sfc", x1830_sfc, 1),
1535         INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
1536         INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
1537         INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
1538         INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),
1539         INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),
1540         INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),
1541         INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),
1542         INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),
1543         INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),
1544         INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),
1545         INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),
1546         INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),
1547         INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),
1548         INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),
1549         INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),
1550         INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),
1551         INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),
1552         INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),
1553         INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),
1554         INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),
1555         INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),
1556         INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),
1557         INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),
1558         INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),
1559         INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),
1560         INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),
1561         INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),
1562         INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
1563         INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
1564         INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
1565         INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit, 0),
1566         INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
1567         INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),
1568         { "lcd-no-pins", },
1569         INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),
1570         INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),
1571         INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),
1572         INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),
1573         INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),
1574         INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),
1575         INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),
1576         INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),
1577         INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),
1578         INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),
1579         INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),
1580         INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),
1581         INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),
1582         INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),
1583         INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),
1584         INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),
1585         INGENIC_PIN_GROUP("mac", x1830_mac, 0),
1586 };
1587
1588 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1589 static const char *x1830_uart1_groups[] = { "uart1-data", };
1590 static const char *x1830_sfc_groups[] = { "sfc", };
1591 static const char *x1830_ssi0_groups[] = {
1592         "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
1593 };
1594 static const char *x1830_ssi1_groups[] = {
1595         "ssi1-dt-c", "ssi1-dt-d",
1596         "ssi1-dr-c", "ssi1-dr-d",
1597         "ssi1-clk-c", "ssi1-clk-d",
1598         "ssi1-gpc-c", "ssi1-gpc-d",
1599         "ssi1-ce0-c", "ssi1-ce0-d",
1600         "ssi1-ce1-c", "ssi1-ce1-d",
1601 };
1602 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
1603 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
1604 static const char *x1830_i2c0_groups[] = { "i2c0-data", };
1605 static const char *x1830_i2c1_groups[] = { "i2c1-data", };
1606 static const char *x1830_i2c2_groups[] = { "i2c2-data", };
1607 static const char *x1830_i2s_groups[] = {
1608         "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1609 };
1610 static const char *x1830_lcd_groups[] = {
1611         "lcd-rgb-18bit", "lcd-slcd-8bit", "lcd-slcd-16bit", "lcd-no-pins",
1612 };
1613 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
1614 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
1615 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
1616 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
1617 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
1618 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
1619 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
1620 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
1621 static const char *x1830_mac_groups[] = { "mac", };
1622
1623 static const struct function_desc x1830_functions[] = {
1624         { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), },
1625         { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), },
1626         { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), },
1627         { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), },
1628         { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), },
1629         { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), },
1630         { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), },
1631         { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
1632         { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
1633         { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
1634         { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), },
1635         { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), },
1636         { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
1637         { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },
1638         { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), },
1639         { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), },
1640         { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1641         { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1642         { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1643         { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1644         { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
1645 };
1646
1647 static const struct ingenic_chip_info x1830_chip_info = {
1648         .num_chips = 4,
1649         .reg_offset = 0x1000,
1650         .version = ID_X1830,
1651         .groups = x1830_groups,
1652         .num_groups = ARRAY_SIZE(x1830_groups),
1653         .functions = x1830_functions,
1654         .num_functions = ARRAY_SIZE(x1830_functions),
1655         .pull_ups = x1830_pull_ups,
1656         .pull_downs = x1830_pull_downs,
1657 };
1658
1659 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
1660 {
1661         unsigned int val;
1662
1663         regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
1664
1665         return (u32) val;
1666 }
1667
1668 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
1669                 u8 reg, u8 offset, bool set)
1670 {
1671         if (set)
1672                 reg = REG_SET(reg);
1673         else
1674                 reg = REG_CLEAR(reg);
1675
1676         regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
1677 }
1678
1679 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
1680                 u8 reg, u8 offset, bool set)
1681 {
1682         if (set)
1683                 reg = REG_SET(reg);
1684         else
1685                 reg = REG_CLEAR(reg);
1686
1687         regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
1688                         jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
1689 }
1690
1691 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
1692 {
1693         regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
1694                         jzgc->jzpc->info->reg_offset),
1695                         jzgc->gc.base / PINS_PER_GPIO_CHIP);
1696 }
1697
1698 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
1699                                           u8 offset)
1700 {
1701         unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
1702
1703         return !!(val & BIT(offset));
1704 }
1705
1706 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
1707                                    u8 offset, int value)
1708 {
1709         if (jzgc->jzpc->info->version >= ID_JZ4770)
1710                 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
1711         else
1712                 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
1713 }
1714
1715 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
1716                 u8 offset, unsigned int type)
1717 {
1718         u8 reg1, reg2;
1719         bool val1, val2;
1720
1721         switch (type) {
1722         case IRQ_TYPE_EDGE_RISING:
1723                 val1 = val2 = true;
1724                 break;
1725         case IRQ_TYPE_EDGE_FALLING:
1726                 val1 = false;
1727                 val2 = true;
1728                 break;
1729         case IRQ_TYPE_LEVEL_HIGH:
1730                 val1 = true;
1731                 val2 = false;
1732                 break;
1733         case IRQ_TYPE_LEVEL_LOW:
1734         default:
1735                 val1 = val2 = false;
1736                 break;
1737         }
1738
1739         if (jzgc->jzpc->info->version >= ID_JZ4770) {
1740                 reg1 = JZ4770_GPIO_PAT1;
1741                 reg2 = JZ4770_GPIO_PAT0;
1742         } else {
1743                 reg1 = JZ4740_GPIO_TRIG;
1744                 reg2 = JZ4740_GPIO_DIR;
1745         }
1746
1747         if (jzgc->jzpc->info->version >= ID_X1000) {
1748                 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
1749                 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
1750                 ingenic_gpio_shadow_set_bit_load(jzgc);
1751         } else {
1752                 ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
1753                 ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
1754         }
1755 }
1756
1757 static void ingenic_gpio_irq_mask(struct irq_data *irqd)
1758 {
1759         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1760         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1761
1762         ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
1763 }
1764
1765 static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
1766 {
1767         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1768         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1769
1770         ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
1771 }
1772
1773 static void ingenic_gpio_irq_enable(struct irq_data *irqd)
1774 {
1775         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1776         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1777         int irq = irqd->hwirq;
1778
1779         if (jzgc->jzpc->info->version >= ID_JZ4770)
1780                 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
1781         else
1782                 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
1783
1784         ingenic_gpio_irq_unmask(irqd);
1785 }
1786
1787 static void ingenic_gpio_irq_disable(struct irq_data *irqd)
1788 {
1789         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1790         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1791         int irq = irqd->hwirq;
1792
1793         ingenic_gpio_irq_mask(irqd);
1794
1795         if (jzgc->jzpc->info->version >= ID_JZ4770)
1796                 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
1797         else
1798                 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
1799 }
1800
1801 static void ingenic_gpio_irq_ack(struct irq_data *irqd)
1802 {
1803         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1804         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1805         int irq = irqd->hwirq;
1806         bool high;
1807
1808         if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) {
1809                 /*
1810                  * Switch to an interrupt for the opposite edge to the one that
1811                  * triggered the interrupt being ACKed.
1812                  */
1813                 high = ingenic_gpio_get_value(jzgc, irq);
1814                 if (high)
1815                         irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
1816                 else
1817                         irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
1818         }
1819
1820         if (jzgc->jzpc->info->version >= ID_JZ4770)
1821                 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
1822         else
1823                 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
1824 }
1825
1826 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
1827 {
1828         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1829         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1830
1831         switch (type) {
1832         case IRQ_TYPE_EDGE_BOTH:
1833         case IRQ_TYPE_EDGE_RISING:
1834         case IRQ_TYPE_EDGE_FALLING:
1835                 irq_set_handler_locked(irqd, handle_edge_irq);
1836                 break;
1837         case IRQ_TYPE_LEVEL_HIGH:
1838         case IRQ_TYPE_LEVEL_LOW:
1839                 irq_set_handler_locked(irqd, handle_level_irq);
1840                 break;
1841         default:
1842                 irq_set_handler_locked(irqd, handle_bad_irq);
1843         }
1844
1845         if (type == IRQ_TYPE_EDGE_BOTH) {
1846                 /*
1847                  * The hardware does not support interrupts on both edges. The
1848                  * best we can do is to set up a single-edge interrupt and then
1849                  * switch to the opposing edge when ACKing the interrupt.
1850                  */
1851                 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
1852
1853                 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH;
1854         }
1855
1856         irq_set_type(jzgc, irqd->hwirq, type);
1857         return 0;
1858 }
1859
1860 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
1861 {
1862         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
1863         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1864
1865         return irq_set_irq_wake(jzgc->irq, on);
1866 }
1867
1868 static void ingenic_gpio_irq_handler(struct irq_desc *desc)
1869 {
1870         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1871         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1872         struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
1873         unsigned long flag, i;
1874
1875         chained_irq_enter(irq_chip, desc);
1876
1877         if (jzgc->jzpc->info->version >= ID_JZ4770)
1878                 flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
1879         else
1880                 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
1881
1882         for_each_set_bit(i, &flag, 32)
1883                 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
1884         chained_irq_exit(irq_chip, desc);
1885 }
1886
1887 static void ingenic_gpio_set(struct gpio_chip *gc,
1888                 unsigned int offset, int value)
1889 {
1890         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1891
1892         ingenic_gpio_set_value(jzgc, offset, value);
1893 }
1894
1895 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
1896 {
1897         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1898
1899         return (int) ingenic_gpio_get_value(jzgc, offset);
1900 }
1901
1902 static int ingenic_gpio_direction_input(struct gpio_chip *gc,
1903                 unsigned int offset)
1904 {
1905         return pinctrl_gpio_direction_input(gc->base + offset);
1906 }
1907
1908 static int ingenic_gpio_direction_output(struct gpio_chip *gc,
1909                 unsigned int offset, int value)
1910 {
1911         ingenic_gpio_set(gc, offset, value);
1912         return pinctrl_gpio_direction_output(gc->base + offset);
1913 }
1914
1915 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
1916                 unsigned int pin, u8 reg, bool set)
1917 {
1918         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1919         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1920
1921         regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
1922                         (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
1923 }
1924
1925 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
1926                 unsigned int pin, u8 reg, bool set)
1927 {
1928         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1929
1930         regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +
1931                         (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
1932 }
1933
1934 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
1935                 unsigned int pin)
1936 {
1937         regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),
1938                         pin / PINS_PER_GPIO_CHIP);
1939 }
1940
1941 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
1942                 unsigned int pin, u8 reg)
1943 {
1944         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1945         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1946         unsigned int val;
1947
1948         regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);
1949
1950         return val & BIT(idx);
1951 }
1952
1953 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1954 {
1955         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
1956         struct ingenic_pinctrl *jzpc = jzgc->jzpc;
1957         unsigned int pin = gc->base + offset;
1958
1959         if (jzpc->info->version >= ID_JZ4770) {
1960                 if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) ||
1961                     ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1))
1962                         return GPIO_LINE_DIRECTION_IN;
1963                 return GPIO_LINE_DIRECTION_OUT;
1964         }
1965
1966         if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
1967                 return GPIO_LINE_DIRECTION_IN;
1968
1969         if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR))
1970                 return GPIO_LINE_DIRECTION_OUT;
1971
1972         return GPIO_LINE_DIRECTION_IN;
1973 }
1974
1975 static const struct pinctrl_ops ingenic_pctlops = {
1976         .get_groups_count = pinctrl_generic_get_group_count,
1977         .get_group_name = pinctrl_generic_get_group_name,
1978         .get_group_pins = pinctrl_generic_get_group_pins,
1979         .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
1980         .dt_free_map = pinconf_generic_dt_free_map,
1981 };
1982
1983 static int ingenic_gpio_irq_request(struct irq_data *data)
1984 {
1985         struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
1986         int ret;
1987
1988         ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq);
1989         if (ret)
1990                 return ret;
1991
1992         return gpiochip_reqres_irq(gpio_chip, data->hwirq);
1993 }
1994
1995 static void ingenic_gpio_irq_release(struct irq_data *data)
1996 {
1997         struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
1998
1999         return gpiochip_relres_irq(gpio_chip, data->hwirq);
2000 }
2001
2002 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
2003                 int pin, int func)
2004 {
2005         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2006         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2007
2008         dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
2009                         'A' + offt, idx, func);
2010
2011         if (jzpc->info->version >= ID_X1000) {
2012                 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
2013                 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
2014                 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
2015                 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
2016                 ingenic_shadow_config_pin_load(jzpc, pin);
2017         } else if (jzpc->info->version >= ID_JZ4770) {
2018                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
2019                 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
2020                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
2021                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
2022         } else {
2023                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
2024                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
2025                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1);
2026         }
2027
2028         return 0;
2029 }
2030
2031 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
2032                 unsigned int selector, unsigned int group)
2033 {
2034         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2035         struct function_desc *func;
2036         struct group_desc *grp;
2037         unsigned int i;
2038         uintptr_t mode;
2039         u8 *pin_modes;
2040
2041         func = pinmux_generic_get_function(pctldev, selector);
2042         if (!func)
2043                 return -EINVAL;
2044
2045         grp = pinctrl_generic_get_group(pctldev, group);
2046         if (!grp)
2047                 return -EINVAL;
2048
2049         dev_dbg(pctldev->dev, "enable function %s group %s\n",
2050                 func->name, grp->name);
2051
2052         mode = (uintptr_t)grp->data;
2053         if (mode <= 3) {
2054                 for (i = 0; i < grp->num_pins; i++)
2055                         ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode);
2056         } else {
2057                 pin_modes = grp->data;
2058
2059                 for (i = 0; i < grp->num_pins; i++)
2060                         ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
2061         }
2062
2063         return 0;
2064 }
2065
2066 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
2067                 struct pinctrl_gpio_range *range,
2068                 unsigned int pin, bool input)
2069 {
2070         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2071         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2072         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2073
2074         dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
2075                         'A' + offt, idx, input ? "in" : "out");
2076
2077         if (jzpc->info->version >= ID_X1000) {
2078                 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
2079                 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
2080                 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
2081                 ingenic_shadow_config_pin_load(jzpc, pin);
2082         } else if (jzpc->info->version >= ID_JZ4770) {
2083                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
2084                 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
2085                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
2086         } else {
2087                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
2088                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
2089                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
2090         }
2091
2092         return 0;
2093 }
2094
2095 static const struct pinmux_ops ingenic_pmxops = {
2096         .get_functions_count = pinmux_generic_get_function_count,
2097         .get_function_name = pinmux_generic_get_function_name,
2098         .get_function_groups = pinmux_generic_get_function_groups,
2099         .set_mux = ingenic_pinmux_set_mux,
2100         .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
2101 };
2102
2103 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
2104                 unsigned int pin, unsigned long *config)
2105 {
2106         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2107         enum pin_config_param param = pinconf_to_config_param(*config);
2108         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2109         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2110         bool pull;
2111
2112         if (jzpc->info->version >= ID_JZ4770)
2113                 pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
2114         else
2115                 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
2116
2117         switch (param) {
2118         case PIN_CONFIG_BIAS_DISABLE:
2119                 if (pull)
2120                         return -EINVAL;
2121                 break;
2122
2123         case PIN_CONFIG_BIAS_PULL_UP:
2124                 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))
2125                         return -EINVAL;
2126                 break;
2127
2128         case PIN_CONFIG_BIAS_PULL_DOWN:
2129                 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))
2130                         return -EINVAL;
2131                 break;
2132
2133         default:
2134                 return -ENOTSUPP;
2135         }
2136
2137         *config = pinconf_to_config_packed(param, 1);
2138         return 0;
2139 }
2140
2141 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
2142                 unsigned int pin, unsigned int bias)
2143 {
2144         if (jzpc->info->version >= ID_X1830) {
2145                 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2146                 unsigned int half = PINS_PER_GPIO_CHIP / 2;
2147                 unsigned int idxh = pin % half * 2;
2148                 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2149
2150                 if (idx < half) {
2151                         regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2152                                         REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);
2153                         regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2154                                         REG_SET(X1830_GPIO_PEL), bias << idxh);
2155                 } else {
2156                         regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2157                                         REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);
2158                         regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2159                                         REG_SET(X1830_GPIO_PEH), bias << idxh);
2160                 }
2161
2162         } else if (jzpc->info->version >= ID_JZ4770) {
2163                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias);
2164         } else {
2165                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
2166         }
2167 }
2168
2169 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
2170                                      unsigned int pin, bool high)
2171 {
2172         if (jzpc->info->version >= ID_JZ4770)
2173                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high);
2174         else
2175                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
2176 }
2177
2178 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2179                 unsigned long *configs, unsigned int num_configs)
2180 {
2181         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2182         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2183         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2184         unsigned int cfg, arg;
2185         int ret;
2186
2187         for (cfg = 0; cfg < num_configs; cfg++) {
2188                 switch (pinconf_to_config_param(configs[cfg])) {
2189                 case PIN_CONFIG_BIAS_DISABLE:
2190                 case PIN_CONFIG_BIAS_PULL_UP:
2191                 case PIN_CONFIG_BIAS_PULL_DOWN:
2192                 case PIN_CONFIG_OUTPUT:
2193                         continue;
2194                 default:
2195                         return -ENOTSUPP;
2196                 }
2197         }
2198
2199         for (cfg = 0; cfg < num_configs; cfg++) {
2200                 arg = pinconf_to_config_argument(configs[cfg]);
2201
2202                 switch (pinconf_to_config_param(configs[cfg])) {
2203                 case PIN_CONFIG_BIAS_DISABLE:
2204                         dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
2205                                         'A' + offt, idx);
2206                         ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);
2207                         break;
2208
2209                 case PIN_CONFIG_BIAS_PULL_UP:
2210                         if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
2211                                 return -EINVAL;
2212                         dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
2213                                         'A' + offt, idx);
2214                         ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);
2215                         break;
2216
2217                 case PIN_CONFIG_BIAS_PULL_DOWN:
2218                         if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
2219                                 return -EINVAL;
2220                         dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
2221                                         'A' + offt, idx);
2222                         ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);
2223                         break;
2224
2225                 case PIN_CONFIG_OUTPUT:
2226                         ret = pinctrl_gpio_direction_output(pin);
2227                         if (ret)
2228                                 return ret;
2229
2230                         ingenic_set_output_level(jzpc, pin, arg);
2231                         break;
2232
2233                 default:
2234                         /* unreachable */
2235                         break;
2236                 }
2237         }
2238
2239         return 0;
2240 }
2241
2242 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
2243                 unsigned int group, unsigned long *config)
2244 {
2245         const unsigned int *pins;
2246         unsigned int i, npins, old = 0;
2247         int ret;
2248
2249         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
2250         if (ret)
2251                 return ret;
2252
2253         for (i = 0; i < npins; i++) {
2254                 if (ingenic_pinconf_get(pctldev, pins[i], config))
2255                         return -ENOTSUPP;
2256
2257                 /* configs do not match between two pins */
2258                 if (i && (old != *config))
2259                         return -ENOTSUPP;
2260
2261                 old = *config;
2262         }
2263
2264         return 0;
2265 }
2266
2267 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
2268                 unsigned int group, unsigned long *configs,
2269                 unsigned int num_configs)
2270 {
2271         const unsigned int *pins;
2272         unsigned int i, npins;
2273         int ret;
2274
2275         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
2276         if (ret)
2277                 return ret;
2278
2279         for (i = 0; i < npins; i++) {
2280                 ret = ingenic_pinconf_set(pctldev,
2281                                 pins[i], configs, num_configs);
2282                 if (ret)
2283                         return ret;
2284         }
2285
2286         return 0;
2287 }
2288
2289 static const struct pinconf_ops ingenic_confops = {
2290         .is_generic = true,
2291         .pin_config_get = ingenic_pinconf_get,
2292         .pin_config_set = ingenic_pinconf_set,
2293         .pin_config_group_get = ingenic_pinconf_group_get,
2294         .pin_config_group_set = ingenic_pinconf_group_set,
2295 };
2296
2297 static const struct regmap_config ingenic_pinctrl_regmap_config = {
2298         .reg_bits = 32,
2299         .val_bits = 32,
2300         .reg_stride = 4,
2301 };
2302
2303 static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
2304         { .compatible = "ingenic,jz4740-gpio", },
2305         { .compatible = "ingenic,jz4725b-gpio", },
2306         { .compatible = "ingenic,jz4760-gpio", },
2307         { .compatible = "ingenic,jz4770-gpio", },
2308         { .compatible = "ingenic,jz4780-gpio", },
2309         { .compatible = "ingenic,x1000-gpio", },
2310         { .compatible = "ingenic,x1830-gpio", },
2311         {},
2312 };
2313
2314 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
2315                                      struct device_node *node)
2316 {
2317         struct ingenic_gpio_chip *jzgc;
2318         struct device *dev = jzpc->dev;
2319         struct gpio_irq_chip *girq;
2320         unsigned int bank;
2321         int err;
2322
2323         err = of_property_read_u32(node, "reg", &bank);
2324         if (err) {
2325                 dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
2326                 return err;
2327         }
2328
2329         jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
2330         if (!jzgc)
2331                 return -ENOMEM;
2332
2333         jzgc->jzpc = jzpc;
2334         jzgc->reg_base = bank * jzpc->info->reg_offset;
2335
2336         jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
2337         if (!jzgc->gc.label)
2338                 return -ENOMEM;
2339
2340         /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
2341          * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
2342          * <linux/gpio/consumer.h> INSTEAD.
2343          */
2344         jzgc->gc.base = bank * 32;
2345
2346         jzgc->gc.ngpio = 32;
2347         jzgc->gc.parent = dev;
2348         jzgc->gc.of_node = node;
2349         jzgc->gc.owner = THIS_MODULE;
2350
2351         jzgc->gc.set = ingenic_gpio_set;
2352         jzgc->gc.get = ingenic_gpio_get;
2353         jzgc->gc.direction_input = ingenic_gpio_direction_input;
2354         jzgc->gc.direction_output = ingenic_gpio_direction_output;
2355         jzgc->gc.get_direction = ingenic_gpio_get_direction;
2356         jzgc->gc.request = gpiochip_generic_request;
2357         jzgc->gc.free = gpiochip_generic_free;
2358
2359         jzgc->irq = irq_of_parse_and_map(node, 0);
2360         if (!jzgc->irq)
2361                 return -EINVAL;
2362
2363         jzgc->irq_chip.name = jzgc->gc.label;
2364         jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
2365         jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
2366         jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
2367         jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
2368         jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
2369         jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
2370         jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
2371         jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request;
2372         jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release;
2373         jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
2374
2375         girq = &jzgc->gc.irq;
2376         girq->chip = &jzgc->irq_chip;
2377         girq->parent_handler = ingenic_gpio_irq_handler;
2378         girq->num_parents = 1;
2379         girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
2380                                      GFP_KERNEL);
2381         if (!girq->parents)
2382                 return -ENOMEM;
2383         girq->parents[0] = jzgc->irq;
2384         girq->default_type = IRQ_TYPE_NONE;
2385         girq->handler = handle_level_irq;
2386
2387         err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
2388         if (err)
2389                 return err;
2390
2391         return 0;
2392 }
2393
2394 static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
2395 {
2396         struct device *dev = &pdev->dev;
2397         struct ingenic_pinctrl *jzpc;
2398         struct pinctrl_desc *pctl_desc;
2399         void __iomem *base;
2400         const struct ingenic_chip_info *chip_info;
2401         struct device_node *node;
2402         unsigned int i;
2403         int err;
2404
2405         chip_info = of_device_get_match_data(dev);
2406         if (!chip_info) {
2407                 dev_err(dev, "Unsupported SoC\n");
2408                 return -EINVAL;
2409         }
2410
2411         jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
2412         if (!jzpc)
2413                 return -ENOMEM;
2414
2415         base = devm_platform_ioremap_resource(pdev, 0);
2416         if (IS_ERR(base))
2417                 return PTR_ERR(base);
2418
2419         jzpc->map = devm_regmap_init_mmio(dev, base,
2420                         &ingenic_pinctrl_regmap_config);
2421         if (IS_ERR(jzpc->map)) {
2422                 dev_err(dev, "Failed to create regmap\n");
2423                 return PTR_ERR(jzpc->map);
2424         }
2425
2426         jzpc->dev = dev;
2427         jzpc->info = chip_info;
2428
2429         pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
2430         if (!pctl_desc)
2431                 return -ENOMEM;
2432
2433         /* fill in pinctrl_desc structure */
2434         pctl_desc->name = dev_name(dev);
2435         pctl_desc->owner = THIS_MODULE;
2436         pctl_desc->pctlops = &ingenic_pctlops;
2437         pctl_desc->pmxops = &ingenic_pmxops;
2438         pctl_desc->confops = &ingenic_confops;
2439         pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
2440         pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
2441                         pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
2442         if (!jzpc->pdesc)
2443                 return -ENOMEM;
2444
2445         for (i = 0; i < pctl_desc->npins; i++) {
2446                 jzpc->pdesc[i].number = i;
2447                 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
2448                                                 'A' + (i / PINS_PER_GPIO_CHIP),
2449                                                 i % PINS_PER_GPIO_CHIP);
2450         }
2451
2452         jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
2453         if (IS_ERR(jzpc->pctl)) {
2454                 dev_err(dev, "Failed to register pinctrl\n");
2455                 return PTR_ERR(jzpc->pctl);
2456         }
2457
2458         for (i = 0; i < chip_info->num_groups; i++) {
2459                 const struct group_desc *group = &chip_info->groups[i];
2460
2461                 err = pinctrl_generic_add_group(jzpc->pctl, group->name,
2462                                 group->pins, group->num_pins, group->data);
2463                 if (err < 0) {
2464                         dev_err(dev, "Failed to register group %s\n",
2465                                         group->name);
2466                         return err;
2467                 }
2468         }
2469
2470         for (i = 0; i < chip_info->num_functions; i++) {
2471                 const struct function_desc *func = &chip_info->functions[i];
2472
2473                 err = pinmux_generic_add_function(jzpc->pctl, func->name,
2474                                 func->group_names, func->num_group_names,
2475                                 func->data);
2476                 if (err < 0) {
2477                         dev_err(dev, "Failed to register function %s\n",
2478                                         func->name);
2479                         return err;
2480                 }
2481         }
2482
2483         dev_set_drvdata(dev, jzpc->map);
2484
2485         for_each_child_of_node(dev->of_node, node) {
2486                 if (of_match_node(ingenic_gpio_of_match, node)) {
2487                         err = ingenic_gpio_probe(jzpc, node);
2488                         if (err)
2489                                 return err;
2490                 }
2491         }
2492
2493         return 0;
2494 }
2495
2496 static const struct of_device_id ingenic_pinctrl_of_match[] = {
2497         {
2498                 .compatible = "ingenic,jz4740-pinctrl",
2499                 .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info)
2500         },
2501         {
2502                 .compatible = "ingenic,jz4725b-pinctrl",
2503                 .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info)
2504         },
2505         {
2506                 .compatible = "ingenic,jz4760-pinctrl",
2507                 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
2508         },
2509         {
2510                 .compatible = "ingenic,jz4760b-pinctrl",
2511                 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
2512         },
2513         {
2514                 .compatible = "ingenic,jz4770-pinctrl",
2515                 .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info)
2516         },
2517         {
2518                 .compatible = "ingenic,jz4780-pinctrl",
2519                 .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info)
2520         },
2521         {
2522                 .compatible = "ingenic,x1000-pinctrl",
2523                 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
2524         },
2525         {
2526                 .compatible = "ingenic,x1000e-pinctrl",
2527                 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
2528         },
2529         {
2530                 .compatible = "ingenic,x1500-pinctrl",
2531                 .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info)
2532         },
2533         {
2534                 .compatible = "ingenic,x1830-pinctrl",
2535                 .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info)
2536         },
2537         { /* sentinel */ },
2538 };
2539
2540 static struct platform_driver ingenic_pinctrl_driver = {
2541         .driver = {
2542                 .name = "pinctrl-ingenic",
2543                 .of_match_table = ingenic_pinctrl_of_match,
2544         },
2545 };
2546
2547 static int __init ingenic_pinctrl_drv_register(void)
2548 {
2549         return platform_driver_probe(&ingenic_pinctrl_driver,
2550                                      ingenic_pinctrl_probe);
2551 }
2552 subsys_initcall(ingenic_pinctrl_drv_register);