drivers/pinctrl/pinctrl-gemini.c

   1 /*
   2  * Driver for the Gemini pin controller
   3  *
   4  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
   5  *
   6  * This is a group-only pin controller.
   7  */
   8 #include <linux/err.h>
   9 #include <linux/init.h>
  10 #include <linux/io.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/of.h>
  13 #include <linux/pinctrl/machine.h>
  14 #include <linux/pinctrl/pinctrl.h>
  15 #include <linux/pinctrl/pinmux.h>
  16 #include <linux/pinctrl/pinconf.h>
  17 #include <linux/pinctrl/pinconf-generic.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/slab.h>
  20 #include <linux/regmap.h>
  21
  22 #include "pinctrl-utils.h"
  23
  24 #define DRIVER_NAME "pinctrl-gemini"
  25
  26 /**
  27  * struct gemini_pin_conf - information about configuring a pin
  28  * @pin: the pin number
  29  * @reg: config register
  30  * @mask: the bits affecting the configuration of the pin
  31  */
  32 struct gemini_pin_conf {
  33         unsigned int pin;
  34         u32 reg;
  35         u32 mask;
  36 };
  37
  38 /**
  39  * struct gemini_pmx - state holder for the gemini pin controller
  40  * @dev: a pointer back to containing device
  41  * @virtbase: the offset to the controller in virtual memory
  42  * @map: regmap to access registers
  43  * @is_3512: whether the SoC/package is the 3512 variant
  44  * @is_3516: whether the SoC/package is the 3516 variant
  45  * @flash_pin: whether the flash pin (extended pins for parallel
  46  * flash) is set
  47  * @confs: pin config information
  48  * @nconfs: number of pin config information items
  49  */
  50 struct gemini_pmx {
  51         struct device *dev;
  52         struct pinctrl_dev *pctl;
  53         struct regmap *map;
  54         bool is_3512;
  55         bool is_3516;
  56         bool flash_pin;
  57         const struct gemini_pin_conf *confs;
  58         unsigned int nconfs;
  59 };
  60
  61 /**
  62  * struct gemini_pin_group - describes a Gemini pin group
  63  * @name: the name of this specific pin group
  64  * @pins: an array of discrete physical pins used in this group, taken
  65  *      from the driver-local pin enumeration space
  66  * @num_pins: the number of pins in this group array, i.e. the number of
  67  *      elements in .pins so we can iterate over that array
  68  * @mask: bits to clear to enable this when doing pin muxing
  69  * @value: bits to set to enable this when doing pin muxing
  70  */
  71 struct gemini_pin_group {
  72         const char *name;
  73         const unsigned int *pins;
  74         const unsigned int num_pins;
  75         u32 mask;
  76         u32 value;
  77 };
  78
  79 /* Some straight-forward control registers */
  80 #define GLOBAL_WORD_ID          0x00
  81 #define GLOBAL_STATUS           0x04
  82 #define GLOBAL_STATUS_FLPIN     BIT(20)
  83 #define GLOBAL_GMAC_CTRL_SKEW   0x1c
  84 #define GLOBAL_GMAC0_DATA_SKEW  0x20
  85 #define GLOBAL_GMAC1_DATA_SKEW  0x24
  86 /*
  87  * Global Miscellaneous Control Register
  88  * This register controls all Gemini pad/pin multiplexing
  89  *
  90  * It is a tricky register though:
  91  * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
  92  *   be brought back online, so it means permanent disablement of the
  93  *   corresponding pads.
  94  * - For the bits named *_DISABLE, once you enable something, it cannot be
  95  *   DISABLED again. So you select a flash configuration once, and then
  96  *   you are stuck with it.
  97  */
  98 #define GLOBAL_MISC_CTRL        0x30
  99 #define TVC_CLK_PAD_ENABLE      BIT(20)
 100 #define PCI_CLK_PAD_ENABLE      BIT(17)
 101 #define LPC_CLK_PAD_ENABLE      BIT(16)
 102 #define TVC_PADS_ENABLE         BIT(9)
 103 #define SSP_PADS_ENABLE         BIT(8)
 104 #define LCD_PADS_ENABLE         BIT(7)
 105 #define LPC_PADS_ENABLE         BIT(6)
 106 #define PCI_PADS_ENABLE         BIT(5)
 107 #define IDE_PADS_ENABLE         BIT(4)
 108 #define DRAM_PADS_POWERDOWN     BIT(3)
 109 #define NAND_PADS_DISABLE       BIT(2)
 110 #define PFLASH_PADS_DISABLE     BIT(1)
 111 #define SFLASH_PADS_DISABLE     BIT(0)
 112 #define PADS_MASK               (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20))
 113 #define PADS_MAXBIT             20
 114
 115 /* Ordered by bit index */
 116 static const char * const gemini_padgroups[] = {
 117         "serial flash",
 118         "parallel flash",
 119         "NAND flash",
 120         "DRAM",
 121         "IDE",
 122         "PCI",
 123         "LPC",
 124         "LCD",
 125         "SSP",
 126         "TVC",
 127         NULL, NULL, NULL, NULL, NULL, NULL,
 128         "LPC CLK",
 129         "PCI CLK",
 130         NULL, NULL,
 131         "TVC CLK",
 132 };
 133
 134 static const struct pinctrl_pin_desc gemini_3512_pins[] = {
 135         /* Row A */
 136         PINCTRL_PIN(0, "A1 VREF CTRL"),
 137         PINCTRL_PIN(1, "A2 VCC2IO CTRL"),
 138         PINCTRL_PIN(2, "A3 DRAM CK"),
 139         PINCTRL_PIN(3, "A4 DRAM CK N"),
 140         PINCTRL_PIN(4, "A5 DRAM A5"),
 141         PINCTRL_PIN(5, "A6 DRAM CKE"),
 142         PINCTRL_PIN(6, "A7 DRAM DQ11"),
 143         PINCTRL_PIN(7, "A8 DRAM DQ0"),
 144         PINCTRL_PIN(8, "A9 DRAM DQ5"),
 145         PINCTRL_PIN(9, "A10 DRAM DQ6"),
 146         PINCTRL_PIN(10, "A11 DRAM DRAM VREF"),
 147         PINCTRL_PIN(11, "A12 DRAM BA1"),
 148         PINCTRL_PIN(12, "A13 DRAM A2"),
 149         PINCTRL_PIN(13, "A14 PCI GNT1 N"),
 150         PINCTRL_PIN(14, "A15 PCI REQ9 N"),
 151         PINCTRL_PIN(15, "A16 PCI REQ2 N"),
 152         PINCTRL_PIN(16, "A17 PCI REQ3 N"),
 153         PINCTRL_PIN(17, "A18 PCI AD31"),
 154         /* Row B */
 155         PINCTRL_PIN(18, "B1 VCCK CTRL"),
 156         PINCTRL_PIN(19, "B2 PWR EN"),
 157         PINCTRL_PIN(20, "B3 RTC CLKI"),
 158         PINCTRL_PIN(21, "B4 DRAM A4"),
 159         PINCTRL_PIN(22, "B5 DRAM A6"),
 160         PINCTRL_PIN(23, "B6 DRAM A12"),
 161         PINCTRL_PIN(24, "B7 DRAM DQS1"),
 162         PINCTRL_PIN(25, "B8 DRAM DQ15"),
 163         PINCTRL_PIN(26, "B9 DRAM DQ4"),
 164         PINCTRL_PIN(27, "B10 DRAM DQS0"),
 165         PINCTRL_PIN(28, "B11 DRAM WE N"),
 166         PINCTRL_PIN(29, "B12 DRAM A10"),
 167         PINCTRL_PIN(30, "B13 DRAM A3"),
 168         PINCTRL_PIN(31, "B14 PCI GNT0 N"),
 169         PINCTRL_PIN(32, "B15 PCI GNT3 N"),
 170         PINCTRL_PIN(33, "B16 PCI REQ1 N"),
 171         PINCTRL_PIN(34, "B17 PCI AD30"),
 172         PINCTRL_PIN(35, "B18 PCI AD29"),
 173         /* Row C */
 174         PINCTRL_PIN(36, "C1 CIR RST N"), /* REALLY? CIR is not in 3512... */
 175         PINCTRL_PIN(37, "C2 XTALI"),
 176         PINCTRL_PIN(38, "C3 PWR BTN"),
 177         PINCTRL_PIN(39, "C4 RTC CLKO"),
 178         PINCTRL_PIN(40, "C5 DRAM A7"),
 179         PINCTRL_PIN(41, "C6 DRAM A11"),
 180         PINCTRL_PIN(42, "C7 DRAM DQ10"),
 181         PINCTRL_PIN(43, "C8 DRAM DQ14"),
 182         PINCTRL_PIN(44, "C9 DRAM DQ3"),
 183         PINCTRL_PIN(45, "C10 DRAM DQ7"),
 184         PINCTRL_PIN(46, "C11 DRAM CAS N"),
 185         PINCTRL_PIN(47, "C12 DRAM A0"),
 186         PINCTRL_PIN(48, "C13 PCI INT0 N"),
 187         PINCTRL_PIN(49, "C14 EXT RESET N"),
 188         PINCTRL_PIN(50, "C15 PCI GNT2 N"),
 189         PINCTRL_PIN(51, "C16 PCI AD28"),
 190         PINCTRL_PIN(52, "C17 PCI AD27"),
 191         PINCTRL_PIN(53, "C18 PCI AD26"),
 192         /* Row D */
 193         PINCTRL_PIN(54, "D1 AVCCKHA"),
 194         PINCTRL_PIN(55, "D2 AGNDIOHA"),
 195         PINCTRL_PIN(56, "D3 XTALO"),
 196         PINCTRL_PIN(57, "D4 AVCC3IOHA"),
 197         PINCTRL_PIN(58, "D5 DRAM A8"),
 198         PINCTRL_PIN(59, "D6 DRAM A9"),
 199         PINCTRL_PIN(60, "D7 DRAM DQ9"),
 200         PINCTRL_PIN(61, "D8 DRAM DQ13"),
 201         PINCTRL_PIN(62, "D9 DRAM DQ2"),
 202         PINCTRL_PIN(63, "D10 DRAM A13"),
 203         PINCTRL_PIN(64, "D11 DRAM RAS N"),
 204         PINCTRL_PIN(65, "D12 DRAM A1"),
 205         PINCTRL_PIN(66, "D13 PCI INTC N"),
 206         PINCTRL_PIN(67, "D14 PCI CLK"),
 207         PINCTRL_PIN(68, "D15 PCI AD25"),
 208         PINCTRL_PIN(69, "D16 PCI AD24"),
 209         PINCTRL_PIN(70, "D17 PCI CBE3 N"),
 210         PINCTRL_PIN(71, "D18 PCI AD23"),
 211         /* Row E */
 212         PINCTRL_PIN(72, "E1 AVCC3IOHA"),
 213         PINCTRL_PIN(73, "E2 EBG"),
 214         PINCTRL_PIN(74, "E3 AVCC3IOHB"),
 215         PINCTRL_PIN(75, "E4 REXT"),
 216         PINCTRL_PIN(76, "E5 GND"),
 217         PINCTRL_PIN(77, "E6 DRAM DQM1"),
 218         PINCTRL_PIN(78, "E7 DRAM DQ8"),
 219         PINCTRL_PIN(79, "E8 DRAM DQ12"),
 220         PINCTRL_PIN(80, "E9 DRAM DQ1"),
 221         PINCTRL_PIN(81, "E10 DRAM DQM0"),
 222         PINCTRL_PIN(82, "E11 DRAM BA0"),
 223         PINCTRL_PIN(83, "E12 PCI INTA N"),
 224         PINCTRL_PIN(84, "E13 PCI INTB N"),
 225         PINCTRL_PIN(85, "E14 GND"),
 226         PINCTRL_PIN(86, "E15 PCI AD22"),
 227         PINCTRL_PIN(87, "E16 PCI AD21"),
 228         PINCTRL_PIN(88, "E17 PCI AD20"),
 229         PINCTRL_PIN(89, "E18 PCI AD19"),
 230         /* Row F */
 231         PINCTRL_PIN(90, "F1 SATA0 RXDP"),
 232         PINCTRL_PIN(91, "F2 SATA0 RXDN"),
 233         PINCTRL_PIN(92, "F3 AGNDK 0"),
 234         PINCTRL_PIN(93, "F4 AVCC3 S"),
 235         PINCTRL_PIN(94, "F5 AVCCK P"),
 236         PINCTRL_PIN(95, "F6 GND"),
 237         PINCTRL_PIN(96, "F7 VCC2IOHA 2"),
 238         PINCTRL_PIN(97, "F8 VCC2IOHA 2"),
 239         PINCTRL_PIN(98, "F9 V1"),
 240         PINCTRL_PIN(99, "F10 V1"),
 241         PINCTRL_PIN(100, "F11 VCC2IOHA 2"),
 242         PINCTRL_PIN(101, "F12 VCC2IOHA 2"),
 243         PINCTRL_PIN(102, "F13 GND"),
 244         PINCTRL_PIN(103, "F14 PCI AD18"),
 245         PINCTRL_PIN(104, "F15 PCI AD17"),
 246         PINCTRL_PIN(105, "F16 PCI AD16"),
 247         PINCTRL_PIN(106, "F17 PCI CBE2 N"),
 248         PINCTRL_PIN(107, "F18 PCI FRAME N"),
 249         /* Row G */
 250         PINCTRL_PIN(108, "G1 SATA0 TXDP"),
 251         PINCTRL_PIN(109, "G2 SATA0 TXDN"),
 252         PINCTRL_PIN(110, "G3 AGNDK 1"),
 253         PINCTRL_PIN(111, "G4 AVCCK 0"),
 254         PINCTRL_PIN(112, "G5 TEST CLKOUT"),
 255         PINCTRL_PIN(113, "G6 AGND"),
 256         PINCTRL_PIN(114, "G7 GND"),
 257         PINCTRL_PIN(115, "G8 VCC2IOHA 2"),
 258         PINCTRL_PIN(116, "G9 V1"),
 259         PINCTRL_PIN(117, "G10 V1"),
 260         PINCTRL_PIN(118, "G11 VCC2IOHA 2"),
 261         PINCTRL_PIN(119, "G12 GND"),
 262         PINCTRL_PIN(120, "G13 VCC3IOHA"),
 263         PINCTRL_PIN(121, "G14 PCI IRDY N"),
 264         PINCTRL_PIN(122, "G15 PCI TRDY N"),
 265         PINCTRL_PIN(123, "G16 PCI DEVSEL N"),
 266         PINCTRL_PIN(124, "G17 PCI STOP N"),
 267         PINCTRL_PIN(125, "G18 PCI PAR"),
 268         /* Row H */
 269         PINCTRL_PIN(126, "H1 SATA1 TXDP"),
 270         PINCTRL_PIN(127, "H2 SATA1 TXDN"),
 271         PINCTRL_PIN(128, "H3 AGNDK 2"),
 272         PINCTRL_PIN(129, "H4 AVCCK 1"),
 273         PINCTRL_PIN(130, "H5 AVCCK S"),
 274         PINCTRL_PIN(131, "H6 AVCCKHB"),
 275         PINCTRL_PIN(132, "H7 AGND"),
 276         PINCTRL_PIN(133, "H8 GND"),
 277         PINCTRL_PIN(134, "H9 GND"),
 278         PINCTRL_PIN(135, "H10 GND"),
 279         PINCTRL_PIN(136, "H11 GND"),
 280         PINCTRL_PIN(137, "H12 VCC3IOHA"),
 281         PINCTRL_PIN(138, "H13 VCC3IOHA"),
 282         PINCTRL_PIN(139, "H14 PCI CBE1 N"),
 283         PINCTRL_PIN(140, "H15 PCI AD15"),
 284         PINCTRL_PIN(141, "H16 PCI AD14"),
 285         PINCTRL_PIN(142, "H17 PCI AD13"),
 286         PINCTRL_PIN(143, "H18 PCI AD12"),
 287         /* Row J (for some reason I is skipped) */
 288         PINCTRL_PIN(144, "J1 SATA1 RXDP"),
 289         PINCTRL_PIN(145, "J2 SATA1 RXDN"),
 290         PINCTRL_PIN(146, "J3 AGNDK 3"),
 291         PINCTRL_PIN(147, "J4 AVCCK 2"),
 292         PINCTRL_PIN(148, "J5 IDE DA1"),
 293         PINCTRL_PIN(149, "J6 V1"),
 294         PINCTRL_PIN(150, "J7 V1"),
 295         PINCTRL_PIN(151, "J8 GND"),
 296         PINCTRL_PIN(152, "J9 GND"),
 297         PINCTRL_PIN(153, "J10 GND"),
 298         PINCTRL_PIN(154, "J11 GND"),
 299         PINCTRL_PIN(155, "J12 V1"),
 300         PINCTRL_PIN(156, "J13 V1"),
 301         PINCTRL_PIN(157, "J14 PCI AD11"),
 302         PINCTRL_PIN(158, "J15 PCI AD10"),
 303         PINCTRL_PIN(159, "J16 PCI AD9"),
 304         PINCTRL_PIN(160, "J17 PCI AD8"),
 305         PINCTRL_PIN(161, "J18 PCI CBE0 N"),
 306         /* Row K */
 307         PINCTRL_PIN(162, "K1 IDE CS1 N"),
 308         PINCTRL_PIN(163, "K2 IDE CS0 N"),
 309         PINCTRL_PIN(164, "K3 AVCCK 3"),
 310         PINCTRL_PIN(165, "K4 IDE DA2"),
 311         PINCTRL_PIN(166, "K5 IDE DA0"),
 312         PINCTRL_PIN(167, "K6 V1"),
 313         PINCTRL_PIN(168, "K7 V1"),
 314         PINCTRL_PIN(169, "K8 GND"),
 315         PINCTRL_PIN(170, "K9 GND"),
 316         PINCTRL_PIN(171, "K10 GND"),
 317         PINCTRL_PIN(172, "K11 GND"),
 318         PINCTRL_PIN(173, "K12 V1"),
 319         PINCTRL_PIN(174, "K13 V1"),
 320         PINCTRL_PIN(175, "K14 PCI AD3"),
 321         PINCTRL_PIN(176, "K15 PCI AD4"),
 322         PINCTRL_PIN(177, "K16 PCI AD5"),
 323         PINCTRL_PIN(178, "K17 PCI AD6"),
 324         PINCTRL_PIN(179, "K18 PCI AD7"),
 325         /* Row L */
 326         PINCTRL_PIN(180, "L1 IDE INTRQ"),
 327         PINCTRL_PIN(181, "L2 IDE DMACK N"),
 328         PINCTRL_PIN(182, "L3 IDE IORDY"),
 329         PINCTRL_PIN(183, "L4 IDE DIOR N"),
 330         PINCTRL_PIN(184, "L5 IDE DIOW N"),
 331         PINCTRL_PIN(185, "L6 VCC3IOHA"),
 332         PINCTRL_PIN(186, "L7 VCC3IOHA"),
 333         PINCTRL_PIN(187, "L8 GND"),
 334         PINCTRL_PIN(188, "L9 GND"),
 335         PINCTRL_PIN(189, "L10 GND"),
 336         PINCTRL_PIN(190, "L11 GND"),
 337         PINCTRL_PIN(191, "L12 VCC3IOHA"),
 338         PINCTRL_PIN(192, "L13 VCC3IOHA"),
 339         PINCTRL_PIN(193, "L14 GPIO0 30"),
 340         PINCTRL_PIN(194, "L15 GPIO0 31"),
 341         PINCTRL_PIN(195, "L16 PCI AD0"),
 342         PINCTRL_PIN(196, "L17 PCI AD1"),
 343         PINCTRL_PIN(197, "L18 PCI AD2"),
 344         /* Row M */
 345         PINCTRL_PIN(198, "M1 IDE DMARQ"),
 346         PINCTRL_PIN(199, "M2 IDE DD15"),
 347         PINCTRL_PIN(200, "M3 IDE DD0"),
 348         PINCTRL_PIN(201, "M4 IDE DD14"),
 349         PINCTRL_PIN(202, "M5 IDE DD1"),
 350         PINCTRL_PIN(203, "M6 VCC3IOHA"),
 351         PINCTRL_PIN(204, "M7 GND"),
 352         PINCTRL_PIN(205, "M8 VCC2IOHA 1"),
 353         PINCTRL_PIN(206, "M9 V1"),
 354         PINCTRL_PIN(207, "M10 V1"),
 355         PINCTRL_PIN(208, "M11 VCC3IOHA"),
 356         PINCTRL_PIN(209, "M12 GND"),
 357         PINCTRL_PIN(210, "M13 VCC3IOHA"),
 358         PINCTRL_PIN(211, "M14 GPIO0 25"),
 359         PINCTRL_PIN(212, "M15 GPIO0 26"),
 360         PINCTRL_PIN(213, "M16 GPIO0 27"),
 361         PINCTRL_PIN(214, "M17 GPIO0 28"),
 362         PINCTRL_PIN(215, "M18 GPIO0 29"),
 363         /* Row N */
 364         PINCTRL_PIN(216, "N1 IDE DD13"),
 365         PINCTRL_PIN(217, "N2 IDE DD2"),
 366         PINCTRL_PIN(218, "N3 IDE DD12"),
 367         PINCTRL_PIN(219, "N4 IDE DD3"),
 368         PINCTRL_PIN(220, "N5 IDE DD11"),
 369         PINCTRL_PIN(221, "N6 GND"),
 370         PINCTRL_PIN(222, "N7 VCC2IOHA 1"),
 371         PINCTRL_PIN(223, "N8 VCC2IOHA 1"),
 372         PINCTRL_PIN(224, "N9 V1"),
 373         PINCTRL_PIN(225, "N10 V1"),
 374         PINCTRL_PIN(226, "N11 VCC3IOHA"),
 375         PINCTRL_PIN(227, "N12 VCC3IOHA"),
 376         PINCTRL_PIN(228, "N13 GND"),
 377         PINCTRL_PIN(229, "N14 GPIO0 20"),
 378         PINCTRL_PIN(230, "N15 GPIO0 21"),
 379         PINCTRL_PIN(231, "N16 GPIO0 22"),
 380         PINCTRL_PIN(232, "N17 GPIO0 23"),
 381         PINCTRL_PIN(233, "N18 GPIO0 24"),
 382         /* Row P (for some reason O is skipped) */
 383         PINCTRL_PIN(234, "P1 IDE DD4"),
 384         PINCTRL_PIN(235, "P2 IDE DD10"),
 385         PINCTRL_PIN(236, "P3 IDE DD5"),
 386         PINCTRL_PIN(237, "P4 IDE DD9"),
 387         PINCTRL_PIN(238, "P5 GND"),
 388         PINCTRL_PIN(239, "P6 USB XSCO"),
 389         PINCTRL_PIN(240, "P7 GMAC0 TXD3"),
 390         PINCTRL_PIN(241, "P8 GMAC0 TXEN"),
 391         PINCTRL_PIN(242, "P9 GMAC0 RXD2"),
 392         PINCTRL_PIN(243, "P10 GMAC1 TXC"),
 393         PINCTRL_PIN(244, "P11 GMAC1 RXD1"),
 394         PINCTRL_PIN(245, "P12 MODE SEL 1"),
 395         PINCTRL_PIN(246, "P13 GPIO1 28"),
 396         PINCTRL_PIN(247, "P14 GND"),
 397         PINCTRL_PIN(248, "P15 GPIO0 5"),
 398         PINCTRL_PIN(249, "P16 GPIO0 17"),
 399         PINCTRL_PIN(250, "P17 GPIO0 18"),
 400         PINCTRL_PIN(251, "P18 GPIO0 19"),
 401         /* Row R (for some reason Q us skipped) */
 402         PINCTRL_PIN(252, "R1 IDE DD6"),
 403         PINCTRL_PIN(253, "R2 IDE DD8"),
 404         PINCTRL_PIN(254, "R3 IDE DD7"),
 405         PINCTRL_PIN(255, "R4 IDE RESET N"),
 406         PINCTRL_PIN(256, "R5 ICE0 DBGACK"),
 407         PINCTRL_PIN(257, "R6 USB XSCI"),
 408         PINCTRL_PIN(258, "R7 GMAC0 TXD2"),
 409         PINCTRL_PIN(259, "R8 GMAC0 RXDV"),
 410         PINCTRL_PIN(260, "R9 GMAC0 RXD3"),
 411         PINCTRL_PIN(261, "R10 GMAC1 TXD0"),
 412         PINCTRL_PIN(262, "R11 GMAC1 RXD0"),
 413         PINCTRL_PIN(263, "R12 MODE SEL 0"),
 414         PINCTRL_PIN(264, "R13 MODE SEL 3"),
 415         PINCTRL_PIN(265, "R14 GPIO0 0"),
 416         PINCTRL_PIN(266, "R15 GPIO0 4"),
 417         PINCTRL_PIN(267, "R16 GPIO0 9"),
 418         PINCTRL_PIN(268, "R17 GPIO0 15"),
 419         PINCTRL_PIN(269, "R18 GPIO0 16"),
 420         /* Row T (for some reason S is skipped) */
 421         PINCTRL_PIN(270, "T1 ICE0 DBGRQ"),
 422         PINCTRL_PIN(271, "T2 ICE0 IDO"),
 423         PINCTRL_PIN(272, "T3 ICE0 ICK"),
 424         PINCTRL_PIN(273, "T4 ICE0 IMS"),
 425         PINCTRL_PIN(274, "T5 ICE0 IDI"),
 426         PINCTRL_PIN(275, "T6 USB RREF"),
 427         PINCTRL_PIN(276, "T7 GMAC0 TXD1"),
 428         PINCTRL_PIN(277, "T8 GMAC0 RXC"),
 429         PINCTRL_PIN(278, "T9 GMAC0 CRS"),
 430         PINCTRL_PIN(279, "T10 GMAC1 TXD1"),
 431         PINCTRL_PIN(280, "T11 GMAC1 RXC"),
 432         PINCTRL_PIN(281, "T12 GMAC1 CRS"),
 433         PINCTRL_PIN(282, "T13 EXT CLK"),
 434         PINCTRL_PIN(283, "T14 GPIO1 31"),
 435         PINCTRL_PIN(284, "T15 GPIO0 3"),
 436         PINCTRL_PIN(285, "T16 GPIO0 8"),
 437         PINCTRL_PIN(286, "T17 GPIO0 12"),
 438         PINCTRL_PIN(287, "T18 GPIO0 14"),
 439         /* Row U */
 440         PINCTRL_PIN(288, "U1 ICE0 IRST N"),
 441         PINCTRL_PIN(289, "U2 USB0 VCCHSRT"),
 442         PINCTRL_PIN(290, "U3 USB0 DP"),
 443         PINCTRL_PIN(291, "U4 USB VCCA U20"),
 444         PINCTRL_PIN(292, "U5 USB1 DP"),
 445         PINCTRL_PIN(293, "U6 USB1 GNDHSRT 1"),
 446         PINCTRL_PIN(294, "U7 GMAC0 TXD0"),
 447         PINCTRL_PIN(295, "U8 GMAC0 RXD0"),
 448         PINCTRL_PIN(296, "U9 GMAC1 COL"),
 449         PINCTRL_PIN(297, "U10 GMAC1 TXD2"),
 450         PINCTRL_PIN(298, "U11 GMAC1 RXDV"),
 451         PINCTRL_PIN(299, "U12 GMAC1 RXD3"),
 452         PINCTRL_PIN(300, "U13 MODE SEL 2"),
 453         PINCTRL_PIN(301, "U14 GPIO1 30"),
 454         PINCTRL_PIN(302, "U15 GPIO0 2"),
 455         PINCTRL_PIN(303, "U16 GPIO0 7"),
 456         PINCTRL_PIN(304, "U17 GPIO0 11"),
 457         PINCTRL_PIN(305, "U18 GPIO0 13"),
 458         /* Row V */
 459         PINCTRL_PIN(306, "V1 USB0 GNDHSRT"),
 460         PINCTRL_PIN(307, "V2 USB0 DM"),
 461         PINCTRL_PIN(308, "V3 USB GNDA U20"),
 462         PINCTRL_PIN(309, "V4 USB1 DM"),
 463         PINCTRL_PIN(310, "V5 USB1 VCCHSRT1"),
 464         PINCTRL_PIN(311, "V6 GMAC0 COL"),
 465         PINCTRL_PIN(312, "V7 GMAC0 TXC"),
 466         PINCTRL_PIN(313, "V8 GMAC0 RXD1"),
 467         PINCTRL_PIN(314, "V9 REF CLK"),
 468         PINCTRL_PIN(315, "V10 GMAC1 TXD3"),
 469         PINCTRL_PIN(316, "V11 GMAC1 TXEN"),
 470         PINCTRL_PIN(317, "V12 GMAC1 RXD2"),
 471         PINCTRL_PIN(318, "V13 M30 CLK"),
 472         PINCTRL_PIN(319, "V14 GPIO1 29"),
 473         PINCTRL_PIN(320, "V15 GPIO0 1"),
 474         PINCTRL_PIN(321, "V16 GPIO0 6"),
 475         PINCTRL_PIN(322, "V17 GPIO0 10"),
 476         PINCTRL_PIN(323, "V18 SYS RESET N"),
 477 };
 478
 479
 480 /* Digital ground */
 481 static const unsigned int gnd_3512_pins[] = {
 482         76, 85, 95, 102, 114, 119, 133, 134, 135, 136, 151, 152, 153, 154, 169,
 483         170, 171, 172, 187, 188, 189, 190, 204, 209, 221, 228, 238, 247
 484 };
 485
 486 static const unsigned int dram_3512_pins[] = {
 487         2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 22, 23, 24, 25, 26, 27, 28, 29,
 488         30, 40, 41, 42, 43, 44, 45, 46, 47, 58, 59, 60, 61, 62, 63, 64, 65, 77,
 489         78, 79, 80, 81, 82
 490 };
 491
 492 static const unsigned int rtc_3512_pins[] = { 57, 20, 39 };
 493
 494 static const unsigned int power_3512_pins[] = { 19, 38, 36, 55, 37, 56, 54, 72 };
 495
 496 static const unsigned int system_3512_pins[] = {
 497         318, 264, 300, 245, 263, 282, 314, 323, 49,
 498 };
 499
 500 static const unsigned int vcontrol_3512_pins[] = { 18, 0, 1 };
 501
 502 static const unsigned int ice_3512_pins[] = { 256, 270, 271, 272, 273, 274, 288 };
 503
 504 static const unsigned int ide_3512_pins[] = {
 505         162, 163, 165, 166, 148, 180, 181, 182, 183, 184, 198, 199, 200, 201, 202,
 506         216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 253, 254, 255
 507 };
 508
 509 static const unsigned int sata_3512_pins[] = {
 510         75, 74, 73, 93, 94, 131, 112, 130, 92, 91, 90, 111, 110, 109, 108, 129,
 511         128, 127, 126, 147, 146, 145, 144, 164
 512 };
 513
 514 static const unsigned int usb_3512_pins[] = {
 515         306, 289, 307, 290, 239, 257, 275, 308, 291, 309, 292, 310, 293
 516 };
 517
 518 /* GMII, ethernet pins */
 519 static const unsigned int gmii_3512_pins[] = {
 520         311, 240, 258, 276, 294, 312, 241, 259, 277, 295, 313, 242, 260, 278, 296,
 521         315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281
 522 };
 523
 524 static const unsigned int pci_3512_pins[] = {
 525         13, 14, 15, 16, 17, 31, 32, 33, 34, 35, 48, 50, 51, 52, 53, 66, 67, 68, 69,
 526         70, 71, 83, 84, 86, 87, 88, 89, 103, 104, 105, 106, 107, 121, 122, 123,
 527         124, 125, 139, 140, 141, 142, 143, 157, 158, 159, 160, 161, 175, 176, 177,
 528         178, 179, 195, 196, 197
 529 };
 530
 531 /*
 532  * Apparently the LPC interface is using the PCICLK for the clocking so
 533  * PCI needs to be active at the same time.
 534  */
 535 static const unsigned int lpc_3512_pins[] = {
 536         285, /* LPC_LAD[0] */
 537         304, /* LPC_SERIRQ */
 538         286, /* LPC_LAD[2] */
 539         305, /* LPC_LFRAME# */
 540         287, /* LPC_LAD[3] */
 541         268, /* LPC_LAD[1] */
 542 };
 543
 544 /* Character LCD */
 545 static const unsigned int lcd_3512_pins[] = {
 546         262, 244, 317, 299, 246, 319, 301, 283, 269, 233, 211
 547 };
 548
 549 static const unsigned int ssp_3512_pins[] = {
 550         285, /* SSP_97RST# SSP AC97 Reset, active low */
 551         304, /* SSP_FSC */
 552         286, /* SSP_ECLK */
 553         305, /* SSP_TXD */
 554         287, /* SSP_RXD */
 555         268, /* SSP_SCLK */
 556 };
 557
 558 static const unsigned int uart_rxtx_3512_pins[] = {
 559         267, /* UART_SIN serial input, RX */
 560         322, /* UART_SOUT serial output, TX */
 561 };
 562
 563 static const unsigned int uart_modem_3512_pins[] = {
 564         285, /* UART_NDCD DCD carrier detect */
 565         304, /* UART_NDTR DTR data terminal ready */
 566         286, /* UART_NDSR DSR data set ready */
 567         305, /* UART_NRTS RTS request to send */
 568         287, /* UART_NCTS CTS clear to send */
 569         268, /* UART_NRI RI ring indicator */
 570 };
 571
 572 static const unsigned int tvc_3512_pins[] = {
 573         246, /* TVC_DATA[0] */
 574         319, /* TVC_DATA[1] */
 575         301, /* TVC_DATA[2] */
 576         283, /* TVC_DATA[3] */
 577         265, /* TVC_CLK */
 578         320, /* TVC_DATA[4] */
 579         302, /* TVC_DATA[5] */
 580         284, /* TVC_DATA[6] */
 581         266, /* TVC_DATA[7] */
 582 };
 583
 584 /* NAND flash pins */
 585 static const unsigned int nflash_3512_pins[] = {
 586         199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252,
 587         253, 254, 249, 250, 232, 233, 211, 193, 194
 588 };
 589
 590 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
 591 static const unsigned int pflash_3512_pins[] = {
 592         162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
 593         234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
 594         214, 215, 193, 194
 595 };
 596
 597 /*
 598  * The parallel flash can be set up in a 26-bit address bus mode exposing
 599  * A[0-15] (A[15] takes the place of ALE), but it has the
 600  * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
 601  * used at the same time.
 602  */
 603 static const unsigned int pflash_3512_pins_extended[] = {
 604         162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220,
 605         234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213,
 606         214, 215, 193, 194,
 607         /* The extra pins */
 608         296, 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281,
 609         265,
 610 };
 611
 612 /* Serial flash pins CE0, CE1, DI, DO, CK */
 613 static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 };
 614
 615 /* The GPIO0A (0) pin overlap with TVC and extended parallel flash */
 616 static const unsigned int gpio0a_3512_pins[] = { 265 };
 617
 618 /* The GPIO0B (1-4) pins overlap with TVC and ICE */
 619 static const unsigned int gpio0b_3512_pins[] = { 320, 302, 284, 266 };
 620
 621 /* The GPIO0C (5-7) pins overlap with ICE */
 622 static const unsigned int gpio0c_3512_pins[] = { 248, 321, 303 };
 623
 624 /* The GPIO0D (9,10) pins overlap with UART RX/TX */
 625 static const unsigned int gpio0d_3512_pins[] = { 267, 322 };
 626
 627 /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */
 628 static const unsigned int gpio0e_3512_pins[] = { 285, 304, 286, 305, 287, 268 };
 629
 630 /* The GPIO0F (16) pins overlap with LCD */
 631 static const unsigned int gpio0f_3512_pins[] = { 269 };
 632
 633 /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */
 634 static const unsigned int gpio0g_3512_pins[] = { 249, 250 };
 635
 636 /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */
 637 static const unsigned int gpio0h_3512_pins[] = { 251, 229 };
 638
 639 /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */
 640 static const unsigned int gpio0i_3512_pins[] = { 230, 231 };
 641
 642 /* The GPIO0J (23) pins overlap with all flash */
 643 static const unsigned int gpio0j_3512_pins[] = { 232 };
 644
 645 /* The GPIO0K (24,25) pins overlap with all flash and LCD */
 646 static const unsigned int gpio0k_3512_pins[] = { 233, 211 };
 647
 648 /* The GPIO0L (26-29) pins overlap with parallel flash */
 649 static const unsigned int gpio0l_3512_pins[] = { 212, 213, 214, 215 };
 650
 651 /* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */
 652 static const unsigned int gpio0m_3512_pins[] = { 193, 194 };
 653
 654 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
 655 static const unsigned int gpio1a_3512_pins[] = { 162, 163, 165, 166, 148 };
 656
 657 /* The GPIO1B (5-10, 27) pins overlap with just IDE */
 658 static const unsigned int gpio1b_3512_pins[] = {
 659         180, 181, 182, 183, 184, 198, 255
 660 };
 661
 662 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
 663 static const unsigned int gpio1c_3512_pins[] = {
 664         199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237,
 665         252, 253, 254
 666 };
 667
 668 /* The GPIO1D (28-31) pins overlap with LCD and TVC */
 669 static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 };
 670
 671 /* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */
 672 static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 };
 673
 674 /* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */
 675 static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 };
 676
 677 /* The GPIO2C (8-31) pins overlap with PCI */
 678 static const unsigned int gpio2c_3512_pins[] = {
 679         17, 34, 35, 51, 52, 53, 68, 69, 71, 86, 87, 88, 89, 103, 104, 105,
 680         140, 141, 142, 143, 157, 158, 159, 160
 681 };
 682
 683 /* Groups for the 3512 SoC/package */
 684 static const struct gemini_pin_group gemini_3512_pin_groups[] = {
 685         {
 686                 .name = "gndgrp",
 687                 .pins = gnd_3512_pins,
 688                 .num_pins = ARRAY_SIZE(gnd_3512_pins),
 689         },
 690         {
 691                 .name = "dramgrp",
 692                 .pins = dram_3512_pins,
 693                 .num_pins = ARRAY_SIZE(dram_3512_pins),
 694                 .mask = DRAM_PADS_POWERDOWN,
 695         },
 696         {
 697                 .name = "rtcgrp",
 698                 .pins = rtc_3512_pins,
 699                 .num_pins = ARRAY_SIZE(rtc_3512_pins),
 700         },
 701         {
 702                 .name = "powergrp",
 703                 .pins = power_3512_pins,
 704                 .num_pins = ARRAY_SIZE(power_3512_pins),
 705         },
 706         {
 707                 .name = "systemgrp",
 708                 .pins = system_3512_pins,
 709                 .num_pins = ARRAY_SIZE(system_3512_pins),
 710         },
 711         {
 712                 .name = "vcontrolgrp",
 713                 .pins = vcontrol_3512_pins,
 714                 .num_pins = ARRAY_SIZE(vcontrol_3512_pins),
 715         },
 716         {
 717                 .name = "icegrp",
 718                 .pins = ice_3512_pins,
 719                 .num_pins = ARRAY_SIZE(ice_3512_pins),
 720                 /* Conflict with some GPIO groups */
 721         },
 722         {
 723                 .name = "idegrp",
 724                 .pins = ide_3512_pins,
 725                 .num_pins = ARRAY_SIZE(ide_3512_pins),
 726                 /* Conflict with all flash usage */
 727                 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
 728                         PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
 729         },
 730         {
 731                 .name = "satagrp",
 732                 .pins = sata_3512_pins,
 733                 .num_pins = ARRAY_SIZE(sata_3512_pins),
 734         },
 735         {
 736                 .name = "usbgrp",
 737                 .pins = usb_3512_pins,
 738                 .num_pins = ARRAY_SIZE(usb_3512_pins),
 739         },
 740         {
 741                 .name = "gmiigrp",
 742                 .pins = gmii_3512_pins,
 743                 .num_pins = ARRAY_SIZE(gmii_3512_pins),
 744         },
 745         {
 746                 .name = "pcigrp",
 747                 .pins = pci_3512_pins,
 748                 .num_pins = ARRAY_SIZE(pci_3512_pins),
 749                 /* Conflict only with GPIO2 */
 750                 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
 751         },
 752         {
 753                 .name = "lpcgrp",
 754                 .pins = lpc_3512_pins,
 755                 .num_pins = ARRAY_SIZE(lpc_3512_pins),
 756                 /* Conflict with SSP and UART modem pins */
 757                 .mask = SSP_PADS_ENABLE,
 758                 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,
 759         },
 760         {
 761                 .name = "lcdgrp",
 762                 .pins = lcd_3512_pins,
 763                 .num_pins = ARRAY_SIZE(lcd_3512_pins),
 764                 /* Conflict with TVC and ICE */
 765                 .mask = TVC_PADS_ENABLE,
 766                 .value = LCD_PADS_ENABLE,
 767         },
 768         {
 769                 .name = "sspgrp",
 770                 .pins = ssp_3512_pins,
 771                 .num_pins = ARRAY_SIZE(ssp_3512_pins),
 772                 /* Conflict with LPC and UART modem pins */
 773                 .mask = LPC_PADS_ENABLE,
 774                 .value = SSP_PADS_ENABLE,
 775         },
 776         {
 777                 .name = "uartrxtxgrp",
 778                 .pins = uart_rxtx_3512_pins,
 779                 .num_pins = ARRAY_SIZE(uart_rxtx_3512_pins),
 780                 /* No conflicts except GPIO */
 781         },
 782         {
 783                 .name = "uartmodemgrp",
 784                 .pins = uart_modem_3512_pins,
 785                 .num_pins = ARRAY_SIZE(uart_modem_3512_pins),
 786                 /*
 787                  * Conflict with LPC and SSP,
 788                  * so when those are both disabled, modem UART can thrive.
 789                  */
 790                 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
 791         },
 792         {
 793                 .name = "tvcgrp",
 794                 .pins = tvc_3512_pins,
 795                 .num_pins = ARRAY_SIZE(tvc_3512_pins),
 796                 /* Conflict with character LCD and ICE */
 797                 .mask = LCD_PADS_ENABLE,
 798                 .value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE,
 799         },
 800         /*
 801          * The construction is done such that it is possible to use a serial
 802          * flash together with a NAND or parallel (NOR) flash, but it is not
 803          * possible to use NAND and parallel flash together. To use serial
 804          * flash with one of the two others, the muxbits need to be flipped
 805          * around before any access.
 806          */
 807         {
 808                 .name = "nflashgrp",
 809                 .pins = nflash_3512_pins,
 810                 .num_pins = ARRAY_SIZE(nflash_3512_pins),
 811                 /* Conflict with IDE, parallel and serial flash */
 812                 .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE,
 813                 .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
 814         },
 815         {
 816                 .name = "pflashgrp",
 817                 .pins = pflash_3512_pins,
 818                 .num_pins = ARRAY_SIZE(pflash_3512_pins),
 819                 /* Conflict with IDE, NAND and serial flash */
 820                 .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
 821                 .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE,
 822         },
 823         {
 824                 .name = "sflashgrp",
 825                 .pins = sflash_3512_pins,
 826                 .num_pins = ARRAY_SIZE(sflash_3512_pins),
 827                 /* Conflict with IDE, NAND and parallel flash */
 828                 .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
 829                 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
 830         },
 831         {
 832                 .name = "gpio0agrp",
 833                 .pins = gpio0a_3512_pins,
 834                 .num_pins = ARRAY_SIZE(gpio0a_3512_pins),
 835                 /* Conflict with TVC */
 836                 .mask = TVC_PADS_ENABLE,
 837         },
 838         {
 839                 .name = "gpio0bgrp",
 840                 .pins = gpio0b_3512_pins,
 841                 .num_pins = ARRAY_SIZE(gpio0b_3512_pins),
 842                 /* Conflict with TVC and ICE */
 843                 .mask = TVC_PADS_ENABLE,
 844         },
 845         {
 846                 .name = "gpio0cgrp",
 847                 .pins = gpio0c_3512_pins,
 848                 .num_pins = ARRAY_SIZE(gpio0c_3512_pins),
 849                 /* Conflict with ICE */
 850         },
 851         {
 852                 .name = "gpio0dgrp",
 853                 .pins = gpio0d_3512_pins,
 854                 .num_pins = ARRAY_SIZE(gpio0d_3512_pins),
 855                 /* Conflict with UART RX/TX */
 856         },
 857         {
 858                 .name = "gpio0egrp",
 859                 .pins = gpio0e_3512_pins,
 860                 .num_pins = ARRAY_SIZE(gpio0e_3512_pins),
 861                 /* Conflict with LPC, UART modem pins, SSP */
 862                 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
 863         },
 864         {
 865                 .name = "gpio0fgrp",
 866                 .pins = gpio0f_3512_pins,
 867                 .num_pins = ARRAY_SIZE(gpio0f_3512_pins),
 868                 /* Conflict with LCD */
 869                 .mask = LCD_PADS_ENABLE,
 870         },
 871         {
 872                 .name = "gpio0ggrp",
 873                 .pins = gpio0g_3512_pins,
 874                 .num_pins = ARRAY_SIZE(gpio0g_3512_pins),
 875                 /* Conflict with NAND flash */
 876                 .value = NAND_PADS_DISABLE,
 877         },
 878         {
 879                 .name = "gpio0hgrp",
 880                 .pins = gpio0h_3512_pins,
 881                 .num_pins = ARRAY_SIZE(gpio0h_3512_pins),
 882                 /* Conflict with parallel flash */
 883                 .value = PFLASH_PADS_DISABLE,
 884         },
 885         {
 886                 .name = "gpio0igrp",
 887                 .pins = gpio0i_3512_pins,
 888                 .num_pins = ARRAY_SIZE(gpio0i_3512_pins),
 889                 /* Conflict with serial flash */
 890                 .value = SFLASH_PADS_DISABLE,
 891         },
 892         {
 893                 .name = "gpio0jgrp",
 894                 .pins = gpio0j_3512_pins,
 895                 .num_pins = ARRAY_SIZE(gpio0j_3512_pins),
 896                 /* Conflict with all flash */
 897                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
 898                         SFLASH_PADS_DISABLE,
 899         },
 900         {
 901                 .name = "gpio0kgrp",
 902                 .pins = gpio0k_3512_pins,
 903                 .num_pins = ARRAY_SIZE(gpio0k_3512_pins),
 904                 /* Conflict with all flash and LCD */
 905                 .mask = LCD_PADS_ENABLE,
 906                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
 907                         SFLASH_PADS_DISABLE,
 908         },
 909         {
 910                 .name = "gpio0lgrp",
 911                 .pins = gpio0l_3512_pins,
 912                 .num_pins = ARRAY_SIZE(gpio0l_3512_pins),
 913                 /* Conflict with parallel flash */
 914                 .value = PFLASH_PADS_DISABLE,
 915         },
 916         {
 917                 .name = "gpio0mgrp",
 918                 .pins = gpio0m_3512_pins,
 919                 .num_pins = ARRAY_SIZE(gpio0m_3512_pins),
 920                 /* Conflict with parallel and NAND flash */
 921                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
 922         },
 923         {
 924                 .name = "gpio1agrp",
 925                 .pins = gpio1a_3512_pins,
 926                 .num_pins = ARRAY_SIZE(gpio1a_3512_pins),
 927                 /* Conflict with IDE and parallel flash */
 928                 .mask = IDE_PADS_ENABLE,
 929                 .value = PFLASH_PADS_DISABLE,
 930         },
 931         {
 932                 .name = "gpio1bgrp",
 933                 .pins = gpio1b_3512_pins,
 934                 .num_pins = ARRAY_SIZE(gpio1b_3512_pins),
 935                 /* Conflict with IDE only */
 936                 .mask = IDE_PADS_ENABLE,
 937         },
 938         {
 939                 .name = "gpio1cgrp",
 940                 .pins = gpio1c_3512_pins,
 941                 .num_pins = ARRAY_SIZE(gpio1c_3512_pins),
 942                 /* Conflict with IDE, parallel and NAND flash */
 943                 .mask = IDE_PADS_ENABLE,
 944                 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
 945         },
 946         {
 947                 .name = "gpio1dgrp",
 948                 .pins = gpio1d_3512_pins,
 949                 .num_pins = ARRAY_SIZE(gpio1d_3512_pins),
 950                 /* Conflict with LCD and TVC */
 951                 .mask = LCD_PADS_ENABLE | TVC_PADS_ENABLE,
 952         },
 953         {
 954                 .name = "gpio2agrp",
 955                 .pins = gpio2a_3512_pins,
 956                 .num_pins = ARRAY_SIZE(gpio2a_3512_pins),
 957                 /* Conflict with GMII and extended parallel flash */
 958         },
 959         {
 960                 .name = "gpio2bgrp",
 961                 .pins = gpio2b_3512_pins,
 962                 .num_pins = ARRAY_SIZE(gpio2b_3512_pins),
 963                 /* Conflict with GMII, extended parallel flash and LCD */
 964                 .mask = LCD_PADS_ENABLE,
 965         },
 966         {
 967                 .name = "gpio2cgrp",
 968                 .pins = gpio2c_3512_pins,
 969                 .num_pins = ARRAY_SIZE(gpio2c_3512_pins),
 970                 /* Conflict with PCI */
 971                 .mask = PCI_PADS_ENABLE,
 972         },
 973 };
 974
 975 /* Pin names for the pinmux subsystem, 3516 variant */
 976 static const struct pinctrl_pin_desc gemini_3516_pins[] = {
 977         /* Row A */
 978         PINCTRL_PIN(0, "A1 AVCC3IOHA"),
 979         PINCTRL_PIN(1, "A2 DRAM CK N"),
 980         PINCTRL_PIN(2, "A3 DRAM CK"),
 981         PINCTRL_PIN(3, "A4 DRAM DQM1"),
 982         PINCTRL_PIN(4, "A5 DRAM DQ9"),
 983         PINCTRL_PIN(5, "A6 DRAM DQ13"),
 984         PINCTRL_PIN(6, "A7 DRAM DQ1"),
 985         PINCTRL_PIN(7, "A8 DRAM DQ2"),
 986         PINCTRL_PIN(8, "A9 DRAM DQ4"),
 987         PINCTRL_PIN(9, "A10 DRAM VREF"),
 988         PINCTRL_PIN(10, "A11 DRAM DQ24"),
 989         PINCTRL_PIN(11, "A12 DRAM DQ28"),
 990         PINCTRL_PIN(12, "A13 DRAM DQ30"),
 991         PINCTRL_PIN(13, "A14 DRAM DQ18"),
 992         PINCTRL_PIN(14, "A15 DRAM DQ21"),
 993         PINCTRL_PIN(15, "A16 DRAM CAS_N"),
 994         PINCTRL_PIN(16, "A17 DRAM BA1"),
 995         PINCTRL_PIN(17, "A18 PCI INTA N"),
 996         PINCTRL_PIN(18, "A19 PCI INTB N"),
 997         PINCTRL_PIN(19, "A20 PCI INTC N"),
 998         /* Row B */
 999         PINCTRL_PIN(20, "B1 PWR EN"),
1000         PINCTRL_PIN(21, "B2 GND"),
1001         PINCTRL_PIN(22, "B3 RTC CLKO"),
1002         PINCTRL_PIN(23, "B4 DRAM A5"),
1003         PINCTRL_PIN(24, "B5 DRAM A6"),
1004         PINCTRL_PIN(25, "B6 DRAM DQS1"),
1005         PINCTRL_PIN(26, "B7 DRAM DQ11"),
1006         PINCTRL_PIN(27, "B8 DRAM DQ0"),
1007         PINCTRL_PIN(28, "B9 DRAM DQS0"),
1008         PINCTRL_PIN(29, "B10 DRAM DQ7"),
1009         PINCTRL_PIN(30, "B11 DRAM DQS3"),
1010         PINCTRL_PIN(31, "B12 DRAM DQ27"),
1011         PINCTRL_PIN(32, "B13 DRAM DQ31"),
1012         PINCTRL_PIN(33, "B14 DRAM DQ20"),
1013         PINCTRL_PIN(34, "B15 DRAM DQS2"),
1014         PINCTRL_PIN(35, "B16 DRAM WE N"),
1015         PINCTRL_PIN(36, "B17 DRAM A10"),
1016         PINCTRL_PIN(37, "B18 DRAM A2"),
1017         PINCTRL_PIN(38, "B19 GND"),
1018         PINCTRL_PIN(39, "B20 PCI GNT0 N"),
1019         /* Row C */
1020         PINCTRL_PIN(40, "C1 AGNDIOHA"),
1021         PINCTRL_PIN(41, "C2 XTALI"),
1022         PINCTRL_PIN(42, "C3 GND"),
1023         PINCTRL_PIN(43, "C4 RTC CLKI"),
1024         PINCTRL_PIN(44, "C5 DRAM A12"),
1025         PINCTRL_PIN(45, "C6 DRAM A11"),
1026         PINCTRL_PIN(46, "C7 DRAM DQ8"),
1027         PINCTRL_PIN(47, "C8 DRAM DQ10"),
1028         PINCTRL_PIN(48, "C9 DRAM DQ3"),
1029         PINCTRL_PIN(49, "C10 DRAM DQ6"),
1030         PINCTRL_PIN(50, "C11 DRAM DQM0"),
1031         PINCTRL_PIN(51, "C12 DRAM DQ26"),
1032         PINCTRL_PIN(52, "C13 DRAM DQ16"),
1033         PINCTRL_PIN(53, "C14 DRAM DQ22"),
1034         PINCTRL_PIN(54, "C15 DRAM DQM2"),
1035         PINCTRL_PIN(55, "C16 DRAM BA0"),
1036         PINCTRL_PIN(56, "C17 DRAM A3"),
1037         PINCTRL_PIN(57, "C18 GND"),
1038         PINCTRL_PIN(58, "C19 PCI GNT1 N"),
1039         PINCTRL_PIN(59, "C20 PCI REQ2 N"),
1040         /* Row D */
1041         PINCTRL_PIN(60, "D1 AVCC3IOAHA"),
1042         PINCTRL_PIN(61, "D2 AVCCKHA"),
1043         PINCTRL_PIN(62, "D3 XTALO"),
1044         PINCTRL_PIN(63, "D4 GND"),
1045         PINCTRL_PIN(64, "D5 CIR RXD"),
1046         PINCTRL_PIN(65, "D6 DRAM A7"),
1047         PINCTRL_PIN(66, "D7 DRAM A4"),
1048         PINCTRL_PIN(67, "D8 DRAM A8"),
1049         PINCTRL_PIN(68, "D9 DRAM CKE"),
1050         PINCTRL_PIN(69, "D10 DRAM DQ14"),
1051         PINCTRL_PIN(70, "D11 DRAM DQ5"),
1052         PINCTRL_PIN(71, "D12 DRAM DQ25"),
1053         PINCTRL_PIN(72, "D13 DRAM DQ17"),
1054         PINCTRL_PIN(73, "D14 DRAM DQ23"),
1055         PINCTRL_PIN(74, "D15 DRAM RAS N"),
1056         PINCTRL_PIN(75, "D16 DRAM A1"),
1057         PINCTRL_PIN(76, "D17 GND"),
1058         PINCTRL_PIN(77, "D18 EXT RESET N"),
1059         PINCTRL_PIN(78, "D19 PCI REQ1 N"),
1060         PINCTRL_PIN(79, "D20 PCI REQ3 N"),
1061         /* Row E */
1062         PINCTRL_PIN(80, "E1 VCC2IO CTRL"),
1063         PINCTRL_PIN(81, "E2 VREF CTRL"),
1064         PINCTRL_PIN(82, "E3 CIR RST N"),
1065         PINCTRL_PIN(83, "E4 PWR BTN"),
1066         PINCTRL_PIN(84, "E5 GND"),
1067         PINCTRL_PIN(85, "E6 CIR TXD"),
1068         PINCTRL_PIN(86, "E7 VCCK CTRL"),
1069         PINCTRL_PIN(87, "E8 DRAM A9"),
1070         PINCTRL_PIN(88, "E9 DRAM DQ12"),
1071         PINCTRL_PIN(89, "E10 DRAM DQ15"),
1072         PINCTRL_PIN(90, "E11 DRAM DQM3"),
1073         PINCTRL_PIN(91, "E12 DRAM DQ29"),
1074         PINCTRL_PIN(92, "E13 DRAM DQ19"),
1075         PINCTRL_PIN(93, "E14 DRAM A13"),
1076         PINCTRL_PIN(94, "E15 DRAM A0"),
1077         PINCTRL_PIN(95, "E16 GND"),
1078         PINCTRL_PIN(96, "E17 PCI INTD N"),
1079         PINCTRL_PIN(97, "E18 PCI GNT3 N"),
1080         PINCTRL_PIN(98, "E19 PCI AD29"),
1081         PINCTRL_PIN(99, "E20 PCI AD28"),
1082         /* Row F */
1083         PINCTRL_PIN(100, "F1 AVCCKHB"),
1084         PINCTRL_PIN(101, "F2 AVCCK P"),
1085         PINCTRL_PIN(102, "F3 EBG"),
1086         PINCTRL_PIN(103, "F4 REXT"),
1087         PINCTRL_PIN(104, "F5 AVCC3IOHB"),
1088         PINCTRL_PIN(105, "F6 GND"),
1089         PINCTRL_PIN(106, "F7 VCC2IOHA 2"),
1090         PINCTRL_PIN(107, "F8 VCC2IOHA 2"),
1091         PINCTRL_PIN(108, "F9 VCC2IOHA 2"),
1092         PINCTRL_PIN(109, "F10 V1"),
1093         PINCTRL_PIN(110, "F11 V1"),
1094         PINCTRL_PIN(111, "F12 VCC2IOHA 2"),
1095         PINCTRL_PIN(112, "F13 VCC2IOHA 2"),
1096         PINCTRL_PIN(113, "F14 VCC2IOHA 2"),
1097         PINCTRL_PIN(114, "F15 GND"),
1098         PINCTRL_PIN(115, "F16 PCI CLK"),
1099         PINCTRL_PIN(116, "F17 PCI GNT2 N"),
1100         PINCTRL_PIN(117, "F18 PCI AD31"),
1101         PINCTRL_PIN(118, "F19 PCI AD26"),
1102         PINCTRL_PIN(119, "F20 PCI CBE3 N"),
1103         /* Row G */
1104         PINCTRL_PIN(120, "G1 SATA0 RXDP"),
1105         PINCTRL_PIN(121, "G2 SATA0 RXDN"),
1106         PINCTRL_PIN(122, "G3 AGNDK 0"),
1107         PINCTRL_PIN(123, "G4 AVCCK S"),
1108         PINCTRL_PIN(124, "G5 AVCC3 S"),
1109         PINCTRL_PIN(125, "G6 VCC2IOHA 2"),
1110         PINCTRL_PIN(126, "G7 GND"),
1111         PINCTRL_PIN(127, "G8 VCC2IOHA 2"),
1112         PINCTRL_PIN(128, "G9 V1"),
1113         PINCTRL_PIN(129, "G10 V1"),
1114         PINCTRL_PIN(130, "G11 V1"),
1115         PINCTRL_PIN(131, "G12 V1"),
1116         PINCTRL_PIN(132, "G13 VCC2IOHA 2"),
1117         PINCTRL_PIN(133, "G14 GND"),
1118         PINCTRL_PIN(134, "G15 VCC3IOHA"),
1119         PINCTRL_PIN(135, "G16 PCI REQ0 N"),
1120         PINCTRL_PIN(136, "G17 PCI AD30"),
1121         PINCTRL_PIN(137, "G18 PCI AD24"),
1122         PINCTRL_PIN(138, "G19 PCI AD23"),
1123         PINCTRL_PIN(139, "G20 PCI AD21"),
1124         /* Row H */
1125         PINCTRL_PIN(140, "H1 SATA0 TXDP"),
1126         PINCTRL_PIN(141, "H2 SATA0 TXDN"),
1127         PINCTRL_PIN(142, "H3 AGNDK 1"),
1128         PINCTRL_PIN(143, "H4 AVCCK 0"),
1129         PINCTRL_PIN(144, "H5 TEST CLKOUT"),
1130         PINCTRL_PIN(145, "H6 AGND"),
1131         PINCTRL_PIN(146, "H7 VCC2IOHA 2"),
1132         PINCTRL_PIN(147, "H8 GND"),
1133         PINCTRL_PIN(148, "H9 GND"),
1134         PINCTRL_PIN(149, "H10 GDN"),
1135         PINCTRL_PIN(150, "H11 GND"),
1136         PINCTRL_PIN(151, "H12 GND"),
1137         PINCTRL_PIN(152, "H13 GND"),
1138         PINCTRL_PIN(153, "H14 VCC3IOHA"),
1139         PINCTRL_PIN(154, "H15 VCC3IOHA"),
1140         PINCTRL_PIN(155, "H16 PCI AD27"),
1141         PINCTRL_PIN(156, "H17 PCI AD25"),
1142         PINCTRL_PIN(157, "H18 PCI AD22"),
1143         PINCTRL_PIN(158, "H19 PCI AD18"),
1144         PINCTRL_PIN(159, "H20 PCI AD17"),
1145         /* Row J (for some reason I is skipped) */
1146         PINCTRL_PIN(160, "J1 SATA1 TXDP"),
1147         PINCTRL_PIN(161, "J2 SATA1 TXDN"),
1148         PINCTRL_PIN(162, "J3 AGNDK 2"),
1149         PINCTRL_PIN(163, "J4 AVCCK 1"),
1150         PINCTRL_PIN(164, "J5 AGND"),
1151         PINCTRL_PIN(165, "J6 AGND"),
1152         PINCTRL_PIN(166, "J7 V1"),
1153         PINCTRL_PIN(167, "J8 GND"),
1154         PINCTRL_PIN(168, "J9 GND"),
1155         PINCTRL_PIN(169, "J10 GND"),
1156         PINCTRL_PIN(170, "J11 GND"),
1157         PINCTRL_PIN(171, "J12 GND"),
1158         PINCTRL_PIN(172, "J13 GND"),
1159         PINCTRL_PIN(173, "J14 V1"),
1160         PINCTRL_PIN(174, "J15 VCC3IOHA"),
1161         PINCTRL_PIN(175, "J16 PCI AD19"),
1162         PINCTRL_PIN(176, "J17 PCI AD20"),
1163         PINCTRL_PIN(177, "J18 PCI AD16"),
1164         PINCTRL_PIN(178, "J19 PCI CBE2 N"),
1165         PINCTRL_PIN(179, "J20 PCI FRAME N"),
1166         /* Row K */
1167         PINCTRL_PIN(180, "K1 SATA1 RXDP"),
1168         PINCTRL_PIN(181, "K2 SATA1 RXDN"),
1169         PINCTRL_PIN(182, "K3 AGNDK 3"),
1170         PINCTRL_PIN(183, "K4 AVCCK 2"),
1171         PINCTRL_PIN(184, "K5 AGND"),
1172         PINCTRL_PIN(185, "K6 V1"),
1173         PINCTRL_PIN(186, "K7 V1"),
1174         PINCTRL_PIN(187, "K8 GND"),
1175         PINCTRL_PIN(188, "K9 GND"),
1176         PINCTRL_PIN(189, "K10 GND"),
1177         PINCTRL_PIN(190, "K11 GND"),
1178         PINCTRL_PIN(191, "K12 GND"),
1179         PINCTRL_PIN(192, "K13 GND"),
1180         PINCTRL_PIN(193, "K14 V1"),
1181         PINCTRL_PIN(194, "K15 V1"),
1182         PINCTRL_PIN(195, "K16 PCI TRDY N"),
1183         PINCTRL_PIN(196, "K17 PCI IRDY N"),
1184         PINCTRL_PIN(197, "K18 PCI DEVSEL N"),
1185         PINCTRL_PIN(198, "K19 PCI STOP N"),
1186         PINCTRL_PIN(199, "K20 PCI PAR"),
1187         /* Row L */
1188         PINCTRL_PIN(200, "L1 IDE CS0 N"),
1189         PINCTRL_PIN(201, "L2 IDE DA0"),
1190         PINCTRL_PIN(202, "L3 AVCCK 3"),
1191         PINCTRL_PIN(203, "L4 AGND"),
1192         PINCTRL_PIN(204, "L5 IDE DIOR N"),
1193         PINCTRL_PIN(205, "L6 V1"),
1194         PINCTRL_PIN(206, "L7 V1"),
1195         PINCTRL_PIN(207, "L8 GND"),
1196         PINCTRL_PIN(208, "L9 GND"),
1197         PINCTRL_PIN(209, "L10 GND"),
1198         PINCTRL_PIN(210, "L11 GND"),
1199         PINCTRL_PIN(211, "L12 GND"),
1200         PINCTRL_PIN(212, "L13 GND"),
1201         PINCTRL_PIN(213, "L14 V1"),
1202         PINCTRL_PIN(214, "L15 V1"),
1203         PINCTRL_PIN(215, "L16 PCI AD12"),
1204         PINCTRL_PIN(216, "L17 PCI AD13"),
1205         PINCTRL_PIN(217, "L18 PCI AD14"),
1206         PINCTRL_PIN(218, "L19 PCI AD15"),
1207         PINCTRL_PIN(219, "L20 PCI CBE1 N"),
1208         /* Row M */
1209         PINCTRL_PIN(220, "M1 IDE DA1"),
1210         PINCTRL_PIN(221, "M2 IDE CS1 N"),
1211         PINCTRL_PIN(222, "M3 IDE DA2"),
1212         PINCTRL_PIN(223, "M4 IDE DMACK N"),
1213         PINCTRL_PIN(224, "M5 IDE DD1"),
1214         PINCTRL_PIN(225, "M6 VCC3IOHA"),
1215         PINCTRL_PIN(226, "M7 V1"),
1216         PINCTRL_PIN(227, "M8 GND"),
1217         PINCTRL_PIN(228, "M9 GND"),
1218         PINCTRL_PIN(229, "M10 GND"),
1219         PINCTRL_PIN(230, "M11 GND"),
1220         PINCTRL_PIN(231, "M12 GND"),
1221         PINCTRL_PIN(232, "M13 GND"),
1222         PINCTRL_PIN(233, "M14 V1"),
1223         PINCTRL_PIN(234, "M15 VCC3IOHA"),
1224         PINCTRL_PIN(235, "M16 PCI AD7"),
1225         PINCTRL_PIN(236, "M17 PCI AD6"),
1226         PINCTRL_PIN(237, "M18 PCI AD9"),
1227         PINCTRL_PIN(238, "M19 PCI AD10"),
1228         PINCTRL_PIN(239, "M20 PCI AD11"),
1229         /* Row N */
1230         PINCTRL_PIN(240, "N1 IDE IORDY"),
1231         PINCTRL_PIN(241, "N2 IDE INTRQ"),
1232         PINCTRL_PIN(242, "N3 IDE DIOW N"),
1233         PINCTRL_PIN(243, "N4 IDE DD15"),
1234         PINCTRL_PIN(244, "N5 IDE DMARQ"),
1235         PINCTRL_PIN(245, "N6 VCC3IOHA"),
1236         PINCTRL_PIN(246, "N7 VCC3IOHA"),
1237         PINCTRL_PIN(247, "N8 GND"),
1238         PINCTRL_PIN(248, "N9 GND"),
1239         PINCTRL_PIN(249, "N10 GND"),
1240         PINCTRL_PIN(250, "N11 GND"),
1241         PINCTRL_PIN(251, "N12 GND"),
1242         PINCTRL_PIN(252, "N13 GND"),
1243         PINCTRL_PIN(253, "N14 VCC3IOHA"),
1244         PINCTRL_PIN(254, "N15 VCC3IOHA"),
1245         PINCTRL_PIN(255, "N16 PCI CLKRUN N"),
1246         PINCTRL_PIN(256, "N17 PCI AD0"),
1247         PINCTRL_PIN(257, "N18 PCI AD4"),
1248         PINCTRL_PIN(258, "N19 PCI CBE0 N"),
1249         PINCTRL_PIN(259, "N20 PCI AD8"),
1250         /* Row P (for some reason O is skipped) */
1251         PINCTRL_PIN(260, "P1 IDE DD0"),
1252         PINCTRL_PIN(261, "P2 IDE DD14"),
1253         PINCTRL_PIN(262, "P3 IDE DD2"),
1254         PINCTRL_PIN(263, "P4 IDE DD4"),
1255         PINCTRL_PIN(264, "P5 IDE DD3"),
1256         PINCTRL_PIN(265, "P6 VCC3IOHA"),
1257         PINCTRL_PIN(266, "P7 GND"),
1258         PINCTRL_PIN(267, "P8 VCC2IOHA 1"),
1259         PINCTRL_PIN(268, "P9 V1"),
1260         PINCTRL_PIN(269, "P10 V1"),
1261         PINCTRL_PIN(270, "P11 V1"),
1262         PINCTRL_PIN(271, "P12 V1"),
1263         PINCTRL_PIN(272, "P13 VCC3IOHA"),
1264         PINCTRL_PIN(273, "P14 GND"),
1265         PINCTRL_PIN(274, "P15 VCC3IOHA"),
1266         PINCTRL_PIN(275, "P16 GPIO0 30"),
1267         PINCTRL_PIN(276, "P17 GPIO0 28"),
1268         PINCTRL_PIN(277, "P18 PCI AD1"),
1269         PINCTRL_PIN(278, "P19 PCI AD3"),
1270         PINCTRL_PIN(279, "P20 PCI AD5"),
1271         /* Row R (for some reason Q us skipped) */
1272         PINCTRL_PIN(280, "R1 IDE DD13"),
1273         PINCTRL_PIN(281, "R2 IDE DD12"),
1274         PINCTRL_PIN(282, "R3 IDE DD10"),
1275         PINCTRL_PIN(283, "R4 IDE DD6"),
1276         PINCTRL_PIN(284, "R5 ICE0 IDI"),
1277         PINCTRL_PIN(285, "R6 GND"),
1278         PINCTRL_PIN(286, "R7 VCC2IOHA 1"),
1279         PINCTRL_PIN(287, "R8 VCC2IOHA 1"),
1280         PINCTRL_PIN(288, "R9 VCC2IOHA 1"),
1281         PINCTRL_PIN(289, "R10 V1"),
1282         PINCTRL_PIN(290, "R11 V1"),
1283         PINCTRL_PIN(291, "R12 VCC3IOHA"),
1284         PINCTRL_PIN(292, "R13 VCC3IOHA"),
1285         PINCTRL_PIN(293, "R14 VCC3IOHA"),
1286         PINCTRL_PIN(294, "R15 GND"),
1287         PINCTRL_PIN(295, "R16 GPIO0 23"),
1288         PINCTRL_PIN(296, "R17 GPIO0 21"),
1289         PINCTRL_PIN(297, "R18 GPIO0 26"),
1290         PINCTRL_PIN(298, "R19 GPIO0 31"),
1291         PINCTRL_PIN(299, "R20 PCI AD2"),
1292         /* Row T (for some reason S is skipped) */
1293         PINCTRL_PIN(300, "T1 IDE DD11"),
1294         PINCTRL_PIN(301, "T2 IDE DD5"),
1295         PINCTRL_PIN(302, "T3 IDE DD8"),
1296         PINCTRL_PIN(303, "T4 ICE0 IDO"),
1297         PINCTRL_PIN(304, "T5 GND"),
1298         PINCTRL_PIN(305, "T6 USB GNDA U20"),
1299         PINCTRL_PIN(306, "T7 GMAC0 TXD0"),
1300         PINCTRL_PIN(307, "T8 GMAC0 TXEN"),
1301         PINCTRL_PIN(308, "T9 GMAC1 TXD3"),
1302         PINCTRL_PIN(309, "T10 GMAC1 RXDV"),
1303         PINCTRL_PIN(310, "T11 GMAC1 RXD2"),
1304         PINCTRL_PIN(311, "T12 GPIO1 29"),
1305         PINCTRL_PIN(312, "T13 GPIO0 3"),
1306         PINCTRL_PIN(313, "T14 GPIO0 9"),
1307         PINCTRL_PIN(314, "T15 GPIO0 16"),
1308         PINCTRL_PIN(315, "T16 GND"),
1309         PINCTRL_PIN(316, "T17 GPIO0 14"),
1310         PINCTRL_PIN(317, "T18 GPIO0 19"),
1311         PINCTRL_PIN(318, "T19 GPIO0 27"),
1312         PINCTRL_PIN(319, "T20 GPIO0 29"),
1313         /* Row U */
1314         PINCTRL_PIN(320, "U1 IDE DD9"),
1315         PINCTRL_PIN(321, "U2 IDE DD7"),
1316         PINCTRL_PIN(322, "U3 ICE0 ICK"),
1317         PINCTRL_PIN(323, "U4 GND"),
1318         PINCTRL_PIN(324, "U5 USB XSCO"),
1319         PINCTRL_PIN(325, "U6 GMAC0 TXD1"),
1320         PINCTRL_PIN(326, "U7 GMAC0 TXD3"),
1321         PINCTRL_PIN(327, "U8 GMAC0 TXC"),
1322         PINCTRL_PIN(328, "U9 GMAC0 RXD3"),
1323         PINCTRL_PIN(329, "U10 GMAC1 TXD0"),
1324         PINCTRL_PIN(330, "U11 GMAC1 CRS"),
1325         PINCTRL_PIN(331, "U12 EXT CLK"),
1326         PINCTRL_PIN(332, "U13 DEV DEF"),
1327         PINCTRL_PIN(333, "U14 GPIO0 0"),
1328         PINCTRL_PIN(334, "U15 GPIO0 4"),
1329         PINCTRL_PIN(335, "U16 GPIO0 10"),
1330         PINCTRL_PIN(336, "U17 GND"),
1331         PINCTRL_PIN(337, "U18 GPIO0 17"),
1332         PINCTRL_PIN(338, "U19 GPIO0 22"),
1333         PINCTRL_PIN(339, "U20 GPIO0 25"),
1334         /* Row V */
1335         PINCTRL_PIN(340, "V1 ICE0 DBGACK"),
1336         PINCTRL_PIN(341, "V2 ICE0 DBGRQ"),
1337         PINCTRL_PIN(342, "V3 GND"),
1338         PINCTRL_PIN(343, "V4 ICE0 IRST N"),
1339         PINCTRL_PIN(344, "V5 USB XSCI"),
1340         PINCTRL_PIN(345, "V6 GMAC0 COL"),
1341         PINCTRL_PIN(346, "V7 GMAC0 TXD2"),
1342         PINCTRL_PIN(347, "V8 GMAC0 RXDV"),
1343         PINCTRL_PIN(348, "V9 GMAC0 RXD1"),
1344         PINCTRL_PIN(349, "V10 GMAC1 COL"),
1345         PINCTRL_PIN(350, "V11 GMAC1 TXC"),
1346         PINCTRL_PIN(351, "V12 GMAC1 RXD1"),
1347         PINCTRL_PIN(352, "V13 MODE SEL1"),
1348         PINCTRL_PIN(353, "V14 GPIO1 28"),
1349         PINCTRL_PIN(354, "V15 GPIO0 1"),
1350         PINCTRL_PIN(355, "V16 GPIO0 8"),
1351         PINCTRL_PIN(356, "V17 GPIO0 11"),
1352         PINCTRL_PIN(357, "V18 GND"),
1353         PINCTRL_PIN(358, "V19 GPIO0 18"),
1354         PINCTRL_PIN(359, "V20 GPIO0 24"),
1355         /* Row W */
1356         PINCTRL_PIN(360, "W1 IDE RESET N"),
1357         PINCTRL_PIN(361, "W2 GND"),
1358         PINCTRL_PIN(362, "W3 USB0 VCCHSRT"),
1359         PINCTRL_PIN(363, "W4 USB0 DP"),
1360         PINCTRL_PIN(364, "W5 USB VCCA U20"),
1361         PINCTRL_PIN(365, "W6 USB1 DP"),
1362         PINCTRL_PIN(366, "W7 USB1 GNDHSRT"),
1363         PINCTRL_PIN(367, "W8 GMAC0 RXD0"),
1364         PINCTRL_PIN(368, "W9 GMAC0 CRS"),
1365         PINCTRL_PIN(369, "W10 GMAC1 TXD2"),
1366         PINCTRL_PIN(370, "W11 GMAC1 TXEN"),
1367         PINCTRL_PIN(371, "W12 GMAC1 RXD3"),
1368         PINCTRL_PIN(372, "W13 MODE SEL0"),
1369         PINCTRL_PIN(373, "W14 MODE SEL3"),
1370         PINCTRL_PIN(374, "W15 GPIO1 31"),
1371         PINCTRL_PIN(375, "W16 GPIO0 5"),
1372         PINCTRL_PIN(376, "W17 GPIO0 7"),
1373         PINCTRL_PIN(377, "W18 GPIO0 12"),
1374         PINCTRL_PIN(378, "W19 GND"),
1375         PINCTRL_PIN(379, "W20 GPIO0 20"),
1376         /* Row Y */
1377         PINCTRL_PIN(380, "Y1 ICE0 IMS"),
1378         PINCTRL_PIN(381, "Y2 USB0 GNDHSRT"),
1379         PINCTRL_PIN(382, "Y3 USB0 DM"),
1380         PINCTRL_PIN(383, "Y4 USB RREF"),
1381         PINCTRL_PIN(384, "Y5 USB1 DM"),
1382         PINCTRL_PIN(385, "Y6 USB1 VCCHSRT"),
1383         PINCTRL_PIN(386, "Y7 GMAC0 RXC"),
1384         PINCTRL_PIN(387, "Y8 GMAC0 RXD2"),
1385         PINCTRL_PIN(388, "Y9 REF CLK"),
1386         PINCTRL_PIN(389, "Y10 GMAC1 TXD1"),
1387         PINCTRL_PIN(390, "Y11 GMAC1 RXC"),
1388         PINCTRL_PIN(391, "Y12 GMAC1 RXD0"),
1389         PINCTRL_PIN(392, "Y13 M30 CLK"),
1390         PINCTRL_PIN(393, "Y14 MODE SEL2"),
1391         PINCTRL_PIN(394, "Y15 GPIO1 30"),
1392         PINCTRL_PIN(395, "Y16 GPIO0 2"),
1393         PINCTRL_PIN(396, "Y17 GPIO0 6"),
1394         PINCTRL_PIN(397, "Y18 SYS RESET N"),
1395         PINCTRL_PIN(398, "Y19 GPIO0 13"),
1396         PINCTRL_PIN(399, "Y20 GPIO0 15"),
1397 };
1398
1399 /* Digital ground */
1400 static const unsigned int gnd_3516_pins[] = {
1401         21, 38, 42, 57, 63, 76, 84, 95, 105, 114, 126, 133, 147, 148, 149, 150,
1402         151, 152, 167, 168, 169, 170, 171, 172, 187, 188, 189, 190, 191, 192,
1403         207, 208, 209, 210, 211, 212, 227, 228, 229, 230, 231, 232, 247, 248,
1404         249, 250, 251, 252, 266, 273, 285, 294, 304, 315, 323, 336, 342, 357,
1405         361, 378
1406 };
1407
1408 static const unsigned int dram_3516_pins[] = {
1409         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 23, 24, 25, 26,
1410         27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 44, 45, 46, 47, 48, 49, 50,
1411         51, 52, 53, 54, 55, 56, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
1412         87, 88, 89, 90, 91, 92, 93, 94
1413 };
1414
1415 static const unsigned int rtc_3516_pins[] = { 0, 43, 22 };
1416
1417 static const unsigned int power_3516_pins[] = { 20, 83, 40, 41, 60, 61, 62 };
1418
1419 static const unsigned int cir_3516_pins[] = { 85, 64, 82 };
1420
1421 static const unsigned int system_3516_pins[] = {
1422         332, 392, 372, 373, 393, 352, 331, 388, 397, 77
1423 };
1424
1425 static const unsigned int vcontrol_3516_pins[] = { 86, 81, 80 };
1426
1427 static const unsigned int ice_3516_pins[] = { 340, 341, 303, 322, 380, 284, 343 };
1428
1429 static const unsigned int ide_3516_pins[] = {
1430         200, 201, 204, 220, 221, 222, 223, 224, 240, 241, 242, 243, 244, 260,
1431         261, 262, 263, 264, 280, 281, 282, 283, 300, 301, 302, 320, 321, 360
1432 };
1433
1434 static const unsigned int sata_3516_pins[] = {
1435         100, 101, 102, 103, 104, 120, 121, 122, 123, 124, 140, 141, 142, 143,
1436         144, 160, 161, 162, 163, 180, 181, 182, 183, 202
1437 };
1438
1439 static const unsigned int usb_3516_pins[] = {
1440         305, 324, 344, 362, 363, 364, 365, 366, 381, 382, 383, 384, 385
1441 };
1442
1443 /* GMII, ethernet pins */
1444 static const unsigned int gmii_3516_pins[] = {
1445         306, 307, 308, 309, 310, 325, 326, 327, 328, 329, 330, 345, 346, 347,
1446         348, 349, 350, 351, 367, 368, 369, 370, 371, 386, 387, 389, 390, 391
1447 };
1448
1449 static const unsigned int pci_3516_pins[] = {
1450         17, 18, 19, 39, 58, 59, 78, 79, 96, 97, 98, 99, 115, 116, 117, 118,
1451         119, 135, 136, 137, 138, 139, 155, 156, 157, 158, 159, 175, 176, 177,
1452         178, 179, 195, 196, 197, 198, 199, 215, 216, 217, 218, 219, 235, 236,
1453         237, 238, 239, 255, 256, 257, 258, 259, 277, 278, 279, 299
1454 };
1455
1456 /*
1457  * Apparently the LPC interface is using the PCICLK for the clocking so
1458  * PCI needs to be active at the same time.
1459  */
1460 static const unsigned int lpc_3516_pins[] = {
1461         355, /* LPC_LAD[0] */
1462         356, /* LPC_SERIRQ */
1463         377, /* LPC_LAD[2] */
1464         398, /* LPC_LFRAME# */
1465         316, /* LPC_LAD[3] */
1466         399, /* LPC_LAD[1] */
1467 };
1468
1469 /* Character LCD */
1470 static const unsigned int lcd_3516_pins[] = {
1471         391, 351, 310, 371, 353, 311, 394, 374, 314, 359, 339
1472 };
1473
1474 static const unsigned int ssp_3516_pins[] = {
1475         355, /* SSP_97RST# SSP AC97 Reset, active low */
1476         356, /* SSP_FSC */
1477         377, /* SSP_ECLK */
1478         398, /* SSP_TXD */
1479         316, /* SSP_RXD */
1480         399, /* SSP_SCLK */
1481 };
1482
1483 static const unsigned int uart_rxtx_3516_pins[] = {
1484         313, /* UART_SIN serial input, RX */
1485         335, /* UART_SOUT serial output, TX */
1486 };
1487
1488 static const unsigned int uart_modem_3516_pins[] = {
1489         355, /* UART_NDCD DCD carrier detect */
1490         356, /* UART_NDTR DTR data terminal ready */
1491         377, /* UART_NDSR DSR data set ready */
1492         398, /* UART_NRTS RTS request to send */
1493         316, /* UART_NCTS CTS clear to send */
1494         399, /* UART_NRI RI ring indicator */
1495 };
1496
1497 static const unsigned int tvc_3516_pins[] = {
1498         353, /* TVC_DATA[0] */
1499         311, /* TVC_DATA[1] */
1500         394, /* TVC_DATA[2] */
1501         374, /* TVC_DATA[3] */
1502         333, /* TVC_CLK */
1503         354, /* TVC_DATA[4] */
1504         395, /* TVC_DATA[5] */
1505         312, /* TVC_DATA[6] */
1506         334, /* TVC_DATA[7] */
1507 };
1508
1509 /* NAND flash pins */
1510 static const unsigned int nflash_3516_pins[] = {
1511         243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283,
1512         302, 321, 337, 358, 295, 359, 339, 275, 298
1513 };
1514
1515 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1516 static const unsigned int pflash_3516_pins[] = {
1517         221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300,
1518         263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318,
1519         276, 319, 275, 298
1520 };
1521
1522 /*
1523  * The parallel flash can be set up in a 26-bit address bus mode exposing
1524  * A[0-15] (A[15] takes the place of ALE), but it has the
1525  * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be
1526  * used at the same time.
1527  */
1528 static const unsigned int pflash_3516_pins_extended[] = {
1529         221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300,
1530         263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318,
1531         276, 319, 275, 298,
1532         /* The extra pins */
1533         349, 308, 369, 389, 329, 350, 370, 309, 390, 391, 351, 310, 371, 330,
1534         333
1535 };
1536
1537 /* Serial flash pins CE0, CE1, DI, DO, CK */
1538 static const unsigned int sflash_3516_pins[] = { 296, 338, 295, 359, 339 };
1539
1540 /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */
1541 static const unsigned int gpio0a_3516_pins[] = { 333, 354, 395, 312, 334 };
1542
1543 /* The GPIO0B (5-7) pins overlap with ICE */
1544 static const unsigned int gpio0b_3516_pins[] = { 375, 396, 376 };
1545
1546 /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */
1547 static const unsigned int gpio0c_3516_pins[] = { 355, 356, 377, 398, 316, 399 };
1548
1549 /* The GPIO0D (9,10) pins overlap with UART RX/TX */
1550 static const unsigned int gpio0d_3516_pins[] = { 313, 335 };
1551
1552 /* The GPIO0E (16) pins overlap with LCD */
1553 static const unsigned int gpio0e_3516_pins[] = { 314 };
1554
1555 /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */
1556 static const unsigned int gpio0f_3516_pins[] = { 337, 358 };
1557
1558 /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */
1559 static const unsigned int gpio0g_3516_pins[] = { 317, 379, 297, 318, 276, 319 };
1560
1561 /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */
1562 static const unsigned int gpio0h_3516_pins[] = { 296, 338 };
1563
1564 /* The GPIO0I (23) pins overlap with all flash */
1565 static const unsigned int gpio0i_3516_pins[] = { 295 };
1566
1567 /* The GPIO0J (24,25) pins overlap with all flash and LCD */
1568 static const unsigned int gpio0j_3516_pins[] = { 359, 339 };
1569
1570 /* The GPIO0K (30,31) pins overlap with NAND flash */
1571 static const unsigned int gpio0k_3516_pins[] = { 275, 298 };
1572
1573 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
1574 static const unsigned int gpio1a_3516_pins[] = { 221, 200, 222, 201, 220 };
1575
1576 /* The GPIO1B (5-10,27) pins overlap with just IDE */
1577 static const unsigned int gpio1b_3516_pins[] = { 241, 223, 240, 204, 242, 244, 360 };
1578
1579 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
1580 static const unsigned int gpio1c_3516_pins[] = {
1581         243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283,
1582         302, 321
1583 };
1584
1585 /* The GPIO1D (28-31) pins overlap with TVC */
1586 static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 };
1587
1588 /* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */
1589 static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 };
1590
1591 /* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */
1592 static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 };
1593
1594 /* The GPIO2C (8-31) pins overlap with PCI */
1595 static const unsigned int gpio2c_3516_pins[] = {
1596         259, 237, 238, 239, 215, 216, 217, 218, 177, 159, 158, 175, 176, 139,
1597         157, 138, 137, 156, 118, 155, 99, 98, 136, 117
1598 };
1599
1600 /* Groups for the 3516 SoC/package */
1601 static const struct gemini_pin_group gemini_3516_pin_groups[] = {
1602         {
1603                 .name = "gndgrp",
1604                 .pins = gnd_3516_pins,
1605                 .num_pins = ARRAY_SIZE(gnd_3516_pins),
1606         },
1607         {
1608                 .name = "dramgrp",
1609                 .pins = dram_3516_pins,
1610                 .num_pins = ARRAY_SIZE(dram_3516_pins),
1611                 .mask = DRAM_PADS_POWERDOWN,
1612         },
1613         {
1614                 .name = "rtcgrp",
1615                 .pins = rtc_3516_pins,
1616                 .num_pins = ARRAY_SIZE(rtc_3516_pins),
1617         },
1618         {
1619                 .name = "powergrp",
1620                 .pins = power_3516_pins,
1621                 .num_pins = ARRAY_SIZE(power_3516_pins),
1622         },
1623         {
1624                 .name = "cirgrp",
1625                 .pins = cir_3516_pins,
1626                 .num_pins = ARRAY_SIZE(cir_3516_pins),
1627         },
1628         {
1629                 .name = "systemgrp",
1630                 .pins = system_3516_pins,
1631                 .num_pins = ARRAY_SIZE(system_3516_pins),
1632         },
1633         {
1634                 .name = "vcontrolgrp",
1635                 .pins = vcontrol_3516_pins,
1636                 .num_pins = ARRAY_SIZE(vcontrol_3516_pins),
1637         },
1638         {
1639                 .name = "icegrp",
1640                 .pins = ice_3516_pins,
1641                 .num_pins = ARRAY_SIZE(ice_3516_pins),
1642                 /* Conflict with some GPIO groups */
1643         },
1644         {
1645                 .name = "idegrp",
1646                 .pins = ide_3516_pins,
1647                 .num_pins = ARRAY_SIZE(ide_3516_pins),
1648                 /* Conflict with all flash usage */
1649                 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
1650                         PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
1651         },
1652         {
1653                 .name = "satagrp",
1654                 .pins = sata_3516_pins,
1655                 .num_pins = ARRAY_SIZE(sata_3516_pins),
1656         },
1657         {
1658                 .name = "usbgrp",
1659                 .pins = usb_3516_pins,
1660                 .num_pins = ARRAY_SIZE(usb_3516_pins),
1661         },
1662         {
1663                 .name = "gmiigrp",
1664                 .pins = gmii_3516_pins,
1665                 .num_pins = ARRAY_SIZE(gmii_3516_pins),
1666         },
1667         {
1668                 .name = "pcigrp",
1669                 .pins = pci_3516_pins,
1670                 .num_pins = ARRAY_SIZE(pci_3516_pins),
1671                 /* Conflict only with GPIO2 */
1672                 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
1673         },
1674         {
1675                 .name = "lpcgrp",
1676                 .pins = lpc_3516_pins,
1677                 .num_pins = ARRAY_SIZE(lpc_3516_pins),
1678                 /* Conflict with SSP */
1679                 .mask = SSP_PADS_ENABLE,
1680                 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,
1681         },
1682         {
1683                 .name = "lcdgrp",
1684                 .pins = lcd_3516_pins,
1685                 .num_pins = ARRAY_SIZE(lcd_3516_pins),
1686                 .mask = TVC_PADS_ENABLE,
1687                 .value = LCD_PADS_ENABLE,
1688         },
1689         {
1690                 .name = "sspgrp",
1691                 .pins = ssp_3516_pins,
1692                 .num_pins = ARRAY_SIZE(ssp_3516_pins),
1693                 /* Conflict with LPC */
1694                 .mask = LPC_PADS_ENABLE,
1695                 .value = SSP_PADS_ENABLE,
1696         },
1697         {
1698                 .name = "uartrxtxgrp",
1699                 .pins = uart_rxtx_3516_pins,
1700                 .num_pins = ARRAY_SIZE(uart_rxtx_3516_pins),
1701                 /* No conflicts except GPIO */
1702         },
1703         {
1704                 .name = "uartmodemgrp",
1705                 .pins = uart_modem_3516_pins,
1706                 .num_pins = ARRAY_SIZE(uart_modem_3516_pins),
1707                 /*
1708                  * Conflict with LPC and SSP,
1709                  * so when those are both disabled, modem UART can thrive.
1710                  */
1711                 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
1712         },
1713         {
1714                 .name = "tvcgrp",
1715                 .pins = tvc_3516_pins,
1716                 .num_pins = ARRAY_SIZE(tvc_3516_pins),
1717                 /* Conflict with character LCD */
1718                 .mask = LCD_PADS_ENABLE,
1719                 .value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE,
1720         },
1721         /*
1722          * The construction is done such that it is possible to use a serial
1723          * flash together with a NAND or parallel (NOR) flash, but it is not
1724          * possible to use NAND and parallel flash together. To use serial
1725          * flash with one of the two others, the muxbits need to be flipped
1726          * around before any access.
1727          */
1728         {
1729                 .name = "nflashgrp",
1730                 .pins = nflash_3516_pins,
1731                 .num_pins = ARRAY_SIZE(nflash_3516_pins),
1732                 /* Conflict with IDE, parallel and serial flash */
1733                 .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE,
1734                 .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
1735         },
1736         {
1737                 .name = "pflashgrp",
1738                 .pins = pflash_3516_pins,
1739                 .num_pins = ARRAY_SIZE(pflash_3516_pins),
1740                 /* Conflict with IDE, NAND and serial flash */
1741                 .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
1742                 .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE,
1743         },
1744         {
1745                 .name = "sflashgrp",
1746                 .pins = sflash_3516_pins,
1747                 .num_pins = ARRAY_SIZE(sflash_3516_pins),
1748                 /* Conflict with IDE, NAND and parallel flash */
1749                 .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE,
1750                 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
1751         },
1752         {
1753                 .name = "gpio0agrp",
1754                 .pins = gpio0a_3516_pins,
1755                 .num_pins = ARRAY_SIZE(gpio0a_3516_pins),
1756                 /* Conflict with TVC and ICE */
1757                 .mask = TVC_PADS_ENABLE,
1758         },
1759         {
1760                 .name = "gpio0bgrp",
1761                 .pins = gpio0b_3516_pins,
1762                 .num_pins = ARRAY_SIZE(gpio0b_3516_pins),
1763                 /* Conflict with ICE */
1764         },
1765         {
1766                 .name = "gpio0cgrp",
1767                 .pins = gpio0c_3516_pins,
1768                 .num_pins = ARRAY_SIZE(gpio0c_3516_pins),
1769                 /* Conflict with LPC, UART and SSP */
1770                 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE,
1771         },
1772         {
1773                 .name = "gpio0dgrp",
1774                 .pins = gpio0d_3516_pins,
1775                 .num_pins = ARRAY_SIZE(gpio0d_3516_pins),
1776                 /* Conflict with UART */
1777         },
1778         {
1779                 .name = "gpio0egrp",
1780                 .pins = gpio0e_3516_pins,
1781                 .num_pins = ARRAY_SIZE(gpio0e_3516_pins),
1782                 /* Conflict with LCD */
1783                 .mask = LCD_PADS_ENABLE,
1784         },
1785         {
1786                 .name = "gpio0fgrp",
1787                 .pins = gpio0f_3516_pins,
1788                 .num_pins = ARRAY_SIZE(gpio0f_3516_pins),
1789                 /* Conflict with NAND flash */
1790                 .value = NAND_PADS_DISABLE,
1791         },
1792         {
1793                 .name = "gpio0ggrp",
1794                 .pins = gpio0g_3516_pins,
1795                 .num_pins = ARRAY_SIZE(gpio0g_3516_pins),
1796                 /* Conflict with parallel flash */
1797                 .value = PFLASH_PADS_DISABLE,
1798         },
1799         {
1800                 .name = "gpio0hgrp",
1801                 .pins = gpio0h_3516_pins,
1802                 .num_pins = ARRAY_SIZE(gpio0h_3516_pins),
1803                 /* Conflict with serial flash */
1804                 .value = SFLASH_PADS_DISABLE,
1805         },
1806         {
1807                 .name = "gpio0igrp",
1808                 .pins = gpio0i_3516_pins,
1809                 .num_pins = ARRAY_SIZE(gpio0i_3516_pins),
1810                 /* Conflict with all flash */
1811                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
1812                         SFLASH_PADS_DISABLE,
1813         },
1814         {
1815                 .name = "gpio0jgrp",
1816                 .pins = gpio0j_3516_pins,
1817                 .num_pins = ARRAY_SIZE(gpio0j_3516_pins),
1818                 /* Conflict with all flash and LCD */
1819                 .mask = LCD_PADS_ENABLE,
1820                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE |
1821                         SFLASH_PADS_DISABLE,
1822         },
1823         {
1824                 .name = "gpio0kgrp",
1825                 .pins = gpio0k_3516_pins,
1826                 .num_pins = ARRAY_SIZE(gpio0k_3516_pins),
1827                 /* Conflict with parallel and NAND flash */
1828                 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE,
1829         },
1830         {
1831                 .name = "gpio1agrp",
1832                 .pins = gpio1a_3516_pins,
1833                 .num_pins = ARRAY_SIZE(gpio1a_3516_pins),
1834                 /* Conflict with IDE and parallel flash */
1835                 .mask = IDE_PADS_ENABLE,
1836                 .value = PFLASH_PADS_DISABLE,
1837         },
1838         {
1839                 .name = "gpio1bgrp",
1840                 .pins = gpio1b_3516_pins,
1841                 .num_pins = ARRAY_SIZE(gpio1b_3516_pins),
1842                 /* Conflict with IDE only */
1843                 .mask = IDE_PADS_ENABLE,
1844         },
1845         {
1846                 .name = "gpio1cgrp",
1847                 .pins = gpio1c_3516_pins,
1848                 .num_pins = ARRAY_SIZE(gpio1c_3516_pins),
1849                 /* Conflict with IDE, parallel and NAND flash */
1850                 .mask = IDE_PADS_ENABLE,
1851                 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE,
1852         },
1853         {
1854                 .name = "gpio1dgrp",
1855                 .pins = gpio1d_3516_pins,
1856                 .num_pins = ARRAY_SIZE(gpio1d_3516_pins),
1857                 /* Conflict with TVC */
1858                 .mask = TVC_PADS_ENABLE,
1859         },
1860         {
1861                 .name = "gpio2agrp",
1862                 .pins = gpio2a_3516_pins,
1863                 .num_pins = ARRAY_SIZE(gpio2a_3516_pins),
1864                 /* Conflict with GMII and extended parallel flash */
1865         },
1866         {
1867                 .name = "gpio2bgrp",
1868                 .pins = gpio2b_3516_pins,
1869                 .num_pins = ARRAY_SIZE(gpio2b_3516_pins),
1870                 /* Conflict with GMII, extended parallel flash and LCD */
1871                 .mask = LCD_PADS_ENABLE,
1872         },
1873         {
1874                 .name = "gpio2cgrp",
1875                 .pins = gpio2c_3516_pins,
1876                 .num_pins = ARRAY_SIZE(gpio2c_3516_pins),
1877                 /* Conflict with PCI */
1878                 .mask = PCI_PADS_ENABLE,
1879         },
1880 };
1881
1882 static int gemini_get_groups_count(struct pinctrl_dev *pctldev)
1883 {
1884         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1885
1886         if (pmx->is_3512)
1887                 return ARRAY_SIZE(gemini_3512_pin_groups);
1888         if (pmx->is_3516)
1889                 return ARRAY_SIZE(gemini_3516_pin_groups);
1890         return 0;
1891 }
1892
1893 static const char *gemini_get_group_name(struct pinctrl_dev *pctldev,
1894                                          unsigned int selector)
1895 {
1896         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1897
1898         if (pmx->is_3512)
1899                 return gemini_3512_pin_groups[selector].name;
1900         if (pmx->is_3516)
1901                 return gemini_3516_pin_groups[selector].name;
1902         return NULL;
1903 }
1904
1905 static int gemini_get_group_pins(struct pinctrl_dev *pctldev,
1906                                  unsigned int selector,
1907                                  const unsigned int **pins,
1908                                  unsigned int *num_pins)
1909 {
1910         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1911
1912         /* The special case with the 3516 flash pin */
1913         if (pmx->flash_pin &&
1914             pmx->is_3512 &&
1915             !strcmp(gemini_3512_pin_groups[selector].name, "pflashgrp")) {
1916                 *pins = pflash_3512_pins_extended;
1917                 *num_pins = ARRAY_SIZE(pflash_3512_pins_extended);
1918                 return 0;
1919         }
1920         if (pmx->flash_pin &&
1921             pmx->is_3516 &&
1922             !strcmp(gemini_3516_pin_groups[selector].name, "pflashgrp")) {
1923                 *pins = pflash_3516_pins_extended;
1924                 *num_pins = ARRAY_SIZE(pflash_3516_pins_extended);
1925                 return 0;
1926         }
1927         if (pmx->is_3512) {
1928                 *pins = gemini_3512_pin_groups[selector].pins;
1929                 *num_pins = gemini_3512_pin_groups[selector].num_pins;
1930         }
1931         if (pmx->is_3516) {
1932                 *pins = gemini_3516_pin_groups[selector].pins;
1933                 *num_pins = gemini_3516_pin_groups[selector].num_pins;
1934         }
1935         return 0;
1936 }
1937
1938 static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1939                                 unsigned int offset)
1940 {
1941         seq_printf(s, " " DRIVER_NAME);
1942 }
1943
1944 static const struct pinctrl_ops gemini_pctrl_ops = {
1945         .get_groups_count = gemini_get_groups_count,
1946         .get_group_name = gemini_get_group_name,
1947         .get_group_pins = gemini_get_group_pins,
1948         .pin_dbg_show = gemini_pin_dbg_show,
1949         .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
1950         .dt_free_map = pinconf_generic_dt_free_map,
1951 };
1952
1953 /**
1954  * struct gemini_pmx_func - describes Gemini pinmux functions
1955  * @name: the name of this specific function
1956  * @groups: corresponding pin groups
1957  */
1958 struct gemini_pmx_func {
1959         const char *name;
1960         const char * const *groups;
1961         const unsigned int num_groups;
1962 };
1963
1964 static const char * const dramgrps[] = { "dramgrp" };
1965 static const char * const rtcgrps[] = { "rtcgrp" };
1966 static const char * const powergrps[] = { "powergrp" };
1967 static const char * const cirgrps[] = { "cirgrp" };
1968 static const char * const systemgrps[] = { "systemgrp" };
1969 static const char * const vcontrolgrps[] = { "vcontrolgrp" };
1970 static const char * const icegrps[] = { "icegrp" };
1971 static const char * const idegrps[] = { "idegrp" };
1972 static const char * const satagrps[] = { "satagrp" };
1973 static const char * const usbgrps[] = { "usbgrp" };
1974 static const char * const gmiigrps[] = { "gmiigrp" };
1975 static const char * const pcigrps[] = { "pcigrp" };
1976 static const char * const lpcgrps[] = { "lpcgrp" };
1977 static const char * const lcdgrps[] = { "lcdgrp" };
1978 static const char * const sspgrps[] = { "sspgrp" };
1979 static const char * const uartgrps[] = { "uartrxtxgrp", "uartmodemgrp" };
1980 static const char * const tvcgrps[] = { "tvcgrp" };
1981 static const char * const nflashgrps[] = { "nflashgrp" };
1982 static const char * const pflashgrps[] = { "pflashgrp", "pflashextgrp" };
1983 static const char * const sflashgrps[] = { "sflashgrp" };
1984 static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp",
1985                                           "gpio0dgrp", "gpio0egrp", "gpio0fgrp",
1986                                           "gpio0ggrp", "gpio0hgrp", "gpio0igrp",
1987                                           "gpio0jgrp", "gpio0kgrp" };
1988 static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp",
1989                                           "gpio1dgrp" };
1990 static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" };
1991
1992 static const struct gemini_pmx_func gemini_pmx_functions[] = {
1993         {
1994                 .name = "dram",
1995                 .groups = dramgrps,
1996                 .num_groups = ARRAY_SIZE(idegrps),
1997         },
1998         {
1999                 .name = "rtc",
2000                 .groups = rtcgrps,
2001                 .num_groups = ARRAY_SIZE(rtcgrps),
2002         },
2003         {
2004                 .name = "power",
2005                 .groups = powergrps,
2006                 .num_groups = ARRAY_SIZE(powergrps),
2007         },
2008         {
2009                 /* This function is strictly unavailable on 3512 */
2010                 .name = "cir",
2011                 .groups = cirgrps,
2012                 .num_groups = ARRAY_SIZE(cirgrps),
2013         },
2014         {
2015                 .name = "system",
2016                 .groups = systemgrps,
2017                 .num_groups = ARRAY_SIZE(systemgrps),
2018         },
2019         {
2020                 .name = "vcontrol",
2021                 .groups = vcontrolgrps,
2022                 .num_groups = ARRAY_SIZE(vcontrolgrps),
2023         },
2024         {
2025                 .name = "ice",
2026                 .groups = icegrps,
2027                 .num_groups = ARRAY_SIZE(icegrps),
2028         },
2029         {
2030                 .name = "ide",
2031                 .groups = idegrps,
2032                 .num_groups = ARRAY_SIZE(idegrps),
2033         },
2034         {
2035                 .name = "sata",
2036                 .groups = satagrps,
2037                 .num_groups = ARRAY_SIZE(satagrps),
2038         },
2039         {
2040                 .name = "usb",
2041                 .groups = usbgrps,
2042                 .num_groups = ARRAY_SIZE(usbgrps),
2043         },
2044         {
2045                 .name = "gmii",
2046                 .groups = gmiigrps,
2047                 .num_groups = ARRAY_SIZE(gmiigrps),
2048         },
2049         {
2050                 .name = "pci",
2051                 .groups = pcigrps,
2052                 .num_groups = ARRAY_SIZE(pcigrps),
2053         },
2054         {
2055                 .name = "lpc",
2056                 .groups = lpcgrps,
2057                 .num_groups = ARRAY_SIZE(lpcgrps),
2058         },
2059         {
2060                 .name = "lcd",
2061                 .groups = lcdgrps,
2062                 .num_groups = ARRAY_SIZE(lcdgrps),
2063         },
2064         {
2065                 .name = "ssp",
2066                 .groups = sspgrps,
2067                 .num_groups = ARRAY_SIZE(sspgrps),
2068         },
2069         {
2070                 .name = "uart",
2071                 .groups = uartgrps,
2072                 .num_groups = ARRAY_SIZE(uartgrps),
2073         },
2074         {
2075                 .name = "tvc",
2076                 .groups = tvcgrps,
2077                 .num_groups = ARRAY_SIZE(tvcgrps),
2078         },
2079         {
2080                 .name = "nflash",
2081                 .groups = nflashgrps,
2082                 .num_groups = ARRAY_SIZE(nflashgrps),
2083         },
2084         {
2085                 .name = "pflash",
2086                 .groups = pflashgrps,
2087                 .num_groups = ARRAY_SIZE(pflashgrps),
2088         },
2089         {
2090                 .name = "sflash",
2091                 .groups = sflashgrps,
2092                 .num_groups = ARRAY_SIZE(sflashgrps),
2093         },
2094         {
2095                 .name = "gpio0",
2096                 .groups = gpio0grps,
2097                 .num_groups = ARRAY_SIZE(gpio0grps),
2098         },
2099         {
2100                 .name = "gpio1",
2101                 .groups = gpio1grps,
2102                 .num_groups = ARRAY_SIZE(gpio1grps),
2103         },
2104         {
2105                 .name = "gpio2",
2106                 .groups = gpio2grps,
2107                 .num_groups = ARRAY_SIZE(gpio2grps),
2108         },
2109 };
2110
2111
2112 static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev,
2113                               unsigned int selector,
2114                               unsigned int group)
2115 {
2116         struct gemini_pmx *pmx;
2117         const struct gemini_pmx_func *func;
2118         const struct gemini_pin_group *grp;
2119         u32 before, after, expected;
2120         unsigned long tmp;
2121         int i;
2122
2123         pmx = pinctrl_dev_get_drvdata(pctldev);
2124
2125         func = &gemini_pmx_functions[selector];
2126         if (pmx->is_3512)
2127                 grp = &gemini_3512_pin_groups[group];
2128         else if (pmx->is_3516)
2129                 grp = &gemini_3516_pin_groups[group];
2130         else {
2131                 dev_err(pmx->dev, "invalid SoC type\n");
2132                 return -ENODEV;
2133         }
2134
2135         dev_info(pmx->dev,
2136                  "ACTIVATE function \"%s\" with group \"%s\"\n",
2137                  func->name, grp->name);
2138
2139         regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before);
2140         regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL, grp->mask,
2141                            grp->value);
2142         regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after);
2143
2144         /* Which bits changed */
2145         before &= PADS_MASK;
2146         after &= PADS_MASK;
2147         expected = before &= ~grp->mask;
2148         expected |= grp->value;
2149         expected &= PADS_MASK;
2150
2151         /* Print changed states */
2152         tmp = grp->mask;
2153         for_each_set_bit(i, &tmp, PADS_MAXBIT) {
2154                 bool enabled = !(i > 3);
2155
2156                 /* Did not go low though it should */
2157                 if (after & BIT(i)) {
2158                         dev_err(pmx->dev,
2159                                 "pin group %s could not be %s: "
2160                                 "probably a hardware limitation\n",
2161                                 gemini_padgroups[i],
2162                                 enabled ? "enabled" : "disabled");
2163                         dev_err(pmx->dev,
2164                                 "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
2165                                 before, after, expected);
2166                 } else {
2167                         dev_info(pmx->dev,
2168                                  "padgroup %s %s\n",
2169                                  gemini_padgroups[i],
2170                                  enabled ? "enabled" : "disabled");
2171                 }
2172         }
2173
2174         tmp = grp->value;
2175         for_each_set_bit(i, &tmp, PADS_MAXBIT) {
2176                 bool enabled = (i > 3);
2177
2178                 /* Did not go high though it should */
2179                 if (!(after & BIT(i))) {
2180                         dev_err(pmx->dev,
2181                                 "pin group %s could not be %s: "
2182                                 "probably a hardware limitation\n",
2183                                 gemini_padgroups[i],
2184                                 enabled ? "enabled" : "disabled");
2185                         dev_err(pmx->dev,
2186                                 "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
2187                                 before, after, expected);
2188                 } else {
2189                         dev_info(pmx->dev,
2190                                  "padgroup %s %s\n",
2191                                  gemini_padgroups[i],
2192                                  enabled ? "enabled" : "disabled");
2193                 }
2194         }
2195
2196         return 0;
2197 }
2198
2199 static int gemini_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2200 {
2201         return ARRAY_SIZE(gemini_pmx_functions);
2202 }
2203
2204 static const char *gemini_pmx_get_func_name(struct pinctrl_dev *pctldev,
2205                                             unsigned int selector)
2206 {
2207         return gemini_pmx_functions[selector].name;
2208 }
2209
2210 static int gemini_pmx_get_groups(struct pinctrl_dev *pctldev,
2211                                  unsigned int selector,
2212                                  const char * const **groups,
2213                                  unsigned int * const num_groups)
2214 {
2215         *groups = gemini_pmx_functions[selector].groups;
2216         *num_groups = gemini_pmx_functions[selector].num_groups;
2217         return 0;
2218 }
2219
2220 static const struct pinmux_ops gemini_pmx_ops = {
2221         .get_functions_count = gemini_pmx_get_funcs_count,
2222         .get_function_name = gemini_pmx_get_func_name,
2223         .get_function_groups = gemini_pmx_get_groups,
2224         .set_mux = gemini_pmx_set_mux,
2225 };
2226
2227 #define GEMINI_CFGPIN(_n, _r, _lb, _hb) {       \
2228         .pin = _n,                              \
2229         .reg = _r,                              \
2230         .mask = GENMASK(_hb, _lb)               \
2231 }
2232
2233 static const struct gemini_pin_conf gemini_confs_3512[] = {
2234         GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
2235         GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
2236         GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
2237         GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
2238         GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
2239         GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
2240         GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
2241         GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
2242         GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
2243         GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
2244         GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
2245         GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
2246         GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
2247         GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
2248         GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
2249         GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
2250         GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
2251         GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
2252         GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
2253         GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
2254         GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
2255         GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
2256         GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
2257         GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
2258 };
2259
2260 static const struct gemini_pin_conf gemini_confs_3516[] = {
2261         GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
2262         GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
2263         GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
2264         GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
2265         GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
2266         GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
2267         GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
2268         GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
2269         GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
2270         GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
2271         GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
2272         GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
2273         GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
2274         GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
2275         GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
2276         GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
2277         GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
2278         GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
2279         GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
2280         GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
2281         GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
2282         GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
2283         GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
2284         GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
2285 };
2286
2287 static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx,
2288                                                          unsigned int pin)
2289 {
2290         const struct gemini_pin_conf *retconf;
2291         int i;
2292
2293         for (i = 0; i < pmx->nconfs; i++) {
2294                 retconf = &gemini_confs_3516[i];
2295                 if (retconf->pin == pin)
2296                         return retconf;
2297         }
2298         return NULL;
2299 }
2300
2301 static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2302                               unsigned long *config)
2303 {
2304         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
2305         enum pin_config_param param = pinconf_to_config_param(*config);
2306         const struct gemini_pin_conf *conf;
2307         u32 val;
2308
2309         switch (param) {
2310         case PIN_CONFIG_SKEW_DELAY:
2311                 conf = gemini_get_pin_conf(pmx, pin);
2312                 if (!conf)
2313                         return -ENOTSUPP;
2314                 regmap_read(pmx->map, conf->reg, &val);
2315                 val &= conf->mask;
2316                 val >>= (ffs(conf->mask) - 1);
2317                 *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val);
2318                 break;
2319         default:
2320                 return -ENOTSUPP;
2321         }
2322
2323         return 0;
2324 }
2325
2326 static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2327                               unsigned long *configs, unsigned int num_configs)
2328 {
2329         struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
2330         const struct gemini_pin_conf *conf;
2331         enum pin_config_param param;
2332         u32 arg;
2333         int ret = 0;
2334         int i;
2335
2336         for (i = 0; i < num_configs; i++) {
2337                 param = pinconf_to_config_param(configs[i]);
2338                 arg = pinconf_to_config_argument(configs[i]);
2339
2340                 switch (param) {
2341                 case PIN_CONFIG_SKEW_DELAY:
2342                         if (arg > 0xf)
2343                                 return -EINVAL;
2344                         conf = gemini_get_pin_conf(pmx, pin);
2345                         if (!conf) {
2346                                 dev_err(pmx->dev,
2347                                         "invalid pin for skew delay %d\n", pin);
2348                                 return -ENOTSUPP;
2349                         }
2350                         arg <<= (ffs(conf->mask) - 1);
2351                         dev_dbg(pmx->dev,
2352                                 "set pin %d to skew delay mask %08x, val %08x\n",
2353                                 pin, conf->mask, arg);
2354                         regmap_update_bits(pmx->map, conf->reg, conf->mask, arg);
2355                         break;
2356                 default:
2357                         dev_err(pmx->dev, "Invalid config param %04x\n", param);
2358                         return -ENOTSUPP;
2359                 }
2360         }
2361
2362         return ret;
2363 }
2364
2365 static const struct pinconf_ops gemini_pinconf_ops = {
2366         .pin_config_get = gemini_pinconf_get,
2367         .pin_config_set = gemini_pinconf_set,
2368         .is_generic = true,
2369 };
2370
2371 static struct pinctrl_desc gemini_pmx_desc = {
2372         .name = DRIVER_NAME,
2373         .pctlops = &gemini_pctrl_ops,
2374         .pmxops = &gemini_pmx_ops,
2375         .confops = &gemini_pinconf_ops,
2376         .owner = THIS_MODULE,
2377 };
2378
2379 static int gemini_pmx_probe(struct platform_device *pdev)
2380 {
2381         struct gemini_pmx *pmx;
2382         struct regmap *map;
2383         struct device *dev = &pdev->dev;
2384         struct device *parent;
2385         unsigned long tmp;
2386         u32 val;
2387         int ret;
2388         int i;
2389
2390         /* Create state holders etc for this driver */
2391         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
2392         if (!pmx)
2393                 return -ENOMEM;
2394
2395         pmx->dev = &pdev->dev;
2396         parent = dev->parent;
2397         if (!parent) {
2398                 dev_err(dev, "no parent to pin controller\n");
2399                 return -ENODEV;
2400         }
2401         map = syscon_node_to_regmap(parent->of_node);
2402         if (IS_ERR(map)) {
2403                 dev_err(dev, "no syscon regmap\n");
2404                 return PTR_ERR(map);
2405         }
2406         pmx->map = map;
2407
2408         /* Check that regmap works at first call, then no more */
2409         ret = regmap_read(map, GLOBAL_WORD_ID, &val);
2410         if (ret) {
2411                 dev_err(dev, "cannot access regmap\n");
2412                 return ret;
2413         }
2414         val >>= 8;
2415         val &= 0xffff;
2416         if (val == 0x3512) {
2417                 pmx->is_3512 = true;
2418                 pmx->confs = gemini_confs_3512;
2419                 pmx->nconfs = ARRAY_SIZE(gemini_confs_3512);
2420                 gemini_pmx_desc.pins = gemini_3512_pins;
2421                 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins);
2422                 dev_info(dev, "detected 3512 chip variant\n");
2423         } else if (val == 0x3516) {
2424                 pmx->is_3516 = true;
2425                 pmx->confs = gemini_confs_3516;
2426                 pmx->nconfs = ARRAY_SIZE(gemini_confs_3516);
2427                 gemini_pmx_desc.pins = gemini_3516_pins;
2428                 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins);
2429                 dev_info(dev, "detected 3516 chip variant\n");
2430         } else {
2431                 dev_err(dev, "unknown chip ID: %04x\n", val);
2432                 return -ENODEV;
2433         }
2434
2435         ret = regmap_read(map, GLOBAL_MISC_CTRL, &val);
2436         dev_info(dev, "GLOBAL MISC CTRL at boot: 0x%08x\n", val);
2437         /* Mask off relevant pads */
2438         val &= PADS_MASK;
2439         /* Invert the meaning of the DRAM+flash pads */
2440         val ^= 0x0f;
2441         /* Print initial state */
2442         tmp = val;
2443         for_each_set_bit(i, &tmp, PADS_MAXBIT) {
2444                 dev_info(dev, "pad group %s %s\n", gemini_padgroups[i],
2445                          (val & BIT(i)) ? "enabled" : "disabled");
2446         }
2447
2448         /* Check if flash pin is set */
2449         regmap_read(map, GLOBAL_STATUS, &val);
2450         pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN);
2451         dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set");
2452
2453         pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx);
2454         if (IS_ERR(pmx->pctl)) {
2455                 dev_err(dev, "could not register pinmux driver\n");
2456                 return PTR_ERR(pmx->pctl);
2457         }
2458
2459         dev_info(dev, "initialized Gemini pin control driver\n");
2460
2461         return 0;
2462 }
2463
2464 static const struct of_device_id gemini_pinctrl_match[] = {
2465         { .compatible = "cortina,gemini-pinctrl" },
2466         {},
2467 };
2468
2469 static struct platform_driver gemini_pmx_driver = {
2470         .driver = {
2471                 .name = DRIVER_NAME,
2472                 .of_match_table = gemini_pinctrl_match,
2473         },
2474         .probe = gemini_pmx_probe,
2475 };
2476
2477 static int __init gemini_pmx_init(void)
2478 {
2479         return platform_driver_register(&gemini_pmx_driver);
2480 }
2481 arch_initcall(gemini_pmx_init);