drivers/pinctrl/pinctrl-at91-pio4.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for the Atmel PIO4 controller
   4  *
   5  * Copyright (C) 2015 Atmel,
   6  *               2015 Ludovic Desroches <ludovic.desroches@atmel.com>
   7  */
   8
   9 #include <dt-bindings/pinctrl/at91.h>
  10 #include <linux/clk.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/init.h>
  15 #include <linux/of.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pinctrl/pinconf.h>
  18 #include <linux/pinctrl/pinconf-generic.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/slab.h>
  22 #include "core.h"
  23 #include "pinconf.h"
  24 #include "pinctrl-utils.h"
  25
  26 /*
  27  * Warning:
  28  * In order to not introduce confusion between Atmel PIO groups and pinctrl
  29  * framework groups, Atmel PIO groups will be called banks, line is kept to
  30  * designed the pin id into this bank.
  31  */
  32
  33 #define ATMEL_PIO_MSKR          0x0000
  34 #define ATMEL_PIO_CFGR          0x0004
  35 #define         ATMEL_PIO_CFGR_FUNC_MASK        GENMASK(2, 0)
  36 #define         ATMEL_PIO_DIR_MASK              BIT(8)
  37 #define         ATMEL_PIO_PUEN_MASK             BIT(9)
  38 #define         ATMEL_PIO_PDEN_MASK             BIT(10)
  39 #define         ATMEL_PIO_IFEN_MASK             BIT(12)
  40 #define         ATMEL_PIO_IFSCEN_MASK           BIT(13)
  41 #define         ATMEL_PIO_OPD_MASK              BIT(14)
  42 #define         ATMEL_PIO_SCHMITT_MASK          BIT(15)
  43 #define         ATMEL_PIO_DRVSTR_MASK           GENMASK(17, 16)
  44 #define         ATMEL_PIO_DRVSTR_OFFSET         16
  45 #define         ATMEL_PIO_CFGR_EVTSEL_MASK      GENMASK(26, 24)
  46 #define         ATMEL_PIO_CFGR_EVTSEL_FALLING   (0 << 24)
  47 #define         ATMEL_PIO_CFGR_EVTSEL_RISING    (1 << 24)
  48 #define         ATMEL_PIO_CFGR_EVTSEL_BOTH      (2 << 24)
  49 #define         ATMEL_PIO_CFGR_EVTSEL_LOW       (3 << 24)
  50 #define         ATMEL_PIO_CFGR_EVTSEL_HIGH      (4 << 24)
  51 #define ATMEL_PIO_PDSR          0x0008
  52 #define ATMEL_PIO_LOCKSR        0x000C
  53 #define ATMEL_PIO_SODR          0x0010
  54 #define ATMEL_PIO_CODR          0x0014
  55 #define ATMEL_PIO_ODSR          0x0018
  56 #define ATMEL_PIO_IER           0x0020
  57 #define ATMEL_PIO_IDR           0x0024
  58 #define ATMEL_PIO_IMR           0x0028
  59 #define ATMEL_PIO_ISR           0x002C
  60 #define ATMEL_PIO_IOFR          0x003C
  61
  62 #define ATMEL_PIO_NPINS_PER_BANK        32
  63 #define ATMEL_PIO_BANK(pin_id)          (pin_id / ATMEL_PIO_NPINS_PER_BANK)
  64 #define ATMEL_PIO_LINE(pin_id)          (pin_id % ATMEL_PIO_NPINS_PER_BANK)
  65 #define ATMEL_PIO_BANK_OFFSET           0x40
  66
  67 #define ATMEL_GET_PIN_NO(pinfunc)       ((pinfunc) & 0xff)
  68 #define ATMEL_GET_PIN_FUNC(pinfunc)     ((pinfunc >> 16) & 0xf)
  69 #define ATMEL_GET_PIN_IOSET(pinfunc)    ((pinfunc >> 20) & 0xf)
  70
  71 /* Custom pinconf parameters */
  72 #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
  73
  74 /**
  75  * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
  76  * @nbanks: number of PIO banks
  77  * @last_bank_count: number of lines in the last bank (can be less than
  78  *      the rest of the banks).
  79  */
  80 struct atmel_pioctrl_data {
  81         unsigned nbanks;
  82         unsigned last_bank_count;
  83 };
  84
  85 struct atmel_group {
  86         const char *name;
  87         u32 pin;
  88 };
  89
  90 struct atmel_pin {
  91         unsigned pin_id;
  92         unsigned mux;
  93         unsigned ioset;
  94         unsigned bank;
  95         unsigned line;
  96         const char *device;
  97 };
  98
  99 /**
 100  * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
 101  * @reg_base: base address of the controller.
 102  * @clk: clock of the controller.
 103  * @nbanks: number of PIO groups, it can vary depending on the SoC.
 104  * @pinctrl_dev: pinctrl device registered.
 105  * @groups: groups table to provide group name and pin in the group to pinctrl.
 106  * @group_names: group names table to provide all the group/pin names to
 107  *     pinctrl or gpio.
 108  * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
 109  *     fields are set at probe time. Other ones are set when parsing dt
 110  *     pinctrl.
 111  * @npins: number of pins.
 112  * @gpio_chip: gpio chip registered.
 113  * @irq_domain: irq domain for the gpio controller.
 114  * @irqs: table containing the hw irq number of the bank. The index of the
 115  *     table is the bank id.
 116  * @pm_wakeup_sources: bitmap of wakeup sources (lines)
 117  * @pm_suspend_backup: backup/restore register values on suspend/resume
 118  * @dev: device entry for the Atmel PIO controller.
 119  * @node: node of the Atmel PIO controller.
 120  */
 121 struct atmel_pioctrl {
 122         void __iomem            *reg_base;
 123         struct clk              *clk;
 124         unsigned                nbanks;
 125         struct pinctrl_dev      *pinctrl_dev;
 126         struct atmel_group      *groups;
 127         const char * const      *group_names;
 128         struct atmel_pin        **pins;
 129         unsigned                npins;
 130         struct gpio_chip        *gpio_chip;
 131         struct irq_domain       *irq_domain;
 132         int                     *irqs;
 133         unsigned                *pm_wakeup_sources;
 134         struct {
 135                 u32             imr;
 136                 u32             odsr;
 137                 u32             cfgr[ATMEL_PIO_NPINS_PER_BANK];
 138         } *pm_suspend_backup;
 139         struct device           *dev;
 140         struct device_node      *node;
 141 };
 142
 143 static const char * const atmel_functions[] = {
 144         "GPIO", "A", "B", "C", "D", "E", "F", "G"
 145 };
 146
 147 static const struct pinconf_generic_params atmel_custom_bindings[] = {
 148         {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
 149 };
 150
 151 /* --- GPIO --- */
 152 static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
 153                                     unsigned int bank, unsigned int reg)
 154 {
 155         return readl_relaxed(atmel_pioctrl->reg_base
 156                              + ATMEL_PIO_BANK_OFFSET * bank + reg);
 157 }
 158
 159 static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
 160                              unsigned int bank, unsigned int reg,
 161                              unsigned int val)
 162 {
 163         writel_relaxed(val, atmel_pioctrl->reg_base
 164                        + ATMEL_PIO_BANK_OFFSET * bank + reg);
 165 }
 166
 167 static void atmel_gpio_irq_ack(struct irq_data *d)
 168 {
 169         /*
 170          * Nothing to do, interrupt is cleared when reading the status
 171          * register.
 172          */
 173 }
 174
 175 static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
 176 {
 177         struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
 178         struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
 179         unsigned reg;
 180
 181         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
 182                          BIT(pin->line));
 183         reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
 184         reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
 185
 186         switch (type) {
 187         case IRQ_TYPE_EDGE_RISING:
 188                 irq_set_handler_locked(d, handle_edge_irq);
 189                 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
 190                 break;
 191         case IRQ_TYPE_EDGE_FALLING:
 192                 irq_set_handler_locked(d, handle_edge_irq);
 193                 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
 194                 break;
 195         case IRQ_TYPE_EDGE_BOTH:
 196                 irq_set_handler_locked(d, handle_edge_irq);
 197                 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
 198                 break;
 199         case IRQ_TYPE_LEVEL_LOW:
 200                 irq_set_handler_locked(d, handle_level_irq);
 201                 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
 202                 break;
 203         case IRQ_TYPE_LEVEL_HIGH:
 204                 irq_set_handler_locked(d, handle_level_irq);
 205                 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
 206                 break;
 207         case IRQ_TYPE_NONE:
 208         default:
 209                 return -EINVAL;
 210         }
 211
 212         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
 213
 214         return 0;
 215 }
 216
 217 static void atmel_gpio_irq_mask(struct irq_data *d)
 218 {
 219         struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
 220         struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
 221
 222         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
 223                          BIT(pin->line));
 224 }
 225
 226 static void atmel_gpio_irq_unmask(struct irq_data *d)
 227 {
 228         struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
 229         struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
 230
 231         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
 232                          BIT(pin->line));
 233 }
 234
 235 #ifdef CONFIG_PM_SLEEP
 236
 237 static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 238 {
 239         struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
 240         int bank = ATMEL_PIO_BANK(d->hwirq);
 241         int line = ATMEL_PIO_LINE(d->hwirq);
 242
 243         /* The gpio controller has one interrupt line per bank. */
 244         irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
 245
 246         if (on)
 247                 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
 248         else
 249                 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
 250
 251         return 0;
 252 }
 253 #else
 254 #define atmel_gpio_irq_set_wake NULL
 255 #endif /* CONFIG_PM_SLEEP */
 256
 257 static struct irq_chip atmel_gpio_irq_chip = {
 258         .name           = "GPIO",
 259         .irq_ack        = atmel_gpio_irq_ack,
 260         .irq_mask       = atmel_gpio_irq_mask,
 261         .irq_unmask     = atmel_gpio_irq_unmask,
 262         .irq_set_type   = atmel_gpio_irq_set_type,
 263         .irq_set_wake   = atmel_gpio_irq_set_wake,
 264 };
 265
 266 static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 267 {
 268         struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
 269
 270         return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
 271 }
 272
 273 static void atmel_gpio_irq_handler(struct irq_desc *desc)
 274 {
 275         unsigned int irq = irq_desc_get_irq(desc);
 276         struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
 277         struct irq_chip *chip = irq_desc_get_chip(desc);
 278         unsigned long isr;
 279         int n, bank = -1;
 280
 281         /* Find from which bank is the irq received. */
 282         for (n = 0; n < atmel_pioctrl->nbanks; n++) {
 283                 if (atmel_pioctrl->irqs[n] == irq) {
 284                         bank = n;
 285                         break;
 286                 }
 287         }
 288
 289         if (bank < 0) {
 290                 dev_err(atmel_pioctrl->dev,
 291                         "no bank associated to irq %u\n", irq);
 292                 return;
 293         }
 294
 295         chained_irq_enter(chip, desc);
 296
 297         for (;;) {
 298                 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
 299                                                      ATMEL_PIO_ISR);
 300                 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
 301                                                       ATMEL_PIO_IMR);
 302                 if (!isr)
 303                         break;
 304
 305                 for_each_set_bit(n, &isr, BITS_PER_LONG)
 306                         generic_handle_irq(atmel_gpio_to_irq(
 307                                         atmel_pioctrl->gpio_chip,
 308                                         bank * ATMEL_PIO_NPINS_PER_BANK + n));
 309         }
 310
 311         chained_irq_exit(chip, desc);
 312 }
 313
 314 static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 315 {
 316         struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
 317         struct atmel_pin *pin = atmel_pioctrl->pins[offset];
 318         unsigned reg;
 319
 320         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
 321                          BIT(pin->line));
 322         reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
 323         reg &= ~ATMEL_PIO_DIR_MASK;
 324         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
 325
 326         return 0;
 327 }
 328
 329 static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
 330 {
 331         struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
 332         struct atmel_pin *pin = atmel_pioctrl->pins[offset];
 333         unsigned reg;
 334
 335         reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
 336
 337         return !!(reg & BIT(pin->line));
 338 }
 339
 340 static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
 341                                    unsigned long *bits)
 342 {
 343         struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
 344         unsigned int bank;
 345
 346         bitmap_zero(bits, atmel_pioctrl->npins);
 347
 348         for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
 349                 unsigned int word = bank;
 350                 unsigned int offset = 0;
 351                 unsigned int reg;
 352
 353 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
 354                 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
 355                 offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;
 356 #endif
 357                 if (!mask[word])
 358                         continue;
 359
 360                 reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);
 361                 bits[word] |= mask[word] & (reg << offset);
 362         }
 363
 364         return 0;
 365 }
 366
 367 static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 368                                        int value)
 369 {
 370         struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
 371         struct atmel_pin *pin = atmel_pioctrl->pins[offset];
 372         unsigned reg;
 373
 374         atmel_gpio_write(atmel_pioctrl, pin->bank,
 375                          value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
 376                          BIT(pin->line));
 377
 378         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
 379                          BIT(pin->line));
 380         reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
 381         reg |= ATMEL_PIO_DIR_MASK;
 382         atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
 383
 384         return 0;
 385 }
 386
 387 static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
 388 {
 389         struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
 390         struct atmel_pin *pin = atmel_pioctrl->pins[offset];
 391
 392         atmel_gpio_write(atmel_pioctrl, pin->bank,
 393                          val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
 394                          BIT(pin->line));
 395 }
 396
 397 static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
 398                                     unsigned long *bits)
 399 {
 400         struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
 401         unsigned int bank;
 402
 403         for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
 404                 unsigned int bitmask;
 405                 unsigned int word = bank;
 406
 407 /*
 408  * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over
 409  * two 32bit words to handle the whole  bitmask
 410  */
 411 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
 412                 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
 413 #endif
 414                 if (!mask[word])
 415                         continue;
 416
 417                 bitmask = mask[word] & bits[word];
 418                 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);
 419
 420                 bitmask = mask[word] & ~bits[word];
 421                 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);
 422
 423 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
 424                 mask[word] >>= ATMEL_PIO_NPINS_PER_BANK;
 425                 bits[word] >>= ATMEL_PIO_NPINS_PER_BANK;
 426 #endif
 427         }
 428 }
 429
 430 static struct gpio_chip atmel_gpio_chip = {
 431         .direction_input        = atmel_gpio_direction_input,
 432         .get                    = atmel_gpio_get,
 433         .get_multiple           = atmel_gpio_get_multiple,
 434         .direction_output       = atmel_gpio_direction_output,
 435         .set                    = atmel_gpio_set,
 436         .set_multiple           = atmel_gpio_set_multiple,
 437         .to_irq                 = atmel_gpio_to_irq,
 438         .base                   = 0,
 439 };
 440
 441 /* --- PINCTRL --- */
 442 static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
 443                                           unsigned pin_id)
 444 {
 445         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 446         unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
 447         unsigned line = atmel_pioctrl->pins[pin_id]->line;
 448         void __iomem *addr = atmel_pioctrl->reg_base
 449                              + bank * ATMEL_PIO_BANK_OFFSET;
 450
 451         writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
 452         /* Have to set MSKR first, to access the right pin CFGR. */
 453         wmb();
 454
 455         return readl_relaxed(addr + ATMEL_PIO_CFGR);
 456 }
 457
 458 static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
 459                                    unsigned pin_id, u32 conf)
 460 {
 461         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 462         unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
 463         unsigned line = atmel_pioctrl->pins[pin_id]->line;
 464         void __iomem *addr = atmel_pioctrl->reg_base
 465                              + bank * ATMEL_PIO_BANK_OFFSET;
 466
 467         writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
 468         /* Have to set MSKR first, to access the right pin CFGR. */
 469         wmb();
 470         writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
 471 }
 472
 473 static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
 474 {
 475         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 476
 477         return atmel_pioctrl->npins;
 478 }
 479
 480 static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
 481                                              unsigned selector)
 482 {
 483         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 484
 485         return atmel_pioctrl->groups[selector].name;
 486 }
 487
 488 static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
 489                                      unsigned selector, const unsigned **pins,
 490                                      unsigned *num_pins)
 491 {
 492         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 493
 494         *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
 495         *num_pins = 1;
 496
 497         return 0;
 498 }
 499
 500 static struct atmel_group *
 501 atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
 502 {
 503         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 504         int i;
 505
 506         for (i = 0; i < atmel_pioctrl->npins; i++) {
 507                 struct atmel_group *grp = atmel_pioctrl->groups + i;
 508
 509                 if (grp->pin == pin)
 510                         return grp;
 511         }
 512
 513         return NULL;
 514 }
 515
 516 static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
 517                                     struct device_node *np,
 518                                     u32 pinfunc, const char **grp_name,
 519                                     const char **func_name)
 520 {
 521         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 522         unsigned pin_id, func_id;
 523         struct atmel_group *grp;
 524
 525         pin_id = ATMEL_GET_PIN_NO(pinfunc);
 526         func_id = ATMEL_GET_PIN_FUNC(pinfunc);
 527
 528         if (func_id >= ARRAY_SIZE(atmel_functions))
 529                 return -EINVAL;
 530
 531         *func_name = atmel_functions[func_id];
 532
 533         grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
 534         if (!grp)
 535                 return -EINVAL;
 536         *grp_name = grp->name;
 537
 538         atmel_pioctrl->pins[pin_id]->mux = func_id;
 539         atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
 540         /* Want the device name not the group one. */
 541         if (np->parent == atmel_pioctrl->node)
 542                 atmel_pioctrl->pins[pin_id]->device = np->name;
 543         else
 544                 atmel_pioctrl->pins[pin_id]->device = np->parent->name;
 545
 546         return 0;
 547 }
 548
 549 static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 550                                         struct device_node *np,
 551                                         struct pinctrl_map **map,
 552                                         unsigned *reserved_maps,
 553                                         unsigned *num_maps)
 554 {
 555         unsigned num_pins, num_configs, reserve;
 556         unsigned long *configs;
 557         struct property *pins;
 558         u32 pinfunc;
 559         int ret, i;
 560
 561         pins = of_find_property(np, "pinmux", NULL);
 562         if (!pins)
 563                 return -EINVAL;
 564
 565         ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
 566                                               &num_configs);
 567         if (ret < 0) {
 568                 dev_err(pctldev->dev, "%pOF: could not parse node property\n",
 569                         np);
 570                 return ret;
 571         }
 572
 573         num_pins = pins->length / sizeof(u32);
 574         if (!num_pins) {
 575                 dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
 576                 ret = -EINVAL;
 577                 goto exit;
 578         }
 579
 580         /*
 581          * Reserve maps, at least there is a mux map and an optional conf
 582          * map for each pin.
 583          */
 584         reserve = 1;
 585         if (num_configs)
 586                 reserve++;
 587         reserve *= num_pins;
 588         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
 589                                         reserve);
 590         if (ret < 0)
 591                 goto exit;
 592
 593         for (i = 0; i < num_pins; i++) {
 594                 const char *group, *func;
 595
 596                 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
 597                 if (ret)
 598                         goto exit;
 599
 600                 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
 601                                                &func);
 602                 if (ret)
 603                         goto exit;
 604
 605                 pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
 606                                           group, func);
 607
 608                 if (num_configs) {
 609                         ret = pinctrl_utils_add_map_configs(pctldev, map,
 610                                         reserved_maps, num_maps, group,
 611                                         configs, num_configs,
 612                                         PIN_MAP_TYPE_CONFIGS_GROUP);
 613                         if (ret < 0)
 614                                 goto exit;
 615                 }
 616         }
 617
 618 exit:
 619         kfree(configs);
 620         return ret;
 621 }
 622
 623 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
 624                                      struct device_node *np_config,
 625                                      struct pinctrl_map **map,
 626                                      unsigned *num_maps)
 627 {
 628         struct device_node *np;
 629         unsigned reserved_maps;
 630         int ret;
 631
 632         *map = NULL;
 633         *num_maps = 0;
 634         reserved_maps = 0;
 635
 636         /*
 637          * If all the pins of a device have the same configuration (or no one),
 638          * it is useless to add a subnode, so directly parse node referenced by
 639          * phandle.
 640          */
 641         ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
 642                                            &reserved_maps, num_maps);
 643         if (ret) {
 644                 for_each_child_of_node(np_config, np) {
 645                         ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
 646                                                     &reserved_maps, num_maps);
 647                         if (ret < 0) {
 648                                 of_node_put(np);
 649                                 break;
 650                         }
 651                 }
 652         }
 653
 654         if (ret < 0) {
 655                 pinctrl_utils_free_map(pctldev, *map, *num_maps);
 656                 dev_err(pctldev->dev, "can't create maps for node %pOF\n",
 657                         np_config);
 658         }
 659
 660         return ret;
 661 }
 662
 663 static const struct pinctrl_ops atmel_pctlops = {
 664         .get_groups_count       = atmel_pctl_get_groups_count,
 665         .get_group_name         = atmel_pctl_get_group_name,
 666         .get_group_pins         = atmel_pctl_get_group_pins,
 667         .dt_node_to_map         = atmel_pctl_dt_node_to_map,
 668         .dt_free_map            = pinctrl_utils_free_map,
 669 };
 670
 671 static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
 672 {
 673         return ARRAY_SIZE(atmel_functions);
 674 }
 675
 676 static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
 677                                                unsigned selector)
 678 {
 679         return atmel_functions[selector];
 680 }
 681
 682 static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
 683                                          unsigned selector,
 684                                          const char * const **groups,
 685                                          unsigned * const num_groups)
 686 {
 687         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 688
 689         *groups = atmel_pioctrl->group_names;
 690         *num_groups = atmel_pioctrl->npins;
 691
 692         return 0;
 693 }
 694
 695 static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
 696                              unsigned function,
 697                              unsigned group)
 698 {
 699         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 700         unsigned pin;
 701         u32 conf;
 702
 703         dev_dbg(pctldev->dev, "enable function %s group %s\n",
 704                 atmel_functions[function], atmel_pioctrl->groups[group].name);
 705
 706         pin = atmel_pioctrl->groups[group].pin;
 707         conf = atmel_pin_config_read(pctldev, pin);
 708         conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
 709         conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
 710         dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
 711         atmel_pin_config_write(pctldev, pin, conf);
 712
 713         return 0;
 714 }
 715
 716 static const struct pinmux_ops atmel_pmxops = {
 717         .get_functions_count    = atmel_pmx_get_functions_count,
 718         .get_function_name      = atmel_pmx_get_function_name,
 719         .get_function_groups    = atmel_pmx_get_function_groups,
 720         .set_mux                = atmel_pmx_set_mux,
 721 };
 722
 723 static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
 724                                            unsigned group,
 725                                            unsigned long *config)
 726 {
 727         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 728         unsigned param = pinconf_to_config_param(*config), arg = 0;
 729         struct atmel_group *grp = atmel_pioctrl->groups + group;
 730         unsigned pin_id = grp->pin;
 731         u32 res;
 732
 733         res = atmel_pin_config_read(pctldev, pin_id);
 734
 735         switch (param) {
 736         case PIN_CONFIG_BIAS_PULL_UP:
 737                 if (!(res & ATMEL_PIO_PUEN_MASK))
 738                         return -EINVAL;
 739                 arg = 1;
 740                 break;
 741         case PIN_CONFIG_BIAS_PULL_DOWN:
 742                 if ((res & ATMEL_PIO_PUEN_MASK) ||
 743                     (!(res & ATMEL_PIO_PDEN_MASK)))
 744                         return -EINVAL;
 745                 arg = 1;
 746                 break;
 747         case PIN_CONFIG_BIAS_DISABLE:
 748                 if ((res & ATMEL_PIO_PUEN_MASK) ||
 749                     ((res & ATMEL_PIO_PDEN_MASK)))
 750                         return -EINVAL;
 751                 arg = 1;
 752                 break;
 753         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 754                 if (!(res & ATMEL_PIO_OPD_MASK))
 755                         return -EINVAL;
 756                 arg = 1;
 757                 break;
 758         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 759                 if (!(res & ATMEL_PIO_SCHMITT_MASK))
 760                         return -EINVAL;
 761                 arg = 1;
 762                 break;
 763         case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
 764                 if (!(res & ATMEL_PIO_DRVSTR_MASK))
 765                         return -EINVAL;
 766                 arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
 767                 break;
 768         default:
 769                 return -ENOTSUPP;
 770         }
 771
 772         *config = pinconf_to_config_packed(param, arg);
 773         return 0;
 774 }
 775
 776 static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
 777                                            unsigned group,
 778                                            unsigned long *configs,
 779                                            unsigned num_configs)
 780 {
 781         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 782         struct atmel_group *grp = atmel_pioctrl->groups + group;
 783         unsigned bank, pin, pin_id = grp->pin;
 784         u32 mask, conf = 0;
 785         int i;
 786
 787         conf = atmel_pin_config_read(pctldev, pin_id);
 788
 789         for (i = 0; i < num_configs; i++) {
 790                 unsigned param = pinconf_to_config_param(configs[i]);
 791                 unsigned arg = pinconf_to_config_argument(configs[i]);
 792
 793                 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
 794                         __func__, pin_id, configs[i]);
 795
 796                 switch (param) {
 797                 case PIN_CONFIG_BIAS_DISABLE:
 798                         conf &= (~ATMEL_PIO_PUEN_MASK);
 799                         conf &= (~ATMEL_PIO_PDEN_MASK);
 800                         break;
 801                 case PIN_CONFIG_BIAS_PULL_UP:
 802                         conf |= ATMEL_PIO_PUEN_MASK;
 803                         conf &= (~ATMEL_PIO_PDEN_MASK);
 804                         break;
 805                 case PIN_CONFIG_BIAS_PULL_DOWN:
 806                         conf |= ATMEL_PIO_PDEN_MASK;
 807                         conf &= (~ATMEL_PIO_PUEN_MASK);
 808                         break;
 809                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 810                         if (arg == 0)
 811                                 conf &= (~ATMEL_PIO_OPD_MASK);
 812                         else
 813                                 conf |= ATMEL_PIO_OPD_MASK;
 814                         break;
 815                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 816                         if (arg == 0)
 817                                 conf |= ATMEL_PIO_SCHMITT_MASK;
 818                         else
 819                                 conf &= (~ATMEL_PIO_SCHMITT_MASK);
 820                         break;
 821                 case PIN_CONFIG_INPUT_DEBOUNCE:
 822                         if (arg == 0) {
 823                                 conf &= (~ATMEL_PIO_IFEN_MASK);
 824                                 conf &= (~ATMEL_PIO_IFSCEN_MASK);
 825                         } else {
 826                                 /*
 827                                  * We don't care about the debounce value for several reasons:
 828                                  * - can't have different debounce periods inside a same group,
 829                                  * - the register to configure this period is a secure register.
 830                                  * The debouncing filter can filter a pulse with a duration of less
 831                                  * than 1/2 slow clock period.
 832                                  */
 833                                 conf |= ATMEL_PIO_IFEN_MASK;
 834                                 conf |= ATMEL_PIO_IFSCEN_MASK;
 835                         }
 836                         break;
 837                 case PIN_CONFIG_OUTPUT:
 838                         conf |= ATMEL_PIO_DIR_MASK;
 839                         bank = ATMEL_PIO_BANK(pin_id);
 840                         pin = ATMEL_PIO_LINE(pin_id);
 841                         mask = 1 << pin;
 842
 843                         if (arg == 0) {
 844                                 writel_relaxed(mask, atmel_pioctrl->reg_base +
 845                                         bank * ATMEL_PIO_BANK_OFFSET +
 846                                         ATMEL_PIO_CODR);
 847                         } else {
 848                                 writel_relaxed(mask, atmel_pioctrl->reg_base +
 849                                         bank * ATMEL_PIO_BANK_OFFSET +
 850                                         ATMEL_PIO_SODR);
 851                         }
 852                         break;
 853                 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
 854                         switch (arg) {
 855                         case ATMEL_PIO_DRVSTR_LO:
 856                         case ATMEL_PIO_DRVSTR_ME:
 857                         case ATMEL_PIO_DRVSTR_HI:
 858                                 conf &= (~ATMEL_PIO_DRVSTR_MASK);
 859                                 conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;
 860                                 break;
 861                         default:
 862                                 dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
 863                         }
 864                         break;
 865                 default:
 866                         dev_warn(pctldev->dev,
 867                                  "unsupported configuration parameter: %u\n",
 868                                  param);
 869                         continue;
 870                 }
 871         }
 872
 873         dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
 874         atmel_pin_config_write(pctldev, pin_id, conf);
 875
 876         return 0;
 877 }
 878
 879 static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
 880                                            struct seq_file *s, unsigned pin_id)
 881 {
 882         struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 883         u32 conf;
 884
 885         if (!atmel_pioctrl->pins[pin_id]->device)
 886                 return;
 887
 888         if (atmel_pioctrl->pins[pin_id])
 889                 seq_printf(s, " (%s, ioset %u) ",
 890                            atmel_pioctrl->pins[pin_id]->device,
 891                            atmel_pioctrl->pins[pin_id]->ioset);
 892
 893         conf = atmel_pin_config_read(pctldev, pin_id);
 894         if (conf & ATMEL_PIO_PUEN_MASK)
 895                 seq_printf(s, "%s ", "pull-up");
 896         if (conf & ATMEL_PIO_PDEN_MASK)
 897                 seq_printf(s, "%s ", "pull-down");
 898         if (conf & ATMEL_PIO_IFEN_MASK)
 899                 seq_printf(s, "%s ", "debounce");
 900         if (conf & ATMEL_PIO_OPD_MASK)
 901                 seq_printf(s, "%s ", "open-drain");
 902         if (conf & ATMEL_PIO_SCHMITT_MASK)
 903                 seq_printf(s, "%s ", "schmitt");
 904         if (conf & ATMEL_PIO_DRVSTR_MASK) {
 905                 switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
 906                 case ATMEL_PIO_DRVSTR_ME:
 907                         seq_printf(s, "%s ", "medium-drive");
 908                         break;
 909                 case ATMEL_PIO_DRVSTR_HI:
 910                         seq_printf(s, "%s ", "high-drive");
 911                         break;
 912                 /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */
 913                 default:
 914                         seq_printf(s, "%s ", "low-drive");
 915                 }
 916         }
 917 }
 918
 919 static const struct pinconf_ops atmel_confops = {
 920         .pin_config_group_get   = atmel_conf_pin_config_group_get,
 921         .pin_config_group_set   = atmel_conf_pin_config_group_set,
 922         .pin_config_dbg_show    = atmel_conf_pin_config_dbg_show,
 923 };
 924
 925 static struct pinctrl_desc atmel_pinctrl_desc = {
 926         .name           = "atmel_pinctrl",
 927         .confops        = &atmel_confops,
 928         .pctlops        = &atmel_pctlops,
 929         .pmxops         = &atmel_pmxops,
 930 };
 931
 932 static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
 933 {
 934         struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
 935         int i, j;
 936
 937         /*
 938          * For each bank, save IMR to restore it later and disable all GPIO
 939          * interrupts excepting the ones marked as wakeup sources.
 940          */
 941         for (i = 0; i < atmel_pioctrl->nbanks; i++) {
 942                 atmel_pioctrl->pm_suspend_backup[i].imr =
 943                         atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
 944                 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
 945                                  ~atmel_pioctrl->pm_wakeup_sources[i]);
 946                 atmel_pioctrl->pm_suspend_backup[i].odsr =
 947                         atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
 948                 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
 949                         atmel_gpio_write(atmel_pioctrl, i,
 950                                          ATMEL_PIO_MSKR, BIT(j));
 951                         atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
 952                                 atmel_gpio_read(atmel_pioctrl, i,
 953                                                 ATMEL_PIO_CFGR);
 954                 }
 955         }
 956
 957         return 0;
 958 }
 959
 960 static int __maybe_unused atmel_pctrl_resume(struct device *dev)
 961 {
 962         struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
 963         int i, j;
 964
 965         for (i = 0; i < atmel_pioctrl->nbanks; i++) {
 966                 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
 967                                  atmel_pioctrl->pm_suspend_backup[i].imr);
 968                 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
 969                                  atmel_pioctrl->pm_suspend_backup[i].odsr);
 970                 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
 971                         atmel_gpio_write(atmel_pioctrl, i,
 972                                          ATMEL_PIO_MSKR, BIT(j));
 973                         atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
 974                                          atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
 975                 }
 976         }
 977
 978         return 0;
 979 }
 980
 981 static const struct dev_pm_ops atmel_pctrl_pm_ops = {
 982         SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
 983 };
 984
 985 /*
 986  * The number of banks can be different from a SoC to another one.
 987  * We can have up to 16 banks.
 988  */
 989 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
 990         .nbanks                 = 4,
 991         .last_bank_count        = ATMEL_PIO_NPINS_PER_BANK,
 992 };
 993
 994 static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
 995         .nbanks                 = 5,
 996         .last_bank_count        = 8, /* sama7g5 has only PE0 to PE7 */
 997 };
 998
 999 static const struct of_device_id atmel_pctrl_of_match[] = {
1000         {
1001                 .compatible = "atmel,sama5d2-pinctrl",
1002                 .data = &atmel_sama5d2_pioctrl_data,
1003         }, {
1004                 .compatible = "microchip,sama7g5-pinctrl",
1005                 .data = &microchip_sama7g5_pioctrl_data,
1006         }, {
1007                 /* sentinel */
1008         }
1009 };
1010
1011 static int atmel_pinctrl_probe(struct platform_device *pdev)
1012 {
1013         struct device *dev = &pdev->dev;
1014         struct pinctrl_pin_desc *pin_desc;
1015         const char **group_names;
1016         const struct of_device_id *match;
1017         int i, ret;
1018         struct resource *res;
1019         struct atmel_pioctrl *atmel_pioctrl;
1020         const struct atmel_pioctrl_data *atmel_pioctrl_data;
1021
1022         atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
1023         if (!atmel_pioctrl)
1024                 return -ENOMEM;
1025         atmel_pioctrl->dev = dev;
1026         atmel_pioctrl->node = dev->of_node;
1027         platform_set_drvdata(pdev, atmel_pioctrl);
1028
1029         match = of_match_node(atmel_pctrl_of_match, dev->of_node);
1030         if (!match) {
1031                 dev_err(dev, "unknown compatible string\n");
1032                 return -ENODEV;
1033         }
1034         atmel_pioctrl_data = match->data;
1035         atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
1036         atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
1037         /* if last bank has limited number of pins, adjust accordingly */
1038         if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
1039                 atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
1040                 atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
1041         }
1042
1043         atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
1044         if (IS_ERR(atmel_pioctrl->reg_base))
1045                 return PTR_ERR(atmel_pioctrl->reg_base);
1046
1047         atmel_pioctrl->clk = devm_clk_get(dev, NULL);
1048         if (IS_ERR(atmel_pioctrl->clk)) {
1049                 dev_err(dev, "failed to get clock\n");
1050                 return PTR_ERR(atmel_pioctrl->clk);
1051         }
1052
1053         atmel_pioctrl->pins = devm_kcalloc(dev,
1054                                            atmel_pioctrl->npins,
1055                                            sizeof(*atmel_pioctrl->pins),
1056                                            GFP_KERNEL);
1057         if (!atmel_pioctrl->pins)
1058                 return -ENOMEM;
1059
1060         pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc),
1061                                 GFP_KERNEL);
1062         if (!pin_desc)
1063                 return -ENOMEM;
1064         atmel_pinctrl_desc.pins = pin_desc;
1065         atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
1066         atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);
1067         atmel_pinctrl_desc.custom_params = atmel_custom_bindings;
1068
1069         /* One pin is one group since a pin can achieve all functions. */
1070         group_names = devm_kcalloc(dev,
1071                                    atmel_pioctrl->npins, sizeof(*group_names),
1072                                    GFP_KERNEL);
1073         if (!group_names)
1074                 return -ENOMEM;
1075         atmel_pioctrl->group_names = group_names;
1076
1077         atmel_pioctrl->groups = devm_kcalloc(&pdev->dev,
1078                         atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups),
1079                         GFP_KERNEL);
1080         if (!atmel_pioctrl->groups)
1081                 return -ENOMEM;
1082         for (i = 0 ; i < atmel_pioctrl->npins; i++) {
1083                 struct atmel_group *group = atmel_pioctrl->groups + i;
1084                 unsigned bank = ATMEL_PIO_BANK(i);
1085                 unsigned line = ATMEL_PIO_LINE(i);
1086
1087                 atmel_pioctrl->pins[i] = devm_kzalloc(dev,
1088                                 sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
1089                 if (!atmel_pioctrl->pins[i])
1090                         return -ENOMEM;
1091
1092                 atmel_pioctrl->pins[i]->pin_id = i;
1093                 atmel_pioctrl->pins[i]->bank = bank;
1094                 atmel_pioctrl->pins[i]->line = line;
1095
1096                 pin_desc[i].number = i;
1097                 /* Pin naming convention: P(bank_name)(bank_pin_number). */
1098                 pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
1099                                              bank + 'A', line);
1100
1101                 group->name = group_names[i] = pin_desc[i].name;
1102                 group->pin = pin_desc[i].number;
1103
1104                 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
1105         }
1106
1107         atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
1108         atmel_pioctrl->gpio_chip->of_node = dev->of_node;
1109         atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
1110         atmel_pioctrl->gpio_chip->label = dev_name(dev);
1111         atmel_pioctrl->gpio_chip->parent = dev;
1112         atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
1113
1114         atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,
1115                         atmel_pioctrl->nbanks,
1116                         sizeof(*atmel_pioctrl->pm_wakeup_sources),
1117                         GFP_KERNEL);
1118         if (!atmel_pioctrl->pm_wakeup_sources)
1119                 return -ENOMEM;
1120
1121         atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev,
1122                         atmel_pioctrl->nbanks,
1123                         sizeof(*atmel_pioctrl->pm_suspend_backup),
1124                         GFP_KERNEL);
1125         if (!atmel_pioctrl->pm_suspend_backup)
1126                 return -ENOMEM;
1127
1128         atmel_pioctrl->irqs = devm_kcalloc(dev,
1129                                            atmel_pioctrl->nbanks,
1130                                            sizeof(*atmel_pioctrl->irqs),
1131                                            GFP_KERNEL);
1132         if (!atmel_pioctrl->irqs)
1133                 return -ENOMEM;
1134
1135         /* There is one controller but each bank has its own irq line. */
1136         for (i = 0; i < atmel_pioctrl->nbanks; i++) {
1137                 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1138                 if (!res) {
1139                         dev_err(dev, "missing irq resource for group %c\n",
1140                                 'A' + i);
1141                         return -EINVAL;
1142                 }
1143                 atmel_pioctrl->irqs[i] = res->start;
1144                 irq_set_chained_handler_and_data(res->start,
1145                         atmel_gpio_irq_handler, atmel_pioctrl);
1146                 dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
1147         }
1148
1149         atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
1150                         atmel_pioctrl->gpio_chip->ngpio,
1151                         &irq_domain_simple_ops, NULL);
1152         if (!atmel_pioctrl->irq_domain) {
1153                 dev_err(dev, "can't add the irq domain\n");
1154                 return -ENODEV;
1155         }
1156         atmel_pioctrl->irq_domain->name = "atmel gpio";
1157
1158         for (i = 0; i < atmel_pioctrl->npins; i++) {
1159                 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
1160
1161                 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
1162                                          handle_simple_irq);
1163                 irq_set_chip_data(irq, atmel_pioctrl);
1164                 dev_dbg(dev,
1165                         "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
1166                         i, irq);
1167         }
1168
1169         ret = clk_prepare_enable(atmel_pioctrl->clk);
1170         if (ret) {
1171                 dev_err(dev, "failed to prepare and enable clock\n");
1172                 goto clk_prepare_enable_error;
1173         }
1174
1175         atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
1176                                                            &atmel_pinctrl_desc,
1177                                                            atmel_pioctrl);
1178         if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
1179                 ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
1180                 dev_err(dev, "pinctrl registration failed\n");
1181                 goto clk_unprep;
1182         }
1183
1184         ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
1185         if (ret) {
1186                 dev_err(dev, "failed to add gpiochip\n");
1187                 goto clk_unprep;
1188         }
1189
1190         ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
1191                                      0, 0, atmel_pioctrl->gpio_chip->ngpio);
1192         if (ret) {
1193                 dev_err(dev, "failed to add gpio pin range\n");
1194                 goto gpiochip_add_pin_range_error;
1195         }
1196
1197         dev_info(&pdev->dev, "atmel pinctrl initialized\n");
1198
1199         return 0;
1200
1201 gpiochip_add_pin_range_error:
1202         gpiochip_remove(atmel_pioctrl->gpio_chip);
1203
1204 clk_unprep:
1205         clk_disable_unprepare(atmel_pioctrl->clk);
1206
1207 clk_prepare_enable_error:
1208         irq_domain_remove(atmel_pioctrl->irq_domain);
1209
1210         return ret;
1211 }
1212
1213 static struct platform_driver atmel_pinctrl_driver = {
1214         .driver = {
1215                 .name = "pinctrl-at91-pio4",
1216                 .of_match_table = atmel_pctrl_of_match,
1217                 .pm = &atmel_pctrl_pm_ops,
1218                 .suppress_bind_attrs = true,
1219         },
1220         .probe = atmel_pinctrl_probe,
1221 };
1222 builtin_platform_driver(atmel_pinctrl_driver);