1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic GPIO driver for logic cells found in the Nomadik SoC
5 * Copyright (C) 2008,2009 STMicroelectronics
6 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
7 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
8 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/device.h>
13 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/spinlock.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/of_device.h>
22 #include <linux/of_address.h>
23 #include <linux/bitops.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 #include <linux/pinctrl/pinconf.h>
28 /* Since we request GPIOs from ourself */
29 #include <linux/pinctrl/consumer.h>
30 #include "pinctrl-nomadik.h"
32 #include "../pinctrl-utils.h"
35 * The GPIO module in the Nomadik family of Systems-on-Chip is an
36 * AMBA device, managing 32 pins and alternate functions. The logic block
37 * is currently used in the Nomadik and ux500.
39 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
43 * pin configurations are represented by 32-bit integers:
45 * bit 0.. 8 - Pin Number (512 Pins Maximum)
46 * bit 9..10 - Alternate Function Selection
47 * bit 11..12 - Pull up/down state
48 * bit 13 - Sleep mode behaviour
50 * bit 15 - Value (if output)
51 * bit 16..18 - SLPM pull up/down state
52 * bit 19..20 - SLPM direction
53 * bit 21..22 - SLPM Value (if output)
54 * bit 23..25 - PDIS value (if input)
58 * to facilitate the definition, the following macros are provided
60 * PIN_CFG_DEFAULT - default config (0):
61 * pull up/down = disabled
62 * sleep mode = input/wakeup
65 * SLPM direction = same as normal
66 * SLPM pull = same as normal
67 * SLPM value = same as normal
69 * PIN_CFG - default config with alternate function
72 typedef unsigned long pin_cfg_t;
74 #define PIN_NUM_MASK 0x1ff
75 #define PIN_NUM(x) ((x) & PIN_NUM_MASK)
77 #define PIN_ALT_SHIFT 9
78 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
79 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
80 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
81 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
82 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
83 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
85 #define PIN_PULL_SHIFT 11
86 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
87 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
88 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
89 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
90 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
92 #define PIN_SLPM_SHIFT 13
93 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
94 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
95 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
96 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
97 /* These two replace the above in DB8500v2+ */
98 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
99 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
100 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
102 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
103 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
105 #define PIN_DIR_SHIFT 14
106 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
107 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
108 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
109 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
111 #define PIN_VAL_SHIFT 15
112 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
113 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
114 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
115 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
117 #define PIN_SLPM_PULL_SHIFT 16
118 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
119 #define PIN_SLPM_PULL(x) \
120 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
121 #define PIN_SLPM_PULL_NONE \
122 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
123 #define PIN_SLPM_PULL_UP \
124 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
125 #define PIN_SLPM_PULL_DOWN \
126 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
128 #define PIN_SLPM_DIR_SHIFT 19
129 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
130 #define PIN_SLPM_DIR(x) \
131 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
132 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
133 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
135 #define PIN_SLPM_VAL_SHIFT 21
136 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
137 #define PIN_SLPM_VAL(x) \
138 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
139 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
140 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
142 #define PIN_SLPM_PDIS_SHIFT 23
143 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
144 #define PIN_SLPM_PDIS(x) \
145 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
146 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
147 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
148 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
150 #define PIN_LOWEMI_SHIFT 25
151 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
152 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
153 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
154 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
156 #define PIN_GPIOMODE_SHIFT 26
157 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
158 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
159 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
160 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
162 #define PIN_SLEEPMODE_SHIFT 27
163 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
164 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
165 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
166 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
169 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
170 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
171 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
172 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
173 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
174 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
176 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
177 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
178 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
179 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
180 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
182 #define PIN_CFG_DEFAULT (0)
184 #define PIN_CFG(num, alt) \
186 (PIN_NUM(num) | PIN_##alt))
188 #define PIN_CFG_INPUT(num, alt, pull) \
190 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
192 #define PIN_CFG_OUTPUT(num, alt, val) \
194 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
197 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
198 * the "gpio" namespace for generic and cross-machine functions
201 #define GPIO_BLOCK_SHIFT 5
202 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
203 #define NMK_MAX_BANKS DIV_ROUND_UP(512, NMK_GPIO_PER_CHIP)
205 /* Register in the logic block */
206 #define NMK_GPIO_DAT 0x00
207 #define NMK_GPIO_DATS 0x04
208 #define NMK_GPIO_DATC 0x08
209 #define NMK_GPIO_PDIS 0x0c
210 #define NMK_GPIO_DIR 0x10
211 #define NMK_GPIO_DIRS 0x14
212 #define NMK_GPIO_DIRC 0x18
213 #define NMK_GPIO_SLPC 0x1c
214 #define NMK_GPIO_AFSLA 0x20
215 #define NMK_GPIO_AFSLB 0x24
216 #define NMK_GPIO_LOWEMI 0x28
218 #define NMK_GPIO_RIMSC 0x40
219 #define NMK_GPIO_FIMSC 0x44
220 #define NMK_GPIO_IS 0x48
221 #define NMK_GPIO_IC 0x4c
222 #define NMK_GPIO_RWIMSC 0x50
223 #define NMK_GPIO_FWIMSC 0x54
224 #define NMK_GPIO_WKS 0x58
225 /* These appear in DB8540 and later ASICs */
226 #define NMK_GPIO_EDGELEVEL 0x5C
227 #define NMK_GPIO_LEVEL 0x60
230 /* Pull up/down values */
240 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
241 NMK_GPIO_SLPM_NOCHANGE,
242 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
245 struct nmk_gpio_chip {
246 struct gpio_chip chip;
247 struct irq_chip irqchip;
251 unsigned int parent_irq;
252 void (*set_ioforce)(bool enable);
255 /* Keep track of configured edges */
268 * struct nmk_pinctrl - state container for the Nomadik pin controller
269 * @dev: containing device pointer
270 * @pctl: corresponding pin controller device
271 * @soc: SoC data for this specific chip
272 * @prcm_base: PRCM register range virtual base
276 struct pinctrl_dev *pctl;
277 const struct nmk_pinctrl_soc_data *soc;
278 void __iomem *prcm_base;
281 static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
283 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
285 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
287 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
288 unsigned offset, int gpio_mode)
292 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
293 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
294 if (gpio_mode & NMK_GPIO_ALT_A)
295 afunc |= BIT(offset);
296 if (gpio_mode & NMK_GPIO_ALT_B)
297 bfunc |= BIT(offset);
298 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
299 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
302 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
303 unsigned offset, enum nmk_gpio_slpm mode)
307 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
308 if (mode == NMK_GPIO_SLPM_NOCHANGE)
311 slpm &= ~BIT(offset);
312 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
315 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
316 unsigned offset, enum nmk_gpio_pull pull)
320 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
321 if (pull == NMK_GPIO_PULL_NONE) {
323 nmk_chip->pull_up &= ~BIT(offset);
325 pdis &= ~BIT(offset);
328 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
330 if (pull == NMK_GPIO_PULL_UP) {
331 nmk_chip->pull_up |= BIT(offset);
332 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
333 } else if (pull == NMK_GPIO_PULL_DOWN) {
334 nmk_chip->pull_up &= ~BIT(offset);
335 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
339 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
340 unsigned offset, bool lowemi)
342 bool enabled = nmk_chip->lowemi & BIT(offset);
344 if (lowemi == enabled)
348 nmk_chip->lowemi |= BIT(offset);
350 nmk_chip->lowemi &= ~BIT(offset);
352 writel_relaxed(nmk_chip->lowemi,
353 nmk_chip->addr + NMK_GPIO_LOWEMI);
356 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
359 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
362 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
363 unsigned offset, int val)
366 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
368 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
371 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
372 unsigned offset, int val)
374 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
375 __nmk_gpio_set_output(nmk_chip, offset, val);
378 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
379 unsigned offset, int gpio_mode,
382 u32 rwimsc = nmk_chip->rwimsc;
383 u32 fwimsc = nmk_chip->fwimsc;
385 if (glitch && nmk_chip->set_ioforce) {
386 u32 bit = BIT(offset);
388 /* Prevent spurious wakeups */
389 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
390 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
392 nmk_chip->set_ioforce(true);
395 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
397 if (glitch && nmk_chip->set_ioforce) {
398 nmk_chip->set_ioforce(false);
400 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
401 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
406 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
408 u32 falling = nmk_chip->fimsc & BIT(offset);
409 u32 rising = nmk_chip->rimsc & BIT(offset);
410 int gpio = nmk_chip->chip.base + offset;
411 int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
412 struct irq_data *d = irq_get_irq_data(irq);
414 if (!rising && !falling)
417 if (!d || !irqd_irq_disabled(d))
421 nmk_chip->rimsc &= ~BIT(offset);
422 writel_relaxed(nmk_chip->rimsc,
423 nmk_chip->addr + NMK_GPIO_RIMSC);
427 nmk_chip->fimsc &= ~BIT(offset);
428 writel_relaxed(nmk_chip->fimsc,
429 nmk_chip->addr + NMK_GPIO_FIMSC);
432 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
435 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
440 val = ((val & ~mask) | (value & mask));
444 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
445 unsigned offset, unsigned alt_num)
451 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
452 const u16 *gpiocr_regs;
454 if (!npct->prcm_base)
457 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
458 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
463 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
464 if (npct->soc->altcx_pins[i].pin == offset)
467 if (i == npct->soc->npins_altcx) {
468 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
473 pin_desc = npct->soc->altcx_pins + i;
474 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
477 * If alt_num is NULL, just clear current ALTCx selection
478 * to make sure we come back to a pure ALTC selection
481 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
482 if (pin_desc->altcx[i].used == true) {
483 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
484 bit = pin_desc->altcx[i].control_bit;
485 if (readl(npct->prcm_base + reg) & BIT(bit)) {
486 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
488 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
496 alt_index = alt_num - 1;
497 if (pin_desc->altcx[alt_index].used == false) {
499 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
505 * Check if any other ALTCx functions are activated on this pin
506 * and disable it first.
508 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
511 if (pin_desc->altcx[i].used == true) {
512 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
513 bit = pin_desc->altcx[i].control_bit;
514 if (readl(npct->prcm_base + reg) & BIT(bit)) {
515 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
517 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
523 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
524 bit = pin_desc->altcx[alt_index].control_bit;
525 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
526 offset, alt_index+1);
527 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
531 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
532 * - Save SLPM registers
533 * - Set SLPM=0 for the IOs you want to switch and others to 1
534 * - Configure the GPIO registers for the IOs that are being switched
536 * - Modify the AFLSA/B registers for the IOs that are being switched
538 * - Restore SLPM registers
539 * - Any spurious wake up event during switch sequence to be ignored and
542 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
546 for (i = 0; i < NUM_BANKS; i++) {
547 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
548 unsigned int temp = slpm[i];
553 clk_enable(chip->clk);
555 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
556 writel(temp, chip->addr + NMK_GPIO_SLPC);
560 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
564 for (i = 0; i < NUM_BANKS; i++) {
565 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
570 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
572 clk_disable(chip->clk);
576 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
581 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
582 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
583 const u16 *gpiocr_regs;
585 if (!npct->prcm_base)
586 return NMK_GPIO_ALT_C;
588 for (i = 0; i < npct->soc->npins_altcx; i++) {
589 if (npct->soc->altcx_pins[i].pin == gpio)
592 if (i == npct->soc->npins_altcx)
593 return NMK_GPIO_ALT_C;
595 pin_desc = npct->soc->altcx_pins + i;
596 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
597 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
598 if (pin_desc->altcx[i].used == true) {
599 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
600 bit = pin_desc->altcx[i].control_bit;
601 if (readl(npct->prcm_base + reg) & BIT(bit))
602 return NMK_GPIO_ALT_C+i+1;
605 return NMK_GPIO_ALT_C;
610 static void nmk_gpio_irq_ack(struct irq_data *d)
612 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
613 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
615 clk_enable(nmk_chip->clk);
616 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
617 clk_disable(nmk_chip->clk);
620 enum nmk_gpio_irq_type {
625 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
626 int offset, enum nmk_gpio_irq_type which,
634 if (which == NORMAL) {
635 rimscreg = NMK_GPIO_RIMSC;
636 fimscreg = NMK_GPIO_FIMSC;
637 rimscval = &nmk_chip->rimsc;
638 fimscval = &nmk_chip->fimsc;
640 rimscreg = NMK_GPIO_RWIMSC;
641 fimscreg = NMK_GPIO_FWIMSC;
642 rimscval = &nmk_chip->rwimsc;
643 fimscval = &nmk_chip->fwimsc;
646 /* we must individually set/clear the two edges */
647 if (nmk_chip->edge_rising & BIT(offset)) {
649 *rimscval |= BIT(offset);
651 *rimscval &= ~BIT(offset);
652 writel(*rimscval, nmk_chip->addr + rimscreg);
654 if (nmk_chip->edge_falling & BIT(offset)) {
656 *fimscval |= BIT(offset);
658 *fimscval &= ~BIT(offset);
659 writel(*fimscval, nmk_chip->addr + fimscreg);
663 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
667 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
668 * disabled, since setting SLPM to 1 increases power consumption, and
669 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
671 if (nmk_chip->sleepmode && on) {
672 __nmk_gpio_set_slpm(nmk_chip, offset,
673 NMK_GPIO_SLPM_WAKEUP_ENABLE);
676 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
679 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
681 struct nmk_gpio_chip *nmk_chip;
684 nmk_chip = irq_data_get_irq_chip_data(d);
688 clk_enable(nmk_chip->clk);
689 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
690 spin_lock(&nmk_chip->lock);
692 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
694 if (!(nmk_chip->real_wake & BIT(d->hwirq)))
695 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
697 spin_unlock(&nmk_chip->lock);
698 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
699 clk_disable(nmk_chip->clk);
704 static void nmk_gpio_irq_mask(struct irq_data *d)
706 nmk_gpio_irq_maskunmask(d, false);
709 static void nmk_gpio_irq_unmask(struct irq_data *d)
711 nmk_gpio_irq_maskunmask(d, true);
714 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
716 struct nmk_gpio_chip *nmk_chip;
719 nmk_chip = irq_data_get_irq_chip_data(d);
723 clk_enable(nmk_chip->clk);
724 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
725 spin_lock(&nmk_chip->lock);
727 if (irqd_irq_disabled(d))
728 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
731 nmk_chip->real_wake |= BIT(d->hwirq);
733 nmk_chip->real_wake &= ~BIT(d->hwirq);
735 spin_unlock(&nmk_chip->lock);
736 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
737 clk_disable(nmk_chip->clk);
742 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
744 bool enabled = !irqd_irq_disabled(d);
745 bool wake = irqd_is_wakeup_set(d);
746 struct nmk_gpio_chip *nmk_chip;
749 nmk_chip = irq_data_get_irq_chip_data(d);
752 if (type & IRQ_TYPE_LEVEL_HIGH)
754 if (type & IRQ_TYPE_LEVEL_LOW)
757 clk_enable(nmk_chip->clk);
758 spin_lock_irqsave(&nmk_chip->lock, flags);
761 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
764 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
766 nmk_chip->edge_rising &= ~BIT(d->hwirq);
767 if (type & IRQ_TYPE_EDGE_RISING)
768 nmk_chip->edge_rising |= BIT(d->hwirq);
770 nmk_chip->edge_falling &= ~BIT(d->hwirq);
771 if (type & IRQ_TYPE_EDGE_FALLING)
772 nmk_chip->edge_falling |= BIT(d->hwirq);
775 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
778 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
780 spin_unlock_irqrestore(&nmk_chip->lock, flags);
781 clk_disable(nmk_chip->clk);
786 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
788 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
790 clk_enable(nmk_chip->clk);
791 nmk_gpio_irq_unmask(d);
795 static void nmk_gpio_irq_shutdown(struct irq_data *d)
797 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
799 nmk_gpio_irq_mask(d);
800 clk_disable(nmk_chip->clk);
803 static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status)
805 struct irq_chip *host_chip = irq_desc_get_chip(desc);
806 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
808 chained_irq_enter(host_chip, desc);
811 int bit = __ffs(status);
813 generic_handle_irq(irq_find_mapping(chip->irq.domain, bit));
817 chained_irq_exit(host_chip, desc);
820 static void nmk_gpio_irq_handler(struct irq_desc *desc)
822 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
823 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
826 clk_enable(nmk_chip->clk);
827 status = readl(nmk_chip->addr + NMK_GPIO_IS);
828 clk_disable(nmk_chip->clk);
830 __nmk_gpio_irq_handler(desc, status);
835 static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset)
837 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
840 clk_enable(nmk_chip->clk);
842 dir = !(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
844 clk_disable(nmk_chip->clk);
849 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
851 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
853 clk_enable(nmk_chip->clk);
855 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
857 clk_disable(nmk_chip->clk);
862 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
864 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
867 clk_enable(nmk_chip->clk);
869 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
871 clk_disable(nmk_chip->clk);
876 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
879 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
881 clk_enable(nmk_chip->clk);
883 __nmk_gpio_set_output(nmk_chip, offset, val);
885 clk_disable(nmk_chip->clk);
888 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
891 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
893 clk_enable(nmk_chip->clk);
895 __nmk_gpio_make_output(nmk_chip, offset, val);
897 clk_disable(nmk_chip->clk);
902 #ifdef CONFIG_DEBUG_FS
903 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
907 clk_enable(nmk_chip->clk);
909 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
910 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
912 clk_disable(nmk_chip->clk);
914 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
917 #include <linux/seq_file.h>
919 static void nmk_gpio_dbg_show_one(struct seq_file *s,
920 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
921 unsigned offset, unsigned gpio)
923 const char *label = gpiochip_is_requested(chip, offset);
924 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
929 const char *modes[] = {
930 [NMK_GPIO_ALT_GPIO] = "gpio",
931 [NMK_GPIO_ALT_A] = "altA",
932 [NMK_GPIO_ALT_B] = "altB",
933 [NMK_GPIO_ALT_C] = "altC",
934 [NMK_GPIO_ALT_C+1] = "altC1",
935 [NMK_GPIO_ALT_C+2] = "altC2",
936 [NMK_GPIO_ALT_C+3] = "altC3",
937 [NMK_GPIO_ALT_C+4] = "altC4",
939 const char *pulls[] = {
945 clk_enable(nmk_chip->clk);
946 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
947 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
948 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
949 mode = nmk_gpio_get_mode(nmk_chip, offset);
950 if ((mode == NMK_GPIO_ALT_C) && pctldev)
951 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
954 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
957 data_out ? "hi" : "lo",
958 (mode < 0) ? "unknown" : modes[mode]);
960 int irq = chip->to_irq(chip, offset);
961 struct irq_desc *desc = irq_to_desc(irq);
966 pullidx = data_out ? 2 : 1;
968 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
972 (mode < 0) ? "unknown" : modes[mode]);
974 val = nmk_gpio_get_input(chip, offset);
975 seq_printf(s, " VAL %d", val);
978 * This races with request_irq(), set_irq_type(),
979 * and set_irq_wake() ... but those are "rare".
981 if (irq > 0 && desc && desc->action) {
984 if (nmk_chip->edge_rising & BIT(offset))
985 trigger = "edge-rising";
986 else if (nmk_chip->edge_falling & BIT(offset))
987 trigger = "edge-falling";
989 trigger = "edge-undefined";
991 seq_printf(s, " irq-%d %s%s",
993 irqd_is_wakeup_set(&desc->irq_data)
997 clk_disable(nmk_chip->clk);
1000 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1003 unsigned gpio = chip->base;
1005 for (i = 0; i < chip->ngpio; i++, gpio++) {
1006 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1007 seq_printf(s, "\n");
1012 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1013 struct pinctrl_dev *pctldev,
1014 struct gpio_chip *chip,
1015 unsigned offset, unsigned gpio)
1018 #define nmk_gpio_dbg_show NULL
1022 * We will allocate memory for the state container using devm* allocators
1023 * binding to the first device reaching this point, it doesn't matter if
1024 * it is the pin controller or GPIO driver. However we need to use the right
1025 * platform device when looking up resources so pay attention to pdev.
1027 static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
1028 struct platform_device *pdev)
1030 struct nmk_gpio_chip *nmk_chip;
1031 struct platform_device *gpio_pdev;
1032 struct gpio_chip *chip;
1033 struct resource *res;
1038 gpio_pdev = of_find_device_by_node(np);
1040 pr_err("populate \"%pOFn\": device not found\n", np);
1041 return ERR_PTR(-ENODEV);
1043 if (of_property_read_u32(np, "gpio-bank", &id)) {
1044 dev_err(&pdev->dev, "populate: gpio-bank property not found\n");
1045 platform_device_put(gpio_pdev);
1046 return ERR_PTR(-EINVAL);
1049 /* Already populated? */
1050 nmk_chip = nmk_gpio_chips[id];
1052 platform_device_put(gpio_pdev);
1056 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1058 platform_device_put(gpio_pdev);
1059 return ERR_PTR(-ENOMEM);
1062 nmk_chip->bank = id;
1063 chip = &nmk_chip->chip;
1064 chip->base = id * NMK_GPIO_PER_CHIP;
1065 chip->ngpio = NMK_GPIO_PER_CHIP;
1066 chip->label = dev_name(&gpio_pdev->dev);
1067 chip->parent = &gpio_pdev->dev;
1069 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
1070 base = devm_ioremap_resource(&pdev->dev, res);
1072 platform_device_put(gpio_pdev);
1073 return ERR_CAST(base);
1075 nmk_chip->addr = base;
1077 clk = clk_get(&gpio_pdev->dev, NULL);
1079 platform_device_put(gpio_pdev);
1080 return (void *) clk;
1083 nmk_chip->clk = clk;
1085 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1086 nmk_gpio_chips[id] = nmk_chip;
1090 static int nmk_gpio_probe(struct platform_device *dev)
1092 struct device_node *np = dev->dev.of_node;
1093 struct nmk_gpio_chip *nmk_chip;
1094 struct gpio_chip *chip;
1095 struct irq_chip *irqchip;
1096 bool supports_sleepmode;
1100 nmk_chip = nmk_gpio_populate_chip(np, dev);
1101 if (IS_ERR(nmk_chip)) {
1102 dev_err(&dev->dev, "could not populate nmk chip struct\n");
1103 return PTR_ERR(nmk_chip);
1106 supports_sleepmode =
1107 of_property_read_bool(np, "st,supports-sleepmode");
1109 /* Correct platform device ID */
1110 dev->id = nmk_chip->bank;
1112 irq = platform_get_irq(dev, 0);
1117 * The virt address in nmk_chip->addr is in the nomadik register space,
1118 * so we can simply convert the resource address, without remapping
1120 nmk_chip->parent_irq = irq;
1121 nmk_chip->sleepmode = supports_sleepmode;
1122 spin_lock_init(&nmk_chip->lock);
1124 chip = &nmk_chip->chip;
1125 chip->request = gpiochip_generic_request;
1126 chip->free = gpiochip_generic_free;
1127 chip->get_direction = nmk_gpio_get_dir;
1128 chip->direction_input = nmk_gpio_make_input;
1129 chip->get = nmk_gpio_get_input;
1130 chip->direction_output = nmk_gpio_make_output;
1131 chip->set = nmk_gpio_set_output;
1132 chip->dbg_show = nmk_gpio_dbg_show;
1133 chip->can_sleep = false;
1134 chip->owner = THIS_MODULE;
1136 irqchip = &nmk_chip->irqchip;
1137 irqchip->irq_ack = nmk_gpio_irq_ack;
1138 irqchip->irq_mask = nmk_gpio_irq_mask;
1139 irqchip->irq_unmask = nmk_gpio_irq_unmask;
1140 irqchip->irq_set_type = nmk_gpio_irq_set_type;
1141 irqchip->irq_set_wake = nmk_gpio_irq_set_wake;
1142 irqchip->irq_startup = nmk_gpio_irq_startup;
1143 irqchip->irq_shutdown = nmk_gpio_irq_shutdown;
1144 irqchip->flags = IRQCHIP_MASK_ON_SUSPEND;
1145 irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u",
1148 chip->base + chip->ngpio - 1);
1150 clk_enable(nmk_chip->clk);
1151 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1152 clk_disable(nmk_chip->clk);
1155 ret = gpiochip_add_data(chip, nmk_chip);
1159 platform_set_drvdata(dev, nmk_chip);
1162 * Let the generic code handle this edge IRQ, the the chained
1163 * handler will perform the actual work of handling the parent
1166 ret = gpiochip_irqchip_add(chip,
1172 dev_err(&dev->dev, "could not add irqchip\n");
1173 gpiochip_remove(&nmk_chip->chip);
1176 /* Then register the chain on the parent IRQ */
1177 gpiochip_set_chained_irqchip(chip,
1179 nmk_chip->parent_irq,
1180 nmk_gpio_irq_handler);
1182 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1187 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1189 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1191 return npct->soc->ngroups;
1194 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1197 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1199 return npct->soc->groups[selector].name;
1202 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1203 const unsigned **pins,
1206 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1208 *pins = npct->soc->groups[selector].pins;
1209 *num_pins = npct->soc->groups[selector].npins;
1213 static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin)
1216 struct nmk_gpio_chip *nmk_gpio;
1218 for(i = 0; i < NMK_MAX_BANKS; i++) {
1219 nmk_gpio = nmk_gpio_chips[i];
1222 if (pin >= nmk_gpio->chip.base &&
1223 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio)
1229 static struct gpio_chip *find_gc_from_pin(unsigned pin)
1231 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin);
1234 return &nmk_gpio->chip;
1238 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1241 struct gpio_chip *chip = find_gc_from_pin(offset);
1244 seq_printf(s, "invalid pin offset");
1247 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1250 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1251 unsigned *num_maps, const char *group,
1252 const char *function)
1254 if (*num_maps == *reserved_maps)
1257 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1258 (*map)[*num_maps].data.mux.group = group;
1259 (*map)[*num_maps].data.mux.function = function;
1265 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1266 unsigned *reserved_maps,
1267 unsigned *num_maps, const char *group,
1268 unsigned long *configs, unsigned num_configs)
1270 unsigned long *dup_configs;
1272 if (*num_maps == *reserved_maps)
1275 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1280 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1282 (*map)[*num_maps].data.configs.group_or_pin = group;
1283 (*map)[*num_maps].data.configs.configs = dup_configs;
1284 (*map)[*num_maps].data.configs.num_configs = num_configs;
1290 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1291 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1292 .size = ARRAY_SIZE(y), }
1294 static const unsigned long nmk_pin_input_modes[] = {
1300 static const unsigned long nmk_pin_output_modes[] = {
1306 static const unsigned long nmk_pin_sleep_modes[] = {
1307 PIN_SLEEPMODE_DISABLED,
1308 PIN_SLEEPMODE_ENABLED,
1311 static const unsigned long nmk_pin_sleep_input_modes[] = {
1312 PIN_SLPM_INPUT_NOPULL,
1313 PIN_SLPM_INPUT_PULLUP,
1314 PIN_SLPM_INPUT_PULLDOWN,
1318 static const unsigned long nmk_pin_sleep_output_modes[] = {
1319 PIN_SLPM_OUTPUT_LOW,
1320 PIN_SLPM_OUTPUT_HIGH,
1321 PIN_SLPM_DIR_OUTPUT,
1324 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1325 PIN_SLPM_WAKEUP_DISABLE,
1326 PIN_SLPM_WAKEUP_ENABLE,
1329 static const unsigned long nmk_pin_gpio_modes[] = {
1330 PIN_GPIOMODE_DISABLED,
1331 PIN_GPIOMODE_ENABLED,
1334 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1335 PIN_SLPM_PDIS_DISABLED,
1336 PIN_SLPM_PDIS_ENABLED,
1339 struct nmk_cfg_param {
1340 const char *property;
1341 unsigned long config;
1342 const unsigned long *choice;
1346 static const struct nmk_cfg_param nmk_cfg_params[] = {
1347 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1348 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1349 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1350 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1351 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1352 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1353 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1354 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1357 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1361 if (nmk_cfg_params[index].choice == NULL)
1362 *config = nmk_cfg_params[index].config;
1364 /* test if out of range */
1365 if (val < nmk_cfg_params[index].size) {
1366 *config = nmk_cfg_params[index].config |
1367 nmk_cfg_params[index].choice[val];
1373 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1376 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1378 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1379 for (i = 0; i < npct->soc->npins; i++)
1380 if (npct->soc->pins[i].number == pin_number)
1381 return npct->soc->pins[i].name;
1385 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1386 unsigned long *configs)
1388 bool has_config = 0;
1389 unsigned long cfg = 0;
1392 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1393 ret = of_property_read_u32(np,
1394 nmk_cfg_params[i].property, &val);
1395 if (ret != -EINVAL) {
1396 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1406 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1407 struct device_node *np,
1408 struct pinctrl_map **map,
1409 unsigned *reserved_maps,
1413 const char *function = NULL;
1414 unsigned long configs = 0;
1415 bool has_config = 0;
1416 struct property *prop;
1417 struct device_node *np_config;
1419 ret = of_property_read_string(np, "function", &function);
1423 ret = of_property_count_strings(np, "groups");
1427 ret = pinctrl_utils_reserve_map(pctldev, map,
1433 of_property_for_each_string(np, "groups", prop, group) {
1434 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1441 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1442 np_config = of_parse_phandle(np, "ste,config", 0);
1444 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1446 const char *gpio_name;
1449 ret = of_property_count_strings(np, "pins");
1452 ret = pinctrl_utils_reserve_map(pctldev, map,
1458 of_property_for_each_string(np, "pins", prop, pin) {
1459 gpio_name = nmk_find_pin_name(pctldev, pin);
1461 ret = nmk_dt_add_map_configs(map, reserved_maps,
1463 gpio_name, &configs, 1);
1473 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1474 struct device_node *np_config,
1475 struct pinctrl_map **map, unsigned *num_maps)
1477 unsigned reserved_maps;
1478 struct device_node *np;
1485 for_each_child_of_node(np_config, np) {
1486 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1487 &reserved_maps, num_maps);
1489 pinctrl_utils_free_map(pctldev, *map, *num_maps);
1498 static const struct pinctrl_ops nmk_pinctrl_ops = {
1499 .get_groups_count = nmk_get_groups_cnt,
1500 .get_group_name = nmk_get_group_name,
1501 .get_group_pins = nmk_get_group_pins,
1502 .pin_dbg_show = nmk_pin_dbg_show,
1503 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1504 .dt_free_map = pinctrl_utils_free_map,
1507 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1509 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1511 return npct->soc->nfunctions;
1514 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1517 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1519 return npct->soc->functions[function].name;
1522 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1524 const char * const **groups,
1525 unsigned * const num_groups)
1527 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1529 *groups = npct->soc->functions[function].groups;
1530 *num_groups = npct->soc->functions[function].ngroups;
1535 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1538 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1539 const struct nmk_pingroup *g;
1540 static unsigned int slpm[NUM_BANKS];
1541 unsigned long flags = 0;
1546 g = &npct->soc->groups[group];
1548 if (g->altsetting < 0)
1551 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1554 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1555 * we may pass through an undesired state. In this case we take
1558 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1559 * - Save SLPM registers (since we have a shadow register in the
1560 * nmk_chip we're using that as backup)
1561 * - Set SLPM=0 for the IOs you want to switch and others to 1
1562 * - Configure the GPIO registers for the IOs that are being switched
1564 * - Modify the AFLSA/B registers for the IOs that are being switched
1566 * - Restore SLPM registers
1567 * - Any spurious wake up event during switch sequence to be ignored
1570 * We REALLY need to save ALL slpm registers, because the external
1571 * IOFORCE will switch *all* ports to their sleepmode setting to as
1572 * to avoid glitches. (Not just one port!)
1574 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1577 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1579 /* Initially don't put any pins to sleep when switching */
1580 memset(slpm, 0xff, sizeof(slpm));
1583 * Then mask the pins that need to be sleeping now when we're
1584 * switching to the ALT C function.
1586 for (i = 0; i < g->npins; i++)
1587 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1588 nmk_gpio_glitch_slpm_init(slpm);
1591 for (i = 0; i < g->npins; i++) {
1592 struct nmk_gpio_chip *nmk_chip;
1595 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]);
1598 "invalid pin offset %d in group %s at index %d\n",
1599 g->pins[i], g->name, i);
1602 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1604 clk_enable(nmk_chip->clk);
1605 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1607 * If the pin is switching to altfunc, and there was an
1608 * interrupt installed on it which has been lazy disabled,
1609 * actually mask the interrupt to prevent spurious interrupts
1610 * that would occur while the pin is under control of the
1611 * peripheral. Only SKE does this.
1613 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1615 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1616 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1617 clk_disable(nmk_chip->clk);
1620 * Call PRCM GPIOCR config function in case ALTC
1621 * has been selected:
1622 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1624 * - If selection is pure ALTC and previous selection was ALTCx,
1625 * then some bits in PRCM GPIOCR registers must be cleared.
1627 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1628 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1629 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1632 /* When all pins are successfully reconfigured we get here */
1637 nmk_gpio_glitch_slpm_restore(slpm);
1638 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1644 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1645 struct pinctrl_gpio_range *range,
1648 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1649 struct nmk_gpio_chip *nmk_chip;
1650 struct gpio_chip *chip;
1654 dev_err(npct->dev, "invalid range\n");
1658 dev_err(npct->dev, "missing GPIO chip in range\n");
1662 nmk_chip = gpiochip_get_data(chip);
1664 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1666 clk_enable(nmk_chip->clk);
1667 bit = offset % NMK_GPIO_PER_CHIP;
1668 /* There is no glitch when converting any pin to GPIO */
1669 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1670 clk_disable(nmk_chip->clk);
1675 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1676 struct pinctrl_gpio_range *range,
1679 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1681 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1682 /* Set the pin to some default state, GPIO is usually default */
1685 static const struct pinmux_ops nmk_pinmux_ops = {
1686 .get_functions_count = nmk_pmx_get_funcs_cnt,
1687 .get_function_name = nmk_pmx_get_func_name,
1688 .get_function_groups = nmk_pmx_get_func_groups,
1689 .set_mux = nmk_pmx_set,
1690 .gpio_request_enable = nmk_gpio_request_enable,
1691 .gpio_disable_free = nmk_gpio_disable_free,
1695 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1696 unsigned long *config)
1698 /* Not implemented */
1702 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1703 unsigned long *configs, unsigned num_configs)
1705 static const char *pullnames[] = {
1706 [NMK_GPIO_PULL_NONE] = "none",
1707 [NMK_GPIO_PULL_UP] = "up",
1708 [NMK_GPIO_PULL_DOWN] = "down",
1709 [3] /* illegal */ = "??"
1711 static const char *slpmnames[] = {
1712 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1713 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1715 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1716 struct nmk_gpio_chip *nmk_chip;
1719 int pull, slpm, output, val, i;
1720 bool lowemi, gpiomode, sleep;
1722 nmk_chip = find_nmk_gpio_from_pin(pin);
1725 "invalid pin offset %d\n", pin);
1729 for (i = 0; i < num_configs; i++) {
1731 * The pin config contains pin number and altfunction fields,
1732 * here we just ignore that part. It's being handled by the
1733 * framework and pinmux callback respectively.
1735 cfg = (pin_cfg_t) configs[i];
1736 pull = PIN_PULL(cfg);
1737 slpm = PIN_SLPM(cfg);
1738 output = PIN_DIR(cfg);
1740 lowemi = PIN_LOWEMI(cfg);
1741 gpiomode = PIN_GPIOMODE(cfg);
1742 sleep = PIN_SLEEPMODE(cfg);
1745 int slpm_pull = PIN_SLPM_PULL(cfg);
1746 int slpm_output = PIN_SLPM_DIR(cfg);
1747 int slpm_val = PIN_SLPM_VAL(cfg);
1749 /* All pins go into GPIO mode at sleep */
1753 * The SLPM_* values are normal values + 1 to allow zero
1754 * to mean "same as normal".
1757 pull = slpm_pull - 1;
1759 output = slpm_output - 1;
1763 dev_dbg(nmk_chip->chip.parent,
1764 "pin %d: sleep pull %s, dir %s, val %s\n",
1766 slpm_pull ? pullnames[pull] : "same",
1767 slpm_output ? (output ? "output" : "input")
1769 slpm_val ? (val ? "high" : "low") : "same");
1772 dev_dbg(nmk_chip->chip.parent,
1773 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1774 pin, cfg, pullnames[pull], slpmnames[slpm],
1775 output ? "output " : "input",
1776 output ? (val ? "high" : "low") : "",
1777 lowemi ? "on" : "off");
1779 clk_enable(nmk_chip->clk);
1780 bit = pin % NMK_GPIO_PER_CHIP;
1782 /* No glitch when going to GPIO mode */
1783 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1785 __nmk_gpio_make_output(nmk_chip, bit, val);
1787 __nmk_gpio_make_input(nmk_chip, bit);
1788 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1790 /* TODO: isn't this only applicable on output pins? */
1791 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1793 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1794 clk_disable(nmk_chip->clk);
1795 } /* for each config */
1800 static const struct pinconf_ops nmk_pinconf_ops = {
1801 .pin_config_get = nmk_pin_config_get,
1802 .pin_config_set = nmk_pin_config_set,
1805 static struct pinctrl_desc nmk_pinctrl_desc = {
1806 .name = "pinctrl-nomadik",
1807 .pctlops = &nmk_pinctrl_ops,
1808 .pmxops = &nmk_pinmux_ops,
1809 .confops = &nmk_pinconf_ops,
1810 .owner = THIS_MODULE,
1813 static const struct of_device_id nmk_pinctrl_match[] = {
1815 .compatible = "stericsson,stn8815-pinctrl",
1816 .data = (void *)PINCTRL_NMK_STN8815,
1819 .compatible = "stericsson,db8500-pinctrl",
1820 .data = (void *)PINCTRL_NMK_DB8500,
1823 .compatible = "stericsson,db8540-pinctrl",
1824 .data = (void *)PINCTRL_NMK_DB8540,
1829 #ifdef CONFIG_PM_SLEEP
1830 static int nmk_pinctrl_suspend(struct device *dev)
1832 struct nmk_pinctrl *npct;
1834 npct = dev_get_drvdata(dev);
1838 return pinctrl_force_sleep(npct->pctl);
1841 static int nmk_pinctrl_resume(struct device *dev)
1843 struct nmk_pinctrl *npct;
1845 npct = dev_get_drvdata(dev);
1849 return pinctrl_force_default(npct->pctl);
1853 static int nmk_pinctrl_probe(struct platform_device *pdev)
1855 const struct of_device_id *match;
1856 struct device_node *np = pdev->dev.of_node;
1857 struct device_node *prcm_np;
1858 struct nmk_pinctrl *npct;
1859 unsigned int version = 0;
1862 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1866 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1869 version = (unsigned int) match->data;
1871 /* Poke in other ASIC variants here */
1872 if (version == PINCTRL_NMK_STN8815)
1873 nmk_pinctrl_stn8815_init(&npct->soc);
1874 if (version == PINCTRL_NMK_DB8500)
1875 nmk_pinctrl_db8500_init(&npct->soc);
1876 if (version == PINCTRL_NMK_DB8540)
1877 nmk_pinctrl_db8540_init(&npct->soc);
1880 * Since we depend on the GPIO chips to provide clock and register base
1881 * for the pin control operations, make sure that we have these
1882 * populated before we continue. Follow the phandles to instantiate
1883 * them. The GPIO portion of the actual hardware may be probed before
1884 * or after this point: it shouldn't matter as the APIs are orthogonal.
1886 for (i = 0; i < NMK_MAX_BANKS; i++) {
1887 struct device_node *gpio_np;
1888 struct nmk_gpio_chip *nmk_chip;
1890 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i);
1892 dev_info(&pdev->dev,
1893 "populate NMK GPIO %d \"%pOFn\"\n",
1895 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
1896 if (IS_ERR(nmk_chip))
1898 "could not populate nmk chip struct "
1899 "- continue anyway\n");
1900 of_node_put(gpio_np);
1904 prcm_np = of_parse_phandle(np, "prcm", 0);
1906 npct->prcm_base = of_iomap(prcm_np, 0);
1907 if (!npct->prcm_base) {
1908 if (version == PINCTRL_NMK_STN8815) {
1909 dev_info(&pdev->dev,
1911 "assuming no ALT-Cx control is available\n");
1913 dev_err(&pdev->dev, "missing PRCM base address\n");
1918 nmk_pinctrl_desc.pins = npct->soc->pins;
1919 nmk_pinctrl_desc.npins = npct->soc->npins;
1920 npct->dev = &pdev->dev;
1922 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct);
1923 if (IS_ERR(npct->pctl)) {
1924 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1925 return PTR_ERR(npct->pctl);
1928 platform_set_drvdata(pdev, npct);
1929 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1934 static const struct of_device_id nmk_gpio_match[] = {
1935 { .compatible = "st,nomadik-gpio", },
1939 static struct platform_driver nmk_gpio_driver = {
1942 .of_match_table = nmk_gpio_match,
1944 .probe = nmk_gpio_probe,
1947 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
1948 nmk_pinctrl_suspend,
1949 nmk_pinctrl_resume);
1951 static struct platform_driver nmk_pinctrl_driver = {
1953 .name = "pinctrl-nomadik",
1954 .of_match_table = nmk_pinctrl_match,
1955 .pm = &nmk_pinctrl_pm_ops,
1957 .probe = nmk_pinctrl_probe,
1960 static int __init nmk_gpio_init(void)
1962 return platform_driver_register(&nmk_gpio_driver);
1964 subsys_initcall(nmk_gpio_init);
1966 static int __init nmk_pinctrl_init(void)
1968 return platform_driver_register(&nmk_pinctrl_driver);
1970 core_initcall(nmk_pinctrl_init);