2 * Marvell 37xx SoC pinctrl driver
4 * Copyright (C) 2017 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
13 #include <linux/gpio/driver.h>
14 #include <linux/mfd/syscon.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/platform_device.h>
24 #include <linux/property.h>
25 #include <linux/regmap.h>
26 #include <linux/slab.h>
27 #include <linux/string_helpers.h>
29 #include "../pinctrl-utils.h"
32 #define INPUT_VAL 0x10
33 #define OUTPUT_VAL 0x18
34 #define OUTPUT_CTL 0x20
35 #define SELECTION 0x30
39 #define IRQ_STATUS 0x10
43 #define GPIO_PER_REG 32
46 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
47 * The pins of a pinmux groups are composed of one or two groups of contiguous
49 * @name: Name of the pin group, used to lookup the group.
50 * @start_pin: Index of the first pin of the main range of pins belonging to
52 * @npins: Number of pins included in the first range
53 * @reg_mask: Bit mask matching the group in the selection register
54 * @val: Value to write to the registers for a given function
55 * @extra_pin: Index of the first pin of the optional second range of pins
56 * belonging to the group
57 * @extra_npins:Number of pins included in the second optional range
58 * @funcs: A list of pinmux functions that can be selected for this group.
59 * @pins: List of the pins included in the group
61 struct armada_37xx_pin_group {
63 unsigned int start_pin;
67 unsigned int extra_pin;
68 unsigned int extra_npins;
69 const char *funcs[NB_FUNCS];
73 struct armada_37xx_pin_data {
76 struct armada_37xx_pin_group *groups;
80 struct armada_37xx_pmx_func {
86 struct armada_37xx_pm_state {
98 struct armada_37xx_pinctrl {
99 struct regmap *regmap;
101 const struct armada_37xx_pin_data *data;
103 struct gpio_chip gpio_chip;
104 struct irq_chip irq_chip;
106 struct pinctrl_desc pctl;
107 struct pinctrl_dev *pctl_dev;
108 struct armada_37xx_pin_group *groups;
109 unsigned int ngroups;
110 struct armada_37xx_pmx_func *funcs;
112 struct armada_37xx_pm_state pm;
115 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
118 .start_pin = _start, \
122 .funcs = {_func1, _func2} \
125 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
128 .start_pin = _start, \
132 .funcs = {_func1, "gpio"} \
135 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
138 .start_pin = _start, \
141 .val = {_val1, _val2}, \
142 .funcs = {_func1, "gpio"} \
145 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
148 .start_pin = _start, \
151 .val = {_v1, _v2, _v3}, \
152 .funcs = {_f1, _f2, "gpio"} \
155 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
159 .start_pin = _start, \
163 .extra_pin = _start2, \
164 .extra_npins = _nr2, \
165 .funcs = {_f1, _f2} \
168 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
169 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
170 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
171 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
172 PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
174 PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
176 PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
178 PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
180 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
181 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
182 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
183 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
184 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
185 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
186 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
187 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
188 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
189 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
190 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
191 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
192 18, 2, "gpio", "uart"),
195 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
196 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
197 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
198 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
199 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
200 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
201 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
202 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
203 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
204 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
205 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
206 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
207 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
211 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
214 .groups = armada_37xx_nb_groups,
215 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
218 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
221 .groups = armada_37xx_sb_groups,
222 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
225 static inline void armada_37xx_update_reg(unsigned int *reg,
226 unsigned int *offset)
228 /* We never have more than 2 registers */
229 if (*offset >= GPIO_PER_REG) {
230 *offset -= GPIO_PER_REG;
235 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
236 struct armada_37xx_pinctrl *info, int pin, int *grp)
238 while (*grp < info->ngroups) {
239 struct armada_37xx_pin_group *group = &info->groups[*grp];
243 for (j = 0; j < (group->npins + group->extra_npins); j++)
244 if (group->pins[j] == pin)
250 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
251 unsigned int selector, unsigned long *config)
256 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
257 unsigned int selector, unsigned long *configs,
258 unsigned int num_configs)
263 static const struct pinconf_ops armada_37xx_pinconf_ops = {
265 .pin_config_group_get = armada_37xx_pin_config_group_get,
266 .pin_config_group_set = armada_37xx_pin_config_group_set,
269 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
271 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
273 return info->ngroups;
276 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
279 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
281 return info->groups[group].name;
284 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
285 unsigned int selector,
286 const unsigned int **pins,
289 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
291 if (selector >= info->ngroups)
294 *pins = info->groups[selector].pins;
295 *npins = info->groups[selector].npins +
296 info->groups[selector].extra_npins;
301 static const struct pinctrl_ops armada_37xx_pctrl_ops = {
302 .get_groups_count = armada_37xx_get_groups_count,
303 .get_group_name = armada_37xx_get_group_name,
304 .get_group_pins = armada_37xx_get_group_pins,
305 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
306 .dt_free_map = pinctrl_utils_free_map,
310 * Pinmux_ops handling
313 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
315 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
320 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
321 unsigned int selector)
323 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
325 return info->funcs[selector].name;
328 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
329 unsigned int selector,
330 const char * const **groups,
331 unsigned int * const num_groups)
333 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
335 *groups = info->funcs[selector].groups;
336 *num_groups = info->funcs[selector].ngroups;
341 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
343 struct armada_37xx_pin_group *grp)
345 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
346 struct device *dev = info->dev;
347 unsigned int reg = SELECTION;
348 unsigned int mask = grp->reg_mask;
351 dev_dbg(dev, "enable function %s group %s\n", name, grp->name);
353 func = match_string(grp->funcs, NB_FUNCS, name);
357 val = grp->val[func];
359 regmap_update_bits(info->regmap, reg, mask, val);
364 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
365 unsigned int selector,
369 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
370 struct armada_37xx_pin_group *grp = &info->groups[group];
371 const char *name = info->funcs[selector].name;
373 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
376 static inline void armada_37xx_irq_update_reg(unsigned int *reg,
379 int offset = irqd_to_hwirq(d);
381 armada_37xx_update_reg(reg, &offset);
384 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
387 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
388 unsigned int reg = OUTPUT_EN;
391 armada_37xx_update_reg(®, &offset);
394 return regmap_update_bits(info->regmap, reg, mask, 0);
397 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
400 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
401 unsigned int reg = OUTPUT_EN;
402 unsigned int val, mask;
404 armada_37xx_update_reg(®, &offset);
406 regmap_read(info->regmap, reg, &val);
409 return GPIO_LINE_DIRECTION_OUT;
411 return GPIO_LINE_DIRECTION_IN;
414 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
415 unsigned int offset, int value)
417 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
418 unsigned int reg = OUTPUT_EN;
419 unsigned int mask, val, ret;
421 armada_37xx_update_reg(®, &offset);
424 ret = regmap_update_bits(info->regmap, reg, mask, mask);
430 val = value ? mask : 0;
431 regmap_update_bits(info->regmap, reg, mask, val);
436 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
438 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
439 unsigned int reg = INPUT_VAL;
440 unsigned int val, mask;
442 armada_37xx_update_reg(®, &offset);
445 regmap_read(info->regmap, reg, &val);
447 return (val & mask) != 0;
450 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
453 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
454 unsigned int reg = OUTPUT_VAL;
455 unsigned int mask, val;
457 armada_37xx_update_reg(®, &offset);
459 val = value ? mask : 0;
461 regmap_update_bits(info->regmap, reg, mask, val);
464 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
465 struct pinctrl_gpio_range *range,
466 unsigned int offset, bool input)
468 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
469 struct gpio_chip *chip = range->gc;
471 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
472 offset, range->name, offset, input ? "input" : "output");
475 armada_37xx_gpio_direction_input(chip, offset);
477 armada_37xx_gpio_direction_output(chip, offset, 0);
482 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
483 struct pinctrl_gpio_range *range,
486 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
487 struct armada_37xx_pin_group *group;
490 dev_dbg(info->dev, "requesting gpio %d\n", offset);
492 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
493 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
498 static const struct pinmux_ops armada_37xx_pmx_ops = {
499 .get_functions_count = armada_37xx_pmx_get_funcs_count,
500 .get_function_name = armada_37xx_pmx_get_func_name,
501 .get_function_groups = armada_37xx_pmx_get_groups,
502 .set_mux = armada_37xx_pmx_set,
503 .gpio_request_enable = armada_37xx_gpio_request_enable,
504 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
507 static const struct gpio_chip armada_37xx_gpiolib_chip = {
508 .request = gpiochip_generic_request,
509 .free = gpiochip_generic_free,
510 .set = armada_37xx_gpio_set,
511 .get = armada_37xx_gpio_get,
512 .get_direction = armada_37xx_gpio_get_direction,
513 .direction_input = armada_37xx_gpio_direction_input,
514 .direction_output = armada_37xx_gpio_direction_output,
515 .owner = THIS_MODULE,
518 static void armada_37xx_irq_ack(struct irq_data *d)
520 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
521 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
522 u32 reg = IRQ_STATUS;
525 armada_37xx_irq_update_reg(®, d);
526 spin_lock_irqsave(&info->irq_lock, flags);
527 writel(d->mask, info->base + reg);
528 spin_unlock_irqrestore(&info->irq_lock, flags);
531 static void armada_37xx_irq_mask(struct irq_data *d)
533 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
534 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
535 u32 val, reg = IRQ_EN;
538 armada_37xx_irq_update_reg(®, d);
539 spin_lock_irqsave(&info->irq_lock, flags);
540 val = readl(info->base + reg);
541 writel(val & ~d->mask, info->base + reg);
542 spin_unlock_irqrestore(&info->irq_lock, flags);
545 static void armada_37xx_irq_unmask(struct irq_data *d)
547 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
548 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
549 u32 val, reg = IRQ_EN;
552 armada_37xx_irq_update_reg(®, d);
553 spin_lock_irqsave(&info->irq_lock, flags);
554 val = readl(info->base + reg);
555 writel(val | d->mask, info->base + reg);
556 spin_unlock_irqrestore(&info->irq_lock, flags);
559 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
561 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
562 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
563 u32 val, reg = IRQ_WKUP;
566 armada_37xx_irq_update_reg(®, d);
567 spin_lock_irqsave(&info->irq_lock, flags);
568 val = readl(info->base + reg);
570 val |= (BIT(d->hwirq % GPIO_PER_REG));
572 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
573 writel(val, info->base + reg);
574 spin_unlock_irqrestore(&info->irq_lock, flags);
579 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
581 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
582 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
583 u32 val, reg = IRQ_POL;
586 spin_lock_irqsave(&info->irq_lock, flags);
587 armada_37xx_irq_update_reg(®, d);
588 val = readl(info->base + reg);
590 case IRQ_TYPE_EDGE_RISING:
591 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
593 case IRQ_TYPE_EDGE_FALLING:
594 val |= (BIT(d->hwirq % GPIO_PER_REG));
596 case IRQ_TYPE_EDGE_BOTH: {
597 u32 in_val, in_reg = INPUT_VAL;
599 armada_37xx_irq_update_reg(&in_reg, d);
600 regmap_read(info->regmap, in_reg, &in_val);
602 /* Set initial polarity based on current input level. */
603 if (in_val & BIT(d->hwirq % GPIO_PER_REG))
604 val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */
606 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */
610 spin_unlock_irqrestore(&info->irq_lock, flags);
613 writel(val, info->base + reg);
614 spin_unlock_irqrestore(&info->irq_lock, flags);
619 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
622 u32 reg_idx = pin_idx / GPIO_PER_REG;
623 u32 bit_num = pin_idx % GPIO_PER_REG;
627 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
629 spin_lock_irqsave(&info->irq_lock, flags);
630 p = readl(info->base + IRQ_POL + 4 * reg_idx);
631 if ((p ^ l) & (1 << bit_num)) {
633 * For the gpios which are used for both-edge irqs, when their
634 * interrupts happen, their input levels are changed,
635 * yet their interrupt polarities are kept in old values, we
636 * should synchronize their interrupt polarities; for example,
637 * at first a gpio's input level is low and its interrupt
638 * polarity control is "Detect rising edge", then the gpio has
639 * a interrupt , its level turns to high, we should change its
640 * polarity control to "Detect falling edge" correspondingly.
643 writel(p, info->base + IRQ_POL + 4 * reg_idx);
650 spin_unlock_irqrestore(&info->irq_lock, flags);
654 static void armada_37xx_irq_handler(struct irq_desc *desc)
656 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
657 struct irq_chip *chip = irq_desc_get_chip(desc);
658 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
659 struct irq_domain *d = gc->irq.domain;
662 chained_irq_enter(chip, desc);
663 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
667 spin_lock_irqsave(&info->irq_lock, flags);
668 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
669 /* Manage only the interrupt that was enabled */
670 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
671 spin_unlock_irqrestore(&info->irq_lock, flags);
673 u32 hwirq = ffs(status) - 1;
674 u32 virq = irq_find_mapping(d, hwirq +
676 u32 t = irq_get_trigger_type(virq);
678 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
679 /* Swap polarity (race with GPIO line) */
680 if (armada_37xx_edge_both_irq_swap_pol(info,
681 hwirq + i * GPIO_PER_REG)) {
683 * For spurious irq, which gpio level
684 * is not as expected after incoming
685 * edge, just ack the gpio irq.
694 generic_handle_irq(virq);
697 /* Update status in case a new IRQ appears */
698 spin_lock_irqsave(&info->irq_lock, flags);
699 status = readl_relaxed(info->base +
701 /* Manage only the interrupt that was enabled */
702 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
703 spin_unlock_irqrestore(&info->irq_lock, flags);
706 chained_irq_exit(chip, desc);
709 static unsigned int armada_37xx_irq_startup(struct irq_data *d)
712 * The mask field is a "precomputed bitmask for accessing the
713 * chip registers" which was introduced for the generic
714 * irqchip framework. As we don't use this framework, we can
715 * reuse this field for our own usage.
717 d->mask = BIT(d->hwirq % GPIO_PER_REG);
719 armada_37xx_irq_unmask(d);
724 static int armada_37xx_irqchip_register(struct platform_device *pdev,
725 struct armada_37xx_pinctrl *info)
727 struct gpio_chip *gc = &info->gpio_chip;
728 struct irq_chip *irqchip = &info->irq_chip;
729 struct gpio_irq_chip *girq = &gc->irq;
730 struct device_node *np = to_of_node(gc->fwnode);
731 struct device *dev = &pdev->dev;
732 unsigned int i, nr_irq_parent;
734 spin_lock_init(&info->irq_lock);
736 nr_irq_parent = of_irq_count(np);
737 if (!nr_irq_parent) {
738 dev_err(dev, "invalid or no IRQ\n");
742 info->base = devm_platform_ioremap_resource(pdev, 1);
743 if (IS_ERR(info->base))
744 return PTR_ERR(info->base);
746 irqchip->irq_ack = armada_37xx_irq_ack;
747 irqchip->irq_mask = armada_37xx_irq_mask;
748 irqchip->irq_unmask = armada_37xx_irq_unmask;
749 irqchip->irq_set_wake = armada_37xx_irq_set_wake;
750 irqchip->irq_set_type = armada_37xx_irq_set_type;
751 irqchip->irq_startup = armada_37xx_irq_startup;
752 irqchip->name = info->data->name;
753 girq->chip = irqchip;
754 girq->parent_handler = armada_37xx_irq_handler;
756 * Many interrupts are connected to the parent interrupt
757 * controller. But we do not take advantage of this and use
758 * the chained irq with all of them.
760 girq->num_parents = nr_irq_parent;
761 girq->parents = devm_kcalloc(dev, nr_irq_parent, sizeof(*girq->parents), GFP_KERNEL);
764 for (i = 0; i < nr_irq_parent; i++) {
765 int irq = irq_of_parse_and_map(np, i);
769 girq->parents[i] = irq;
771 girq->default_type = IRQ_TYPE_NONE;
772 girq->handler = handle_edge_irq;
777 static int armada_37xx_gpiochip_register(struct platform_device *pdev,
778 struct armada_37xx_pinctrl *info)
780 struct device *dev = &pdev->dev;
781 struct fwnode_handle *fwnode;
782 struct gpio_chip *gc;
785 fwnode = gpiochip_node_get_first(dev);
789 info->gpio_chip = armada_37xx_gpiolib_chip;
791 gc = &info->gpio_chip;
792 gc->ngpio = info->data->nr_pins;
796 gc->label = info->data->name;
798 ret = armada_37xx_irqchip_register(pdev, info);
802 return devm_gpiochip_add_data(dev, gc, info);
806 * armada_37xx_add_function() - Add a new function to the list
807 * @funcs: array of function to add the new one
808 * @funcsize: size of the remaining space for the function
809 * @name: name of the function to add
811 * If it is a new function then create it by adding its name else
812 * increment the number of group associated to this function.
814 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
815 int *funcsize, const char *name)
822 while (funcs->ngroups) {
823 /* function already there */
824 if (strcmp(funcs->name, name) == 0) {
833 /* append new unique function */
842 * armada_37xx_fill_group() - complete the group array
843 * @info: info driver instance
845 * Based on the data available from the armada_37xx_pin_group array
846 * completes the last member of the struct for each function: the list
847 * of the groups associated to this function.
850 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
852 int n, num = 0, funcsize = info->data->nr_pins;
853 struct device *dev = info->dev;
855 for (n = 0; n < info->ngroups; n++) {
856 struct armada_37xx_pin_group *grp = &info->groups[n];
859 grp->pins = devm_kcalloc(dev, grp->npins + grp->extra_npins,
865 for (i = 0; i < grp->npins; i++)
866 grp->pins[i] = grp->start_pin + i;
868 for (j = 0; j < grp->extra_npins; j++)
869 grp->pins[i+j] = grp->extra_pin + j;
871 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
873 /* check for unique functions and count groups */
874 ret = armada_37xx_add_function(info->funcs, &funcsize,
876 if (ret == -EOVERFLOW)
877 dev_err(dev, "More functions than pins(%d)\n",
878 info->data->nr_pins);
891 * armada_37xx_fill_func() - complete the funcs array
892 * @info: info driver instance
894 * Based on the data available from the armada_37xx_pin_group array
895 * completes the last two member of the struct for each group:
896 * - the list of the pins included in the group
897 * - the list of pinmux functions that can be selected for this group
900 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
902 struct armada_37xx_pmx_func *funcs = info->funcs;
903 struct device *dev = info->dev;
906 for (n = 0; n < info->nfuncs; n++) {
907 const char *name = funcs[n].name;
911 funcs[n].groups = devm_kcalloc(dev, funcs[n].ngroups,
912 sizeof(*(funcs[n].groups)),
914 if (!funcs[n].groups)
917 groups = funcs[n].groups;
919 for (g = 0; g < info->ngroups; g++) {
920 struct armada_37xx_pin_group *gp = &info->groups[g];
923 f = match_string(gp->funcs, NB_FUNCS, name);
934 static int armada_37xx_pinctrl_register(struct platform_device *pdev,
935 struct armada_37xx_pinctrl *info)
937 const struct armada_37xx_pin_data *pin_data = info->data;
938 struct pinctrl_desc *ctrldesc = &info->pctl;
939 struct pinctrl_pin_desc *pindesc, *pdesc;
940 struct device *dev = &pdev->dev;
944 info->groups = pin_data->groups;
945 info->ngroups = pin_data->ngroups;
947 ctrldesc->name = "armada_37xx-pinctrl";
948 ctrldesc->owner = THIS_MODULE;
949 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
950 ctrldesc->pmxops = &armada_37xx_pmx_ops;
951 ctrldesc->confops = &armada_37xx_pinconf_ops;
953 pindesc = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*pindesc), GFP_KERNEL);
957 ctrldesc->pins = pindesc;
958 ctrldesc->npins = pin_data->nr_pins;
960 pin_names = devm_kasprintf_strarray(dev, pin_data->name, pin_data->nr_pins);
961 if (IS_ERR(pin_names))
962 return PTR_ERR(pin_names);
965 for (pin = 0; pin < pin_data->nr_pins; pin++) {
967 pdesc->name = pin_names[pin];
972 * we allocate functions for number of pins and hope there are
973 * fewer unique functions than pins available
975 info->funcs = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*info->funcs), GFP_KERNEL);
979 ret = armada_37xx_fill_group(info);
983 ret = armada_37xx_fill_func(info);
987 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
988 if (IS_ERR(info->pctl_dev))
989 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
994 #if defined(CONFIG_PM)
995 static int armada_3700_pinctrl_suspend(struct device *dev)
997 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
999 /* Save GPIO state */
1000 regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
1001 regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
1002 regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
1003 regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
1004 &info->pm.out_val_h);
1006 info->pm.irq_en_l = readl(info->base + IRQ_EN);
1007 info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
1008 info->pm.irq_pol_l = readl(info->base + IRQ_POL);
1009 info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
1011 /* Save pinctrl state */
1012 regmap_read(info->regmap, SELECTION, &info->pm.selection);
1017 static int armada_3700_pinctrl_resume(struct device *dev)
1019 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1020 struct gpio_chip *gc;
1021 struct irq_domain *d;
1024 /* Restore GPIO state */
1025 regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
1026 regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
1028 regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
1029 regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
1030 info->pm.out_val_h);
1033 * Input levels may change during suspend, which is not monitored at
1034 * that time. GPIOs used for both-edge IRQs may not be synchronized
1035 * anymore with their polarities (rising/falling edge) and must be
1036 * re-configured manually.
1038 gc = &info->gpio_chip;
1040 for (i = 0; i < gc->ngpio; i++) {
1041 u32 irq_bit = BIT(i % GPIO_PER_REG);
1042 u32 mask, *irq_pol, input_reg, virq, type, level;
1044 if (i < GPIO_PER_REG) {
1045 mask = info->pm.irq_en_l;
1046 irq_pol = &info->pm.irq_pol_l;
1047 input_reg = INPUT_VAL;
1049 mask = info->pm.irq_en_h;
1050 irq_pol = &info->pm.irq_pol_h;
1051 input_reg = INPUT_VAL + sizeof(u32);
1054 if (!(mask & irq_bit))
1057 virq = irq_find_mapping(d, i);
1058 type = irq_get_trigger_type(virq);
1061 * Synchronize level and polarity for both-edge irqs:
1062 * - a high input level expects a falling edge,
1063 * - a low input level exepects a rising edge.
1065 if ((type & IRQ_TYPE_SENSE_MASK) ==
1066 IRQ_TYPE_EDGE_BOTH) {
1067 regmap_read(info->regmap, input_reg, &level);
1068 if ((*irq_pol ^ level) & irq_bit)
1069 *irq_pol ^= irq_bit;
1073 writel(info->pm.irq_en_l, info->base + IRQ_EN);
1074 writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
1075 writel(info->pm.irq_pol_l, info->base + IRQ_POL);
1076 writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
1078 /* Restore pinctrl state */
1079 regmap_write(info->regmap, SELECTION, info->pm.selection);
1085 * Since pinctrl is an infrastructure module, its resume should be issued prior
1086 * to other IO drivers.
1088 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
1089 .suspend_noirq = armada_3700_pinctrl_suspend,
1090 .resume_noirq = armada_3700_pinctrl_resume,
1093 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
1095 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL
1096 #endif /* CONFIG_PM */
1098 static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
1100 .compatible = "marvell,armada3710-sb-pinctrl",
1101 .data = &armada_37xx_pin_sb,
1104 .compatible = "marvell,armada3710-nb-pinctrl",
1105 .data = &armada_37xx_pin_nb,
1110 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
1112 struct armada_37xx_pinctrl *info;
1113 struct device *dev = &pdev->dev;
1114 struct device_node *np = dev->of_node;
1115 struct regmap *regmap;
1118 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1124 regmap = syscon_node_to_regmap(np);
1126 return dev_err_probe(dev, PTR_ERR(regmap), "cannot get regmap\n");
1127 info->regmap = regmap;
1129 info->data = of_device_get_match_data(dev);
1131 ret = armada_37xx_pinctrl_register(pdev, info);
1135 ret = armada_37xx_gpiochip_register(pdev, info);
1139 platform_set_drvdata(pdev, info);
1144 static struct platform_driver armada_37xx_pinctrl_driver = {
1146 .name = "armada-37xx-pinctrl",
1147 .of_match_table = armada_37xx_pinctrl_of_match,
1148 .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS,
1152 builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1153 armada_37xx_pinctrl_probe);