1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
4 * bindings for MediaTek SoC.
6 * Copyright (C) 2018 MediaTek Inc.
7 * Author: Sean Wang <sean.wang@mediatek.com>
8 * Zhiyong Tao <zhiyong.tao@mediatek.com>
9 * Hongzhou.Yang <hongzhou.yang@mediatek.com>
12 #include <linux/gpio/driver.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include "pinctrl-paris.h"
16 #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
18 /* Custom pinconf parameters */
19 #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
20 #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
21 #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
22 #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
23 #define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
25 static const struct pinconf_generic_params mtk_custom_bindings[] = {
26 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
27 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
28 {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
29 {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
30 {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
33 #ifdef CONFIG_DEBUG_FS
34 static const struct pin_config_item mtk_conf_items[] = {
35 PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
36 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
37 PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
38 PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
39 PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
43 static const char * const mtk_gpio_functions[] = {
44 "func0", "func1", "func2", "func3",
45 "func4", "func5", "func6", "func7",
46 "func8", "func9", "func10", "func11",
47 "func12", "func13", "func14", "func15",
50 static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
51 struct pinctrl_gpio_range *range,
54 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
55 const struct mtk_pin_desc *desc;
57 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
59 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
63 static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
64 struct pinctrl_gpio_range *range,
65 unsigned int pin, bool input)
67 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
68 const struct mtk_pin_desc *desc;
70 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
72 /* hardware would take 0 as input direction */
73 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
76 static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
77 unsigned int pin, unsigned long *config)
79 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
80 u32 param = pinconf_to_config_param(*config);
81 int pullup, err, reg, ret = 1;
82 const struct mtk_pin_desc *desc;
84 if (pin >= hw->soc->npins) {
88 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
91 case PIN_CONFIG_BIAS_DISABLE:
92 case PIN_CONFIG_BIAS_PULL_UP:
93 case PIN_CONFIG_BIAS_PULL_DOWN:
94 if (hw->soc->bias_get_combo) {
95 err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
98 if (param == PIN_CONFIG_BIAS_DISABLE) {
99 if (ret == MTK_PUPD_SET_R1R0_00)
101 } else if (param == PIN_CONFIG_BIAS_PULL_UP) {
102 /* When desire to get pull-up value, return
103 * error if current setting is pull-down
107 } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
108 /* When desire to get pull-down value, return
109 * error if current setting is pull-up
118 case PIN_CONFIG_SLEW_RATE:
119 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &ret);
121 case PIN_CONFIG_INPUT_ENABLE:
122 case PIN_CONFIG_OUTPUT_ENABLE:
123 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
126 /* CONFIG Current direction return value
127 * ------------- ----------------- ----------------------
128 * OUTPUT_ENABLE output 1 (= HW value)
129 * input 0 (= HW value)
130 * INPUT_ENABLE output 0 (= reverse HW value)
131 * input 1 (= reverse HW value)
133 if (param == PIN_CONFIG_INPUT_ENABLE)
137 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
138 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
141 /* return error when in output mode
142 * because schmitt trigger only work in input mode
149 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
152 case PIN_CONFIG_DRIVE_STRENGTH:
153 if (hw->soc->drive_get)
154 err = hw->soc->drive_get(hw, desc, &ret);
158 case MTK_PIN_CONFIG_TDSEL:
159 case MTK_PIN_CONFIG_RDSEL:
160 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
161 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
162 err = mtk_hw_get_value(hw, desc, reg, &ret);
164 case MTK_PIN_CONFIG_PU_ADV:
165 case MTK_PIN_CONFIG_PD_ADV:
166 if (hw->soc->adv_pull_get) {
167 pullup = param == MTK_PIN_CONFIG_PU_ADV;
168 err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
172 case MTK_PIN_CONFIG_DRV_ADV:
173 if (hw->soc->adv_drive_get)
174 err = hw->soc->adv_drive_get(hw, desc, &ret);
184 *config = pinconf_to_config_packed(param, ret);
189 static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
190 enum pin_config_param param,
191 enum pin_config_param arg)
193 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
194 const struct mtk_pin_desc *desc;
198 if (pin >= hw->soc->npins) {
202 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
204 switch ((u32)param) {
205 case PIN_CONFIG_BIAS_DISABLE:
206 if (hw->soc->bias_set_combo)
207 err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
211 case PIN_CONFIG_BIAS_PULL_UP:
212 if (hw->soc->bias_set_combo)
213 err = hw->soc->bias_set_combo(hw, desc, 1, arg);
217 case PIN_CONFIG_BIAS_PULL_DOWN:
218 if (hw->soc->bias_set_combo)
219 err = hw->soc->bias_set_combo(hw, desc, 0, arg);
223 case PIN_CONFIG_OUTPUT_ENABLE:
224 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
226 /* Keep set direction to consider the case that a GPIO pin
227 * does not have SMT control
229 if (err != -ENOTSUPP)
232 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
235 case PIN_CONFIG_INPUT_ENABLE:
236 /* regard all non-zero value as enable */
237 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);
241 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
244 case PIN_CONFIG_SLEW_RATE:
245 /* regard all non-zero value as enable */
246 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg);
248 case PIN_CONFIG_OUTPUT:
249 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
254 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
257 case PIN_CONFIG_INPUT_SCHMITT:
258 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
259 /* arg = 1: Input mode & SMT enable ;
260 * arg = 0: Output mode & SMT disable
262 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);
266 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);
268 case PIN_CONFIG_DRIVE_STRENGTH:
269 if (hw->soc->drive_set)
270 err = hw->soc->drive_set(hw, desc, arg);
274 case MTK_PIN_CONFIG_TDSEL:
275 case MTK_PIN_CONFIG_RDSEL:
276 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
277 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
278 err = mtk_hw_set_value(hw, desc, reg, arg);
280 case MTK_PIN_CONFIG_PU_ADV:
281 case MTK_PIN_CONFIG_PD_ADV:
282 if (hw->soc->adv_pull_set) {
285 pullup = param == MTK_PIN_CONFIG_PU_ADV;
286 err = hw->soc->adv_pull_set(hw, desc, pullup,
291 case MTK_PIN_CONFIG_DRV_ADV:
292 if (hw->soc->adv_drive_set)
293 err = hw->soc->adv_drive_set(hw, desc, arg);
305 static struct mtk_pinctrl_group *
306 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
310 for (i = 0; i < hw->soc->ngrps; i++) {
311 struct mtk_pinctrl_group *grp = hw->groups + i;
320 static const struct mtk_func_desc *
321 mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
323 const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
324 const struct mtk_func_desc *func = pin->funcs;
326 while (func && func->name) {
327 if (func->muxval == fnum)
335 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
340 for (i = 0; i < hw->soc->npins; i++) {
341 const struct mtk_pin_desc *pin = hw->soc->pins + i;
343 if (pin->number == pin_num) {
344 const struct mtk_func_desc *func = pin->funcs;
346 while (func && func->name) {
347 if (func->muxval == fnum)
359 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
361 struct mtk_pinctrl_group *grp,
362 struct pinctrl_map **map,
363 unsigned *reserved_maps,
368 if (*num_maps == *reserved_maps)
371 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
372 (*map)[*num_maps].data.mux.group = grp->name;
374 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
376 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
381 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
387 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
388 struct device_node *node,
389 struct pinctrl_map **map,
390 unsigned *reserved_maps,
393 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
394 int num_pins, num_funcs, maps_per_pin, i, err;
395 struct mtk_pinctrl_group *grp;
396 unsigned int num_configs;
397 bool has_config = false;
398 unsigned long *configs;
399 u32 pinfunc, pin, func;
400 struct property *pins;
401 unsigned reserve = 0;
403 pins = of_find_property(node, "pinmux", NULL);
405 dev_err(hw->dev, "missing pins property in node %pOFn .\n",
410 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
418 num_pins = pins->length / sizeof(u32);
419 num_funcs = num_pins;
423 if (has_config && num_pins >= 1)
426 if (!num_pins || !maps_per_pin) {
431 reserve = num_pins * maps_per_pin;
433 err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
438 for (i = 0; i < num_pins; i++) {
439 err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
443 pin = MTK_GET_PIN_NO(pinfunc);
444 func = MTK_GET_PIN_FUNC(pinfunc);
446 if (pin >= hw->soc->npins ||
447 func >= ARRAY_SIZE(mtk_gpio_functions)) {
448 dev_err(hw->dev, "invalid pins value.\n");
453 grp = mtk_pctrl_find_group_by_pin(hw, pin);
455 dev_err(hw->dev, "unable to match pin %d to group\n",
461 err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
462 reserved_maps, num_maps);
467 err = pinctrl_utils_add_map_configs(pctldev, map,
473 PIN_MAP_TYPE_CONFIGS_GROUP);
486 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
487 struct device_node *np_config,
488 struct pinctrl_map **map,
491 struct device_node *np;
492 unsigned reserved_maps;
499 for_each_child_of_node(np_config, np) {
500 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
504 pinctrl_utils_free_map(pctldev, *map, *num_maps);
513 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
515 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
517 return hw->soc->ngrps;
520 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
523 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
525 return hw->groups[group].name;
528 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
529 unsigned group, const unsigned **pins,
532 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
534 *pins = (unsigned *)&hw->groups[group].pin;
540 static int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int field)
542 const struct mtk_pin_desc *desc;
545 if (gpio >= hw->soc->npins)
548 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
550 err = mtk_hw_get_value(hw, desc, field, &value);
557 #define mtk_pctrl_get_pinmux(hw, gpio) \
558 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_MODE)
560 #define mtk_pctrl_get_direction(hw, gpio) \
561 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DIR)
563 #define mtk_pctrl_get_out(hw, gpio) \
564 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DO)
566 #define mtk_pctrl_get_in(hw, gpio) \
567 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DI)
569 #define mtk_pctrl_get_smt(hw, gpio) \
570 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_SMT)
572 #define mtk_pctrl_get_ies(hw, gpio) \
573 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_IES)
575 #define mtk_pctrl_get_driving(hw, gpio) \
576 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DRV)
578 ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
579 unsigned int gpio, char *buf, unsigned int bufLen)
581 int pinmux, pullup, pullen, len = 0, r1 = -1, r0 = -1;
582 const struct mtk_pin_desc *desc;
584 if (gpio >= hw->soc->npins)
587 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
588 pinmux = mtk_pctrl_get_pinmux(hw, gpio);
589 if (pinmux >= hw->soc->nfuncs)
590 pinmux -= hw->soc->nfuncs;
592 mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
593 if (pullen == MTK_PUPD_SET_R1R0_00) {
597 } else if (pullen == MTK_PUPD_SET_R1R0_01) {
601 } else if (pullen == MTK_PUPD_SET_R1R0_10) {
605 } else if (pullen == MTK_PUPD_SET_R1R0_11) {
609 } else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE) {
612 len += scnprintf(buf + len, bufLen - len,
613 "%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d",
616 mtk_pctrl_get_direction(hw, gpio),
617 mtk_pctrl_get_out(hw, gpio),
618 mtk_pctrl_get_in(hw, gpio),
619 mtk_pctrl_get_driving(hw, gpio),
620 mtk_pctrl_get_smt(hw, gpio),
621 mtk_pctrl_get_ies(hw, gpio),
626 len += scnprintf(buf + len, bufLen - len, " (%1d %1d)\n",
629 len += scnprintf(buf + len, bufLen - len, "\n");
635 #define PIN_DBG_BUF_SZ 96
636 static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
639 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
640 char buf[PIN_DBG_BUF_SZ];
642 (void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ);
644 seq_printf(s, "%s", buf);
647 static const struct pinctrl_ops mtk_pctlops = {
648 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
649 .dt_free_map = pinctrl_utils_free_map,
650 .get_groups_count = mtk_pctrl_get_groups_count,
651 .get_group_name = mtk_pctrl_get_group_name,
652 .get_group_pins = mtk_pctrl_get_group_pins,
653 .pin_dbg_show = mtk_pctrl_dbg_show,
656 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
658 return ARRAY_SIZE(mtk_gpio_functions);
661 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
664 return mtk_gpio_functions[selector];
667 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
669 const char * const **groups,
670 unsigned * const num_groups)
672 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
674 *groups = hw->grp_names;
675 *num_groups = hw->soc->ngrps;
680 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
684 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
685 struct mtk_pinctrl_group *grp = hw->groups + group;
686 const struct mtk_func_desc *desc_func;
687 const struct mtk_pin_desc *desc;
690 ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
692 dev_err(hw->dev, "invalid function %d on group %d .\n",
697 desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
701 desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
702 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
707 static const struct pinmux_ops mtk_pmxops = {
708 .get_functions_count = mtk_pmx_get_funcs_cnt,
709 .get_function_name = mtk_pmx_get_func_name,
710 .get_function_groups = mtk_pmx_get_func_groups,
711 .set_mux = mtk_pmx_set_mux,
712 .gpio_set_direction = mtk_pinmux_gpio_set_direction,
713 .gpio_request_enable = mtk_pinmux_gpio_request_enable,
716 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
717 unsigned long *config)
719 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
721 *config = hw->groups[group].config;
726 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
727 unsigned long *configs, unsigned num_configs)
729 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
730 struct mtk_pinctrl_group *grp = &hw->groups[group];
733 for (i = 0; i < num_configs; i++) {
734 ret = mtk_pinconf_set(pctldev, grp->pin,
735 pinconf_to_config_param(configs[i]),
736 pinconf_to_config_argument(configs[i]));
740 grp->config = configs[i];
746 static const struct pinconf_ops mtk_confops = {
747 .pin_config_get = mtk_pinconf_get,
748 .pin_config_group_get = mtk_pconf_group_get,
749 .pin_config_group_set = mtk_pconf_group_set,
753 static struct pinctrl_desc mtk_desc = {
754 .name = PINCTRL_PINCTRL_DEV,
755 .pctlops = &mtk_pctlops,
756 .pmxops = &mtk_pmxops,
757 .confops = &mtk_confops,
758 .owner = THIS_MODULE,
761 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
763 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
764 const struct mtk_pin_desc *desc;
767 if (gpio >= hw->soc->npins)
770 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
772 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
777 return GPIO_LINE_DIRECTION_OUT;
779 return GPIO_LINE_DIRECTION_IN;
782 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
784 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
785 const struct mtk_pin_desc *desc;
788 if (gpio >= hw->soc->npins)
791 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
793 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
800 static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
802 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
803 const struct mtk_pin_desc *desc;
805 if (gpio >= hw->soc->npins)
808 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
810 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
813 static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
815 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
817 if (gpio >= hw->soc->npins)
820 return pinctrl_gpio_direction_input(chip->base + gpio);
823 static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
826 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
828 if (gpio >= hw->soc->npins)
831 mtk_gpio_set(chip, gpio, value);
833 return pinctrl_gpio_direction_output(chip->base + gpio);
836 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
838 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
839 const struct mtk_pin_desc *desc;
844 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
846 if (desc->eint.eint_n == EINT_NA)
849 return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
852 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
853 unsigned long config)
855 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
856 const struct mtk_pin_desc *desc;
859 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
862 pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
863 desc->eint.eint_n == EINT_NA)
866 debounce = pinconf_to_config_argument(config);
868 return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
871 static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
873 struct gpio_chip *chip = &hw->chip;
876 chip->label = PINCTRL_PINCTRL_DEV;
877 chip->parent = hw->dev;
878 chip->request = gpiochip_generic_request;
879 chip->free = gpiochip_generic_free;
880 chip->get_direction = mtk_gpio_get_direction;
881 chip->direction_input = mtk_gpio_direction_input;
882 chip->direction_output = mtk_gpio_direction_output;
883 chip->get = mtk_gpio_get;
884 chip->set = mtk_gpio_set;
885 chip->to_irq = mtk_gpio_to_irq,
886 chip->set_config = mtk_gpio_set_config,
888 chip->ngpio = hw->soc->npins;
890 chip->of_gpio_n_cells = 2;
892 ret = gpiochip_add_data(chip, hw);
899 static int mtk_pctrl_build_state(struct platform_device *pdev)
901 struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
904 /* Allocate groups */
905 hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
906 sizeof(*hw->groups), GFP_KERNEL);
910 /* We assume that one pin is one group, use pin name as group name. */
911 hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
912 sizeof(*hw->grp_names), GFP_KERNEL);
916 for (i = 0; i < hw->soc->npins; i++) {
917 const struct mtk_pin_desc *pin = hw->soc->pins + i;
918 struct mtk_pinctrl_group *group = hw->groups + i;
920 group->name = pin->name;
921 group->pin = pin->number;
923 hw->grp_names[i] = pin->name;
929 int mtk_paris_pinctrl_probe(struct platform_device *pdev,
930 const struct mtk_pin_soc *soc)
932 struct pinctrl_pin_desc *pins;
933 struct mtk_pinctrl *hw;
934 struct resource *res;
937 hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
941 platform_set_drvdata(pdev, hw);
943 hw->dev = &pdev->dev;
945 if (!hw->soc->nbase_names) {
947 "SoC should be assigned at least one register base\n");
951 hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
952 sizeof(*hw->base), GFP_KERNEL);
956 for (i = 0; i < hw->soc->nbase_names; i++) {
957 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
958 hw->soc->base_names[i]);
960 dev_err(&pdev->dev, "missing IO resource\n");
964 hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
965 if (IS_ERR(hw->base[i]))
966 return PTR_ERR(hw->base[i]);
969 hw->nbase = hw->soc->nbase_names;
971 err = mtk_pctrl_build_state(pdev);
973 dev_err(&pdev->dev, "build state failed: %d\n", err);
977 /* Copy from internal struct mtk_pin_desc to register to the core */
978 pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
983 for (i = 0; i < hw->soc->npins; i++) {
984 pins[i].number = hw->soc->pins[i].number;
985 pins[i].name = hw->soc->pins[i].name;
988 /* Setup pins descriptions per SoC types */
989 mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
990 mtk_desc.npins = hw->soc->npins;
991 mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
992 mtk_desc.custom_params = mtk_custom_bindings;
993 #ifdef CONFIG_DEBUG_FS
994 mtk_desc.custom_conf_items = mtk_conf_items;
997 err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
1002 err = pinctrl_enable(hw->pctrl);
1006 err = mtk_build_eint(hw, pdev);
1008 dev_warn(&pdev->dev,
1009 "Failed to add EINT, but pinctrl still can work\n");
1011 /* Build gpiochip should be after pinctrl_enable is done */
1012 err = mtk_build_gpiochip(hw, pdev->dev.of_node);
1014 dev_err(&pdev->dev, "Failed to add gpio_chip\n");
1018 platform_set_drvdata(pdev, hw);
1023 static int mtk_paris_pinctrl_suspend(struct device *device)
1025 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1027 return mtk_eint_do_suspend(pctl->eint);
1030 static int mtk_paris_pinctrl_resume(struct device *device)
1032 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1034 return mtk_eint_do_resume(pctl->eint);
1037 const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = {
1038 .suspend_noirq = mtk_paris_pinctrl_suspend,
1039 .resume_noirq = mtk_paris_pinctrl_resume,