1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 MediaTek Inc.
5 * Author: Sean Wang <sean.wang@mediatek.com>
9 #include <dt-bindings/pinctrl/mt65xx.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/platform_device.h>
15 #include <linux/of_irq.h>
18 #include "pinctrl-mtk-common-v2.h"
21 * struct mtk_drive_desc - the structure that holds the information
22 * of the driving current
23 * @min: the minimum current of this group
24 * @max: the maximum current of this group
25 * @step: the step current of this group
26 * @scal: the weight factor
28 * formula: output = ((input) / step - 1) * scal
30 struct mtk_drive_desc {
37 /* The groups of drive strength */
38 static const struct mtk_drive_desc mtk_drive[] = {
39 [DRV_GRP0] = { 4, 16, 4, 1 },
40 [DRV_GRP1] = { 4, 16, 4, 2 },
41 [DRV_GRP2] = { 2, 8, 2, 1 },
42 [DRV_GRP3] = { 2, 8, 2, 2 },
43 [DRV_GRP4] = { 2, 16, 2, 1 },
46 static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val)
48 writel_relaxed(val, pctl->base[i] + reg);
51 static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
53 return readl_relaxed(pctl->base[i] + reg);
56 void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
60 val = mtk_r32(pctl, i, reg);
63 mtk_w32(pctl, i, reg, val);
66 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
67 const struct mtk_pin_desc *desc,
68 int field, struct mtk_pin_field *pfd)
70 const struct mtk_pin_field_calc *c;
71 const struct mtk_pin_reg_calc *rc;
72 int start = 0, end, check;
76 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
77 rc = &hw->soc->reg_cal[field];
80 "Not support field %d for this soc\n", field);
84 end = rc->nranges - 1;
86 while (start <= end) {
87 check = (start + end) >> 1;
88 if (desc->number >= rc->range[check].s_pin
89 && desc->number <= rc->range[check].e_pin) {
92 } else if (start == end)
94 else if (desc->number < rc->range[check].s_pin)
101 dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n",
102 field, desc->number, desc->name);
106 c = rc->range + check;
108 if (c->i_base > hw->nbase - 1) {
110 "Invalid base for field %d for pin = %d (%s)\n",
111 field, desc->number, desc->name);
115 /* Calculated bits as the overall offset the pin is located at,
116 * if c->fixed is held, that determines the all the pins in the
117 * range use the same field with the s_pin.
119 bits = c->fixed ? c->s_bit : c->s_bit +
120 (desc->number - c->s_pin) * (c->x_bits);
122 /* Fill pfd from bits. For example 32-bit register applied is assumed
123 * when c->sz_reg is equal to 32.
125 pfd->index = c->i_base;
126 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
127 pfd->bitpos = bits % c->sz_reg;
128 pfd->mask = (1 << c->x_bits) - 1;
130 /* pfd->next is used for indicating that bit wrapping-around happens
131 * which requires the manipulation for bit 0 starting in the next
132 * register to form the complete field read/write.
134 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
139 static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw,
140 const struct mtk_pin_desc *desc,
141 int field, struct mtk_pin_field *pfd)
143 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
144 dev_err(hw->dev, "Invalid Field %d\n", field);
148 return mtk_hw_pin_field_lookup(hw, desc, field, pfd);
151 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
153 *l = 32 - pf->bitpos;
154 *h = get_count_order(pf->mask) - *l;
157 static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
158 struct mtk_pin_field *pf, int value)
160 int nbits_l, nbits_h;
162 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
164 mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
165 (value & pf->mask) << pf->bitpos);
167 mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
168 (value & pf->mask) >> nbits_l);
171 static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
172 struct mtk_pin_field *pf, int *value)
174 int nbits_l, nbits_h, h, l;
176 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
178 l = (mtk_r32(hw, pf->index, pf->offset)
179 >> pf->bitpos) & (BIT(nbits_l) - 1);
180 h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
181 & (BIT(nbits_h) - 1);
183 *value = (h << nbits_l) | l;
186 int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
187 int field, int value)
189 struct mtk_pin_field pf;
192 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
196 if (value < 0 || value > pf.mask)
200 mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
201 (value & pf.mask) << pf.bitpos);
203 mtk_hw_write_cross_field(hw, &pf, value);
208 int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
209 int field, int *value)
211 struct mtk_pin_field pf;
214 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
219 *value = (mtk_r32(hw, pf.index, pf.offset)
220 >> pf.bitpos) & pf.mask;
222 mtk_hw_read_cross_field(hw, &pf, value);
227 static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
229 const struct mtk_pin_desc *desc;
232 desc = (const struct mtk_pin_desc *)hw->soc->pins;
234 while (i < hw->soc->npins) {
235 if (desc[i].eint.eint_n == eint_n)
236 return desc[i].number;
243 static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
244 unsigned int *gpio_n,
245 struct gpio_chip **gpio_chip)
247 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
248 const struct mtk_pin_desc *desc;
250 desc = (const struct mtk_pin_desc *)hw->soc->pins;
251 *gpio_chip = &hw->chip;
253 /* Be greedy to guess first gpio_n is equal to eint_n */
254 if (desc[eint_n].eint.eint_n == eint_n)
257 *gpio_n = mtk_xt_find_eint_num(hw, eint_n);
259 return *gpio_n == EINT_NA ? -EINVAL : 0;
262 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
264 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
265 const struct mtk_pin_desc *desc;
266 struct gpio_chip *gpio_chip;
270 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
274 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
276 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
283 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
285 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
286 const struct mtk_pin_desc *desc;
287 struct gpio_chip *gpio_chip;
291 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
295 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
297 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
302 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT);
306 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
307 /* SMT is supposed to be supported by every real GPIO and doesn't
308 * support virtual GPIOs, so the extra condition err != -ENOTSUPP
309 * is just for adding EINT support to these virtual GPIOs. It should
310 * add an extra flag in the pin descriptor when more pins with
311 * distinctive characteristic come out.
313 if (err && err != -ENOTSUPP)
319 static const struct mtk_eint_xt mtk_eint_xt = {
320 .get_gpio_n = mtk_xt_get_gpio_n,
321 .get_gpio_state = mtk_xt_get_gpio_state,
322 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
325 int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
327 struct device_node *np = pdev->dev.of_node;
328 struct resource *res;
330 if (!IS_ENABLED(CONFIG_EINT_MTK))
333 if (!of_property_read_bool(np, "interrupt-controller"))
336 hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
340 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint");
342 dev_err(&pdev->dev, "Unable to get eint resource\n");
346 hw->eint->base = devm_ioremap_resource(&pdev->dev, res);
347 if (IS_ERR(hw->eint->base))
348 return PTR_ERR(hw->eint->base);
350 hw->eint->irq = irq_of_parse_and_map(np, 0);
354 if (!hw->soc->eint_hw)
357 hw->eint->dev = &pdev->dev;
358 hw->eint->hw = hw->soc->eint_hw;
360 hw->eint->gpio_xlate = &mtk_eint_xt;
362 return mtk_eint_do_init(hw->eint);
366 int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
367 const struct mtk_pin_desc *desc)
371 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU,
376 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
384 int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
385 const struct mtk_pin_desc *desc, int *res)
390 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v);
394 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2);
398 if (v == MTK_ENABLE || v2 == MTK_ENABLE)
406 int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
407 const struct mtk_pin_desc *desc, bool pullup)
411 arg = pullup ? 1 : 2;
413 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1);
417 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
425 int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
426 const struct mtk_pin_desc *desc, bool pullup, int *res)
430 reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD;
432 err = mtk_hw_get_value(hw, desc, reg, &v);
445 int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
446 const struct mtk_pin_desc *desc)
450 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
458 int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
459 const struct mtk_pin_desc *desc, int *res)
463 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
475 int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
476 const struct mtk_pin_desc *desc, bool pullup)
480 arg = pullup ? MTK_PULLUP : MTK_PULLDOWN;
482 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
487 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg);
494 int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
495 const struct mtk_pin_desc *desc, bool pullup,
500 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
504 if (v == MTK_DISABLE)
507 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v);
511 if (pullup ^ (v == MTK_PULLUP))
519 /* Combo for the following pull register type:
521 * 2. PULLSEL + PULLEN
524 static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
525 const struct mtk_pin_desc *desc,
530 if (arg == MTK_DISABLE) {
533 } else if ((arg == MTK_ENABLE) && pullup) {
536 } else if ((arg == MTK_ENABLE) && !pullup) {
544 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
548 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
554 static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
555 const struct mtk_pin_desc *desc,
560 if (arg == MTK_DISABLE)
562 else if (arg == MTK_ENABLE)
569 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
573 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
579 static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw,
580 const struct mtk_pin_desc *desc,
585 if ((arg == MTK_DISABLE) || (arg == MTK_PUPD_SET_R1R0_00)) {
589 } else if (arg == MTK_PUPD_SET_R1R0_01) {
592 } else if (arg == MTK_PUPD_SET_R1R0_10) {
595 } else if (arg == MTK_PUPD_SET_R1R0_11) {
603 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
604 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, !pullup);
608 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, r0);
612 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, r1);
618 static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,
619 const struct mtk_pin_desc *desc,
620 u32 *pullup, u32 *enable)
624 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu);
628 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
632 if (pu == 0 && pd == 0) {
634 *enable = MTK_DISABLE;
635 } else if (pu == 1 && pd == 0) {
637 *enable = MTK_ENABLE;
638 } else if (pu == 0 && pd == 1) {
640 *enable = MTK_ENABLE;
648 static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
649 const struct mtk_pin_desc *desc,
650 u32 *pullup, u32 *enable)
654 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
658 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
664 static int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl *hw,
665 const struct mtk_pin_desc *desc,
666 u32 *pullup, u32 *enable)
670 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, pullup);
673 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
674 *pullup = !(*pullup);
676 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &r0);
680 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &r1);
684 if ((r1 == 0) && (r0 == 0))
685 *enable = MTK_PUPD_SET_R1R0_00;
686 else if ((r1 == 0) && (r0 == 1))
687 *enable = MTK_PUPD_SET_R1R0_01;
688 else if ((r1 == 1) && (r0 == 0))
689 *enable = MTK_PUPD_SET_R1R0_10;
690 else if ((r1 == 1) && (r0 == 1))
691 *enable = MTK_PUPD_SET_R1R0_11;
699 int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
700 const struct mtk_pin_desc *desc,
705 err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
709 err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg);
713 err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
719 int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
720 const struct mtk_pin_desc *desc,
721 u32 *pullup, u32 *enable)
725 err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
729 err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable);
733 err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
740 int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
741 const struct mtk_pin_desc *desc, u32 arg)
743 const struct mtk_drive_desc *tb;
746 tb = &mtk_drive[desc->drv_n];
747 /* 4mA when (e8, e4) = (0, 0)
748 * 8mA when (e8, e4) = (0, 1)
749 * 12mA when (e8, e4) = (1, 0)
750 * 16mA when (e8, e4) = (1, 1)
752 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
753 arg = (arg / tb->step - 1) * tb->scal;
754 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4,
759 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8,
768 int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
769 const struct mtk_pin_desc *desc, int *val)
771 const struct mtk_drive_desc *tb;
774 tb = &mtk_drive[desc->drv_n];
776 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1);
780 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2);
784 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
785 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
787 *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step;
793 int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
794 const struct mtk_pin_desc *desc, u32 arg)
796 const struct mtk_drive_desc *tb;
799 tb = &mtk_drive[desc->drv_n];
801 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
802 arg = (arg / tb->step - 1) * tb->scal;
804 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV,
813 int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
814 const struct mtk_pin_desc *desc, int *val)
816 const struct mtk_drive_desc *tb;
819 tb = &mtk_drive[desc->drv_n];
821 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1);
825 *val = ((val1 & 0x7) / tb->scal + 1) * tb->step;
830 int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw,
831 const struct mtk_pin_desc *desc, u32 arg)
833 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg);
836 int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw,
837 const struct mtk_pin_desc *desc, int *val)
839 return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val);
842 int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
843 const struct mtk_pin_desc *desc, bool pullup,
848 /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0);
849 * 10K off & 50K (75K) on, when (R0, R1) = (0, 1);
850 * 10K on & 50K (75K) off, when (R0, R1) = (1, 0);
851 * 10K on & 50K (75K) on, when (R0, R1) = (1, 1)
853 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1);
857 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1,
862 arg = pullup ? 0 : 1;
864 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg);
866 /* If PUPD register is not supported for that pin, let's fallback to
867 * general bias control.
869 if (err == -ENOTSUPP) {
870 if (hw->soc->bias_set) {
871 err = hw->soc->bias_set(hw, desc, pullup);
882 int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
883 const struct mtk_pin_desc *desc, bool pullup,
889 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t);
891 /* If PUPD register is not supported for that pin, let's fallback to
892 * general bias control.
894 if (err == -ENOTSUPP) {
895 if (hw->soc->bias_get) {
896 err = hw->soc->bias_get(hw, desc, pullup, val);
903 /* t == 0 supposes PULLUP for the customized PULL setup */
911 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t);
915 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2);
919 *val = (t | t2 << 1) & 0x7;
924 int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
925 const struct mtk_pin_desc *desc, u32 arg)
929 int e0 = !!(arg & 2);
930 int e1 = !!(arg & 4);
932 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
939 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0);
943 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1);
950 int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
951 const struct mtk_pin_desc *desc, u32 *val)
956 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
960 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0);
964 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1);
968 *val = (en | e0 << 1 | e1 << 2) & 0x7;