1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 MediaTek Inc.
5 * Author: Sean Wang <sean.wang@mediatek.com>
9 #include <dt-bindings/pinctrl/mt65xx.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/platform_device.h>
15 #include <linux/module.h>
16 #include <linux/of_irq.h>
19 #include "pinctrl-mtk-common-v2.h"
22 * struct mtk_drive_desc - the structure that holds the information
23 * of the driving current
24 * @min: the minimum current of this group
25 * @max: the maximum current of this group
26 * @step: the step current of this group
27 * @scal: the weight factor
29 * formula: output = ((input) / step - 1) * scal
31 struct mtk_drive_desc {
38 /* The groups of drive strength */
39 static const struct mtk_drive_desc mtk_drive[] = {
40 [DRV_GRP0] = { 4, 16, 4, 1 },
41 [DRV_GRP1] = { 4, 16, 4, 2 },
42 [DRV_GRP2] = { 2, 8, 2, 1 },
43 [DRV_GRP3] = { 2, 8, 2, 2 },
44 [DRV_GRP4] = { 2, 16, 2, 1 },
47 static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val)
49 writel_relaxed(val, pctl->base[i] + reg);
52 static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
54 return readl_relaxed(pctl->base[i] + reg);
57 void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
61 val = mtk_r32(pctl, i, reg);
64 mtk_w32(pctl, i, reg, val);
67 static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
68 const struct mtk_pin_desc *desc,
69 int field, struct mtk_pin_field *pfd)
71 const struct mtk_pin_field_calc *c;
72 const struct mtk_pin_reg_calc *rc;
73 int start = 0, end, check;
77 if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
78 rc = &hw->soc->reg_cal[field];
81 "Not support field %d for this soc\n", field);
85 end = rc->nranges - 1;
87 while (start <= end) {
88 check = (start + end) >> 1;
89 if (desc->number >= rc->range[check].s_pin
90 && desc->number <= rc->range[check].e_pin) {
93 } else if (start == end)
95 else if (desc->number < rc->range[check].s_pin)
102 dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n",
103 field, desc->number, desc->name);
107 c = rc->range + check;
109 if (c->i_base > hw->nbase - 1) {
111 "Invalid base for field %d for pin = %d (%s)\n",
112 field, desc->number, desc->name);
116 /* Calculated bits as the overall offset the pin is located at,
117 * if c->fixed is held, that determines the all the pins in the
118 * range use the same field with the s_pin.
120 bits = c->fixed ? c->s_bit : c->s_bit +
121 (desc->number - c->s_pin) * (c->x_bits);
123 /* Fill pfd from bits. For example 32-bit register applied is assumed
124 * when c->sz_reg is equal to 32.
126 pfd->index = c->i_base;
127 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
128 pfd->bitpos = bits % c->sz_reg;
129 pfd->mask = (1 << c->x_bits) - 1;
131 /* pfd->next is used for indicating that bit wrapping-around happens
132 * which requires the manipulation for bit 0 starting in the next
133 * register to form the complete field read/write.
135 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
140 static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw,
141 const struct mtk_pin_desc *desc,
142 int field, struct mtk_pin_field *pfd)
144 if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
145 dev_err(hw->dev, "Invalid Field %d\n", field);
149 return mtk_hw_pin_field_lookup(hw, desc, field, pfd);
152 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
154 *l = 32 - pf->bitpos;
155 *h = get_count_order(pf->mask) - *l;
158 static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
159 struct mtk_pin_field *pf, int value)
161 int nbits_l, nbits_h;
163 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
165 mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
166 (value & pf->mask) << pf->bitpos);
168 mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
169 (value & pf->mask) >> nbits_l);
172 static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
173 struct mtk_pin_field *pf, int *value)
175 int nbits_l, nbits_h, h, l;
177 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
179 l = (mtk_r32(hw, pf->index, pf->offset)
180 >> pf->bitpos) & (BIT(nbits_l) - 1);
181 h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
182 & (BIT(nbits_h) - 1);
184 *value = (h << nbits_l) | l;
187 int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
188 int field, int value)
190 struct mtk_pin_field pf;
193 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
197 if (value < 0 || value > pf.mask)
201 mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
202 (value & pf.mask) << pf.bitpos);
204 mtk_hw_write_cross_field(hw, &pf, value);
208 EXPORT_SYMBOL_GPL(mtk_hw_set_value);
210 int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
211 int field, int *value)
213 struct mtk_pin_field pf;
216 err = mtk_hw_pin_field_get(hw, desc, field, &pf);
221 *value = (mtk_r32(hw, pf.index, pf.offset)
222 >> pf.bitpos) & pf.mask;
224 mtk_hw_read_cross_field(hw, &pf, value);
228 EXPORT_SYMBOL_GPL(mtk_hw_get_value);
230 static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
232 const struct mtk_pin_desc *desc;
235 desc = (const struct mtk_pin_desc *)hw->soc->pins;
237 while (i < hw->soc->npins) {
238 if (desc[i].eint.eint_n == eint_n)
239 return desc[i].number;
247 * Virtual GPIO only used inside SOC and not being exported to outside SOC.
248 * Some modules use virtual GPIO as eint (e.g. pmif or usb).
249 * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
250 * and we can set GPIO as eint.
251 * But some modules use specific eint which doesn't have real GPIO pin.
252 * So we use virtual GPIO to map it.
255 bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
257 const struct mtk_pin_desc *desc;
258 bool virt_gpio = false;
260 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
262 if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
268 static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
269 unsigned int *gpio_n,
270 struct gpio_chip **gpio_chip)
272 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
273 const struct mtk_pin_desc *desc;
275 desc = (const struct mtk_pin_desc *)hw->soc->pins;
276 *gpio_chip = &hw->chip;
278 /* Be greedy to guess first gpio_n is equal to eint_n */
279 if (desc[eint_n].eint.eint_n == eint_n)
282 *gpio_n = mtk_xt_find_eint_num(hw, eint_n);
284 return *gpio_n == EINT_NA ? -EINVAL : 0;
287 static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
289 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
290 const struct mtk_pin_desc *desc;
291 struct gpio_chip *gpio_chip;
295 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
299 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
301 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
308 static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
310 struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
311 const struct mtk_pin_desc *desc;
312 struct gpio_chip *gpio_chip;
316 err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
320 if (mtk_is_virt_gpio(hw, gpio_n))
323 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
325 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
330 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT);
334 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
335 /* SMT is supposed to be supported by every real GPIO and doesn't
336 * support virtual GPIOs, so the extra condition err != -ENOTSUPP
337 * is just for adding EINT support to these virtual GPIOs. It should
338 * add an extra flag in the pin descriptor when more pins with
339 * distinctive characteristic come out.
341 if (err && err != -ENOTSUPP)
347 static const struct mtk_eint_xt mtk_eint_xt = {
348 .get_gpio_n = mtk_xt_get_gpio_n,
349 .get_gpio_state = mtk_xt_get_gpio_state,
350 .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
353 int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
355 struct device_node *np = pdev->dev.of_node;
356 struct resource *res;
358 if (!IS_ENABLED(CONFIG_EINT_MTK))
361 if (!of_property_read_bool(np, "interrupt-controller"))
364 hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
368 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint");
370 dev_err(&pdev->dev, "Unable to get eint resource\n");
374 hw->eint->base = devm_ioremap_resource(&pdev->dev, res);
375 if (IS_ERR(hw->eint->base))
376 return PTR_ERR(hw->eint->base);
378 hw->eint->irq = irq_of_parse_and_map(np, 0);
382 if (!hw->soc->eint_hw)
385 hw->eint->dev = &pdev->dev;
386 hw->eint->hw = hw->soc->eint_hw;
388 hw->eint->gpio_xlate = &mtk_eint_xt;
390 return mtk_eint_do_init(hw->eint);
392 EXPORT_SYMBOL_GPL(mtk_build_eint);
395 int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
396 const struct mtk_pin_desc *desc)
400 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU,
405 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
412 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set);
414 int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
415 const struct mtk_pin_desc *desc, int *res)
420 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v);
424 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2);
428 if (v == MTK_ENABLE || v2 == MTK_ENABLE)
435 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get);
437 int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
438 const struct mtk_pin_desc *desc, bool pullup)
442 arg = pullup ? 1 : 2;
444 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1);
448 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
455 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set);
457 int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
458 const struct mtk_pin_desc *desc, bool pullup, int *res)
462 reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD;
464 err = mtk_hw_get_value(hw, desc, reg, &v);
475 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get);
478 int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
479 const struct mtk_pin_desc *desc)
483 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
490 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1);
492 int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
493 const struct mtk_pin_desc *desc, int *res)
497 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
508 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get_rev1);
510 int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
511 const struct mtk_pin_desc *desc, bool pullup)
515 arg = pullup ? MTK_PULLUP : MTK_PULLDOWN;
517 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
522 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg);
528 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_rev1);
530 int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
531 const struct mtk_pin_desc *desc, bool pullup,
536 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
540 if (v == MTK_DISABLE)
543 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v);
547 if (pullup ^ (v == MTK_PULLUP))
554 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1);
556 /* Combo for the following pull register type:
558 * 2. PULLSEL + PULLEN
561 static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
562 const struct mtk_pin_desc *desc,
567 if (arg == MTK_DISABLE) {
570 } else if ((arg == MTK_ENABLE) && pullup) {
573 } else if ((arg == MTK_ENABLE) && !pullup) {
581 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
585 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
591 static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
592 const struct mtk_pin_desc *desc,
597 if (arg == MTK_DISABLE)
599 else if (arg == MTK_ENABLE)
606 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
610 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
616 static int mtk_pinconf_bias_set_pupd_r1_r0(struct mtk_pinctrl *hw,
617 const struct mtk_pin_desc *desc,
622 if ((arg == MTK_DISABLE) || (arg == MTK_PUPD_SET_R1R0_00)) {
626 } else if (arg == MTK_PUPD_SET_R1R0_01) {
629 } else if (arg == MTK_PUPD_SET_R1R0_10) {
632 } else if (arg == MTK_PUPD_SET_R1R0_11) {
640 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
641 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, !pullup);
645 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, r0);
649 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1, r1);
655 static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,
656 const struct mtk_pin_desc *desc,
657 u32 *pullup, u32 *enable)
661 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &pu);
665 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
669 if (pu == 0 && pd == 0) {
671 *enable = MTK_DISABLE;
672 } else if (pu == 1 && pd == 0) {
674 *enable = MTK_ENABLE;
675 } else if (pu == 0 && pd == 1) {
677 *enable = MTK_ENABLE;
685 static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
686 const struct mtk_pin_desc *desc,
687 u32 *pullup, u32 *enable)
691 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, pullup);
695 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, enable);
701 static int mtk_pinconf_bias_get_pupd_r1_r0(struct mtk_pinctrl *hw,
702 const struct mtk_pin_desc *desc,
703 u32 *pullup, u32 *enable)
707 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, pullup);
710 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
711 *pullup = !(*pullup);
713 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &r0);
717 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &r1);
721 if ((r1 == 0) && (r0 == 0))
722 *enable = MTK_PUPD_SET_R1R0_00;
723 else if ((r1 == 0) && (r0 == 1))
724 *enable = MTK_PUPD_SET_R1R0_01;
725 else if ((r1 == 1) && (r0 == 0))
726 *enable = MTK_PUPD_SET_R1R0_10;
727 else if ((r1 == 1) && (r0 == 1))
728 *enable = MTK_PUPD_SET_R1R0_11;
736 int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
737 const struct mtk_pin_desc *desc,
742 err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
746 err = mtk_pinconf_bias_set_pullsel_pullen(hw, desc, pullup, arg);
750 err = mtk_pinconf_bias_set_pupd_r1_r0(hw, desc, pullup, arg);
755 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo);
757 int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
758 const struct mtk_pin_desc *desc,
759 u32 *pullup, u32 *enable)
763 err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
767 err = mtk_pinconf_bias_get_pullsel_pullen(hw, desc, pullup, enable);
771 err = mtk_pinconf_bias_get_pupd_r1_r0(hw, desc, pullup, enable);
776 EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo);
779 int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
780 const struct mtk_pin_desc *desc, u32 arg)
782 const struct mtk_drive_desc *tb;
785 tb = &mtk_drive[desc->drv_n];
786 /* 4mA when (e8, e4) = (0, 0)
787 * 8mA when (e8, e4) = (0, 1)
788 * 12mA when (e8, e4) = (1, 0)
789 * 16mA when (e8, e4) = (1, 1)
791 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
792 arg = (arg / tb->step - 1) * tb->scal;
793 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4,
798 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8,
806 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set);
808 int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
809 const struct mtk_pin_desc *desc, int *val)
811 const struct mtk_drive_desc *tb;
814 tb = &mtk_drive[desc->drv_n];
816 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1);
820 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2);
824 /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
825 * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
827 *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step;
831 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get);
834 int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
835 const struct mtk_pin_desc *desc, u32 arg)
837 const struct mtk_drive_desc *tb;
840 tb = &mtk_drive[desc->drv_n];
842 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
843 arg = (arg / tb->step - 1) * tb->scal;
845 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV,
853 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_rev1);
855 int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
856 const struct mtk_pin_desc *desc, int *val)
858 const struct mtk_drive_desc *tb;
861 tb = &mtk_drive[desc->drv_n];
863 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1);
867 *val = ((val1 & 0x7) / tb->scal + 1) * tb->step;
871 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_rev1);
873 int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw,
874 const struct mtk_pin_desc *desc, u32 arg)
876 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg);
878 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_raw);
880 int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw,
881 const struct mtk_pin_desc *desc, int *val)
883 return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val);
885 EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_raw);
887 int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
888 const struct mtk_pin_desc *desc, bool pullup,
893 /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0);
894 * 10K off & 50K (75K) on, when (R0, R1) = (0, 1);
895 * 10K on & 50K (75K) off, when (R0, R1) = (1, 0);
896 * 10K on & 50K (75K) on, when (R0, R1) = (1, 1)
898 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1);
902 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1,
907 arg = pullup ? 0 : 1;
909 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg);
911 /* If PUPD register is not supported for that pin, let's fallback to
912 * general bias control.
914 if (err == -ENOTSUPP) {
915 if (hw->soc->bias_set) {
916 err = hw->soc->bias_set(hw, desc, pullup);
926 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_set);
928 int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
929 const struct mtk_pin_desc *desc, bool pullup,
935 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t);
937 /* If PUPD register is not supported for that pin, let's fallback to
938 * general bias control.
940 if (err == -ENOTSUPP) {
941 if (hw->soc->bias_get) {
942 err = hw->soc->bias_get(hw, desc, pullup, val);
949 /* t == 0 supposes PULLUP for the customized PULL setup */
957 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t);
961 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2);
965 *val = (t | t2 << 1) & 0x7;
969 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_get);
971 int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
972 const struct mtk_pin_desc *desc, u32 arg)
976 int e0 = !!(arg & 2);
977 int e1 = !!(arg & 4);
979 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
986 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0);
990 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1);
996 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set);
998 int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
999 const struct mtk_pin_desc *desc, u32 *val)
1004 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
1008 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0);
1012 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1);
1016 *val = (en | e0 << 1 | e1 << 2) & 0x7;
1020 EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get);
1022 MODULE_LICENSE("GPL v2");
1023 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1024 MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs");