1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Jasper Lake PCH pinctrl/GPIO driver
5 * Copyright (C) 2020, Intel Corporation
6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
9 #include <linux/mod_devicetable.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
13 #include <linux/pinctrl/pinctrl.h>
15 #include "pinctrl-intel.h"
17 #define JSL_PAD_OWN 0x020
18 #define JSL_PADCFGLOCK 0x080
19 #define JSL_HOSTSW_OWN 0x0b0
20 #define JSL_GPI_IS 0x100
21 #define JSL_GPI_IE 0x120
23 #define JSL_GPP(r, s, e, g) \
27 .size = ((e) - (s) + 1), \
31 #define JSL_COMMUNITY(b, s, e, g) \
34 .padown_offset = JSL_PAD_OWN, \
35 .padcfglock_offset = JSL_PADCFGLOCK, \
36 .hostown_offset = JSL_HOSTSW_OWN, \
37 .is_offset = JSL_GPI_IS, \
38 .ie_offset = JSL_GPI_IE, \
40 .npins = ((e) - (s) + 1), \
42 .ngpps = ARRAY_SIZE(g), \
46 static const struct pinctrl_pin_desc jsl_pins[] = {
48 PINCTRL_PIN(0, "CNV_BRI_DT_UART0_RTSB"),
49 PINCTRL_PIN(1, "CNV_BRI_RSP_UART0_RXD"),
50 PINCTRL_PIN(2, "EMMC_HIP_MON"),
51 PINCTRL_PIN(3, "CNV_RGI_RSP_UART0_CTSB"),
52 PINCTRL_PIN(4, "CNV_RF_RESET_B"),
53 PINCTRL_PIN(5, "MODEM_CLKREQ"),
54 PINCTRL_PIN(6, "CNV_PA_BLANKING"),
55 PINCTRL_PIN(7, "EMMC_CMD"),
56 PINCTRL_PIN(8, "EMMC_DATA0"),
57 PINCTRL_PIN(9, "EMMC_DATA1"),
58 PINCTRL_PIN(10, "EMMC_DATA2"),
59 PINCTRL_PIN(11, "EMMC_DATA3"),
60 PINCTRL_PIN(12, "EMMC_DATA4"),
61 PINCTRL_PIN(13, "EMMC_DATA5"),
62 PINCTRL_PIN(14, "EMMC_DATA6"),
63 PINCTRL_PIN(15, "EMMC_DATA7"),
64 PINCTRL_PIN(16, "EMMC_RCLK"),
65 PINCTRL_PIN(17, "EMMC_CLK"),
66 PINCTRL_PIN(18, "EMMC_RESETB"),
67 PINCTRL_PIN(19, "A4WP_PRESENT"),
69 PINCTRL_PIN(20, "CORE_VID_0"),
70 PINCTRL_PIN(21, "CORE_VID_1"),
71 PINCTRL_PIN(22, "VRALERTB"),
72 PINCTRL_PIN(23, "CPU_GP_2"),
73 PINCTRL_PIN(24, "CPU_GP_3"),
74 PINCTRL_PIN(25, "SRCCLKREQB_0"),
75 PINCTRL_PIN(26, "SRCCLKREQB_1"),
76 PINCTRL_PIN(27, "SRCCLKREQB_2"),
77 PINCTRL_PIN(28, "SRCCLKREQB_3"),
78 PINCTRL_PIN(29, "SRCCLKREQB_4"),
79 PINCTRL_PIN(30, "SRCCLKREQB_5"),
80 PINCTRL_PIN(31, "PMCALERTB"),
81 PINCTRL_PIN(32, "SLP_S0B"),
82 PINCTRL_PIN(33, "PLTRSTB"),
83 PINCTRL_PIN(34, "SPKR"),
84 PINCTRL_PIN(35, "GSPI0_CS0B"),
85 PINCTRL_PIN(36, "GSPI0_CLK"),
86 PINCTRL_PIN(37, "GSPI0_MISO"),
87 PINCTRL_PIN(38, "GSPI0_MOSI"),
88 PINCTRL_PIN(39, "GSPI1_CS0B"),
89 PINCTRL_PIN(40, "GSPI1_CLK"),
90 PINCTRL_PIN(41, "GSPI1_MISO"),
91 PINCTRL_PIN(42, "GSPI1_MOSI"),
92 PINCTRL_PIN(43, "DDSP_HPD_A"),
93 PINCTRL_PIN(44, "GSPI0_CLK_LOOPBK"),
94 PINCTRL_PIN(45, "GSPI1_CLK_LOOPBK"),
96 PINCTRL_PIN(46, "ESPI_IO_0"),
97 PINCTRL_PIN(47, "ESPI_IO_1"),
98 PINCTRL_PIN(48, "ESPI_IO_2"),
99 PINCTRL_PIN(49, "ESPI_IO_3"),
100 PINCTRL_PIN(50, "ESPI_CSB"),
101 PINCTRL_PIN(51, "ESPI_CLK"),
102 PINCTRL_PIN(52, "ESPI_RESETB"),
103 PINCTRL_PIN(53, "SMBCLK"),
104 PINCTRL_PIN(54, "SMBDATA"),
105 PINCTRL_PIN(55, "SMBALERTB"),
106 PINCTRL_PIN(56, "CPU_GP_0"),
107 PINCTRL_PIN(57, "CPU_GP_1"),
108 PINCTRL_PIN(58, "USB2_OCB_1"),
109 PINCTRL_PIN(59, "USB2_OCB_2"),
110 PINCTRL_PIN(60, "USB2_OCB_3"),
111 PINCTRL_PIN(61, "DDSP_HPD_A_TIME_SYNC_0"),
112 PINCTRL_PIN(62, "DDSP_HPD_B"),
113 PINCTRL_PIN(63, "DDSP_HPD_C"),
114 PINCTRL_PIN(64, "USB2_OCB_0"),
115 PINCTRL_PIN(65, "PCHHOTB"),
116 PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
118 PINCTRL_PIN(67, "SNDW1_CLK"),
119 PINCTRL_PIN(68, "SNDW1_DATA"),
120 PINCTRL_PIN(69, "SNDW2_CLK"),
121 PINCTRL_PIN(70, "SNDW2_DATA"),
122 PINCTRL_PIN(71, "SNDW1_CLK"),
123 PINCTRL_PIN(72, "SNDW1_DATA"),
124 PINCTRL_PIN(73, "SNDW4_CLK_DMIC_CLK_0"),
125 PINCTRL_PIN(74, "SNDW4_DATA_DMIC_DATA_0"),
127 PINCTRL_PIN(75, "HDA_BCLK"),
128 PINCTRL_PIN(76, "HDA_SYNC"),
129 PINCTRL_PIN(77, "HDA_SDO"),
130 PINCTRL_PIN(78, "HDA_SDI_0"),
131 PINCTRL_PIN(79, "HDA_RSTB"),
132 PINCTRL_PIN(80, "HDA_SDI_1"),
133 PINCTRL_PIN(81, "I2S1_SFRM"),
134 PINCTRL_PIN(82, "I2S1_TXD"),
136 PINCTRL_PIN(83, "GPPC_H_0"),
137 PINCTRL_PIN(84, "SD_PWR_EN_B"),
138 PINCTRL_PIN(85, "MODEM_CLKREQ"),
139 PINCTRL_PIN(86, "SX_EXIT_HOLDOFFB"),
140 PINCTRL_PIN(87, "I2C2_SDA"),
141 PINCTRL_PIN(88, "I2C2_SCL"),
142 PINCTRL_PIN(89, "I2C3_SDA"),
143 PINCTRL_PIN(90, "I2C3_SCL"),
144 PINCTRL_PIN(91, "I2C4_SDA"),
145 PINCTRL_PIN(92, "I2C4_SCL"),
146 PINCTRL_PIN(93, "CPU_VCCIO_PWR_GATEB"),
147 PINCTRL_PIN(94, "I2S2_SCLK"),
148 PINCTRL_PIN(95, "I2S2_SFRM"),
149 PINCTRL_PIN(96, "I2S2_TXD"),
150 PINCTRL_PIN(97, "I2S2_RXD"),
151 PINCTRL_PIN(98, "I2S1_SCLK"),
152 PINCTRL_PIN(99, "GPPC_H_16"),
153 PINCTRL_PIN(100, "GPPC_H_17"),
154 PINCTRL_PIN(101, "GPPC_H_18"),
155 PINCTRL_PIN(102, "GPPC_H_19"),
156 PINCTRL_PIN(103, "GPPC_H_20"),
157 PINCTRL_PIN(104, "GPPC_H_21"),
158 PINCTRL_PIN(105, "GPPC_H_22"),
159 PINCTRL_PIN(106, "GPPC_H_23"),
161 PINCTRL_PIN(107, "SPI1_CSB"),
162 PINCTRL_PIN(108, "SPI1_CLK"),
163 PINCTRL_PIN(109, "SPI1_MISO_IO_1"),
164 PINCTRL_PIN(110, "SPI1_MOSI_IO_0"),
165 PINCTRL_PIN(111, "ISH_I2C0_SDA"),
166 PINCTRL_PIN(112, "ISH_I2C0_SCL"),
167 PINCTRL_PIN(113, "ISH_I2C1_SDA"),
168 PINCTRL_PIN(114, "ISH_I2C1_SCL"),
169 PINCTRL_PIN(115, "ISH_SPI_CSB"),
170 PINCTRL_PIN(116, "ISH_SPI_CLK"),
171 PINCTRL_PIN(117, "ISH_SPI_MISO"),
172 PINCTRL_PIN(118, "ISH_SPI_MOSI"),
173 PINCTRL_PIN(119, "ISH_UART0_RXD"),
174 PINCTRL_PIN(120, "ISH_UART0_TXD"),
175 PINCTRL_PIN(121, "ISH_UART0_RTSB"),
176 PINCTRL_PIN(122, "ISH_UART0_CTSB"),
177 PINCTRL_PIN(123, "SPI1_IO_2"),
178 PINCTRL_PIN(124, "SPI1_IO_3"),
179 PINCTRL_PIN(125, "I2S_MCLK"),
180 PINCTRL_PIN(126, "CNV_MFUART2_RXD"),
181 PINCTRL_PIN(127, "CNV_MFUART2_TXD"),
182 PINCTRL_PIN(128, "CNV_PA_BLANKING"),
183 PINCTRL_PIN(129, "I2C5_SDA"),
184 PINCTRL_PIN(130, "I2C5_SCL"),
185 PINCTRL_PIN(131, "GSPI2_CLK_LOOPBK"),
186 PINCTRL_PIN(132, "SPI1_CLK_LOOPBK"),
188 PINCTRL_PIN(133, "CNV_BTEN"),
189 PINCTRL_PIN(134, "CNV_WCEN"),
190 PINCTRL_PIN(135, "CNV_BT_HOST_WAKEB"),
191 PINCTRL_PIN(136, "CNV_BT_IF_SELECT"),
192 PINCTRL_PIN(137, "vCNV_BT_UART_TXD"),
193 PINCTRL_PIN(138, "vCNV_BT_UART_RXD"),
194 PINCTRL_PIN(139, "vCNV_BT_UART_CTS_B"),
195 PINCTRL_PIN(140, "vCNV_BT_UART_RTS_B"),
196 PINCTRL_PIN(141, "vCNV_MFUART1_TXD"),
197 PINCTRL_PIN(142, "vCNV_MFUART1_RXD"),
198 PINCTRL_PIN(143, "vCNV_MFUART1_CTS_B"),
199 PINCTRL_PIN(144, "vCNV_MFUART1_RTS_B"),
200 PINCTRL_PIN(145, "vUART0_TXD"),
201 PINCTRL_PIN(146, "vUART0_RXD"),
202 PINCTRL_PIN(147, "vUART0_CTS_B"),
203 PINCTRL_PIN(148, "vUART0_RTS_B"),
204 PINCTRL_PIN(149, "vISH_UART0_TXD"),
205 PINCTRL_PIN(150, "vISH_UART0_RXD"),
206 PINCTRL_PIN(151, "vISH_UART0_CTS_B"),
207 PINCTRL_PIN(152, "vISH_UART0_RTS_B"),
208 PINCTRL_PIN(153, "vCNV_BT_I2S_BCLK"),
209 PINCTRL_PIN(154, "vCNV_BT_I2S_WS_SYNC"),
210 PINCTRL_PIN(155, "vCNV_BT_I2S_SDO"),
211 PINCTRL_PIN(156, "vCNV_BT_I2S_SDI"),
212 PINCTRL_PIN(157, "vI2S2_SCLK"),
213 PINCTRL_PIN(158, "vI2S2_SFRM"),
214 PINCTRL_PIN(159, "vI2S2_TXD"),
215 PINCTRL_PIN(160, "vI2S2_RXD"),
216 PINCTRL_PIN(161, "vSD3_CD_B"),
218 PINCTRL_PIN(162, "GPPC_C_0"),
219 PINCTRL_PIN(163, "GPPC_C_1"),
220 PINCTRL_PIN(164, "GPPC_C_2"),
221 PINCTRL_PIN(165, "GPPC_C_3"),
222 PINCTRL_PIN(166, "GPPC_C_4"),
223 PINCTRL_PIN(167, "GPPC_C_5"),
224 PINCTRL_PIN(168, "SUSWARNB_SUSPWRDNACK"),
225 PINCTRL_PIN(169, "SUSACKB"),
226 PINCTRL_PIN(170, "UART0_RXD"),
227 PINCTRL_PIN(171, "UART0_TXD"),
228 PINCTRL_PIN(172, "UART0_RTSB"),
229 PINCTRL_PIN(173, "UART0_CTSB"),
230 PINCTRL_PIN(174, "UART1_RXD"),
231 PINCTRL_PIN(175, "UART1_TXD"),
232 PINCTRL_PIN(176, "UART1_RTSB"),
233 PINCTRL_PIN(177, "UART1_CTSB"),
234 PINCTRL_PIN(178, "I2C0_SDA"),
235 PINCTRL_PIN(179, "I2C0_SCL"),
236 PINCTRL_PIN(180, "I2C1_SDA"),
237 PINCTRL_PIN(181, "I2C1_SCL"),
238 PINCTRL_PIN(182, "UART2_RXD"),
239 PINCTRL_PIN(183, "UART2_TXD"),
240 PINCTRL_PIN(184, "UART2_RTSB"),
241 PINCTRL_PIN(185, "UART2_CTSB"),
243 PINCTRL_PIN(186, "L_BKLTEN"),
244 PINCTRL_PIN(187, "L_BKLTCTL"),
245 PINCTRL_PIN(188, "L_VDDEN"),
246 PINCTRL_PIN(189, "SYS_PWROK"),
247 PINCTRL_PIN(190, "SYS_RESETB"),
248 PINCTRL_PIN(191, "MLK_RSTB"),
250 PINCTRL_PIN(192, "ISH_GP_0"),
251 PINCTRL_PIN(193, "ISH_GP_1"),
252 PINCTRL_PIN(194, "IMGCLKOUT_1"),
253 PINCTRL_PIN(195, "ISH_GP_2"),
254 PINCTRL_PIN(196, "IMGCLKOUT_2"),
255 PINCTRL_PIN(197, "SATA_LEDB"),
256 PINCTRL_PIN(198, "IMGCLKOUT_3"),
257 PINCTRL_PIN(199, "ISH_GP_3"),
258 PINCTRL_PIN(200, "ISH_GP_4"),
259 PINCTRL_PIN(201, "ISH_GP_5"),
260 PINCTRL_PIN(202, "ISH_GP_6"),
261 PINCTRL_PIN(203, "ISH_GP_7"),
262 PINCTRL_PIN(204, "IMGCLKOUT_4"),
263 PINCTRL_PIN(205, "DDPA_CTRLCLK"),
264 PINCTRL_PIN(206, "DDPA_CTRLDATA"),
265 PINCTRL_PIN(207, "DDPB_CTRLCLK"),
266 PINCTRL_PIN(208, "DDPB_CTRLDATA"),
267 PINCTRL_PIN(209, "DDPC_CTRLCLK"),
268 PINCTRL_PIN(210, "DDPC_CTRLDATA"),
269 PINCTRL_PIN(211, "IMGCLKOUT_5"),
270 PINCTRL_PIN(212, "CNV_BRI_DT"),
271 PINCTRL_PIN(213, "CNV_BRI_RSP"),
272 PINCTRL_PIN(214, "CNV_RGI_DT"),
273 PINCTRL_PIN(215, "CNV_RGI_RSP"),
275 PINCTRL_PIN(216, "SD3_CMD"),
276 PINCTRL_PIN(217, "SD3_D0"),
277 PINCTRL_PIN(218, "SD3_D1"),
278 PINCTRL_PIN(219, "SD3_D2"),
279 PINCTRL_PIN(220, "SD3_D3"),
280 PINCTRL_PIN(221, "SD3_CDB"),
281 PINCTRL_PIN(222, "SD3_CLK"),
282 PINCTRL_PIN(223, "SD3_WP"),
285 static const struct intel_padgroup jsl_community0_gpps[] = {
286 JSL_GPP(0, 0, 19, 320), /* GPP_F */
287 JSL_GPP(1, 20, 45, 32), /* GPP_B */
288 JSL_GPP(2, 46, 66, 64), /* GPP_A */
289 JSL_GPP(3, 67, 74, 96), /* GPP_S */
290 JSL_GPP(4, 75, 82, 128), /* GPP_R */
293 static const struct intel_padgroup jsl_community1_gpps[] = {
294 JSL_GPP(0, 83, 106, 160), /* GPP_H */
295 JSL_GPP(1, 107, 132, 192), /* GPP_D */
296 JSL_GPP(2, 133, 161, 224), /* vGPIO */
297 JSL_GPP(3, 162, 185, 256), /* GPP_C */
300 static const struct intel_padgroup jsl_community4_gpps[] = {
301 JSL_GPP(0, 186, 191, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
302 JSL_GPP(1, 192, 215, 288), /* GPP_E */
305 static const struct intel_padgroup jsl_community5_gpps[] = {
306 JSL_GPP(0, 216, 223, INTEL_GPIO_BASE_ZERO), /* GPP_G */
309 static const struct intel_community jsl_communities[] = {
310 JSL_COMMUNITY(0, 0, 82, jsl_community0_gpps),
311 JSL_COMMUNITY(1, 83, 185, jsl_community1_gpps),
312 JSL_COMMUNITY(2, 186, 215, jsl_community4_gpps),
313 JSL_COMMUNITY(3, 216, 223, jsl_community5_gpps),
316 static const struct intel_pinctrl_soc_data jsl_soc_data = {
318 .npins = ARRAY_SIZE(jsl_pins),
319 .communities = jsl_communities,
320 .ncommunities = ARRAY_SIZE(jsl_communities),
323 static const struct acpi_device_id jsl_pinctrl_acpi_match[] = {
324 { "INT34C8", (kernel_ulong_t)&jsl_soc_data },
327 MODULE_DEVICE_TABLE(acpi, jsl_pinctrl_acpi_match);
329 static INTEL_PINCTRL_PM_OPS(jsl_pinctrl_pm_ops);
331 static struct platform_driver jsl_pinctrl_driver = {
332 .probe = intel_pinctrl_probe_by_hid,
334 .name = "jasperlake-pinctrl",
335 .acpi_match_table = jsl_pinctrl_acpi_match,
336 .pm = &jsl_pinctrl_pm_ops,
340 module_platform_driver(jsl_pinctrl_driver);
342 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
343 MODULE_DESCRIPTION("Intel Jasper Lake PCH pinctrl/GPIO driver");
344 MODULE_LICENSE("GPL v2");