2 * Intel pinctrl/GPIO core driver.
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/acpi.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/driver.h>
19 #include <linux/platform_device.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
26 #include "pinctrl-intel.h"
28 /* Maximum number of pads in each group */
29 #define NPADS_IN_GPP 24
31 /* Offset from regs */
34 #define GPI_GPE_STS 0x140
35 #define GPI_GPE_EN 0x160
38 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
39 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
41 /* Offset from pad_regs */
43 #define PADCFG0_RXEVCFG_SHIFT 25
44 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
45 #define PADCFG0_RXEVCFG_LEVEL 0
46 #define PADCFG0_RXEVCFG_EDGE 1
47 #define PADCFG0_RXEVCFG_DISABLED 2
48 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
49 #define PADCFG0_RXINV BIT(23)
50 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
51 #define PADCFG0_GPIROUTSCI BIT(19)
52 #define PADCFG0_GPIROUTSMI BIT(18)
53 #define PADCFG0_GPIROUTNMI BIT(17)
54 #define PADCFG0_PMODE_SHIFT 10
55 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
56 #define PADCFG0_GPIORXDIS BIT(9)
57 #define PADCFG0_GPIOTXDIS BIT(8)
58 #define PADCFG0_GPIORXSTATE BIT(1)
59 #define PADCFG0_GPIOTXSTATE BIT(0)
62 #define PADCFG1_TERM_UP BIT(13)
63 #define PADCFG1_TERM_SHIFT 10
64 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
65 #define PADCFG1_TERM_20K 4
66 #define PADCFG1_TERM_2K 3
67 #define PADCFG1_TERM_5K 2
68 #define PADCFG1_TERM_1K 1
70 struct intel_pad_context {
75 struct intel_community_context {
79 struct intel_pinctrl_context {
80 struct intel_pad_context *pads;
81 struct intel_community_context *communities;
85 * struct intel_pinctrl - Intel pinctrl private structure
86 * @dev: Pointer to the device structure
87 * @lock: Lock to serialize register access
88 * @pctldesc: Pin controller description
89 * @pctldev: Pointer to the pin controller device
90 * @chip: GPIO chip in this pin controller
91 * @soc: SoC/PCH specific pin configuration data
92 * @communities: All communities in this pin controller
93 * @ncommunities: Number of communities in this pin controller
94 * @context: Configuration saved over system sleep
96 struct intel_pinctrl {
99 struct pinctrl_desc pctldesc;
100 struct pinctrl_dev *pctldev;
101 struct gpio_chip chip;
102 const struct intel_pinctrl_soc_data *soc;
103 struct intel_community *communities;
105 struct intel_pinctrl_context context;
108 #define gpiochip_to_pinctrl(c) container_of(c, struct intel_pinctrl, chip)
109 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
111 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
114 struct intel_community *community;
117 for (i = 0; i < pctrl->ncommunities; i++) {
118 community = &pctrl->communities[i];
119 if (pin >= community->pin_base &&
120 pin < community->pin_base + community->npins)
124 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
128 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
131 const struct intel_community *community;
134 community = intel_get_community(pctrl, pin);
138 padno = pin_to_padno(community, pin);
139 return community->pad_regs + reg + padno * 8;
142 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
144 const struct intel_community *community;
145 unsigned padno, gpp, gpp_offset, offset;
146 void __iomem *padown;
148 community = intel_get_community(pctrl, pin);
151 if (!community->padown_offset)
154 padno = pin_to_padno(community, pin);
155 gpp = padno / NPADS_IN_GPP;
156 gpp_offset = padno % NPADS_IN_GPP;
157 offset = community->padown_offset + gpp * 16 + (gpp_offset / 8) * 4;
158 padown = community->regs + offset;
160 return !(readl(padown) & PADOWN_MASK(padno));
163 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
165 const struct intel_community *community;
166 unsigned padno, gpp, offset;
167 void __iomem *hostown;
169 community = intel_get_community(pctrl, pin);
172 if (!community->hostown_offset)
175 padno = pin_to_padno(community, pin);
176 gpp = padno / NPADS_IN_GPP;
177 offset = community->hostown_offset + gpp * 4;
178 hostown = community->regs + offset;
180 return !(readl(hostown) & BIT(padno % NPADS_IN_GPP));
183 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
185 struct intel_community *community;
186 unsigned padno, gpp, offset;
189 community = intel_get_community(pctrl, pin);
192 if (!community->padcfglock_offset)
195 padno = pin_to_padno(community, pin);
196 gpp = padno / NPADS_IN_GPP;
199 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
200 * the pad is considered unlocked. Any other case means that it is
201 * either fully or partially locked and we don't touch it.
203 offset = community->padcfglock_offset + gpp * 8;
204 value = readl(community->regs + offset);
205 if (value & BIT(pin % NPADS_IN_GPP))
208 offset = community->padcfglock_offset + 4 + gpp * 8;
209 value = readl(community->regs + offset);
210 if (value & BIT(pin % NPADS_IN_GPP))
216 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
218 return intel_pad_owned_by_host(pctrl, pin) &&
219 !intel_pad_locked(pctrl, pin);
222 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
224 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
226 return pctrl->soc->ngroups;
229 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
232 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
234 return pctrl->soc->groups[group].name;
237 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
238 const unsigned **pins, unsigned *npins)
240 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
242 *pins = pctrl->soc->groups[group].pins;
243 *npins = pctrl->soc->groups[group].npins;
247 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
250 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
251 u32 cfg0, cfg1, mode;
254 if (!intel_pad_owned_by_host(pctrl, pin)) {
255 seq_puts(s, "not available");
259 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
260 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
262 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
264 seq_puts(s, "GPIO ");
266 seq_printf(s, "mode %d ", mode);
268 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
270 locked = intel_pad_locked(pctrl, pin);
271 acpi = intel_pad_acpi_mode(pctrl, pin);
273 if (locked || acpi) {
276 seq_puts(s, "LOCKED");
286 static const struct pinctrl_ops intel_pinctrl_ops = {
287 .get_groups_count = intel_get_groups_count,
288 .get_group_name = intel_get_group_name,
289 .get_group_pins = intel_get_group_pins,
290 .pin_dbg_show = intel_pin_dbg_show,
293 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
295 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
297 return pctrl->soc->nfunctions;
300 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
303 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
305 return pctrl->soc->functions[function].name;
308 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
310 const char * const **groups,
311 unsigned * const ngroups)
313 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
315 *groups = pctrl->soc->functions[function].groups;
316 *ngroups = pctrl->soc->functions[function].ngroups;
320 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
323 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
324 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
328 spin_lock_irqsave(&pctrl->lock, flags);
331 * All pins in the groups needs to be accessible and writable
332 * before we can enable the mux for this group.
334 for (i = 0; i < grp->npins; i++) {
335 if (!intel_pad_usable(pctrl, grp->pins[i])) {
336 spin_unlock_irqrestore(&pctrl->lock, flags);
341 /* Now enable the mux setting for each pin in the group */
342 for (i = 0; i < grp->npins; i++) {
343 void __iomem *padcfg0;
346 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
347 value = readl(padcfg0);
349 value &= ~PADCFG0_PMODE_MASK;
350 value |= grp->mode << PADCFG0_PMODE_SHIFT;
352 writel(value, padcfg0);
355 spin_unlock_irqrestore(&pctrl->lock, flags);
360 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
361 struct pinctrl_gpio_range *range,
364 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
365 void __iomem *padcfg0;
369 spin_lock_irqsave(&pctrl->lock, flags);
371 if (!intel_pad_usable(pctrl, pin)) {
372 spin_unlock_irqrestore(&pctrl->lock, flags);
376 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
377 /* Put the pad into GPIO mode */
378 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
379 /* Disable SCI/SMI/NMI generation */
380 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
381 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
382 /* Disable TX buffer and enable RX (this will be input) */
383 value &= ~PADCFG0_GPIORXDIS;
384 value |= PADCFG0_GPIOTXDIS;
385 writel(value, padcfg0);
387 spin_unlock_irqrestore(&pctrl->lock, flags);
392 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
393 struct pinctrl_gpio_range *range,
394 unsigned pin, bool input)
396 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
397 void __iomem *padcfg0;
401 spin_lock_irqsave(&pctrl->lock, flags);
403 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
405 value = readl(padcfg0);
407 value |= PADCFG0_GPIOTXDIS;
409 value &= ~PADCFG0_GPIOTXDIS;
410 writel(value, padcfg0);
412 spin_unlock_irqrestore(&pctrl->lock, flags);
417 static const struct pinmux_ops intel_pinmux_ops = {
418 .get_functions_count = intel_get_functions_count,
419 .get_function_name = intel_get_function_name,
420 .get_function_groups = intel_get_function_groups,
421 .set_mux = intel_pinmux_set_mux,
422 .gpio_request_enable = intel_gpio_request_enable,
423 .gpio_set_direction = intel_gpio_set_direction,
426 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
427 unsigned long *config)
429 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
430 enum pin_config_param param = pinconf_to_config_param(*config);
434 if (!intel_pad_owned_by_host(pctrl, pin))
437 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
438 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
441 case PIN_CONFIG_BIAS_DISABLE:
446 case PIN_CONFIG_BIAS_PULL_UP:
447 if (!term || !(value & PADCFG1_TERM_UP))
451 case PADCFG1_TERM_1K:
454 case PADCFG1_TERM_2K:
457 case PADCFG1_TERM_5K:
460 case PADCFG1_TERM_20K:
467 case PIN_CONFIG_BIAS_PULL_DOWN:
468 if (!term || value & PADCFG1_TERM_UP)
472 case PADCFG1_TERM_5K:
475 case PADCFG1_TERM_20K:
486 *config = pinconf_to_config_packed(param, arg);
490 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
491 unsigned long config)
493 unsigned param = pinconf_to_config_param(config);
494 unsigned arg = pinconf_to_config_argument(config);
495 void __iomem *padcfg1;
500 spin_lock_irqsave(&pctrl->lock, flags);
502 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
503 value = readl(padcfg1);
506 case PIN_CONFIG_BIAS_DISABLE:
507 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
510 case PIN_CONFIG_BIAS_PULL_UP:
511 value &= ~PADCFG1_TERM_MASK;
513 value |= PADCFG1_TERM_UP;
517 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
520 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
523 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
526 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
534 case PIN_CONFIG_BIAS_PULL_DOWN:
535 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
539 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
542 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
552 writel(value, padcfg1);
554 spin_unlock_irqrestore(&pctrl->lock, flags);
559 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
560 unsigned long *configs, unsigned nconfigs)
562 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
565 if (!intel_pad_usable(pctrl, pin))
568 for (i = 0; i < nconfigs; i++) {
569 switch (pinconf_to_config_param(configs[i])) {
570 case PIN_CONFIG_BIAS_DISABLE:
571 case PIN_CONFIG_BIAS_PULL_UP:
572 case PIN_CONFIG_BIAS_PULL_DOWN:
573 ret = intel_config_set_pull(pctrl, pin, configs[i]);
586 static const struct pinconf_ops intel_pinconf_ops = {
588 .pin_config_get = intel_config_get,
589 .pin_config_set = intel_config_set,
592 static const struct pinctrl_desc intel_pinctrl_desc = {
593 .pctlops = &intel_pinctrl_ops,
594 .pmxops = &intel_pinmux_ops,
595 .confops = &intel_pinconf_ops,
596 .owner = THIS_MODULE,
599 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
601 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
604 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
608 return !!(readl(reg) & PADCFG0_GPIORXSTATE);
611 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
613 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
616 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
621 spin_lock_irqsave(&pctrl->lock, flags);
622 padcfg0 = readl(reg);
624 padcfg0 |= PADCFG0_GPIOTXSTATE;
626 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
627 writel(padcfg0, reg);
628 spin_unlock_irqrestore(&pctrl->lock, flags);
632 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
634 return pinctrl_gpio_direction_input(chip->base + offset);
637 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
640 intel_gpio_set(chip, offset, value);
641 return pinctrl_gpio_direction_output(chip->base + offset);
644 static const struct gpio_chip intel_gpio_chip = {
645 .owner = THIS_MODULE,
646 .request = gpiochip_generic_request,
647 .free = gpiochip_generic_free,
648 .direction_input = intel_gpio_direction_input,
649 .direction_output = intel_gpio_direction_output,
650 .get = intel_gpio_get,
651 .set = intel_gpio_set,
654 static void intel_gpio_irq_ack(struct irq_data *d)
656 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
657 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
658 const struct intel_community *community;
659 unsigned pin = irqd_to_hwirq(d);
661 spin_lock(&pctrl->lock);
663 community = intel_get_community(pctrl, pin);
665 unsigned padno = pin_to_padno(community, pin);
666 unsigned gpp_offset = padno % NPADS_IN_GPP;
667 unsigned gpp = padno / NPADS_IN_GPP;
669 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
672 spin_unlock(&pctrl->lock);
675 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
677 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
678 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
679 const struct intel_community *community;
680 unsigned pin = irqd_to_hwirq(d);
683 spin_lock_irqsave(&pctrl->lock, flags);
685 community = intel_get_community(pctrl, pin);
687 unsigned padno = pin_to_padno(community, pin);
688 unsigned gpp_offset = padno % NPADS_IN_GPP;
689 unsigned gpp = padno / NPADS_IN_GPP;
693 reg = community->regs + community->ie_offset + gpp * 4;
696 value &= ~BIT(gpp_offset);
698 value |= BIT(gpp_offset);
702 spin_unlock_irqrestore(&pctrl->lock, flags);
705 static void intel_gpio_irq_mask(struct irq_data *d)
707 intel_gpio_irq_mask_unmask(d, true);
710 static void intel_gpio_irq_unmask(struct irq_data *d)
712 intel_gpio_irq_mask_unmask(d, false);
715 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
717 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
718 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
719 unsigned pin = irqd_to_hwirq(d);
724 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
729 * If the pin is in ACPI mode it is still usable as a GPIO but it
730 * cannot be used as IRQ because GPI_IS status bit will not be
731 * updated by the host controller hardware.
733 if (intel_pad_acpi_mode(pctrl, pin)) {
734 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
738 spin_lock_irqsave(&pctrl->lock, flags);
742 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
744 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
745 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
746 } else if (type & IRQ_TYPE_EDGE_FALLING) {
747 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
748 value |= PADCFG0_RXINV;
749 } else if (type & IRQ_TYPE_EDGE_RISING) {
750 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
751 } else if (type & IRQ_TYPE_LEVEL_LOW) {
752 value |= PADCFG0_RXINV;
754 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
759 if (type & IRQ_TYPE_EDGE_BOTH)
760 irq_set_handler_locked(d, handle_edge_irq);
761 else if (type & IRQ_TYPE_LEVEL_MASK)
762 irq_set_handler_locked(d, handle_level_irq);
764 spin_unlock_irqrestore(&pctrl->lock, flags);
769 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
771 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
772 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
773 const struct intel_community *community;
774 unsigned pin = irqd_to_hwirq(d);
775 unsigned padno, gpp, gpp_offset;
778 community = intel_get_community(pctrl, pin);
782 padno = pin_to_padno(community, pin);
783 gpp = padno / NPADS_IN_GPP;
784 gpp_offset = padno % NPADS_IN_GPP;
786 /* Clear the existing wake status */
787 writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4);
790 * The controller will generate wake when GPE of the corresponding
791 * pad is enabled and it is not routed to SCI (GPIROUTSCI is not
794 gpe_en = readl(community->regs + GPI_GPE_EN + gpp * 4);
796 gpe_en |= BIT(gpp_offset);
798 gpe_en &= ~BIT(gpp_offset);
799 writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4);
801 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
805 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
806 const struct intel_community *community)
808 struct gpio_chip *gc = &pctrl->chip;
809 irqreturn_t ret = IRQ_NONE;
812 for (gpp = 0; gpp < community->ngpps; gpp++) {
813 unsigned long pending, enabled, gpp_offset;
815 pending = readl(community->regs + GPI_IS + gpp * 4);
816 enabled = readl(community->regs + community->ie_offset +
819 /* Only interrupts that are enabled */
822 for_each_set_bit(gpp_offset, &pending, NPADS_IN_GPP) {
826 * The last group in community can have less pins
829 padno = gpp_offset + gpp * NPADS_IN_GPP;
830 if (padno >= community->npins)
833 irq = irq_find_mapping(gc->irqdomain,
834 community->pin_base + padno);
835 generic_handle_irq(irq);
844 static irqreturn_t intel_gpio_irq(int irq, void *data)
846 const struct intel_community *community;
847 struct intel_pinctrl *pctrl = data;
848 irqreturn_t ret = IRQ_NONE;
851 /* Need to check all communities for pending interrupts */
852 for (i = 0; i < pctrl->ncommunities; i++) {
853 community = &pctrl->communities[i];
854 ret |= intel_gpio_community_irq_handler(pctrl, community);
860 static struct irq_chip intel_gpio_irqchip = {
861 .name = "intel-gpio",
862 .irq_ack = intel_gpio_irq_ack,
863 .irq_mask = intel_gpio_irq_mask,
864 .irq_unmask = intel_gpio_irq_unmask,
865 .irq_set_type = intel_gpio_irq_type,
866 .irq_set_wake = intel_gpio_irq_wake,
869 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
873 pctrl->chip = intel_gpio_chip;
875 pctrl->chip.ngpio = pctrl->soc->npins;
876 pctrl->chip.label = dev_name(pctrl->dev);
877 pctrl->chip.dev = pctrl->dev;
878 pctrl->chip.base = -1;
880 ret = gpiochip_add(&pctrl->chip);
882 dev_err(pctrl->dev, "failed to register gpiochip\n");
886 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
887 0, 0, pctrl->soc->npins);
889 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
894 * We need to request the interrupt here (instead of providing chip
895 * to the irq directly) because on some platforms several GPIO
896 * controllers share the same interrupt line.
898 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED,
899 dev_name(pctrl->dev), pctrl);
901 dev_err(pctrl->dev, "failed to request interrupt\n");
905 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
906 handle_simple_irq, IRQ_TYPE_NONE);
908 dev_err(pctrl->dev, "failed to add irqchip\n");
912 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
917 gpiochip_remove(&pctrl->chip);
922 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
924 #ifdef CONFIG_PM_SLEEP
925 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
926 struct intel_community_context *communities;
927 struct intel_pad_context *pads;
930 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
934 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
935 sizeof(*communities), GFP_KERNEL);
940 for (i = 0; i < pctrl->ncommunities; i++) {
941 struct intel_community *community = &pctrl->communities[i];
944 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
945 sizeof(*intmask), GFP_KERNEL);
949 communities[i].intmask = intmask;
952 pctrl->context.pads = pads;
953 pctrl->context.communities = communities;
959 int intel_pinctrl_probe(struct platform_device *pdev,
960 const struct intel_pinctrl_soc_data *soc_data)
962 struct intel_pinctrl *pctrl;
968 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
972 pctrl->dev = &pdev->dev;
973 pctrl->soc = soc_data;
974 spin_lock_init(&pctrl->lock);
977 * Make a copy of the communities which we can use to hold pointers
980 pctrl->ncommunities = pctrl->soc->ncommunities;
981 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
982 sizeof(*pctrl->communities), GFP_KERNEL);
983 if (!pctrl->communities)
986 for (i = 0; i < pctrl->ncommunities; i++) {
987 struct intel_community *community = &pctrl->communities[i];
988 struct resource *res;
992 *community = pctrl->soc->communities[i];
994 res = platform_get_resource(pdev, IORESOURCE_MEM,
996 regs = devm_ioremap_resource(&pdev->dev, res);
998 return PTR_ERR(regs);
1000 /* Read offset of the pad configuration registers */
1001 padbar = readl(regs + PADBAR);
1003 community->regs = regs;
1004 community->pad_regs = regs + padbar;
1005 community->ngpps = DIV_ROUND_UP(community->npins, NPADS_IN_GPP);
1008 irq = platform_get_irq(pdev, 0);
1010 dev_err(&pdev->dev, "failed to get interrupt number\n");
1014 ret = intel_pinctrl_pm_init(pctrl);
1018 pctrl->pctldesc = intel_pinctrl_desc;
1019 pctrl->pctldesc.name = dev_name(&pdev->dev);
1020 pctrl->pctldesc.pins = pctrl->soc->pins;
1021 pctrl->pctldesc.npins = pctrl->soc->npins;
1023 pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl);
1024 if (IS_ERR(pctrl->pctldev)) {
1025 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1026 return PTR_ERR(pctrl->pctldev);
1029 ret = intel_gpio_probe(pctrl, irq);
1031 pinctrl_unregister(pctrl->pctldev);
1035 platform_set_drvdata(pdev, pctrl);
1039 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1041 int intel_pinctrl_remove(struct platform_device *pdev)
1043 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1045 gpiochip_remove(&pctrl->chip);
1046 pinctrl_unregister(pctrl->pctldev);
1050 EXPORT_SYMBOL_GPL(intel_pinctrl_remove);
1052 #ifdef CONFIG_PM_SLEEP
1053 int intel_pinctrl_suspend(struct device *dev)
1055 struct platform_device *pdev = to_platform_device(dev);
1056 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1057 struct intel_community_context *communities;
1058 struct intel_pad_context *pads;
1061 pads = pctrl->context.pads;
1062 for (i = 0; i < pctrl->soc->npins; i++) {
1063 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1066 if (!intel_pad_usable(pctrl, desc->number))
1069 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1070 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1071 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1072 pads[i].padcfg1 = val;
1075 communities = pctrl->context.communities;
1076 for (i = 0; i < pctrl->ncommunities; i++) {
1077 struct intel_community *community = &pctrl->communities[i];
1081 base = community->regs + community->ie_offset;
1082 for (gpp = 0; gpp < community->ngpps; gpp++)
1083 communities[i].intmask[gpp] = readl(base + gpp * 4);
1088 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1090 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1094 for (i = 0; i < pctrl->ncommunities; i++) {
1095 const struct intel_community *community;
1099 community = &pctrl->communities[i];
1100 base = community->regs;
1102 for (gpp = 0; gpp < community->ngpps; gpp++) {
1103 /* Mask and clear all interrupts */
1104 writel(0, base + community->ie_offset + gpp * 4);
1105 writel(0xffff, base + GPI_IS + gpp * 4);
1110 int intel_pinctrl_resume(struct device *dev)
1112 struct platform_device *pdev = to_platform_device(dev);
1113 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1114 const struct intel_community_context *communities;
1115 const struct intel_pad_context *pads;
1118 /* Mask all interrupts */
1119 intel_gpio_irq_init(pctrl);
1121 pads = pctrl->context.pads;
1122 for (i = 0; i < pctrl->soc->npins; i++) {
1123 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1124 void __iomem *padcfg;
1127 if (!intel_pad_usable(pctrl, desc->number))
1130 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1131 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1132 if (val != pads[i].padcfg0) {
1133 writel(pads[i].padcfg0, padcfg);
1134 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1135 desc->number, readl(padcfg));
1138 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1139 val = readl(padcfg);
1140 if (val != pads[i].padcfg1) {
1141 writel(pads[i].padcfg1, padcfg);
1142 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1143 desc->number, readl(padcfg));
1147 communities = pctrl->context.communities;
1148 for (i = 0; i < pctrl->ncommunities; i++) {
1149 struct intel_community *community = &pctrl->communities[i];
1153 base = community->regs + community->ie_offset;
1154 for (gpp = 0; gpp < community->ngpps; gpp++) {
1155 writel(communities[i].intmask[gpp], base + gpp * 4);
1156 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1157 readl(base + gpp * 4));
1163 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1166 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1167 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1168 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1169 MODULE_LICENSE("GPL v2");