1 // SPDX-License-Identifier: GPL-2.0
3 * Intel pinctrl/GPIO core driver.
5 * Copyright (C) 2015, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
10 #include <linux/acpi.h>
11 #include <linux/cleanup.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/interrupt.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/property.h>
18 #include <linux/seq_file.h>
19 #include <linux/string_helpers.h>
20 #include <linux/time.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
28 #include <linux/platform_data/x86/pwm-lpss.h>
31 #include "pinctrl-intel.h"
33 /* Offset from regs */
35 #define REVID_SHIFT 16
36 #define REVID_MASK GENMASK(31, 16)
39 #define CAPLIST_ID_SHIFT 16
40 #define CAPLIST_ID_MASK GENMASK(23, 16)
41 #define CAPLIST_ID_GPIO_HW_INFO 1
42 #define CAPLIST_ID_PWM 2
43 #define CAPLIST_ID_BLINK 3
44 #define CAPLIST_ID_EXP 4
45 #define CAPLIST_NEXT_SHIFT 0
46 #define CAPLIST_NEXT_MASK GENMASK(15, 0)
51 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
52 #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
53 #define PADOWN_GPP(p) ((p) / 8)
57 /* Offset from pad_regs */
59 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
60 #define PADCFG0_RXEVCFG_LEVEL (0 << 25)
61 #define PADCFG0_RXEVCFG_EDGE (1 << 25)
62 #define PADCFG0_RXEVCFG_DISABLED (2 << 25)
63 #define PADCFG0_RXEVCFG_EDGE_BOTH (3 << 25)
64 #define PADCFG0_PREGFRXSEL BIT(24)
65 #define PADCFG0_RXINV BIT(23)
66 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
67 #define PADCFG0_GPIROUTSCI BIT(19)
68 #define PADCFG0_GPIROUTSMI BIT(18)
69 #define PADCFG0_GPIROUTNMI BIT(17)
70 #define PADCFG0_PMODE_SHIFT 10
71 #define PADCFG0_PMODE_MASK GENMASK(13, 10)
72 #define PADCFG0_PMODE_GPIO 0
73 #define PADCFG0_GPIORXDIS BIT(9)
74 #define PADCFG0_GPIOTXDIS BIT(8)
75 #define PADCFG0_GPIORXSTATE BIT(1)
76 #define PADCFG0_GPIOTXSTATE BIT(0)
79 #define PADCFG1_TERM_UP BIT(13)
80 #define PADCFG1_TERM_SHIFT 10
81 #define PADCFG1_TERM_MASK GENMASK(12, 10)
82 #define PADCFG1_TERM_20K BIT(2)
83 #define PADCFG1_TERM_5K BIT(1)
84 #define PADCFG1_TERM_4K (BIT(2) | BIT(1))
85 #define PADCFG1_TERM_1K BIT(0)
86 #define PADCFG1_TERM_952 (BIT(2) | BIT(0))
87 #define PADCFG1_TERM_833 (BIT(1) | BIT(0))
88 #define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0))
91 #define PADCFG2_DEBOUNCE_SHIFT 1
92 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
93 #define PADCFG2_DEBEN BIT(0)
95 #define DEBOUNCE_PERIOD_NSEC 31250
97 struct intel_pad_context {
103 struct intel_community_context {
108 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
109 #define padgroup_offset(g, p) ((p) - (g)->base)
111 struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned int pin)
113 struct intel_community *community;
116 for (i = 0; i < pctrl->ncommunities; i++) {
117 community = &pctrl->communities[i];
118 if (pin >= community->pin_base &&
119 pin < community->pin_base + community->npins)
123 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
126 EXPORT_SYMBOL_NS_GPL(intel_get_community, PINCTRL_INTEL);
128 static const struct intel_padgroup *
129 intel_community_get_padgroup(const struct intel_community *community,
134 for (i = 0; i < community->ngpps; i++) {
135 const struct intel_padgroup *padgrp = &community->gpps[i];
137 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
144 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
145 unsigned int pin, unsigned int reg)
147 const struct intel_community *community;
151 community = intel_get_community(pctrl, pin);
155 padno = pin_to_padno(community, pin);
156 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
158 if (reg >= nregs * 4)
161 return community->pad_regs + reg + padno * nregs * 4;
164 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
166 const struct intel_community *community;
167 const struct intel_padgroup *padgrp;
168 unsigned int gpp, offset, gpp_offset;
169 void __iomem *padown;
171 community = intel_get_community(pctrl, pin);
174 if (!community->padown_offset)
177 padgrp = intel_community_get_padgroup(community, pin);
181 gpp_offset = padgroup_offset(padgrp, pin);
182 gpp = PADOWN_GPP(gpp_offset);
183 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
184 padown = community->regs + offset;
186 return !(readl(padown) & PADOWN_MASK(gpp_offset));
189 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
191 const struct intel_community *community;
192 const struct intel_padgroup *padgrp;
193 unsigned int offset, gpp_offset;
194 void __iomem *hostown;
196 community = intel_get_community(pctrl, pin);
199 if (!community->hostown_offset)
202 padgrp = intel_community_get_padgroup(community, pin);
206 gpp_offset = padgroup_offset(padgrp, pin);
207 offset = community->hostown_offset + padgrp->reg_num * 4;
208 hostown = community->regs + offset;
210 return !(readl(hostown) & BIT(gpp_offset));
214 * enum - Locking variants of the pad configuration
216 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers
217 * @PAD_LOCKED: pad configuration registers, except TX state, are locked
218 * @PAD_LOCKED_TX: pad configuration TX state is locked
219 * @PAD_LOCKED_FULL: pad configuration registers are locked completely
221 * Locking is considered as read-only mode for corresponding registers and
222 * their respective fields. That said, TX state bit is locked separately from
223 * the main locking scheme.
229 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
232 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
234 struct intel_community *community;
235 const struct intel_padgroup *padgrp;
236 unsigned int offset, gpp_offset;
238 int ret = PAD_UNLOCKED;
240 community = intel_get_community(pctrl, pin);
242 return PAD_LOCKED_FULL;
243 if (!community->padcfglock_offset)
246 padgrp = intel_community_get_padgroup(community, pin);
248 return PAD_LOCKED_FULL;
250 gpp_offset = padgroup_offset(padgrp, pin);
253 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
254 * the pad is considered unlocked. Any other case means that it is
255 * either fully or partially locked.
257 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
258 value = readl(community->regs + offset);
259 if (value & BIT(gpp_offset))
262 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
263 value = readl(community->regs + offset);
264 if (value & BIT(gpp_offset))
265 ret |= PAD_LOCKED_TX;
270 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
272 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
275 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
277 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
280 int intel_get_groups_count(struct pinctrl_dev *pctldev)
282 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
284 return pctrl->soc->ngroups;
286 EXPORT_SYMBOL_NS_GPL(intel_get_groups_count, PINCTRL_INTEL);
288 const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group)
290 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
292 return pctrl->soc->groups[group].grp.name;
294 EXPORT_SYMBOL_NS_GPL(intel_get_group_name, PINCTRL_INTEL);
296 int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
297 const unsigned int **pins, unsigned int *npins)
299 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
301 *pins = pctrl->soc->groups[group].grp.pins;
302 *npins = pctrl->soc->groups[group].grp.npins;
305 EXPORT_SYMBOL_NS_GPL(intel_get_group_pins, PINCTRL_INTEL);
307 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
310 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
311 void __iomem *padcfg;
312 u32 cfg0, cfg1, mode;
316 if (!intel_pad_owned_by_host(pctrl, pin)) {
317 seq_puts(s, "not available");
321 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
322 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
324 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
325 if (mode == PADCFG0_PMODE_GPIO)
326 seq_puts(s, "GPIO ");
328 seq_printf(s, "mode %d ", mode);
330 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
332 /* Dump the additional PADCFG registers if available */
333 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
335 seq_printf(s, " 0x%08x", readl(padcfg));
337 locked = intel_pad_locked(pctrl, pin);
338 acpi = intel_pad_acpi_mode(pctrl, pin);
340 if (locked || acpi) {
343 seq_puts(s, "LOCKED");
344 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
346 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
347 seq_puts(s, " full");
358 static const struct pinctrl_ops intel_pinctrl_ops = {
359 .get_groups_count = intel_get_groups_count,
360 .get_group_name = intel_get_group_name,
361 .get_group_pins = intel_get_group_pins,
362 .pin_dbg_show = intel_pin_dbg_show,
365 int intel_get_functions_count(struct pinctrl_dev *pctldev)
367 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
369 return pctrl->soc->nfunctions;
371 EXPORT_SYMBOL_NS_GPL(intel_get_functions_count, PINCTRL_INTEL);
373 const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function)
375 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
377 return pctrl->soc->functions[function].func.name;
379 EXPORT_SYMBOL_NS_GPL(intel_get_function_name, PINCTRL_INTEL);
381 int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
382 const char * const **groups, unsigned int * const ngroups)
384 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
386 *groups = pctrl->soc->functions[function].func.groups;
387 *ngroups = pctrl->soc->functions[function].func.ngroups;
390 EXPORT_SYMBOL_NS_GPL(intel_get_function_groups, PINCTRL_INTEL);
392 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
393 unsigned int function, unsigned int group)
395 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
396 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
399 guard(raw_spinlock_irqsave)(&pctrl->lock);
402 * All pins in the groups needs to be accessible and writable
403 * before we can enable the mux for this group.
405 for (i = 0; i < grp->grp.npins; i++) {
406 if (!intel_pad_usable(pctrl, grp->grp.pins[i]))
410 /* Now enable the mux setting for each pin in the group */
411 for (i = 0; i < grp->grp.npins; i++) {
412 void __iomem *padcfg0;
415 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0);
417 value = readl(padcfg0);
418 value &= ~PADCFG0_PMODE_MASK;
421 pmode = grp->modes[i];
425 value |= pmode << PADCFG0_PMODE_SHIFT;
426 writel(value, padcfg0);
432 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
436 value = readl(padcfg0);
438 value &= ~PADCFG0_GPIORXDIS;
439 value |= PADCFG0_GPIOTXDIS;
441 value &= ~PADCFG0_GPIOTXDIS;
442 value |= PADCFG0_GPIORXDIS;
444 writel(value, padcfg0);
447 static int __intel_gpio_get_gpio_mode(u32 value)
449 return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
452 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
454 return __intel_gpio_get_gpio_mode(readl(padcfg0));
457 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
461 value = readl(padcfg0);
463 /* Put the pad into GPIO mode */
464 value &= ~PADCFG0_PMODE_MASK;
465 value |= PADCFG0_PMODE_GPIO;
467 /* Disable TX buffer and enable RX (this will be input) */
468 value &= ~PADCFG0_GPIORXDIS;
469 value |= PADCFG0_GPIOTXDIS;
471 /* Disable SCI/SMI/NMI generation */
472 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
473 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
475 writel(value, padcfg0);
478 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
479 struct pinctrl_gpio_range *range,
482 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
483 void __iomem *padcfg0;
485 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
487 guard(raw_spinlock_irqsave)(&pctrl->lock);
489 if (!intel_pad_owned_by_host(pctrl, pin))
492 if (!intel_pad_is_unlocked(pctrl, pin))
496 * If pin is already configured in GPIO mode, we assume that
497 * firmware provides correct settings. In such case we avoid
498 * potential glitches on the pin. Otherwise, for the pin in
499 * alternative mode, consumer has to supply respective flags.
501 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO)
504 intel_gpio_set_gpio_mode(padcfg0);
509 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
510 struct pinctrl_gpio_range *range,
511 unsigned int pin, bool input)
513 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
514 void __iomem *padcfg0;
516 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
518 guard(raw_spinlock_irqsave)(&pctrl->lock);
520 __intel_gpio_set_direction(padcfg0, input);
525 static const struct pinmux_ops intel_pinmux_ops = {
526 .get_functions_count = intel_get_functions_count,
527 .get_function_name = intel_get_function_name,
528 .get_function_groups = intel_get_function_groups,
529 .set_mux = intel_pinmux_set_mux,
530 .gpio_request_enable = intel_gpio_request_enable,
531 .gpio_set_direction = intel_gpio_set_direction,
534 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
535 enum pin_config_param param, u32 *arg)
537 void __iomem *padcfg1;
540 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
542 scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
543 value = readl(padcfg1);
545 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
548 case PIN_CONFIG_BIAS_DISABLE:
553 case PIN_CONFIG_BIAS_PULL_UP:
554 if (!term || !(value & PADCFG1_TERM_UP))
558 case PADCFG1_TERM_833:
561 case PADCFG1_TERM_1K:
564 case PADCFG1_TERM_4K:
567 case PADCFG1_TERM_5K:
570 case PADCFG1_TERM_20K:
577 case PIN_CONFIG_BIAS_PULL_DOWN: {
578 const struct intel_community *community = intel_get_community(pctrl, pin);
580 if (!term || value & PADCFG1_TERM_UP)
584 case PADCFG1_TERM_833:
585 if (!(community->features & PINCTRL_FEATURE_1K_PD))
589 case PADCFG1_TERM_1K:
590 if (!(community->features & PINCTRL_FEATURE_1K_PD))
594 case PADCFG1_TERM_4K:
597 case PADCFG1_TERM_5K:
600 case PADCFG1_TERM_20K:
615 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
616 enum pin_config_param param, u32 *arg)
618 void __iomem *padcfg2;
622 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
626 scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
627 value2 = readl(padcfg2);
629 if (!(value2 & PADCFG2_DEBEN))
632 v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
633 *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
638 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
639 unsigned long *config)
641 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
642 enum pin_config_param param = pinconf_to_config_param(*config);
646 if (!intel_pad_owned_by_host(pctrl, pin))
650 case PIN_CONFIG_BIAS_DISABLE:
651 case PIN_CONFIG_BIAS_PULL_UP:
652 case PIN_CONFIG_BIAS_PULL_DOWN:
653 ret = intel_config_get_pull(pctrl, pin, param, &arg);
658 case PIN_CONFIG_INPUT_DEBOUNCE:
659 ret = intel_config_get_debounce(pctrl, pin, param, &arg);
668 *config = pinconf_to_config_packed(param, arg);
672 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
673 unsigned long config)
675 unsigned int param = pinconf_to_config_param(config);
676 unsigned int arg = pinconf_to_config_argument(config);
677 u32 term = 0, up = 0, value;
678 void __iomem *padcfg1;
681 case PIN_CONFIG_BIAS_DISABLE:
684 case PIN_CONFIG_BIAS_PULL_UP:
687 term = PADCFG1_TERM_20K;
689 case 1: /* Set default strength value in case none is given */
691 term = PADCFG1_TERM_5K;
694 term = PADCFG1_TERM_4K;
697 term = PADCFG1_TERM_1K;
700 term = PADCFG1_TERM_833;
706 up = PADCFG1_TERM_UP;
709 case PIN_CONFIG_BIAS_PULL_DOWN: {
710 const struct intel_community *community = intel_get_community(pctrl, pin);
714 term = PADCFG1_TERM_20K;
716 case 1: /* Set default strength value in case none is given */
718 term = PADCFG1_TERM_5K;
721 term = PADCFG1_TERM_4K;
724 if (!(community->features & PINCTRL_FEATURE_1K_PD))
726 term = PADCFG1_TERM_1K;
729 if (!(community->features & PINCTRL_FEATURE_1K_PD))
731 term = PADCFG1_TERM_833;
744 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
746 guard(raw_spinlock_irqsave)(&pctrl->lock);
748 value = readl(padcfg1);
749 value = (value & ~PADCFG1_TERM_MASK) | (term << PADCFG1_TERM_SHIFT);
750 value = (value & ~PADCFG1_TERM_UP) | up;
751 writel(value, padcfg1);
756 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
757 unsigned int pin, unsigned int debounce)
759 void __iomem *padcfg0, *padcfg2;
762 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
766 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
768 guard(raw_spinlock_irqsave)(&pctrl->lock);
770 value0 = readl(padcfg0);
771 value2 = readl(padcfg2);
773 /* Disable glitch filter and debouncer */
774 value0 &= ~PADCFG0_PREGFRXSEL;
775 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
780 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
784 /* Enable glitch filter and debouncer */
785 value0 |= PADCFG0_PREGFRXSEL;
786 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
787 value2 |= PADCFG2_DEBEN;
790 writel(value0, padcfg0);
791 writel(value2, padcfg2);
796 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
797 unsigned long *configs, unsigned int nconfigs)
799 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
802 if (!intel_pad_usable(pctrl, pin))
805 for (i = 0; i < nconfigs; i++) {
806 switch (pinconf_to_config_param(configs[i])) {
807 case PIN_CONFIG_BIAS_DISABLE:
808 case PIN_CONFIG_BIAS_PULL_UP:
809 case PIN_CONFIG_BIAS_PULL_DOWN:
810 ret = intel_config_set_pull(pctrl, pin, configs[i]);
815 case PIN_CONFIG_INPUT_DEBOUNCE:
816 ret = intel_config_set_debounce(pctrl, pin,
817 pinconf_to_config_argument(configs[i]));
830 static const struct pinconf_ops intel_pinconf_ops = {
832 .pin_config_get = intel_config_get,
833 .pin_config_set = intel_config_set,
836 static const struct pinctrl_desc intel_pinctrl_desc = {
837 .pctlops = &intel_pinctrl_ops,
838 .pmxops = &intel_pinmux_ops,
839 .confops = &intel_pinconf_ops,
840 .owner = THIS_MODULE,
844 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
845 * @pctrl: Pinctrl structure
846 * @offset: GPIO offset from gpiolib
847 * @community: Community is filled here if not %NULL
848 * @padgrp: Pad group is filled here if not %NULL
850 * When coming through gpiolib irqchip, the GPIO offset is not
851 * automatically translated to pinctrl pin number. This function can be
852 * used to find out the corresponding pinctrl pin.
854 * Return: a pin number and pointers to the community and pad group, which
855 * the pin belongs to, or negative error code if translation can't be done.
857 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
858 const struct intel_community **community,
859 const struct intel_padgroup **padgrp)
863 for (i = 0; i < pctrl->ncommunities; i++) {
864 const struct intel_community *comm = &pctrl->communities[i];
867 for (j = 0; j < comm->ngpps; j++) {
868 const struct intel_padgroup *pgrp = &comm->gpps[j];
870 if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
873 if (offset >= pgrp->gpio_base &&
874 offset < pgrp->gpio_base + pgrp->size) {
877 pin = pgrp->base + offset - pgrp->gpio_base;
892 * intel_pin_to_gpio() - Translate from pin number to GPIO offset
893 * @pctrl: Pinctrl structure
896 * Translate the pin number of pinctrl to GPIO offset
898 * Return: a GPIO offset, or negative error code if translation can't be done.
900 static int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
902 const struct intel_community *community;
903 const struct intel_padgroup *padgrp;
905 community = intel_get_community(pctrl, pin);
909 padgrp = intel_community_get_padgroup(community, pin);
913 return pin - padgrp->base + padgrp->gpio_base;
916 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
918 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
923 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
927 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
931 padcfg0 = readl(reg);
932 if (!(padcfg0 & PADCFG0_GPIOTXDIS))
933 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
935 return !!(padcfg0 & PADCFG0_GPIORXSTATE);
938 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
941 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
946 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
950 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
954 guard(raw_spinlock_irqsave)(&pctrl->lock);
956 padcfg0 = readl(reg);
958 padcfg0 |= PADCFG0_GPIOTXSTATE;
960 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
961 writel(padcfg0, reg);
964 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
966 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
971 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
975 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
979 scoped_guard(raw_spinlock_irqsave, &pctrl->lock)
980 padcfg0 = readl(reg);
982 if (padcfg0 & PADCFG0_PMODE_MASK)
985 if (padcfg0 & PADCFG0_GPIOTXDIS)
986 return GPIO_LINE_DIRECTION_IN;
988 return GPIO_LINE_DIRECTION_OUT;
991 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
993 return pinctrl_gpio_direction_input(chip, offset);
996 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
999 intel_gpio_set(chip, offset, value);
1000 return pinctrl_gpio_direction_output(chip, offset);
1003 static const struct gpio_chip intel_gpio_chip = {
1004 .owner = THIS_MODULE,
1005 .request = gpiochip_generic_request,
1006 .free = gpiochip_generic_free,
1007 .get_direction = intel_gpio_get_direction,
1008 .direction_input = intel_gpio_direction_input,
1009 .direction_output = intel_gpio_direction_output,
1010 .get = intel_gpio_get,
1011 .set = intel_gpio_set,
1012 .set_config = gpiochip_generic_config,
1015 static void intel_gpio_irq_ack(struct irq_data *d)
1017 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1018 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1019 const struct intel_community *community;
1020 const struct intel_padgroup *padgrp;
1023 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1025 unsigned int gpp, gpp_offset;
1028 gpp = padgrp->reg_num;
1029 gpp_offset = padgroup_offset(padgrp, pin);
1031 is = community->regs + community->is_offset + gpp * 4;
1033 guard(raw_spinlock)(&pctrl->lock);
1035 writel(BIT(gpp_offset), is);
1039 static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
1041 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1042 const struct intel_community *community;
1043 const struct intel_padgroup *padgrp;
1046 pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp);
1048 unsigned int gpp, gpp_offset;
1049 void __iomem *reg, *is;
1052 gpp = padgrp->reg_num;
1053 gpp_offset = padgroup_offset(padgrp, pin);
1055 reg = community->regs + community->ie_offset + gpp * 4;
1056 is = community->regs + community->is_offset + gpp * 4;
1058 guard(raw_spinlock_irqsave)(&pctrl->lock);
1060 /* Clear interrupt status first to avoid unexpected interrupt */
1061 writel(BIT(gpp_offset), is);
1065 value &= ~BIT(gpp_offset);
1067 value |= BIT(gpp_offset);
1072 static void intel_gpio_irq_mask(struct irq_data *d)
1074 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1075 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1077 intel_gpio_irq_mask_unmask(gc, hwirq, true);
1078 gpiochip_disable_irq(gc, hwirq);
1081 static void intel_gpio_irq_unmask(struct irq_data *d)
1083 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1084 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1086 gpiochip_enable_irq(gc, hwirq);
1087 intel_gpio_irq_mask_unmask(gc, hwirq, false);
1090 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1092 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1093 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1094 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1095 u32 rxevcfg, rxinv, value;
1098 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1103 * If the pin is in ACPI mode it is still usable as a GPIO but it
1104 * cannot be used as IRQ because GPI_IS status bit will not be
1105 * updated by the host controller hardware.
1107 if (intel_pad_acpi_mode(pctrl, pin)) {
1108 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1112 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1113 rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH;
1114 } else if (type & IRQ_TYPE_EDGE_FALLING) {
1115 rxevcfg = PADCFG0_RXEVCFG_EDGE;
1116 } else if (type & IRQ_TYPE_EDGE_RISING) {
1117 rxevcfg = PADCFG0_RXEVCFG_EDGE;
1118 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1119 rxevcfg = PADCFG0_RXEVCFG_LEVEL;
1121 rxevcfg = PADCFG0_RXEVCFG_DISABLED;
1124 if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW)
1125 rxinv = PADCFG0_RXINV;
1129 guard(raw_spinlock_irqsave)(&pctrl->lock);
1131 intel_gpio_set_gpio_mode(reg);
1135 value = (value & ~PADCFG0_RXEVCFG_MASK) | rxevcfg;
1136 value = (value & ~PADCFG0_RXINV) | rxinv;
1140 if (type & IRQ_TYPE_EDGE_BOTH)
1141 irq_set_handler_locked(d, handle_edge_irq);
1142 else if (type & IRQ_TYPE_LEVEL_MASK)
1143 irq_set_handler_locked(d, handle_level_irq);
1148 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1150 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1151 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1152 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1155 enable_irq_wake(pctrl->irq);
1157 disable_irq_wake(pctrl->irq);
1159 dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin);
1163 static const struct irq_chip intel_gpio_irq_chip = {
1164 .name = "intel-gpio",
1165 .irq_ack = intel_gpio_irq_ack,
1166 .irq_mask = intel_gpio_irq_mask,
1167 .irq_unmask = intel_gpio_irq_unmask,
1168 .irq_set_type = intel_gpio_irq_type,
1169 .irq_set_wake = intel_gpio_irq_wake,
1170 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
1171 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1174 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1175 const struct intel_community *community)
1177 struct gpio_chip *gc = &pctrl->chip;
1181 for (gpp = 0; gpp < community->ngpps; gpp++) {
1182 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1183 unsigned long pending, enabled;
1184 unsigned int gpp, gpp_offset;
1185 void __iomem *reg, *is;
1187 gpp = padgrp->reg_num;
1189 reg = community->regs + community->ie_offset + gpp * 4;
1190 is = community->regs + community->is_offset + gpp * 4;
1192 scoped_guard(raw_spinlock, &pctrl->lock) {
1193 pending = readl(is);
1194 enabled = readl(reg);
1197 /* Only interrupts that are enabled */
1200 for_each_set_bit(gpp_offset, &pending, padgrp->size)
1201 generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset);
1203 ret += pending ? 1 : 0;
1209 static irqreturn_t intel_gpio_irq(int irq, void *data)
1211 const struct intel_community *community;
1212 struct intel_pinctrl *pctrl = data;
1216 /* Need to check all communities for pending interrupts */
1217 for (i = 0; i < pctrl->ncommunities; i++) {
1218 community = &pctrl->communities[i];
1219 ret += intel_gpio_community_irq_handler(pctrl, community);
1222 return IRQ_RETVAL(ret);
1225 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1229 for (i = 0; i < pctrl->ncommunities; i++) {
1230 const struct intel_community *community;
1231 void __iomem *reg, *is;
1234 community = &pctrl->communities[i];
1236 for (gpp = 0; gpp < community->ngpps; gpp++) {
1237 reg = community->regs + community->ie_offset + gpp * 4;
1238 is = community->regs + community->is_offset + gpp * 4;
1240 /* Mask and clear all interrupts */
1247 static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
1249 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1252 * Make sure the interrupt lines are in a proper state before
1253 * further configuration.
1255 intel_gpio_irq_init(pctrl);
1260 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
1261 const struct intel_community *community)
1265 for (i = 0; i < community->ngpps; i++) {
1266 const struct intel_padgroup *gpp = &community->gpps[i];
1268 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1271 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1272 gpp->gpio_base, gpp->base,
1281 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1283 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1286 for (i = 0; i < pctrl->ncommunities; i++) {
1287 struct intel_community *community = &pctrl->communities[i];
1289 ret = intel_gpio_add_community_ranges(pctrl, community);
1291 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1299 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1301 const struct intel_community *community;
1302 unsigned int ngpio = 0;
1305 for (i = 0; i < pctrl->ncommunities; i++) {
1306 community = &pctrl->communities[i];
1307 for (j = 0; j < community->ngpps; j++) {
1308 const struct intel_padgroup *gpp = &community->gpps[j];
1310 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1313 if (gpp->gpio_base + gpp->size > ngpio)
1314 ngpio = gpp->gpio_base + gpp->size;
1321 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1324 struct gpio_irq_chip *girq;
1326 pctrl->chip = intel_gpio_chip;
1328 /* Setup GPIO chip */
1329 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1330 pctrl->chip.label = dev_name(pctrl->dev);
1331 pctrl->chip.parent = pctrl->dev;
1332 pctrl->chip.base = -1;
1333 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1337 * On some platforms several GPIO controllers share the same interrupt
1340 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1341 IRQF_SHARED | IRQF_NO_THREAD,
1342 dev_name(pctrl->dev), pctrl);
1344 dev_err(pctrl->dev, "failed to request interrupt\n");
1348 /* Setup IRQ chip */
1349 girq = &pctrl->chip.irq;
1350 gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip);
1351 /* This will let us handle the IRQ in the driver */
1352 girq->parent_handler = NULL;
1353 girq->num_parents = 0;
1354 girq->default_type = IRQ_TYPE_NONE;
1355 girq->handler = handle_bad_irq;
1356 girq->init_hw = intel_gpio_irq_init_hw;
1358 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1360 dev_err(pctrl->dev, "failed to register gpiochip\n");
1367 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
1368 struct intel_community *community)
1370 struct intel_padgroup *gpps;
1371 unsigned int padown_num = 0;
1372 size_t i, ngpps = community->ngpps;
1374 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1378 for (i = 0; i < ngpps; i++) {
1379 gpps[i] = community->gpps[i];
1381 if (gpps[i].size > INTEL_PINCTRL_MAX_GPP_SIZE)
1384 /* Special treatment for GPIO base */
1385 switch (gpps[i].gpio_base) {
1386 case INTEL_GPIO_BASE_MATCH:
1387 gpps[i].gpio_base = gpps[i].base;
1389 case INTEL_GPIO_BASE_ZERO:
1390 gpps[i].gpio_base = 0;
1392 case INTEL_GPIO_BASE_NOMAP:
1398 gpps[i].padown_num = padown_num;
1399 padown_num += DIV_ROUND_UP(gpps[i].size * 4, INTEL_PINCTRL_MAX_GPP_SIZE);
1402 community->gpps = gpps;
1407 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
1408 struct intel_community *community)
1410 struct intel_padgroup *gpps;
1411 unsigned int npins = community->npins;
1412 unsigned int padown_num = 0;
1413 size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
1415 if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE)
1418 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1422 for (i = 0; i < ngpps; i++) {
1423 unsigned int gpp_size = community->gpp_size;
1425 gpps[i].reg_num = i;
1426 gpps[i].base = community->pin_base + i * gpp_size;
1427 gpps[i].size = min(gpp_size, npins);
1428 npins -= gpps[i].size;
1430 gpps[i].gpio_base = gpps[i].base;
1431 gpps[i].padown_num = padown_num;
1433 padown_num += community->gpp_num_padown_regs;
1436 community->ngpps = ngpps;
1437 community->gpps = gpps;
1442 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1444 #ifdef CONFIG_PM_SLEEP
1445 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1446 struct intel_community_context *communities;
1447 struct intel_pad_context *pads;
1450 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1454 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1455 sizeof(*communities), GFP_KERNEL);
1460 for (i = 0; i < pctrl->ncommunities; i++) {
1461 struct intel_community *community = &pctrl->communities[i];
1462 u32 *intmask, *hostown;
1464 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1465 sizeof(*intmask), GFP_KERNEL);
1469 communities[i].intmask = intmask;
1471 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1472 sizeof(*hostown), GFP_KERNEL);
1476 communities[i].hostown = hostown;
1479 pctrl->context.pads = pads;
1480 pctrl->context.communities = communities;
1486 static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl,
1487 struct intel_community *community)
1489 static const struct pwm_lpss_boardinfo info = {
1490 .clk_rate = 19200000,
1492 .base_unit_bits = 22,
1495 struct pwm_lpss_chip *pwm;
1497 if (!(community->features & PINCTRL_FEATURE_PWM))
1500 if (!IS_REACHABLE(CONFIG_PWM_LPSS))
1503 pwm = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info);
1504 return PTR_ERR_OR_ZERO(pwm);
1507 int intel_pinctrl_probe(struct platform_device *pdev,
1508 const struct intel_pinctrl_soc_data *soc_data)
1510 struct device *dev = &pdev->dev;
1511 struct intel_pinctrl *pctrl;
1514 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1519 pctrl->soc = soc_data;
1520 raw_spin_lock_init(&pctrl->lock);
1523 * Make a copy of the communities which we can use to hold pointers
1526 pctrl->ncommunities = pctrl->soc->ncommunities;
1527 pctrl->communities = devm_kcalloc(dev, pctrl->ncommunities,
1528 sizeof(*pctrl->communities), GFP_KERNEL);
1529 if (!pctrl->communities)
1532 for (i = 0; i < pctrl->ncommunities; i++) {
1533 struct intel_community *community = &pctrl->communities[i];
1538 *community = pctrl->soc->communities[i];
1540 regs = devm_platform_ioremap_resource(pdev, community->barno);
1542 return PTR_ERR(regs);
1545 * Determine community features based on the revision.
1546 * A value of all ones means the device is not present.
1548 value = readl(regs + REVID);
1551 if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
1552 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1553 community->features |= PINCTRL_FEATURE_1K_PD;
1556 /* Determine community features based on the capabilities */
1559 value = readl(regs + offset);
1560 switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
1561 case CAPLIST_ID_GPIO_HW_INFO:
1562 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;
1564 case CAPLIST_ID_PWM:
1565 community->features |= PINCTRL_FEATURE_PWM;
1567 case CAPLIST_ID_BLINK:
1568 community->features |= PINCTRL_FEATURE_BLINK;
1570 case CAPLIST_ID_EXP:
1571 community->features |= PINCTRL_FEATURE_EXP;
1576 offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
1579 dev_dbg(dev, "Community%d features: %#08x\n", i, community->features);
1581 /* Read offset of the pad configuration registers */
1582 offset = readl(regs + PADBAR);
1584 community->regs = regs;
1585 community->pad_regs = regs + offset;
1587 if (community->gpps)
1588 ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community);
1590 ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
1594 ret = intel_pinctrl_probe_pwm(pctrl, community);
1599 irq = platform_get_irq(pdev, 0);
1603 ret = intel_pinctrl_pm_init(pctrl);
1607 pctrl->pctldesc = intel_pinctrl_desc;
1608 pctrl->pctldesc.name = dev_name(dev);
1609 pctrl->pctldesc.pins = pctrl->soc->pins;
1610 pctrl->pctldesc.npins = pctrl->soc->npins;
1612 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
1613 if (IS_ERR(pctrl->pctldev)) {
1614 dev_err(dev, "failed to register pinctrl driver\n");
1615 return PTR_ERR(pctrl->pctldev);
1618 ret = intel_gpio_probe(pctrl, irq);
1622 platform_set_drvdata(pdev, pctrl);
1626 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe, PINCTRL_INTEL);
1628 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1630 const struct intel_pinctrl_soc_data *data;
1632 data = device_get_match_data(&pdev->dev);
1636 return intel_pinctrl_probe(pdev, data);
1638 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_hid, PINCTRL_INTEL);
1640 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1642 const struct intel_pinctrl_soc_data *data;
1644 data = intel_pinctrl_get_soc_data(pdev);
1646 return PTR_ERR(data);
1648 return intel_pinctrl_probe(pdev, data);
1650 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_probe_by_uid, PINCTRL_INTEL);
1652 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
1654 const struct intel_pinctrl_soc_data * const *table;
1655 const struct intel_pinctrl_soc_data *data;
1656 struct device *dev = &pdev->dev;
1658 table = device_get_match_data(dev);
1660 struct acpi_device *adev = ACPI_COMPANION(dev);
1663 for (i = 0; table[i]; i++) {
1664 if (acpi_dev_uid_match(adev, table[i]->uid))
1669 const struct platform_device_id *id;
1671 id = platform_get_device_id(pdev);
1673 return ERR_PTR(-ENODEV);
1675 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data;
1676 data = table[pdev->id];
1679 return data ?: ERR_PTR(-ENODATA);
1681 EXPORT_SYMBOL_NS_GPL(intel_pinctrl_get_soc_data, PINCTRL_INTEL);
1683 static bool __intel_gpio_is_direct_irq(u32 value)
1685 return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
1686 (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
1689 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1691 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1694 if (!pd || !intel_pad_usable(pctrl, pin))
1698 * Only restore the pin if it is actually in use by the kernel (or
1699 * by userspace). It is possible that some pins are used by the
1700 * BIOS during resume and those are not always locked down so leave
1703 if (pd->mux_owner || pd->gpio_owner ||
1704 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1708 * The firmware on some systems may configure GPIO pins to be
1709 * an interrupt source in so called "direct IRQ" mode. In such
1710 * cases the GPIO controller driver has no idea if those pins
1711 * are being used or not. At the same time, there is a known bug
1712 * in the firmwares that don't restore the pin settings correctly
1713 * after suspend, i.e. by an unknown reason the Rx value becomes
1716 * Hence, let's save and restore the pins that are configured
1717 * as GPIOs in the input mode with GPIROUTIOXAPIC bit set.
1719 * See https://bugzilla.kernel.org/show_bug.cgi?id=214749.
1721 value = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
1722 if (__intel_gpio_is_direct_irq(value))
1728 static int intel_pinctrl_suspend_noirq(struct device *dev)
1730 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1731 struct intel_community_context *communities;
1732 struct intel_pad_context *pads;
1735 pads = pctrl->context.pads;
1736 for (i = 0; i < pctrl->soc->npins; i++) {
1737 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1738 void __iomem *padcfg;
1741 if (!intel_pinctrl_should_save(pctrl, desc->number))
1744 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1745 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1746 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1747 pads[i].padcfg1 = val;
1749 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1751 pads[i].padcfg2 = readl(padcfg);
1754 communities = pctrl->context.communities;
1755 for (i = 0; i < pctrl->ncommunities; i++) {
1756 struct intel_community *community = &pctrl->communities[i];
1760 base = community->regs + community->ie_offset;
1761 for (gpp = 0; gpp < community->ngpps; gpp++)
1762 communities[i].intmask[gpp] = readl(base + gpp * 4);
1764 base = community->regs + community->hostown_offset;
1765 for (gpp = 0; gpp < community->ngpps; gpp++)
1766 communities[i].hostown[gpp] = readl(base + gpp * 4);
1772 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1778 updated = (curr & ~mask) | (value & mask);
1779 if (curr == updated)
1782 writel(updated, reg);
1786 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1787 void __iomem *base, unsigned int gpp, u32 saved)
1789 const struct intel_community *community = &pctrl->communities[c];
1790 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1791 struct device *dev = pctrl->dev;
1796 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1799 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
1800 requested |= BIT(i);
1802 if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1805 dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1808 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1809 void __iomem *base, unsigned int gpp, u32 saved)
1811 struct device *dev = pctrl->dev;
1813 if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1816 dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1819 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1820 unsigned int reg, u32 saved)
1822 u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1823 unsigned int n = reg / sizeof(u32);
1824 struct device *dev = pctrl->dev;
1825 void __iomem *padcfg;
1827 padcfg = intel_get_padcfg(pctrl, pin, reg);
1831 if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1834 dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1837 static int intel_pinctrl_resume_noirq(struct device *dev)
1839 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1840 const struct intel_community_context *communities;
1841 const struct intel_pad_context *pads;
1844 /* Mask all interrupts */
1845 intel_gpio_irq_init(pctrl);
1847 pads = pctrl->context.pads;
1848 for (i = 0; i < pctrl->soc->npins; i++) {
1849 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1851 if (!(intel_pinctrl_should_save(pctrl, desc->number) ||
1853 * If the firmware mangled the register contents too much,
1854 * check the saved value for the Direct IRQ mode.
1856 __intel_gpio_is_direct_irq(pads[i].padcfg0)))
1859 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1860 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1861 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1864 communities = pctrl->context.communities;
1865 for (i = 0; i < pctrl->ncommunities; i++) {
1866 struct intel_community *community = &pctrl->communities[i];
1870 base = community->regs + community->ie_offset;
1871 for (gpp = 0; gpp < community->ngpps; gpp++)
1872 intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1874 base = community->regs + community->hostown_offset;
1875 for (gpp = 0; gpp < community->ngpps; gpp++)
1876 intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1882 EXPORT_NS_GPL_DEV_SLEEP_PM_OPS(intel_pinctrl_pm_ops, PINCTRL_INTEL) = {
1883 NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, intel_pinctrl_resume_noirq)
1886 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1887 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1888 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1889 MODULE_LICENSE("GPL v2");