drivers/pinctrl/intel/pinctrl-intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel pinctrl/GPIO core driver.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/gpio/driver.h>
  13 #include <linux/log2.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/property.h>
  17 #include <linux/time.h>
  18
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/pinctrl/pinconf.h>
  22 #include <linux/pinctrl/pinconf-generic.h>
  23
  24 #include "../core.h"
  25 #include "pinctrl-intel.h"
  26
  27 /* Offset from regs */
  28 #define REVID                           0x000
  29 #define REVID_SHIFT                     16
  30 #define REVID_MASK                      GENMASK(31, 16)
  31
  32 #define PADBAR                          0x00c
  33
  34 #define PADOWN_BITS                     4
  35 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  36 #define PADOWN_MASK(p)                  (GENMASK(3, 0) << PADOWN_SHIFT(p))
  37 #define PADOWN_GPP(p)                   ((p) / 8)
  38
  39 /* Offset from pad_regs */
  40 #define PADCFG0                         0x000
  41 #define PADCFG0_RXEVCFG_SHIFT           25
  42 #define PADCFG0_RXEVCFG_MASK            GENMASK(26, 25)
  43 #define PADCFG0_RXEVCFG_LEVEL           0
  44 #define PADCFG0_RXEVCFG_EDGE            1
  45 #define PADCFG0_RXEVCFG_DISABLED        2
  46 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  47 #define PADCFG0_PREGFRXSEL              BIT(24)
  48 #define PADCFG0_RXINV                   BIT(23)
  49 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  50 #define PADCFG0_GPIROUTSCI              BIT(19)
  51 #define PADCFG0_GPIROUTSMI              BIT(18)
  52 #define PADCFG0_GPIROUTNMI              BIT(17)
  53 #define PADCFG0_PMODE_SHIFT             10
  54 #define PADCFG0_PMODE_MASK              GENMASK(13, 10)
  55 #define PADCFG0_GPIORXDIS               BIT(9)
  56 #define PADCFG0_GPIOTXDIS               BIT(8)
  57 #define PADCFG0_GPIORXSTATE             BIT(1)
  58 #define PADCFG0_GPIOTXSTATE             BIT(0)
  59
  60 #define PADCFG1                         0x004
  61 #define PADCFG1_TERM_UP                 BIT(13)
  62 #define PADCFG1_TERM_SHIFT              10
  63 #define PADCFG1_TERM_MASK               GENMASK(12, 10)
  64 #define PADCFG1_TERM_20K                4
  65 #define PADCFG1_TERM_2K                 3
  66 #define PADCFG1_TERM_5K                 2
  67 #define PADCFG1_TERM_1K                 1
  68
  69 #define PADCFG2                         0x008
  70 #define PADCFG2_DEBEN                   BIT(0)
  71 #define PADCFG2_DEBOUNCE_SHIFT          1
  72 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
  73
  74 #define DEBOUNCE_PERIOD_NSEC            31250
  75
  76 struct intel_pad_context {
  77         u32 padcfg0;
  78         u32 padcfg1;
  79         u32 padcfg2;
  80 };
  81
  82 struct intel_community_context {
  83         u32 *intmask;
  84         u32 *hostown;
  85 };
  86
  87 struct intel_pinctrl_context {
  88         struct intel_pad_context *pads;
  89         struct intel_community_context *communities;
  90 };
  91
  92 /**
  93  * struct intel_pinctrl - Intel pinctrl private structure
  94  * @dev: Pointer to the device structure
  95  * @lock: Lock to serialize register access
  96  * @pctldesc: Pin controller description
  97  * @pctldev: Pointer to the pin controller device
  98  * @chip: GPIO chip in this pin controller
  99  * @soc: SoC/PCH specific pin configuration data
 100  * @communities: All communities in this pin controller
 101  * @ncommunities: Number of communities in this pin controller
 102  * @context: Configuration saved over system sleep
 103  * @irq: pinctrl/GPIO chip irq number
 104  */
 105 struct intel_pinctrl {
 106         struct device *dev;
 107         raw_spinlock_t lock;
 108         struct pinctrl_desc pctldesc;
 109         struct pinctrl_dev *pctldev;
 110         struct gpio_chip chip;
 111         const struct intel_pinctrl_soc_data *soc;
 112         struct intel_community *communities;
 113         size_t ncommunities;
 114         struct intel_pinctrl_context context;
 115         int irq;
 116 };
 117
 118 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 119 #define padgroup_offset(g, p)   ((p) - (g)->base)
 120
 121 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
 122                                                    unsigned int pin)
 123 {
 124         struct intel_community *community;
 125         int i;
 126
 127         for (i = 0; i < pctrl->ncommunities; i++) {
 128                 community = &pctrl->communities[i];
 129                 if (pin >= community->pin_base &&
 130                     pin < community->pin_base + community->npins)
 131                         return community;
 132         }
 133
 134         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 135         return NULL;
 136 }
 137
 138 static const struct intel_padgroup *
 139 intel_community_get_padgroup(const struct intel_community *community,
 140                              unsigned int pin)
 141 {
 142         int i;
 143
 144         for (i = 0; i < community->ngpps; i++) {
 145                 const struct intel_padgroup *padgrp = &community->gpps[i];
 146
 147                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 148                         return padgrp;
 149         }
 150
 151         return NULL;
 152 }
 153
 154 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
 155                                       unsigned int pin, unsigned int reg)
 156 {
 157         const struct intel_community *community;
 158         unsigned int padno;
 159         size_t nregs;
 160
 161         community = intel_get_community(pctrl, pin);
 162         if (!community)
 163                 return NULL;
 164
 165         padno = pin_to_padno(community, pin);
 166         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 167
 168         if (reg >= nregs * 4)
 169                 return NULL;
 170
 171         return community->pad_regs + reg + padno * nregs * 4;
 172 }
 173
 174 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
 175 {
 176         const struct intel_community *community;
 177         const struct intel_padgroup *padgrp;
 178         unsigned int gpp, offset, gpp_offset;
 179         void __iomem *padown;
 180
 181         community = intel_get_community(pctrl, pin);
 182         if (!community)
 183                 return false;
 184         if (!community->padown_offset)
 185                 return true;
 186
 187         padgrp = intel_community_get_padgroup(community, pin);
 188         if (!padgrp)
 189                 return false;
 190
 191         gpp_offset = padgroup_offset(padgrp, pin);
 192         gpp = PADOWN_GPP(gpp_offset);
 193         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 194         padown = community->regs + offset;
 195
 196         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 197 }
 198
 199 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
 200 {
 201         const struct intel_community *community;
 202         const struct intel_padgroup *padgrp;
 203         unsigned int offset, gpp_offset;
 204         void __iomem *hostown;
 205
 206         community = intel_get_community(pctrl, pin);
 207         if (!community)
 208                 return true;
 209         if (!community->hostown_offset)
 210                 return false;
 211
 212         padgrp = intel_community_get_padgroup(community, pin);
 213         if (!padgrp)
 214                 return true;
 215
 216         gpp_offset = padgroup_offset(padgrp, pin);
 217         offset = community->hostown_offset + padgrp->reg_num * 4;
 218         hostown = community->regs + offset;
 219
 220         return !(readl(hostown) & BIT(gpp_offset));
 221 }
 222
 223 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
 224 {
 225         struct intel_community *community;
 226         const struct intel_padgroup *padgrp;
 227         unsigned int offset, gpp_offset;
 228         u32 value;
 229
 230         community = intel_get_community(pctrl, pin);
 231         if (!community)
 232                 return true;
 233         if (!community->padcfglock_offset)
 234                 return false;
 235
 236         padgrp = intel_community_get_padgroup(community, pin);
 237         if (!padgrp)
 238                 return true;
 239
 240         gpp_offset = padgroup_offset(padgrp, pin);
 241
 242         /*
 243          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 244          * the pad is considered unlocked. Any other case means that it is
 245          * either fully or partially locked and we don't touch it.
 246          */
 247         offset = community->padcfglock_offset + padgrp->reg_num * 8;
 248         value = readl(community->regs + offset);
 249         if (value & BIT(gpp_offset))
 250                 return true;
 251
 252         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 253         value = readl(community->regs + offset);
 254         if (value & BIT(gpp_offset))
 255                 return true;
 256
 257         return false;
 258 }
 259
 260 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
 261 {
 262         return intel_pad_owned_by_host(pctrl, pin) &&
 263                 !intel_pad_locked(pctrl, pin);
 264 }
 265
 266 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 267 {
 268         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 269
 270         return pctrl->soc->ngroups;
 271 }
 272
 273 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 274                                       unsigned int group)
 275 {
 276         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 277
 278         return pctrl->soc->groups[group].name;
 279 }
 280
 281 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 282                               const unsigned int **pins, unsigned int *npins)
 283 {
 284         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 285
 286         *pins = pctrl->soc->groups[group].pins;
 287         *npins = pctrl->soc->groups[group].npins;
 288         return 0;
 289 }
 290
 291 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 292                                unsigned int pin)
 293 {
 294         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 295         void __iomem *padcfg;
 296         u32 cfg0, cfg1, mode;
 297         bool locked, acpi;
 298
 299         if (!intel_pad_owned_by_host(pctrl, pin)) {
 300                 seq_puts(s, "not available");
 301                 return;
 302         }
 303
 304         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 305         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 306
 307         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 308         if (!mode)
 309                 seq_puts(s, "GPIO ");
 310         else
 311                 seq_printf(s, "mode %d ", mode);
 312
 313         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 314
 315         /* Dump the additional PADCFG registers if available */
 316         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 317         if (padcfg)
 318                 seq_printf(s, " 0x%08x", readl(padcfg));
 319
 320         locked = intel_pad_locked(pctrl, pin);
 321         acpi = intel_pad_acpi_mode(pctrl, pin);
 322
 323         if (locked || acpi) {
 324                 seq_puts(s, " [");
 325                 if (locked) {
 326                         seq_puts(s, "LOCKED");
 327                         if (acpi)
 328                                 seq_puts(s, ", ");
 329                 }
 330                 if (acpi)
 331                         seq_puts(s, "ACPI");
 332                 seq_puts(s, "]");
 333         }
 334 }
 335
 336 static const struct pinctrl_ops intel_pinctrl_ops = {
 337         .get_groups_count = intel_get_groups_count,
 338         .get_group_name = intel_get_group_name,
 339         .get_group_pins = intel_get_group_pins,
 340         .pin_dbg_show = intel_pin_dbg_show,
 341 };
 342
 343 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 344 {
 345         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 346
 347         return pctrl->soc->nfunctions;
 348 }
 349
 350 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 351                                            unsigned int function)
 352 {
 353         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 354
 355         return pctrl->soc->functions[function].name;
 356 }
 357
 358 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 359                                      unsigned int function,
 360                                      const char * const **groups,
 361                                      unsigned int * const ngroups)
 362 {
 363         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 364
 365         *groups = pctrl->soc->functions[function].groups;
 366         *ngroups = pctrl->soc->functions[function].ngroups;
 367         return 0;
 368 }
 369
 370 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
 371                                 unsigned int function, unsigned int group)
 372 {
 373         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 374         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 375         unsigned long flags;
 376         int i;
 377
 378         raw_spin_lock_irqsave(&pctrl->lock, flags);
 379
 380         /*
 381          * All pins in the groups needs to be accessible and writable
 382          * before we can enable the mux for this group.
 383          */
 384         for (i = 0; i < grp->npins; i++) {
 385                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
 386                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 387                         return -EBUSY;
 388                 }
 389         }
 390
 391         /* Now enable the mux setting for each pin in the group */
 392         for (i = 0; i < grp->npins; i++) {
 393                 void __iomem *padcfg0;
 394                 u32 value;
 395
 396                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
 397                 value = readl(padcfg0);
 398
 399                 value &= ~PADCFG0_PMODE_MASK;
 400
 401                 if (grp->modes)
 402                         value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
 403                 else
 404                         value |= grp->mode << PADCFG0_PMODE_SHIFT;
 405
 406                 writel(value, padcfg0);
 407         }
 408
 409         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 410
 411         return 0;
 412 }
 413
 414 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 415 {
 416         u32 value;
 417
 418         value = readl(padcfg0);
 419         if (input) {
 420                 value &= ~PADCFG0_GPIORXDIS;
 421                 value |= PADCFG0_GPIOTXDIS;
 422         } else {
 423                 value &= ~PADCFG0_GPIOTXDIS;
 424                 value |= PADCFG0_GPIORXDIS;
 425         }
 426         writel(value, padcfg0);
 427 }
 428
 429 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 430 {
 431         u32 value;
 432
 433         /* Put the pad into GPIO mode */
 434         value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
 435         /* Disable SCI/SMI/NMI generation */
 436         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 437         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 438         writel(value, padcfg0);
 439 }
 440
 441 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 442                                      struct pinctrl_gpio_range *range,
 443                                      unsigned int pin)
 444 {
 445         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 446         void __iomem *padcfg0;
 447         unsigned long flags;
 448
 449         raw_spin_lock_irqsave(&pctrl->lock, flags);
 450
 451         if (!intel_pad_usable(pctrl, pin)) {
 452                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 453                 return -EBUSY;
 454         }
 455
 456         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 457         intel_gpio_set_gpio_mode(padcfg0);
 458         /* Disable TX buffer and enable RX (this will be input) */
 459         __intel_gpio_set_direction(padcfg0, true);
 460
 461         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 462
 463         return 0;
 464 }
 465
 466 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 467                                     struct pinctrl_gpio_range *range,
 468                                     unsigned int pin, bool input)
 469 {
 470         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 471         void __iomem *padcfg0;
 472         unsigned long flags;
 473
 474         raw_spin_lock_irqsave(&pctrl->lock, flags);
 475
 476         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 477         __intel_gpio_set_direction(padcfg0, input);
 478
 479         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 480
 481         return 0;
 482 }
 483
 484 static const struct pinmux_ops intel_pinmux_ops = {
 485         .get_functions_count = intel_get_functions_count,
 486         .get_function_name = intel_get_function_name,
 487         .get_function_groups = intel_get_function_groups,
 488         .set_mux = intel_pinmux_set_mux,
 489         .gpio_request_enable = intel_gpio_request_enable,
 490         .gpio_set_direction = intel_gpio_set_direction,
 491 };
 492
 493 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 494                             unsigned long *config)
 495 {
 496         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 497         enum pin_config_param param = pinconf_to_config_param(*config);
 498         const struct intel_community *community;
 499         u32 value, term;
 500         u32 arg = 0;
 501
 502         if (!intel_pad_owned_by_host(pctrl, pin))
 503                 return -ENOTSUPP;
 504
 505         community = intel_get_community(pctrl, pin);
 506         value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 507         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 508
 509         switch (param) {
 510         case PIN_CONFIG_BIAS_DISABLE:
 511                 if (term)
 512                         return -EINVAL;
 513                 break;
 514
 515         case PIN_CONFIG_BIAS_PULL_UP:
 516                 if (!term || !(value & PADCFG1_TERM_UP))
 517                         return -EINVAL;
 518
 519                 switch (term) {
 520                 case PADCFG1_TERM_1K:
 521                         arg = 1000;
 522                         break;
 523                 case PADCFG1_TERM_2K:
 524                         arg = 2000;
 525                         break;
 526                 case PADCFG1_TERM_5K:
 527                         arg = 5000;
 528                         break;
 529                 case PADCFG1_TERM_20K:
 530                         arg = 20000;
 531                         break;
 532                 }
 533
 534                 break;
 535
 536         case PIN_CONFIG_BIAS_PULL_DOWN:
 537                 if (!term || value & PADCFG1_TERM_UP)
 538                         return -EINVAL;
 539
 540                 switch (term) {
 541                 case PADCFG1_TERM_1K:
 542                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 543                                 return -EINVAL;
 544                         arg = 1000;
 545                         break;
 546                 case PADCFG1_TERM_5K:
 547                         arg = 5000;
 548                         break;
 549                 case PADCFG1_TERM_20K:
 550                         arg = 20000;
 551                         break;
 552                 }
 553
 554                 break;
 555
 556         case PIN_CONFIG_INPUT_DEBOUNCE: {
 557                 void __iomem *padcfg2;
 558                 u32 v;
 559
 560                 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 561                 if (!padcfg2)
 562                         return -ENOTSUPP;
 563
 564                 v = readl(padcfg2);
 565                 if (!(v & PADCFG2_DEBEN))
 566                         return -EINVAL;
 567
 568                 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 569                 arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
 570
 571                 break;
 572         }
 573
 574         default:
 575                 return -ENOTSUPP;
 576         }
 577
 578         *config = pinconf_to_config_packed(param, arg);
 579         return 0;
 580 }
 581
 582 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 583                                  unsigned long config)
 584 {
 585         unsigned int param = pinconf_to_config_param(config);
 586         unsigned int arg = pinconf_to_config_argument(config);
 587         const struct intel_community *community;
 588         void __iomem *padcfg1;
 589         unsigned long flags;
 590         int ret = 0;
 591         u32 value;
 592
 593         raw_spin_lock_irqsave(&pctrl->lock, flags);
 594
 595         community = intel_get_community(pctrl, pin);
 596         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 597         value = readl(padcfg1);
 598
 599         switch (param) {
 600         case PIN_CONFIG_BIAS_DISABLE:
 601                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 602                 break;
 603
 604         case PIN_CONFIG_BIAS_PULL_UP:
 605                 value &= ~PADCFG1_TERM_MASK;
 606
 607                 value |= PADCFG1_TERM_UP;
 608
 609                 switch (arg) {
 610                 case 20000:
 611                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 612                         break;
 613                 case 5000:
 614                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 615                         break;
 616                 case 2000:
 617                         value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
 618                         break;
 619                 case 1000:
 620                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 621                         break;
 622                 default:
 623                         ret = -EINVAL;
 624                 }
 625
 626                 break;
 627
 628         case PIN_CONFIG_BIAS_PULL_DOWN:
 629                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 630
 631                 switch (arg) {
 632                 case 20000:
 633                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 634                         break;
 635                 case 5000:
 636                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 637                         break;
 638                 case 1000:
 639                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 640                                 ret = -EINVAL;
 641                                 break;
 642                         }
 643                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 644                         break;
 645                 default:
 646                         ret = -EINVAL;
 647                 }
 648
 649                 break;
 650         }
 651
 652         if (!ret)
 653                 writel(value, padcfg1);
 654
 655         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 656
 657         return ret;
 658 }
 659
 660 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
 661                                      unsigned int pin, unsigned int debounce)
 662 {
 663         void __iomem *padcfg0, *padcfg2;
 664         unsigned long flags;
 665         u32 value0, value2;
 666         int ret = 0;
 667
 668         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 669         if (!padcfg2)
 670                 return -ENOTSUPP;
 671
 672         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 673
 674         raw_spin_lock_irqsave(&pctrl->lock, flags);
 675
 676         value0 = readl(padcfg0);
 677         value2 = readl(padcfg2);
 678
 679         /* Disable glitch filter and debouncer */
 680         value0 &= ~PADCFG0_PREGFRXSEL;
 681         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
 682
 683         if (debounce) {
 684                 unsigned long v;
 685
 686                 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
 687                 if (v < 3 || v > 15) {
 688                         ret = -EINVAL;
 689                         goto exit_unlock;
 690                 } else {
 691                         /* Enable glitch filter and debouncer */
 692                         value0 |= PADCFG0_PREGFRXSEL;
 693                         value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
 694                         value2 |= PADCFG2_DEBEN;
 695                 }
 696         }
 697
 698         writel(value0, padcfg0);
 699         writel(value2, padcfg2);
 700
 701 exit_unlock:
 702         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 703
 704         return ret;
 705 }
 706
 707 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 708                           unsigned long *configs, unsigned int nconfigs)
 709 {
 710         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 711         int i, ret;
 712
 713         if (!intel_pad_usable(pctrl, pin))
 714                 return -ENOTSUPP;
 715
 716         for (i = 0; i < nconfigs; i++) {
 717                 switch (pinconf_to_config_param(configs[i])) {
 718                 case PIN_CONFIG_BIAS_DISABLE:
 719                 case PIN_CONFIG_BIAS_PULL_UP:
 720                 case PIN_CONFIG_BIAS_PULL_DOWN:
 721                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 722                         if (ret)
 723                                 return ret;
 724                         break;
 725
 726                 case PIN_CONFIG_INPUT_DEBOUNCE:
 727                         ret = intel_config_set_debounce(pctrl, pin,
 728                                 pinconf_to_config_argument(configs[i]));
 729                         if (ret)
 730                                 return ret;
 731                         break;
 732
 733                 default:
 734                         return -ENOTSUPP;
 735                 }
 736         }
 737
 738         return 0;
 739 }
 740
 741 static const struct pinconf_ops intel_pinconf_ops = {
 742         .is_generic = true,
 743         .pin_config_get = intel_config_get,
 744         .pin_config_set = intel_config_set,
 745 };
 746
 747 static const struct pinctrl_desc intel_pinctrl_desc = {
 748         .pctlops = &intel_pinctrl_ops,
 749         .pmxops = &intel_pinmux_ops,
 750         .confops = &intel_pinconf_ops,
 751         .owner = THIS_MODULE,
 752 };
 753
 754 /**
 755  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 756  * @pctrl: Pinctrl structure
 757  * @offset: GPIO offset from gpiolib
 758  * @community: Community is filled here if not %NULL
 759  * @padgrp: Pad group is filled here if not %NULL
 760  *
 761  * When coming through gpiolib irqchip, the GPIO offset is not
 762  * automatically translated to pinctrl pin number. This function can be
 763  * used to find out the corresponding pinctrl pin.
 764  */
 765 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
 766                              const struct intel_community **community,
 767                              const struct intel_padgroup **padgrp)
 768 {
 769         int i;
 770
 771         for (i = 0; i < pctrl->ncommunities; i++) {
 772                 const struct intel_community *comm = &pctrl->communities[i];
 773                 int j;
 774
 775                 for (j = 0; j < comm->ngpps; j++) {
 776                         const struct intel_padgroup *pgrp = &comm->gpps[j];
 777
 778                         if (pgrp->gpio_base < 0)
 779                                 continue;
 780
 781                         if (offset >= pgrp->gpio_base &&
 782                             offset < pgrp->gpio_base + pgrp->size) {
 783                                 int pin;
 784
 785                                 pin = pgrp->base + offset - pgrp->gpio_base;
 786                                 if (community)
 787                                         *community = comm;
 788                                 if (padgrp)
 789                                         *padgrp = pgrp;
 790
 791                                 return pin;
 792                         }
 793                 }
 794         }
 795
 796         return -EINVAL;
 797 }
 798
 799 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
 800 {
 801         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 802         void __iomem *reg;
 803         u32 padcfg0;
 804         int pin;
 805
 806         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 807         if (pin < 0)
 808                 return -EINVAL;
 809
 810         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 811         if (!reg)
 812                 return -EINVAL;
 813
 814         padcfg0 = readl(reg);
 815         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
 816                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
 817
 818         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 819 }
 820
 821 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
 822                            int value)
 823 {
 824         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 825         unsigned long flags;
 826         void __iomem *reg;
 827         u32 padcfg0;
 828         int pin;
 829
 830         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 831         if (pin < 0)
 832                 return;
 833
 834         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 835         if (!reg)
 836                 return;
 837
 838         raw_spin_lock_irqsave(&pctrl->lock, flags);
 839         padcfg0 = readl(reg);
 840         if (value)
 841                 padcfg0 |= PADCFG0_GPIOTXSTATE;
 842         else
 843                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 844         writel(padcfg0, reg);
 845         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 846 }
 847
 848 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 849 {
 850         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 851         void __iomem *reg;
 852         u32 padcfg0;
 853         int pin;
 854
 855         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 856         if (pin < 0)
 857                 return -EINVAL;
 858
 859         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 860         if (!reg)
 861                 return -EINVAL;
 862
 863         padcfg0 = readl(reg);
 864
 865         if (padcfg0 & PADCFG0_PMODE_MASK)
 866                 return -EINVAL;
 867
 868         return !!(padcfg0 & PADCFG0_GPIOTXDIS);
 869 }
 870
 871 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 872 {
 873         return pinctrl_gpio_direction_input(chip->base + offset);
 874 }
 875
 876 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
 877                                        int value)
 878 {
 879         intel_gpio_set(chip, offset, value);
 880         return pinctrl_gpio_direction_output(chip->base + offset);
 881 }
 882
 883 static const struct gpio_chip intel_gpio_chip = {
 884         .owner = THIS_MODULE,
 885         .request = gpiochip_generic_request,
 886         .free = gpiochip_generic_free,
 887         .get_direction = intel_gpio_get_direction,
 888         .direction_input = intel_gpio_direction_input,
 889         .direction_output = intel_gpio_direction_output,
 890         .get = intel_gpio_get,
 891         .set = intel_gpio_set,
 892         .set_config = gpiochip_generic_config,
 893 };
 894
 895 static void intel_gpio_irq_ack(struct irq_data *d)
 896 {
 897         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 898         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 899         const struct intel_community *community;
 900         const struct intel_padgroup *padgrp;
 901         int pin;
 902
 903         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 904         if (pin >= 0) {
 905                 unsigned int gpp, gpp_offset, is_offset;
 906
 907                 gpp = padgrp->reg_num;
 908                 gpp_offset = padgroup_offset(padgrp, pin);
 909                 is_offset = community->is_offset + gpp * 4;
 910
 911                 raw_spin_lock(&pctrl->lock);
 912                 writel(BIT(gpp_offset), community->regs + is_offset);
 913                 raw_spin_unlock(&pctrl->lock);
 914         }
 915 }
 916
 917 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
 918 {
 919         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 920         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 921         const struct intel_community *community;
 922         const struct intel_padgroup *padgrp;
 923         int pin;
 924
 925         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 926         if (pin >= 0) {
 927                 unsigned int gpp, gpp_offset;
 928                 unsigned long flags;
 929                 void __iomem *reg, *is;
 930                 u32 value;
 931
 932                 gpp = padgrp->reg_num;
 933                 gpp_offset = padgroup_offset(padgrp, pin);
 934
 935                 reg = community->regs + community->ie_offset + gpp * 4;
 936                 is = community->regs + community->is_offset + gpp * 4;
 937
 938                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 939
 940                 /* Clear interrupt status first to avoid unexpected interrupt */
 941                 writel(BIT(gpp_offset), is);
 942
 943                 value = readl(reg);
 944                 if (mask)
 945                         value &= ~BIT(gpp_offset);
 946                 else
 947                         value |= BIT(gpp_offset);
 948                 writel(value, reg);
 949                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 950         }
 951 }
 952
 953 static void intel_gpio_irq_mask(struct irq_data *d)
 954 {
 955         intel_gpio_irq_mask_unmask(d, true);
 956 }
 957
 958 static void intel_gpio_irq_unmask(struct irq_data *d)
 959 {
 960         intel_gpio_irq_mask_unmask(d, false);
 961 }
 962
 963 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
 964 {
 965         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 966         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 967         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
 968         unsigned long flags;
 969         void __iomem *reg;
 970         u32 value;
 971
 972         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 973         if (!reg)
 974                 return -EINVAL;
 975
 976         /*
 977          * If the pin is in ACPI mode it is still usable as a GPIO but it
 978          * cannot be used as IRQ because GPI_IS status bit will not be
 979          * updated by the host controller hardware.
 980          */
 981         if (intel_pad_acpi_mode(pctrl, pin)) {
 982                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
 983                 return -EPERM;
 984         }
 985
 986         raw_spin_lock_irqsave(&pctrl->lock, flags);
 987
 988         intel_gpio_set_gpio_mode(reg);
 989
 990         value = readl(reg);
 991
 992         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
 993
 994         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 995                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
 996         } else if (type & IRQ_TYPE_EDGE_FALLING) {
 997                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
 998                 value |= PADCFG0_RXINV;
 999         } else if (type & IRQ_TYPE_EDGE_RISING) {
1000                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1001         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1002                 if (type & IRQ_TYPE_LEVEL_LOW)
1003                         value |= PADCFG0_RXINV;
1004         } else {
1005                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1006         }
1007
1008         writel(value, reg);
1009
1010         if (type & IRQ_TYPE_EDGE_BOTH)
1011                 irq_set_handler_locked(d, handle_edge_irq);
1012         else if (type & IRQ_TYPE_LEVEL_MASK)
1013                 irq_set_handler_locked(d, handle_level_irq);
1014
1015         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1016
1017         return 0;
1018 }
1019
1020 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1021 {
1022         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1023         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1024         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1025
1026         if (on)
1027                 enable_irq_wake(pctrl->irq);
1028         else
1029                 disable_irq_wake(pctrl->irq);
1030
1031         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1032         return 0;
1033 }
1034
1035 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1036         const struct intel_community *community)
1037 {
1038         struct gpio_chip *gc = &pctrl->chip;
1039         irqreturn_t ret = IRQ_NONE;
1040         int gpp;
1041
1042         for (gpp = 0; gpp < community->ngpps; gpp++) {
1043                 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1044                 unsigned long pending, enabled, gpp_offset;
1045
1046                 pending = readl(community->regs + community->is_offset +
1047                                 padgrp->reg_num * 4);
1048                 enabled = readl(community->regs + community->ie_offset +
1049                                 padgrp->reg_num * 4);
1050
1051                 /* Only interrupts that are enabled */
1052                 pending &= enabled;
1053
1054                 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1055                         unsigned irq;
1056
1057                         irq = irq_find_mapping(gc->irq.domain,
1058                                                padgrp->gpio_base + gpp_offset);
1059                         generic_handle_irq(irq);
1060
1061                         ret |= IRQ_HANDLED;
1062                 }
1063         }
1064
1065         return ret;
1066 }
1067
1068 static irqreturn_t intel_gpio_irq(int irq, void *data)
1069 {
1070         const struct intel_community *community;
1071         struct intel_pinctrl *pctrl = data;
1072         irqreturn_t ret = IRQ_NONE;
1073         int i;
1074
1075         /* Need to check all communities for pending interrupts */
1076         for (i = 0; i < pctrl->ncommunities; i++) {
1077                 community = &pctrl->communities[i];
1078                 ret |= intel_gpio_community_irq_handler(pctrl, community);
1079         }
1080
1081         return ret;
1082 }
1083
1084 static struct irq_chip intel_gpio_irqchip = {
1085         .name = "intel-gpio",
1086         .irq_ack = intel_gpio_irq_ack,
1087         .irq_mask = intel_gpio_irq_mask,
1088         .irq_unmask = intel_gpio_irq_unmask,
1089         .irq_set_type = intel_gpio_irq_type,
1090         .irq_set_wake = intel_gpio_irq_wake,
1091         .flags = IRQCHIP_MASK_ON_SUSPEND,
1092 };
1093
1094 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1095                                      const struct intel_community *community)
1096 {
1097         int ret = 0, i;
1098
1099         for (i = 0; i < community->ngpps; i++) {
1100                 const struct intel_padgroup *gpp = &community->gpps[i];
1101
1102                 if (gpp->gpio_base < 0)
1103                         continue;
1104
1105                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1106                                              gpp->gpio_base, gpp->base,
1107                                              gpp->size);
1108                 if (ret)
1109                         return ret;
1110         }
1111
1112         return ret;
1113 }
1114
1115 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1116 {
1117         const struct intel_community *community;
1118         unsigned int ngpio = 0;
1119         int i, j;
1120
1121         for (i = 0; i < pctrl->ncommunities; i++) {
1122                 community = &pctrl->communities[i];
1123                 for (j = 0; j < community->ngpps; j++) {
1124                         const struct intel_padgroup *gpp = &community->gpps[j];
1125
1126                         if (gpp->gpio_base < 0)
1127                                 continue;
1128
1129                         if (gpp->gpio_base + gpp->size > ngpio)
1130                                 ngpio = gpp->gpio_base + gpp->size;
1131                 }
1132         }
1133
1134         return ngpio;
1135 }
1136
1137 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1138 {
1139         int ret, i;
1140
1141         pctrl->chip = intel_gpio_chip;
1142
1143         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1144         pctrl->chip.label = dev_name(pctrl->dev);
1145         pctrl->chip.parent = pctrl->dev;
1146         pctrl->chip.base = -1;
1147         pctrl->irq = irq;
1148
1149         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1150         if (ret) {
1151                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1152                 return ret;
1153         }
1154
1155         for (i = 0; i < pctrl->ncommunities; i++) {
1156                 struct intel_community *community = &pctrl->communities[i];
1157
1158                 ret = intel_gpio_add_pin_ranges(pctrl, community);
1159                 if (ret) {
1160                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1161                         return ret;
1162                 }
1163         }
1164
1165         /*
1166          * We need to request the interrupt here (instead of providing chip
1167          * to the irq directly) because on some platforms several GPIO
1168          * controllers share the same interrupt line.
1169          */
1170         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1171                                IRQF_SHARED | IRQF_NO_THREAD,
1172                                dev_name(pctrl->dev), pctrl);
1173         if (ret) {
1174                 dev_err(pctrl->dev, "failed to request interrupt\n");
1175                 return ret;
1176         }
1177
1178         ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1179                                    handle_bad_irq, IRQ_TYPE_NONE);
1180         if (ret) {
1181                 dev_err(pctrl->dev, "failed to add irqchip\n");
1182                 return ret;
1183         }
1184
1185         gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1186                                      NULL);
1187         return 0;
1188 }
1189
1190 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1191                                        struct intel_community *community)
1192 {
1193         struct intel_padgroup *gpps;
1194         unsigned int npins = community->npins;
1195         unsigned int padown_num = 0;
1196         size_t ngpps, i;
1197
1198         if (community->gpps)
1199                 ngpps = community->ngpps;
1200         else
1201                 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1202
1203         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1204         if (!gpps)
1205                 return -ENOMEM;
1206
1207         for (i = 0; i < ngpps; i++) {
1208                 if (community->gpps) {
1209                         gpps[i] = community->gpps[i];
1210                 } else {
1211                         unsigned int gpp_size = community->gpp_size;
1212
1213                         gpps[i].reg_num = i;
1214                         gpps[i].base = community->pin_base + i * gpp_size;
1215                         gpps[i].size = min(gpp_size, npins);
1216                         npins -= gpps[i].size;
1217                 }
1218
1219                 if (gpps[i].size > 32)
1220                         return -EINVAL;
1221
1222                 if (!gpps[i].gpio_base)
1223                         gpps[i].gpio_base = gpps[i].base;
1224
1225                 gpps[i].padown_num = padown_num;
1226
1227                 /*
1228                  * In older hardware the number of padown registers per
1229                  * group is fixed regardless of the group size.
1230                  */
1231                 if (community->gpp_num_padown_regs)
1232                         padown_num += community->gpp_num_padown_regs;
1233                 else
1234                         padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1235         }
1236
1237         community->ngpps = ngpps;
1238         community->gpps = gpps;
1239
1240         return 0;
1241 }
1242
1243 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1244 {
1245 #ifdef CONFIG_PM_SLEEP
1246         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1247         struct intel_community_context *communities;
1248         struct intel_pad_context *pads;
1249         int i;
1250
1251         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1252         if (!pads)
1253                 return -ENOMEM;
1254
1255         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1256                                    sizeof(*communities), GFP_KERNEL);
1257         if (!communities)
1258                 return -ENOMEM;
1259
1260
1261         for (i = 0; i < pctrl->ncommunities; i++) {
1262                 struct intel_community *community = &pctrl->communities[i];
1263                 u32 *intmask, *hostown;
1264
1265                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1266                                        sizeof(*intmask), GFP_KERNEL);
1267                 if (!intmask)
1268                         return -ENOMEM;
1269
1270                 communities[i].intmask = intmask;
1271
1272                 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1273                                        sizeof(*hostown), GFP_KERNEL);
1274                 if (!hostown)
1275                         return -ENOMEM;
1276
1277                 communities[i].hostown = hostown;
1278         }
1279
1280         pctrl->context.pads = pads;
1281         pctrl->context.communities = communities;
1282 #endif
1283
1284         return 0;
1285 }
1286
1287 static int intel_pinctrl_probe(struct platform_device *pdev,
1288                                const struct intel_pinctrl_soc_data *soc_data)
1289 {
1290         struct intel_pinctrl *pctrl;
1291         int i, ret, irq;
1292
1293         if (!soc_data)
1294                 return -EINVAL;
1295
1296         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1297         if (!pctrl)
1298                 return -ENOMEM;
1299
1300         pctrl->dev = &pdev->dev;
1301         pctrl->soc = soc_data;
1302         raw_spin_lock_init(&pctrl->lock);
1303
1304         /*
1305          * Make a copy of the communities which we can use to hold pointers
1306          * to the registers.
1307          */
1308         pctrl->ncommunities = pctrl->soc->ncommunities;
1309         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1310                                   sizeof(*pctrl->communities), GFP_KERNEL);
1311         if (!pctrl->communities)
1312                 return -ENOMEM;
1313
1314         for (i = 0; i < pctrl->ncommunities; i++) {
1315                 struct intel_community *community = &pctrl->communities[i];
1316                 void __iomem *regs;
1317                 u32 padbar;
1318
1319                 *community = pctrl->soc->communities[i];
1320
1321                 regs = devm_platform_ioremap_resource(pdev, community->barno);
1322                 if (IS_ERR(regs))
1323                         return PTR_ERR(regs);
1324
1325                 /*
1326                  * Determine community features based on the revision if
1327                  * not specified already.
1328                  */
1329                 if (!community->features) {
1330                         u32 rev;
1331
1332                         rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1333                         if (rev >= 0x94) {
1334                                 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1335                                 community->features |= PINCTRL_FEATURE_1K_PD;
1336                         }
1337                 }
1338
1339                 /* Read offset of the pad configuration registers */
1340                 padbar = readl(regs + PADBAR);
1341
1342                 community->regs = regs;
1343                 community->pad_regs = regs + padbar;
1344
1345                 ret = intel_pinctrl_add_padgroups(pctrl, community);
1346                 if (ret)
1347                         return ret;
1348         }
1349
1350         irq = platform_get_irq(pdev, 0);
1351         if (irq < 0)
1352                 return irq;
1353
1354         ret = intel_pinctrl_pm_init(pctrl);
1355         if (ret)
1356                 return ret;
1357
1358         pctrl->pctldesc = intel_pinctrl_desc;
1359         pctrl->pctldesc.name = dev_name(&pdev->dev);
1360         pctrl->pctldesc.pins = pctrl->soc->pins;
1361         pctrl->pctldesc.npins = pctrl->soc->npins;
1362
1363         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1364                                                pctrl);
1365         if (IS_ERR(pctrl->pctldev)) {
1366                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1367                 return PTR_ERR(pctrl->pctldev);
1368         }
1369
1370         ret = intel_gpio_probe(pctrl, irq);
1371         if (ret)
1372                 return ret;
1373
1374         platform_set_drvdata(pdev, pctrl);
1375
1376         return 0;
1377 }
1378
1379 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1380 {
1381         const struct intel_pinctrl_soc_data *data;
1382
1383         data = device_get_match_data(&pdev->dev);
1384         return intel_pinctrl_probe(pdev, data);
1385 }
1386 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
1387
1388 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1389 {
1390         const struct intel_pinctrl_soc_data *data = NULL;
1391         const struct intel_pinctrl_soc_data **table;
1392         struct acpi_device *adev;
1393         unsigned int i;
1394
1395         adev = ACPI_COMPANION(&pdev->dev);
1396         if (adev) {
1397                 const void *match = device_get_match_data(&pdev->dev);
1398
1399                 table = (const struct intel_pinctrl_soc_data **)match;
1400                 for (i = 0; table[i]; i++) {
1401                         if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
1402                                 data = table[i];
1403                                 break;
1404                         }
1405                 }
1406         } else {
1407                 const struct platform_device_id *id;
1408
1409                 id = platform_get_device_id(pdev);
1410                 if (!id)
1411                         return -ENODEV;
1412
1413                 table = (const struct intel_pinctrl_soc_data **)id->driver_data;
1414                 data = table[pdev->id];
1415         }
1416
1417         return intel_pinctrl_probe(pdev, data);
1418 }
1419 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
1420
1421 #ifdef CONFIG_PM_SLEEP
1422 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1423 {
1424         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1425
1426         if (!pd || !intel_pad_usable(pctrl, pin))
1427                 return false;
1428
1429         /*
1430          * Only restore the pin if it is actually in use by the kernel (or
1431          * by userspace). It is possible that some pins are used by the
1432          * BIOS during resume and those are not always locked down so leave
1433          * them alone.
1434          */
1435         if (pd->mux_owner || pd->gpio_owner ||
1436             gpiochip_line_is_irq(&pctrl->chip, pin))
1437                 return true;
1438
1439         return false;
1440 }
1441
1442 int intel_pinctrl_suspend_noirq(struct device *dev)
1443 {
1444         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1445         struct intel_community_context *communities;
1446         struct intel_pad_context *pads;
1447         int i;
1448
1449         pads = pctrl->context.pads;
1450         for (i = 0; i < pctrl->soc->npins; i++) {
1451                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1452                 void __iomem *padcfg;
1453                 u32 val;
1454
1455                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1456                         continue;
1457
1458                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1459                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1460                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1461                 pads[i].padcfg1 = val;
1462
1463                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1464                 if (padcfg)
1465                         pads[i].padcfg2 = readl(padcfg);
1466         }
1467
1468         communities = pctrl->context.communities;
1469         for (i = 0; i < pctrl->ncommunities; i++) {
1470                 struct intel_community *community = &pctrl->communities[i];
1471                 void __iomem *base;
1472                 unsigned int gpp;
1473
1474                 base = community->regs + community->ie_offset;
1475                 for (gpp = 0; gpp < community->ngpps; gpp++)
1476                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1477
1478                 base = community->regs + community->hostown_offset;
1479                 for (gpp = 0; gpp < community->ngpps; gpp++)
1480                         communities[i].hostown[gpp] = readl(base + gpp * 4);
1481         }
1482
1483         return 0;
1484 }
1485 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1486
1487 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1488 {
1489         size_t i;
1490
1491         for (i = 0; i < pctrl->ncommunities; i++) {
1492                 const struct intel_community *community;
1493                 void __iomem *base;
1494                 unsigned int gpp;
1495
1496                 community = &pctrl->communities[i];
1497                 base = community->regs;
1498
1499                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1500                         /* Mask and clear all interrupts */
1501                         writel(0, base + community->ie_offset + gpp * 4);
1502                         writel(0xffff, base + community->is_offset + gpp * 4);
1503                 }
1504         }
1505 }
1506
1507 static u32
1508 intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size)
1509 {
1510         u32 requested = 0;
1511         unsigned int i;
1512
1513         for (i = 0; i < size; i++)
1514                 if (gpiochip_is_requested(chip, base + i))
1515                         requested |= BIT(i);
1516
1517         return requested;
1518 }
1519
1520 static u32
1521 intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value)
1522 {
1523         u32 curr, updated;
1524
1525         curr = readl(hostown);
1526         updated = (curr & ~mask) | (value & mask);
1527         writel(updated, hostown);
1528
1529         return curr;
1530 }
1531
1532 int intel_pinctrl_resume_noirq(struct device *dev)
1533 {
1534         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1535         const struct intel_community_context *communities;
1536         const struct intel_pad_context *pads;
1537         int i;
1538
1539         /* Mask all interrupts */
1540         intel_gpio_irq_init(pctrl);
1541
1542         pads = pctrl->context.pads;
1543         for (i = 0; i < pctrl->soc->npins; i++) {
1544                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1545                 void __iomem *padcfg;
1546                 u32 val;
1547
1548                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1549                         continue;
1550
1551                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1552                 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1553                 if (val != pads[i].padcfg0) {
1554                         writel(pads[i].padcfg0, padcfg);
1555                         dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1556                                 desc->number, readl(padcfg));
1557                 }
1558
1559                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1560                 val = readl(padcfg);
1561                 if (val != pads[i].padcfg1) {
1562                         writel(pads[i].padcfg1, padcfg);
1563                         dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1564                                 desc->number, readl(padcfg));
1565                 }
1566
1567                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1568                 if (padcfg) {
1569                         val = readl(padcfg);
1570                         if (val != pads[i].padcfg2) {
1571                                 writel(pads[i].padcfg2, padcfg);
1572                                 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1573                                         desc->number, readl(padcfg));
1574                         }
1575                 }
1576         }
1577
1578         communities = pctrl->context.communities;
1579         for (i = 0; i < pctrl->ncommunities; i++) {
1580                 struct intel_community *community = &pctrl->communities[i];
1581                 void __iomem *base;
1582                 unsigned int gpp;
1583
1584                 base = community->regs + community->ie_offset;
1585                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1586                         writel(communities[i].intmask[gpp], base + gpp * 4);
1587                         dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1588                                 readl(base + gpp * 4));
1589                 }
1590
1591                 base = community->regs + community->hostown_offset;
1592                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1593                         const struct intel_padgroup *padgrp = &community->gpps[gpp];
1594                         u32 requested = 0, value = 0;
1595                         u32 saved = communities[i].hostown[gpp];
1596
1597                         if (padgrp->gpio_base < 0)
1598                                 continue;
1599
1600                         requested = intel_gpio_is_requested(&pctrl->chip,
1601                                         padgrp->gpio_base, padgrp->size);
1602                         value = intel_gpio_update_pad_mode(base + gpp * 4,
1603                                         requested, saved);
1604                         if ((value ^ saved) & requested) {
1605                                 dev_warn(dev, "restore hostown %d/%u %#8x->%#8x\n",
1606                                         i, gpp, value, saved);
1607                         }
1608                 }
1609         }
1610
1611         return 0;
1612 }
1613 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1614 #endif
1615
1616 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1617 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1618 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1619 MODULE_LICENSE("GPL v2");