1 // SPDX-License-Identifier: GPL-2.0
3 * Intel pinctrl/GPIO core driver.
5 * Copyright (C) 2015, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
10 #include <linux/acpi.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/log2.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/property.h>
17 #include <linux/time.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinconf-generic.h>
25 #include "pinctrl-intel.h"
27 /* Offset from regs */
29 #define REVID_SHIFT 16
30 #define REVID_MASK GENMASK(31, 16)
35 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
36 #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
37 #define PADOWN_GPP(p) ((p) / 8)
39 /* Offset from pad_regs */
41 #define PADCFG0_RXEVCFG_SHIFT 25
42 #define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
43 #define PADCFG0_RXEVCFG_LEVEL 0
44 #define PADCFG0_RXEVCFG_EDGE 1
45 #define PADCFG0_RXEVCFG_DISABLED 2
46 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
47 #define PADCFG0_PREGFRXSEL BIT(24)
48 #define PADCFG0_RXINV BIT(23)
49 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
50 #define PADCFG0_GPIROUTSCI BIT(19)
51 #define PADCFG0_GPIROUTSMI BIT(18)
52 #define PADCFG0_GPIROUTNMI BIT(17)
53 #define PADCFG0_PMODE_SHIFT 10
54 #define PADCFG0_PMODE_MASK GENMASK(13, 10)
55 #define PADCFG0_PMODE_GPIO 0
56 #define PADCFG0_GPIORXDIS BIT(9)
57 #define PADCFG0_GPIOTXDIS BIT(8)
58 #define PADCFG0_GPIORXSTATE BIT(1)
59 #define PADCFG0_GPIOTXSTATE BIT(0)
62 #define PADCFG1_TERM_UP BIT(13)
63 #define PADCFG1_TERM_SHIFT 10
64 #define PADCFG1_TERM_MASK GENMASK(12, 10)
65 #define PADCFG1_TERM_20K 4
66 #define PADCFG1_TERM_2K 3
67 #define PADCFG1_TERM_5K 2
68 #define PADCFG1_TERM_1K 1
71 #define PADCFG2_DEBEN BIT(0)
72 #define PADCFG2_DEBOUNCE_SHIFT 1
73 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
75 #define DEBOUNCE_PERIOD_NSEC 31250
77 struct intel_pad_context {
83 struct intel_community_context {
88 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
89 #define padgroup_offset(g, p) ((p) - (g)->base)
91 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
94 struct intel_community *community;
97 for (i = 0; i < pctrl->ncommunities; i++) {
98 community = &pctrl->communities[i];
99 if (pin >= community->pin_base &&
100 pin < community->pin_base + community->npins)
104 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
108 static const struct intel_padgroup *
109 intel_community_get_padgroup(const struct intel_community *community,
114 for (i = 0; i < community->ngpps; i++) {
115 const struct intel_padgroup *padgrp = &community->gpps[i];
117 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
124 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
125 unsigned int pin, unsigned int reg)
127 const struct intel_community *community;
131 community = intel_get_community(pctrl, pin);
135 padno = pin_to_padno(community, pin);
136 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
138 if (reg >= nregs * 4)
141 return community->pad_regs + reg + padno * nregs * 4;
144 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
146 const struct intel_community *community;
147 const struct intel_padgroup *padgrp;
148 unsigned int gpp, offset, gpp_offset;
149 void __iomem *padown;
151 community = intel_get_community(pctrl, pin);
154 if (!community->padown_offset)
157 padgrp = intel_community_get_padgroup(community, pin);
161 gpp_offset = padgroup_offset(padgrp, pin);
162 gpp = PADOWN_GPP(gpp_offset);
163 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
164 padown = community->regs + offset;
166 return !(readl(padown) & PADOWN_MASK(gpp_offset));
169 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
171 const struct intel_community *community;
172 const struct intel_padgroup *padgrp;
173 unsigned int offset, gpp_offset;
174 void __iomem *hostown;
176 community = intel_get_community(pctrl, pin);
179 if (!community->hostown_offset)
182 padgrp = intel_community_get_padgroup(community, pin);
186 gpp_offset = padgroup_offset(padgrp, pin);
187 offset = community->hostown_offset + padgrp->reg_num * 4;
188 hostown = community->regs + offset;
190 return !(readl(hostown) & BIT(gpp_offset));
194 * enum - Locking variants of the pad configuration
196 * @PAD_UNLOCKED: pad is fully controlled by the configuration registers
197 * @PAD_LOCKED: pad configuration registers, except TX state, are locked
198 * @PAD_LOCKED_TX: pad configuration TX state is locked
199 * @PAD_LOCKED_FULL: pad configuration registers are locked completely
201 * Locking is considered as read-only mode for corresponding registers and
202 * their respective fields. That said, TX state bit is locked separately from
203 * the main locking scheme.
209 PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
212 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
214 struct intel_community *community;
215 const struct intel_padgroup *padgrp;
216 unsigned int offset, gpp_offset;
218 int ret = PAD_UNLOCKED;
220 community = intel_get_community(pctrl, pin);
222 return PAD_LOCKED_FULL;
223 if (!community->padcfglock_offset)
226 padgrp = intel_community_get_padgroup(community, pin);
228 return PAD_LOCKED_FULL;
230 gpp_offset = padgroup_offset(padgrp, pin);
233 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
234 * the pad is considered unlocked. Any other case means that it is
235 * either fully or partially locked.
237 offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
238 value = readl(community->regs + offset);
239 if (value & BIT(gpp_offset))
242 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
243 value = readl(community->regs + offset);
244 if (value & BIT(gpp_offset))
245 ret |= PAD_LOCKED_TX;
250 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
252 return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
255 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
257 return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
260 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
262 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
264 return pctrl->soc->ngroups;
267 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
270 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
272 return pctrl->soc->groups[group].name;
275 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
276 const unsigned int **pins, unsigned int *npins)
278 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
280 *pins = pctrl->soc->groups[group].pins;
281 *npins = pctrl->soc->groups[group].npins;
285 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
288 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
289 void __iomem *padcfg;
290 u32 cfg0, cfg1, mode;
294 if (!intel_pad_owned_by_host(pctrl, pin)) {
295 seq_puts(s, "not available");
299 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
300 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
302 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
303 if (mode == PADCFG0_PMODE_GPIO)
304 seq_puts(s, "GPIO ");
306 seq_printf(s, "mode %d ", mode);
308 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
310 /* Dump the additional PADCFG registers if available */
311 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
313 seq_printf(s, " 0x%08x", readl(padcfg));
315 locked = intel_pad_locked(pctrl, pin);
316 acpi = intel_pad_acpi_mode(pctrl, pin);
318 if (locked || acpi) {
321 seq_puts(s, "LOCKED");
322 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
324 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
325 seq_puts(s, " full");
336 static const struct pinctrl_ops intel_pinctrl_ops = {
337 .get_groups_count = intel_get_groups_count,
338 .get_group_name = intel_get_group_name,
339 .get_group_pins = intel_get_group_pins,
340 .pin_dbg_show = intel_pin_dbg_show,
343 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
345 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
347 return pctrl->soc->nfunctions;
350 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
351 unsigned int function)
353 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
355 return pctrl->soc->functions[function].name;
358 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
359 unsigned int function,
360 const char * const **groups,
361 unsigned int * const ngroups)
363 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
365 *groups = pctrl->soc->functions[function].groups;
366 *ngroups = pctrl->soc->functions[function].ngroups;
370 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
371 unsigned int function, unsigned int group)
373 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
374 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
378 raw_spin_lock_irqsave(&pctrl->lock, flags);
381 * All pins in the groups needs to be accessible and writable
382 * before we can enable the mux for this group.
384 for (i = 0; i < grp->npins; i++) {
385 if (!intel_pad_usable(pctrl, grp->pins[i])) {
386 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
391 /* Now enable the mux setting for each pin in the group */
392 for (i = 0; i < grp->npins; i++) {
393 void __iomem *padcfg0;
396 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
397 value = readl(padcfg0);
399 value &= ~PADCFG0_PMODE_MASK;
402 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
404 value |= grp->mode << PADCFG0_PMODE_SHIFT;
406 writel(value, padcfg0);
409 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
414 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
418 value = readl(padcfg0);
420 value &= ~PADCFG0_GPIORXDIS;
421 value |= PADCFG0_GPIOTXDIS;
423 value &= ~PADCFG0_GPIOTXDIS;
424 value |= PADCFG0_GPIORXDIS;
426 writel(value, padcfg0);
429 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
431 return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
434 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
438 value = readl(padcfg0);
440 /* Put the pad into GPIO mode */
441 value &= ~PADCFG0_PMODE_MASK;
442 value |= PADCFG0_PMODE_GPIO;
444 /* Disable input and output buffers */
445 value &= ~PADCFG0_GPIORXDIS;
446 value &= ~PADCFG0_GPIOTXDIS;
448 /* Disable SCI/SMI/NMI generation */
449 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
450 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
452 writel(value, padcfg0);
455 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
456 struct pinctrl_gpio_range *range,
459 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
460 void __iomem *padcfg0;
463 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
465 raw_spin_lock_irqsave(&pctrl->lock, flags);
467 if (!intel_pad_owned_by_host(pctrl, pin)) {
468 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
472 if (!intel_pad_is_unlocked(pctrl, pin)) {
473 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
478 * If pin is already configured in GPIO mode, we assume that
479 * firmware provides correct settings. In such case we avoid
480 * potential glitches on the pin. Otherwise, for the pin in
481 * alternative mode, consumer has to supply respective flags.
483 if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
484 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
488 intel_gpio_set_gpio_mode(padcfg0);
490 /* Disable TX buffer and enable RX (this will be input) */
491 __intel_gpio_set_direction(padcfg0, true);
493 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
498 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
499 struct pinctrl_gpio_range *range,
500 unsigned int pin, bool input)
502 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
503 void __iomem *padcfg0;
506 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
508 raw_spin_lock_irqsave(&pctrl->lock, flags);
509 __intel_gpio_set_direction(padcfg0, input);
510 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
515 static const struct pinmux_ops intel_pinmux_ops = {
516 .get_functions_count = intel_get_functions_count,
517 .get_function_name = intel_get_function_name,
518 .get_function_groups = intel_get_function_groups,
519 .set_mux = intel_pinmux_set_mux,
520 .gpio_request_enable = intel_gpio_request_enable,
521 .gpio_set_direction = intel_gpio_set_direction,
524 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
525 enum pin_config_param param, u32 *arg)
527 const struct intel_community *community;
528 void __iomem *padcfg1;
532 community = intel_get_community(pctrl, pin);
533 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
535 raw_spin_lock_irqsave(&pctrl->lock, flags);
536 value = readl(padcfg1);
537 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
539 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
542 case PIN_CONFIG_BIAS_DISABLE:
547 case PIN_CONFIG_BIAS_PULL_UP:
548 if (!term || !(value & PADCFG1_TERM_UP))
552 case PADCFG1_TERM_1K:
555 case PADCFG1_TERM_2K:
558 case PADCFG1_TERM_5K:
561 case PADCFG1_TERM_20K:
568 case PIN_CONFIG_BIAS_PULL_DOWN:
569 if (!term || value & PADCFG1_TERM_UP)
573 case PADCFG1_TERM_1K:
574 if (!(community->features & PINCTRL_FEATURE_1K_PD))
578 case PADCFG1_TERM_5K:
581 case PADCFG1_TERM_20K:
595 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
596 enum pin_config_param param, u32 *arg)
598 void __iomem *padcfg2;
603 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
607 raw_spin_lock_irqsave(&pctrl->lock, flags);
608 value2 = readl(padcfg2);
609 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
610 if (!(value2 & PADCFG2_DEBEN))
613 v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
614 *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
619 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
620 unsigned long *config)
622 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
623 enum pin_config_param param = pinconf_to_config_param(*config);
627 if (!intel_pad_owned_by_host(pctrl, pin))
631 case PIN_CONFIG_BIAS_DISABLE:
632 case PIN_CONFIG_BIAS_PULL_UP:
633 case PIN_CONFIG_BIAS_PULL_DOWN:
634 ret = intel_config_get_pull(pctrl, pin, param, &arg);
639 case PIN_CONFIG_INPUT_DEBOUNCE:
640 ret = intel_config_get_debounce(pctrl, pin, param, &arg);
649 *config = pinconf_to_config_packed(param, arg);
653 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
654 unsigned long config)
656 unsigned int param = pinconf_to_config_param(config);
657 unsigned int arg = pinconf_to_config_argument(config);
658 const struct intel_community *community;
659 void __iomem *padcfg1;
664 community = intel_get_community(pctrl, pin);
665 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
667 raw_spin_lock_irqsave(&pctrl->lock, flags);
669 value = readl(padcfg1);
672 case PIN_CONFIG_BIAS_DISABLE:
673 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
676 case PIN_CONFIG_BIAS_PULL_UP:
677 value &= ~PADCFG1_TERM_MASK;
679 value |= PADCFG1_TERM_UP;
683 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
686 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
689 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
692 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
700 case PIN_CONFIG_BIAS_PULL_DOWN:
701 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
705 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
708 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
711 if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
715 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
725 writel(value, padcfg1);
727 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
732 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
733 unsigned int pin, unsigned int debounce)
735 void __iomem *padcfg0, *padcfg2;
739 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
743 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
745 raw_spin_lock_irqsave(&pctrl->lock, flags);
747 value0 = readl(padcfg0);
748 value2 = readl(padcfg2);
750 /* Disable glitch filter and debouncer */
751 value0 &= ~PADCFG0_PREGFRXSEL;
752 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
757 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
758 if (v < 3 || v > 15) {
759 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
763 /* Enable glitch filter and debouncer */
764 value0 |= PADCFG0_PREGFRXSEL;
765 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
766 value2 |= PADCFG2_DEBEN;
769 writel(value0, padcfg0);
770 writel(value2, padcfg2);
772 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
777 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
778 unsigned long *configs, unsigned int nconfigs)
780 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
783 if (!intel_pad_usable(pctrl, pin))
786 for (i = 0; i < nconfigs; i++) {
787 switch (pinconf_to_config_param(configs[i])) {
788 case PIN_CONFIG_BIAS_DISABLE:
789 case PIN_CONFIG_BIAS_PULL_UP:
790 case PIN_CONFIG_BIAS_PULL_DOWN:
791 ret = intel_config_set_pull(pctrl, pin, configs[i]);
796 case PIN_CONFIG_INPUT_DEBOUNCE:
797 ret = intel_config_set_debounce(pctrl, pin,
798 pinconf_to_config_argument(configs[i]));
811 static const struct pinconf_ops intel_pinconf_ops = {
813 .pin_config_get = intel_config_get,
814 .pin_config_set = intel_config_set,
817 static const struct pinctrl_desc intel_pinctrl_desc = {
818 .pctlops = &intel_pinctrl_ops,
819 .pmxops = &intel_pinmux_ops,
820 .confops = &intel_pinconf_ops,
821 .owner = THIS_MODULE,
825 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
826 * @pctrl: Pinctrl structure
827 * @offset: GPIO offset from gpiolib
828 * @community: Community is filled here if not %NULL
829 * @padgrp: Pad group is filled here if not %NULL
831 * When coming through gpiolib irqchip, the GPIO offset is not
832 * automatically translated to pinctrl pin number. This function can be
833 * used to find out the corresponding pinctrl pin.
835 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
836 const struct intel_community **community,
837 const struct intel_padgroup **padgrp)
841 for (i = 0; i < pctrl->ncommunities; i++) {
842 const struct intel_community *comm = &pctrl->communities[i];
845 for (j = 0; j < comm->ngpps; j++) {
846 const struct intel_padgroup *pgrp = &comm->gpps[j];
848 if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
851 if (offset >= pgrp->gpio_base &&
852 offset < pgrp->gpio_base + pgrp->size) {
855 pin = pgrp->base + offset - pgrp->gpio_base;
870 * intel_pin_to_gpio() - Translate from pin number to GPIO offset
871 * @pctrl: Pinctrl structure
874 * Translate the pin number of pinctrl to GPIO offset
876 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
878 const struct intel_community *community;
879 const struct intel_padgroup *padgrp;
881 community = intel_get_community(pctrl, pin);
885 padgrp = intel_community_get_padgroup(community, pin);
889 return pin - padgrp->base + padgrp->gpio_base;
892 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
894 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
899 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
903 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
907 padcfg0 = readl(reg);
908 if (!(padcfg0 & PADCFG0_GPIOTXDIS))
909 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
911 return !!(padcfg0 & PADCFG0_GPIORXSTATE);
914 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
917 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
923 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
927 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
931 raw_spin_lock_irqsave(&pctrl->lock, flags);
932 padcfg0 = readl(reg);
934 padcfg0 |= PADCFG0_GPIOTXSTATE;
936 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
937 writel(padcfg0, reg);
938 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
941 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
943 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
949 pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
953 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
957 raw_spin_lock_irqsave(&pctrl->lock, flags);
958 padcfg0 = readl(reg);
959 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
960 if (padcfg0 & PADCFG0_PMODE_MASK)
963 if (padcfg0 & PADCFG0_GPIOTXDIS)
964 return GPIO_LINE_DIRECTION_IN;
966 return GPIO_LINE_DIRECTION_OUT;
969 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
971 return pinctrl_gpio_direction_input(chip->base + offset);
974 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
977 intel_gpio_set(chip, offset, value);
978 return pinctrl_gpio_direction_output(chip->base + offset);
981 static const struct gpio_chip intel_gpio_chip = {
982 .owner = THIS_MODULE,
983 .request = gpiochip_generic_request,
984 .free = gpiochip_generic_free,
985 .get_direction = intel_gpio_get_direction,
986 .direction_input = intel_gpio_direction_input,
987 .direction_output = intel_gpio_direction_output,
988 .get = intel_gpio_get,
989 .set = intel_gpio_set,
990 .set_config = gpiochip_generic_config,
993 static void intel_gpio_irq_ack(struct irq_data *d)
995 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
996 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
997 const struct intel_community *community;
998 const struct intel_padgroup *padgrp;
1001 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1003 unsigned int gpp, gpp_offset, is_offset;
1005 gpp = padgrp->reg_num;
1006 gpp_offset = padgroup_offset(padgrp, pin);
1007 is_offset = community->is_offset + gpp * 4;
1009 raw_spin_lock(&pctrl->lock);
1010 writel(BIT(gpp_offset), community->regs + is_offset);
1011 raw_spin_unlock(&pctrl->lock);
1015 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1017 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1018 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1019 const struct intel_community *community;
1020 const struct intel_padgroup *padgrp;
1023 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1025 unsigned int gpp, gpp_offset;
1026 unsigned long flags;
1027 void __iomem *reg, *is;
1030 gpp = padgrp->reg_num;
1031 gpp_offset = padgroup_offset(padgrp, pin);
1033 reg = community->regs + community->ie_offset + gpp * 4;
1034 is = community->regs + community->is_offset + gpp * 4;
1036 raw_spin_lock_irqsave(&pctrl->lock, flags);
1038 /* Clear interrupt status first to avoid unexpected interrupt */
1039 writel(BIT(gpp_offset), is);
1043 value &= ~BIT(gpp_offset);
1045 value |= BIT(gpp_offset);
1047 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1051 static void intel_gpio_irq_mask(struct irq_data *d)
1053 intel_gpio_irq_mask_unmask(d, true);
1056 static void intel_gpio_irq_unmask(struct irq_data *d)
1058 intel_gpio_irq_mask_unmask(d, false);
1061 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1063 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1064 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1065 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1066 unsigned long flags;
1070 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1075 * If the pin is in ACPI mode it is still usable as a GPIO but it
1076 * cannot be used as IRQ because GPI_IS status bit will not be
1077 * updated by the host controller hardware.
1079 if (intel_pad_acpi_mode(pctrl, pin)) {
1080 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1084 raw_spin_lock_irqsave(&pctrl->lock, flags);
1086 intel_gpio_set_gpio_mode(reg);
1088 /* Disable TX buffer and enable RX (this will be input) */
1089 __intel_gpio_set_direction(reg, true);
1093 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1095 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1096 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1097 } else if (type & IRQ_TYPE_EDGE_FALLING) {
1098 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1099 value |= PADCFG0_RXINV;
1100 } else if (type & IRQ_TYPE_EDGE_RISING) {
1101 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1102 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1103 if (type & IRQ_TYPE_LEVEL_LOW)
1104 value |= PADCFG0_RXINV;
1106 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1111 if (type & IRQ_TYPE_EDGE_BOTH)
1112 irq_set_handler_locked(d, handle_edge_irq);
1113 else if (type & IRQ_TYPE_LEVEL_MASK)
1114 irq_set_handler_locked(d, handle_level_irq);
1116 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1121 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1123 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1124 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1125 unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1128 enable_irq_wake(pctrl->irq);
1130 disable_irq_wake(pctrl->irq);
1132 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1136 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1137 const struct intel_community *community)
1139 struct gpio_chip *gc = &pctrl->chip;
1143 for (gpp = 0; gpp < community->ngpps; gpp++) {
1144 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1145 unsigned long pending, enabled, gpp_offset;
1146 unsigned long flags;
1148 raw_spin_lock_irqsave(&pctrl->lock, flags);
1150 pending = readl(community->regs + community->is_offset +
1151 padgrp->reg_num * 4);
1152 enabled = readl(community->regs + community->ie_offset +
1153 padgrp->reg_num * 4);
1155 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1157 /* Only interrupts that are enabled */
1160 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1163 irq = irq_find_mapping(gc->irq.domain,
1164 padgrp->gpio_base + gpp_offset);
1165 generic_handle_irq(irq);
1168 ret += pending ? 1 : 0;
1174 static irqreturn_t intel_gpio_irq(int irq, void *data)
1176 const struct intel_community *community;
1177 struct intel_pinctrl *pctrl = data;
1181 /* Need to check all communities for pending interrupts */
1182 for (i = 0; i < pctrl->ncommunities; i++) {
1183 community = &pctrl->communities[i];
1184 ret += intel_gpio_community_irq_handler(pctrl, community);
1187 return IRQ_RETVAL(ret);
1190 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
1191 const struct intel_community *community)
1195 for (i = 0; i < community->ngpps; i++) {
1196 const struct intel_padgroup *gpp = &community->gpps[i];
1198 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1201 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1202 gpp->gpio_base, gpp->base,
1211 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1213 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1216 for (i = 0; i < pctrl->ncommunities; i++) {
1217 struct intel_community *community = &pctrl->communities[i];
1219 ret = intel_gpio_add_community_ranges(pctrl, community);
1221 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1229 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1231 const struct intel_community *community;
1232 unsigned int ngpio = 0;
1235 for (i = 0; i < pctrl->ncommunities; i++) {
1236 community = &pctrl->communities[i];
1237 for (j = 0; j < community->ngpps; j++) {
1238 const struct intel_padgroup *gpp = &community->gpps[j];
1240 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1243 if (gpp->gpio_base + gpp->size > ngpio)
1244 ngpio = gpp->gpio_base + gpp->size;
1251 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1254 struct gpio_irq_chip *girq;
1256 pctrl->chip = intel_gpio_chip;
1258 /* Setup GPIO chip */
1259 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1260 pctrl->chip.label = dev_name(pctrl->dev);
1261 pctrl->chip.parent = pctrl->dev;
1262 pctrl->chip.base = -1;
1263 pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1266 /* Setup IRQ chip */
1267 pctrl->irqchip.name = dev_name(pctrl->dev);
1268 pctrl->irqchip.irq_ack = intel_gpio_irq_ack;
1269 pctrl->irqchip.irq_mask = intel_gpio_irq_mask;
1270 pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;
1271 pctrl->irqchip.irq_set_type = intel_gpio_irq_type;
1272 pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
1273 pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
1276 * On some platforms several GPIO controllers share the same interrupt
1279 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1280 IRQF_SHARED | IRQF_NO_THREAD,
1281 dev_name(pctrl->dev), pctrl);
1283 dev_err(pctrl->dev, "failed to request interrupt\n");
1287 girq = &pctrl->chip.irq;
1288 girq->chip = &pctrl->irqchip;
1289 /* This will let us handle the IRQ in the driver */
1290 girq->parent_handler = NULL;
1291 girq->num_parents = 0;
1292 girq->default_type = IRQ_TYPE_NONE;
1293 girq->handler = handle_bad_irq;
1295 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1297 dev_err(pctrl->dev, "failed to register gpiochip\n");
1304 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1305 struct intel_community *community)
1307 struct intel_padgroup *gpps;
1308 unsigned int npins = community->npins;
1309 unsigned int padown_num = 0;
1312 if (community->gpps)
1313 ngpps = community->ngpps;
1315 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1317 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1321 for (i = 0; i < ngpps; i++) {
1322 if (community->gpps) {
1323 gpps[i] = community->gpps[i];
1325 unsigned int gpp_size = community->gpp_size;
1327 gpps[i].reg_num = i;
1328 gpps[i].base = community->pin_base + i * gpp_size;
1329 gpps[i].size = min(gpp_size, npins);
1330 npins -= gpps[i].size;
1333 if (gpps[i].size > 32)
1336 /* Special treatment for GPIO base */
1337 switch (gpps[i].gpio_base) {
1338 case INTEL_GPIO_BASE_MATCH:
1339 gpps[i].gpio_base = gpps[i].base;
1341 case INTEL_GPIO_BASE_ZERO:
1342 gpps[i].gpio_base = 0;
1344 case INTEL_GPIO_BASE_NOMAP:
1349 gpps[i].padown_num = padown_num;
1352 * In older hardware the number of padown registers per
1353 * group is fixed regardless of the group size.
1355 if (community->gpp_num_padown_regs)
1356 padown_num += community->gpp_num_padown_regs;
1358 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1361 community->ngpps = ngpps;
1362 community->gpps = gpps;
1367 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1369 #ifdef CONFIG_PM_SLEEP
1370 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1371 struct intel_community_context *communities;
1372 struct intel_pad_context *pads;
1375 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1379 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1380 sizeof(*communities), GFP_KERNEL);
1385 for (i = 0; i < pctrl->ncommunities; i++) {
1386 struct intel_community *community = &pctrl->communities[i];
1387 u32 *intmask, *hostown;
1389 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1390 sizeof(*intmask), GFP_KERNEL);
1394 communities[i].intmask = intmask;
1396 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1397 sizeof(*hostown), GFP_KERNEL);
1401 communities[i].hostown = hostown;
1404 pctrl->context.pads = pads;
1405 pctrl->context.communities = communities;
1411 static int intel_pinctrl_probe(struct platform_device *pdev,
1412 const struct intel_pinctrl_soc_data *soc_data)
1414 struct intel_pinctrl *pctrl;
1420 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1424 pctrl->dev = &pdev->dev;
1425 pctrl->soc = soc_data;
1426 raw_spin_lock_init(&pctrl->lock);
1429 * Make a copy of the communities which we can use to hold pointers
1432 pctrl->ncommunities = pctrl->soc->ncommunities;
1433 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1434 sizeof(*pctrl->communities), GFP_KERNEL);
1435 if (!pctrl->communities)
1438 for (i = 0; i < pctrl->ncommunities; i++) {
1439 struct intel_community *community = &pctrl->communities[i];
1443 *community = pctrl->soc->communities[i];
1445 regs = devm_platform_ioremap_resource(pdev, community->barno);
1447 return PTR_ERR(regs);
1450 * Determine community features based on the revision if
1451 * not specified already.
1453 if (!community->features) {
1456 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1458 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1459 community->features |= PINCTRL_FEATURE_1K_PD;
1463 /* Read offset of the pad configuration registers */
1464 padbar = readl(regs + PADBAR);
1466 community->regs = regs;
1467 community->pad_regs = regs + padbar;
1469 ret = intel_pinctrl_add_padgroups(pctrl, community);
1474 irq = platform_get_irq(pdev, 0);
1478 ret = intel_pinctrl_pm_init(pctrl);
1482 pctrl->pctldesc = intel_pinctrl_desc;
1483 pctrl->pctldesc.name = dev_name(&pdev->dev);
1484 pctrl->pctldesc.pins = pctrl->soc->pins;
1485 pctrl->pctldesc.npins = pctrl->soc->npins;
1487 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1489 if (IS_ERR(pctrl->pctldev)) {
1490 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1491 return PTR_ERR(pctrl->pctldev);
1494 ret = intel_gpio_probe(pctrl, irq);
1498 platform_set_drvdata(pdev, pctrl);
1503 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1505 const struct intel_pinctrl_soc_data *data;
1507 data = device_get_match_data(&pdev->dev);
1508 return intel_pinctrl_probe(pdev, data);
1510 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
1512 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1514 const struct intel_pinctrl_soc_data *data = NULL;
1515 const struct intel_pinctrl_soc_data **table;
1516 struct acpi_device *adev;
1519 adev = ACPI_COMPANION(&pdev->dev);
1521 const void *match = device_get_match_data(&pdev->dev);
1523 table = (const struct intel_pinctrl_soc_data **)match;
1524 for (i = 0; table[i]; i++) {
1525 if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
1531 const struct platform_device_id *id;
1533 id = platform_get_device_id(pdev);
1537 table = (const struct intel_pinctrl_soc_data **)id->driver_data;
1538 data = table[pdev->id];
1541 return intel_pinctrl_probe(pdev, data);
1543 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
1545 #ifdef CONFIG_PM_SLEEP
1546 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1548 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1550 if (!pd || !intel_pad_usable(pctrl, pin))
1554 * Only restore the pin if it is actually in use by the kernel (or
1555 * by userspace). It is possible that some pins are used by the
1556 * BIOS during resume and those are not always locked down so leave
1559 if (pd->mux_owner || pd->gpio_owner ||
1560 gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1566 int intel_pinctrl_suspend_noirq(struct device *dev)
1568 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1569 struct intel_community_context *communities;
1570 struct intel_pad_context *pads;
1573 pads = pctrl->context.pads;
1574 for (i = 0; i < pctrl->soc->npins; i++) {
1575 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1576 void __iomem *padcfg;
1579 if (!intel_pinctrl_should_save(pctrl, desc->number))
1582 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1583 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1584 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1585 pads[i].padcfg1 = val;
1587 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1589 pads[i].padcfg2 = readl(padcfg);
1592 communities = pctrl->context.communities;
1593 for (i = 0; i < pctrl->ncommunities; i++) {
1594 struct intel_community *community = &pctrl->communities[i];
1598 base = community->regs + community->ie_offset;
1599 for (gpp = 0; gpp < community->ngpps; gpp++)
1600 communities[i].intmask[gpp] = readl(base + gpp * 4);
1602 base = community->regs + community->hostown_offset;
1603 for (gpp = 0; gpp < community->ngpps; gpp++)
1604 communities[i].hostown[gpp] = readl(base + gpp * 4);
1609 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1611 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1615 for (i = 0; i < pctrl->ncommunities; i++) {
1616 const struct intel_community *community;
1620 community = &pctrl->communities[i];
1621 base = community->regs;
1623 for (gpp = 0; gpp < community->ngpps; gpp++) {
1624 /* Mask and clear all interrupts */
1625 writel(0, base + community->ie_offset + gpp * 4);
1626 writel(0xffff, base + community->is_offset + gpp * 4);
1631 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1637 updated = (curr & ~mask) | (value & mask);
1638 if (curr == updated)
1641 writel(updated, reg);
1645 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1646 void __iomem *base, unsigned int gpp, u32 saved)
1648 const struct intel_community *community = &pctrl->communities[c];
1649 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1650 struct device *dev = pctrl->dev;
1655 if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1658 for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
1659 requested |= BIT(i);
1661 if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1664 dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1667 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1668 void __iomem *base, unsigned int gpp, u32 saved)
1670 struct device *dev = pctrl->dev;
1672 if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1675 dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1678 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1679 unsigned int reg, u32 saved)
1681 u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1682 unsigned int n = reg / sizeof(u32);
1683 struct device *dev = pctrl->dev;
1684 void __iomem *padcfg;
1686 padcfg = intel_get_padcfg(pctrl, pin, reg);
1690 if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1693 dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1696 int intel_pinctrl_resume_noirq(struct device *dev)
1698 struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1699 const struct intel_community_context *communities;
1700 const struct intel_pad_context *pads;
1703 /* Mask all interrupts */
1704 intel_gpio_irq_init(pctrl);
1706 pads = pctrl->context.pads;
1707 for (i = 0; i < pctrl->soc->npins; i++) {
1708 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1710 if (!intel_pinctrl_should_save(pctrl, desc->number))
1713 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1714 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1715 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1718 communities = pctrl->context.communities;
1719 for (i = 0; i < pctrl->ncommunities; i++) {
1720 struct intel_community *community = &pctrl->communities[i];
1724 base = community->regs + community->ie_offset;
1725 for (gpp = 0; gpp < community->ngpps; gpp++)
1726 intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1728 base = community->regs + community->hostown_offset;
1729 for (gpp = 0; gpp < community->ngpps; gpp++)
1730 intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1735 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1738 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1739 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1740 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1741 MODULE_LICENSE("GPL v2");