drivers/pinctrl/intel/pinctrl-intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel pinctrl/GPIO core driver.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/log2.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/property.h>
  17 #include <linux/time.h>
  18
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/pinctrl/pinconf.h>
  22 #include <linux/pinctrl/pinconf-generic.h>
  23
  24 #include "../core.h"
  25 #include "pinctrl-intel.h"
  26
  27 /* Offset from regs */
  28 #define REVID                           0x000
  29 #define REVID_SHIFT                     16
  30 #define REVID_MASK                      GENMASK(31, 16)
  31
  32 #define PADBAR                          0x00c
  33
  34 #define PADOWN_BITS                     4
  35 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  36 #define PADOWN_MASK(p)                  (GENMASK(3, 0) << PADOWN_SHIFT(p))
  37 #define PADOWN_GPP(p)                   ((p) / 8)
  38
  39 /* Offset from pad_regs */
  40 #define PADCFG0                         0x000
  41 #define PADCFG0_RXEVCFG_SHIFT           25
  42 #define PADCFG0_RXEVCFG_MASK            GENMASK(26, 25)
  43 #define PADCFG0_RXEVCFG_LEVEL           0
  44 #define PADCFG0_RXEVCFG_EDGE            1
  45 #define PADCFG0_RXEVCFG_DISABLED        2
  46 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  47 #define PADCFG0_PREGFRXSEL              BIT(24)
  48 #define PADCFG0_RXINV                   BIT(23)
  49 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  50 #define PADCFG0_GPIROUTSCI              BIT(19)
  51 #define PADCFG0_GPIROUTSMI              BIT(18)
  52 #define PADCFG0_GPIROUTNMI              BIT(17)
  53 #define PADCFG0_PMODE_SHIFT             10
  54 #define PADCFG0_PMODE_MASK              GENMASK(13, 10)
  55 #define PADCFG0_PMODE_GPIO              0
  56 #define PADCFG0_GPIORXDIS               BIT(9)
  57 #define PADCFG0_GPIOTXDIS               BIT(8)
  58 #define PADCFG0_GPIORXSTATE             BIT(1)
  59 #define PADCFG0_GPIOTXSTATE             BIT(0)
  60
  61 #define PADCFG1                         0x004
  62 #define PADCFG1_TERM_UP                 BIT(13)
  63 #define PADCFG1_TERM_SHIFT              10
  64 #define PADCFG1_TERM_MASK               GENMASK(12, 10)
  65 #define PADCFG1_TERM_20K                4
  66 #define PADCFG1_TERM_2K                 3
  67 #define PADCFG1_TERM_5K                 2
  68 #define PADCFG1_TERM_1K                 1
  69
  70 #define PADCFG2                         0x008
  71 #define PADCFG2_DEBEN                   BIT(0)
  72 #define PADCFG2_DEBOUNCE_SHIFT          1
  73 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
  74
  75 #define DEBOUNCE_PERIOD_NSEC            31250
  76
  77 struct intel_pad_context {
  78         u32 padcfg0;
  79         u32 padcfg1;
  80         u32 padcfg2;
  81 };
  82
  83 struct intel_community_context {
  84         u32 *intmask;
  85         u32 *hostown;
  86 };
  87
  88 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
  89 #define padgroup_offset(g, p)   ((p) - (g)->base)
  90
  91 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
  92                                                    unsigned int pin)
  93 {
  94         struct intel_community *community;
  95         int i;
  96
  97         for (i = 0; i < pctrl->ncommunities; i++) {
  98                 community = &pctrl->communities[i];
  99                 if (pin >= community->pin_base &&
 100                     pin < community->pin_base + community->npins)
 101                         return community;
 102         }
 103
 104         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 105         return NULL;
 106 }
 107
 108 static const struct intel_padgroup *
 109 intel_community_get_padgroup(const struct intel_community *community,
 110                              unsigned int pin)
 111 {
 112         int i;
 113
 114         for (i = 0; i < community->ngpps; i++) {
 115                 const struct intel_padgroup *padgrp = &community->gpps[i];
 116
 117                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 118                         return padgrp;
 119         }
 120
 121         return NULL;
 122 }
 123
 124 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
 125                                       unsigned int pin, unsigned int reg)
 126 {
 127         const struct intel_community *community;
 128         unsigned int padno;
 129         size_t nregs;
 130
 131         community = intel_get_community(pctrl, pin);
 132         if (!community)
 133                 return NULL;
 134
 135         padno = pin_to_padno(community, pin);
 136         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 137
 138         if (reg >= nregs * 4)
 139                 return NULL;
 140
 141         return community->pad_regs + reg + padno * nregs * 4;
 142 }
 143
 144 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
 145 {
 146         const struct intel_community *community;
 147         const struct intel_padgroup *padgrp;
 148         unsigned int gpp, offset, gpp_offset;
 149         void __iomem *padown;
 150
 151         community = intel_get_community(pctrl, pin);
 152         if (!community)
 153                 return false;
 154         if (!community->padown_offset)
 155                 return true;
 156
 157         padgrp = intel_community_get_padgroup(community, pin);
 158         if (!padgrp)
 159                 return false;
 160
 161         gpp_offset = padgroup_offset(padgrp, pin);
 162         gpp = PADOWN_GPP(gpp_offset);
 163         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 164         padown = community->regs + offset;
 165
 166         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 167 }
 168
 169 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
 170 {
 171         const struct intel_community *community;
 172         const struct intel_padgroup *padgrp;
 173         unsigned int offset, gpp_offset;
 174         void __iomem *hostown;
 175
 176         community = intel_get_community(pctrl, pin);
 177         if (!community)
 178                 return true;
 179         if (!community->hostown_offset)
 180                 return false;
 181
 182         padgrp = intel_community_get_padgroup(community, pin);
 183         if (!padgrp)
 184                 return true;
 185
 186         gpp_offset = padgroup_offset(padgrp, pin);
 187         offset = community->hostown_offset + padgrp->reg_num * 4;
 188         hostown = community->regs + offset;
 189
 190         return !(readl(hostown) & BIT(gpp_offset));
 191 }
 192
 193 /**
 194  * enum - Locking variants of the pad configuration
 195  *
 196  * @PAD_UNLOCKED:       pad is fully controlled by the configuration registers
 197  * @PAD_LOCKED:         pad configuration registers, except TX state, are locked
 198  * @PAD_LOCKED_TX:      pad configuration TX state is locked
 199  * @PAD_LOCKED_FULL:    pad configuration registers are locked completely
 200  *
 201  * Locking is considered as read-only mode for corresponding registers and
 202  * their respective fields. That said, TX state bit is locked separately from
 203  * the main locking scheme.
 204  */
 205 enum {
 206         PAD_UNLOCKED    = 0,
 207         PAD_LOCKED      = 1,
 208         PAD_LOCKED_TX   = 2,
 209         PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
 210 };
 211
 212 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
 213 {
 214         struct intel_community *community;
 215         const struct intel_padgroup *padgrp;
 216         unsigned int offset, gpp_offset;
 217         u32 value;
 218         int ret = PAD_UNLOCKED;
 219
 220         community = intel_get_community(pctrl, pin);
 221         if (!community)
 222                 return PAD_LOCKED_FULL;
 223         if (!community->padcfglock_offset)
 224                 return PAD_UNLOCKED;
 225
 226         padgrp = intel_community_get_padgroup(community, pin);
 227         if (!padgrp)
 228                 return PAD_LOCKED_FULL;
 229
 230         gpp_offset = padgroup_offset(padgrp, pin);
 231
 232         /*
 233          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 234          * the pad is considered unlocked. Any other case means that it is
 235          * either fully or partially locked.
 236          */
 237         offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
 238         value = readl(community->regs + offset);
 239         if (value & BIT(gpp_offset))
 240                 ret |= PAD_LOCKED;
 241
 242         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 243         value = readl(community->regs + offset);
 244         if (value & BIT(gpp_offset))
 245                 ret |= PAD_LOCKED_TX;
 246
 247         return ret;
 248 }
 249
 250 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
 251 {
 252         return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
 253 }
 254
 255 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
 256 {
 257         return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
 258 }
 259
 260 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 261 {
 262         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 263
 264         return pctrl->soc->ngroups;
 265 }
 266
 267 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 268                                       unsigned int group)
 269 {
 270         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 271
 272         return pctrl->soc->groups[group].name;
 273 }
 274
 275 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 276                               const unsigned int **pins, unsigned int *npins)
 277 {
 278         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 279
 280         *pins = pctrl->soc->groups[group].pins;
 281         *npins = pctrl->soc->groups[group].npins;
 282         return 0;
 283 }
 284
 285 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 286                                unsigned int pin)
 287 {
 288         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 289         void __iomem *padcfg;
 290         u32 cfg0, cfg1, mode;
 291         int locked;
 292         bool acpi;
 293
 294         if (!intel_pad_owned_by_host(pctrl, pin)) {
 295                 seq_puts(s, "not available");
 296                 return;
 297         }
 298
 299         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 300         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 301
 302         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 303         if (mode == PADCFG0_PMODE_GPIO)
 304                 seq_puts(s, "GPIO ");
 305         else
 306                 seq_printf(s, "mode %d ", mode);
 307
 308         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 309
 310         /* Dump the additional PADCFG registers if available */
 311         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 312         if (padcfg)
 313                 seq_printf(s, " 0x%08x", readl(padcfg));
 314
 315         locked = intel_pad_locked(pctrl, pin);
 316         acpi = intel_pad_acpi_mode(pctrl, pin);
 317
 318         if (locked || acpi) {
 319                 seq_puts(s, " [");
 320                 if (locked)
 321                         seq_puts(s, "LOCKED");
 322                 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
 323                         seq_puts(s, " tx");
 324                 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
 325                         seq_puts(s, " full");
 326
 327                 if (locked && acpi)
 328                         seq_puts(s, ", ");
 329
 330                 if (acpi)
 331                         seq_puts(s, "ACPI");
 332                 seq_puts(s, "]");
 333         }
 334 }
 335
 336 static const struct pinctrl_ops intel_pinctrl_ops = {
 337         .get_groups_count = intel_get_groups_count,
 338         .get_group_name = intel_get_group_name,
 339         .get_group_pins = intel_get_group_pins,
 340         .pin_dbg_show = intel_pin_dbg_show,
 341 };
 342
 343 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 344 {
 345         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 346
 347         return pctrl->soc->nfunctions;
 348 }
 349
 350 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 351                                            unsigned int function)
 352 {
 353         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 354
 355         return pctrl->soc->functions[function].name;
 356 }
 357
 358 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 359                                      unsigned int function,
 360                                      const char * const **groups,
 361                                      unsigned int * const ngroups)
 362 {
 363         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 364
 365         *groups = pctrl->soc->functions[function].groups;
 366         *ngroups = pctrl->soc->functions[function].ngroups;
 367         return 0;
 368 }
 369
 370 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
 371                                 unsigned int function, unsigned int group)
 372 {
 373         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 374         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 375         unsigned long flags;
 376         int i;
 377
 378         raw_spin_lock_irqsave(&pctrl->lock, flags);
 379
 380         /*
 381          * All pins in the groups needs to be accessible and writable
 382          * before we can enable the mux for this group.
 383          */
 384         for (i = 0; i < grp->npins; i++) {
 385                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
 386                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 387                         return -EBUSY;
 388                 }
 389         }
 390
 391         /* Now enable the mux setting for each pin in the group */
 392         for (i = 0; i < grp->npins; i++) {
 393                 void __iomem *padcfg0;
 394                 u32 value;
 395
 396                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
 397                 value = readl(padcfg0);
 398
 399                 value &= ~PADCFG0_PMODE_MASK;
 400
 401                 if (grp->modes)
 402                         value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
 403                 else
 404                         value |= grp->mode << PADCFG0_PMODE_SHIFT;
 405
 406                 writel(value, padcfg0);
 407         }
 408
 409         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 410
 411         return 0;
 412 }
 413
 414 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 415 {
 416         u32 value;
 417
 418         value = readl(padcfg0);
 419         if (input) {
 420                 value &= ~PADCFG0_GPIORXDIS;
 421                 value |= PADCFG0_GPIOTXDIS;
 422         } else {
 423                 value &= ~PADCFG0_GPIOTXDIS;
 424                 value |= PADCFG0_GPIORXDIS;
 425         }
 426         writel(value, padcfg0);
 427 }
 428
 429 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
 430 {
 431         return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 432 }
 433
 434 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 435 {
 436         u32 value;
 437
 438         /* Put the pad into GPIO mode */
 439         value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
 440         /* Disable SCI/SMI/NMI generation */
 441         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 442         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 443         writel(value, padcfg0);
 444 }
 445
 446 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 447                                      struct pinctrl_gpio_range *range,
 448                                      unsigned int pin)
 449 {
 450         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 451         void __iomem *padcfg0;
 452         unsigned long flags;
 453
 454         raw_spin_lock_irqsave(&pctrl->lock, flags);
 455
 456         if (!intel_pad_owned_by_host(pctrl, pin)) {
 457                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 458                 return -EBUSY;
 459         }
 460
 461         if (!intel_pad_is_unlocked(pctrl, pin)) {
 462                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 463                 return 0;
 464         }
 465
 466         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 467
 468         /*
 469          * If pin is already configured in GPIO mode, we assume that
 470          * firmware provides correct settings. In such case we avoid
 471          * potential glitches on the pin. Otherwise, for the pin in
 472          * alternative mode, consumer has to supply respective flags.
 473          */
 474         if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
 475                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 476                 return 0;
 477         }
 478
 479         intel_gpio_set_gpio_mode(padcfg0);
 480
 481         /* Disable TX buffer and enable RX (this will be input) */
 482         __intel_gpio_set_direction(padcfg0, true);
 483
 484         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 485
 486         return 0;
 487 }
 488
 489 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 490                                     struct pinctrl_gpio_range *range,
 491                                     unsigned int pin, bool input)
 492 {
 493         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 494         void __iomem *padcfg0;
 495         unsigned long flags;
 496
 497         raw_spin_lock_irqsave(&pctrl->lock, flags);
 498
 499         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 500         __intel_gpio_set_direction(padcfg0, input);
 501
 502         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 503
 504         return 0;
 505 }
 506
 507 static const struct pinmux_ops intel_pinmux_ops = {
 508         .get_functions_count = intel_get_functions_count,
 509         .get_function_name = intel_get_function_name,
 510         .get_function_groups = intel_get_function_groups,
 511         .set_mux = intel_pinmux_set_mux,
 512         .gpio_request_enable = intel_gpio_request_enable,
 513         .gpio_set_direction = intel_gpio_set_direction,
 514 };
 515
 516 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 517                             unsigned long *config)
 518 {
 519         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 520         enum pin_config_param param = pinconf_to_config_param(*config);
 521         const struct intel_community *community;
 522         u32 value, term;
 523         u32 arg = 0;
 524
 525         if (!intel_pad_owned_by_host(pctrl, pin))
 526                 return -ENOTSUPP;
 527
 528         community = intel_get_community(pctrl, pin);
 529         value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 530         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 531
 532         switch (param) {
 533         case PIN_CONFIG_BIAS_DISABLE:
 534                 if (term)
 535                         return -EINVAL;
 536                 break;
 537
 538         case PIN_CONFIG_BIAS_PULL_UP:
 539                 if (!term || !(value & PADCFG1_TERM_UP))
 540                         return -EINVAL;
 541
 542                 switch (term) {
 543                 case PADCFG1_TERM_1K:
 544                         arg = 1000;
 545                         break;
 546                 case PADCFG1_TERM_2K:
 547                         arg = 2000;
 548                         break;
 549                 case PADCFG1_TERM_5K:
 550                         arg = 5000;
 551                         break;
 552                 case PADCFG1_TERM_20K:
 553                         arg = 20000;
 554                         break;
 555                 }
 556
 557                 break;
 558
 559         case PIN_CONFIG_BIAS_PULL_DOWN:
 560                 if (!term || value & PADCFG1_TERM_UP)
 561                         return -EINVAL;
 562
 563                 switch (term) {
 564                 case PADCFG1_TERM_1K:
 565                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 566                                 return -EINVAL;
 567                         arg = 1000;
 568                         break;
 569                 case PADCFG1_TERM_5K:
 570                         arg = 5000;
 571                         break;
 572                 case PADCFG1_TERM_20K:
 573                         arg = 20000;
 574                         break;
 575                 }
 576
 577                 break;
 578
 579         case PIN_CONFIG_INPUT_DEBOUNCE: {
 580                 void __iomem *padcfg2;
 581                 u32 v;
 582
 583                 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 584                 if (!padcfg2)
 585                         return -ENOTSUPP;
 586
 587                 v = readl(padcfg2);
 588                 if (!(v & PADCFG2_DEBEN))
 589                         return -EINVAL;
 590
 591                 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 592                 arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
 593
 594                 break;
 595         }
 596
 597         default:
 598                 return -ENOTSUPP;
 599         }
 600
 601         *config = pinconf_to_config_packed(param, arg);
 602         return 0;
 603 }
 604
 605 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 606                                  unsigned long config)
 607 {
 608         unsigned int param = pinconf_to_config_param(config);
 609         unsigned int arg = pinconf_to_config_argument(config);
 610         const struct intel_community *community;
 611         void __iomem *padcfg1;
 612         unsigned long flags;
 613         int ret = 0;
 614         u32 value;
 615
 616         raw_spin_lock_irqsave(&pctrl->lock, flags);
 617
 618         community = intel_get_community(pctrl, pin);
 619         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 620         value = readl(padcfg1);
 621
 622         switch (param) {
 623         case PIN_CONFIG_BIAS_DISABLE:
 624                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 625                 break;
 626
 627         case PIN_CONFIG_BIAS_PULL_UP:
 628                 value &= ~PADCFG1_TERM_MASK;
 629
 630                 value |= PADCFG1_TERM_UP;
 631
 632                 switch (arg) {
 633                 case 20000:
 634                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 635                         break;
 636                 case 5000:
 637                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 638                         break;
 639                 case 2000:
 640                         value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
 641                         break;
 642                 case 1000:
 643                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 644                         break;
 645                 default:
 646                         ret = -EINVAL;
 647                 }
 648
 649                 break;
 650
 651         case PIN_CONFIG_BIAS_PULL_DOWN:
 652                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 653
 654                 switch (arg) {
 655                 case 20000:
 656                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 657                         break;
 658                 case 5000:
 659                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 660                         break;
 661                 case 1000:
 662                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 663                                 ret = -EINVAL;
 664                                 break;
 665                         }
 666                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 667                         break;
 668                 default:
 669                         ret = -EINVAL;
 670                 }
 671
 672                 break;
 673         }
 674
 675         if (!ret)
 676                 writel(value, padcfg1);
 677
 678         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 679
 680         return ret;
 681 }
 682
 683 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
 684                                      unsigned int pin, unsigned int debounce)
 685 {
 686         void __iomem *padcfg0, *padcfg2;
 687         unsigned long flags;
 688         u32 value0, value2;
 689         int ret = 0;
 690
 691         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 692         if (!padcfg2)
 693                 return -ENOTSUPP;
 694
 695         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 696
 697         raw_spin_lock_irqsave(&pctrl->lock, flags);
 698
 699         value0 = readl(padcfg0);
 700         value2 = readl(padcfg2);
 701
 702         /* Disable glitch filter and debouncer */
 703         value0 &= ~PADCFG0_PREGFRXSEL;
 704         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
 705
 706         if (debounce) {
 707                 unsigned long v;
 708
 709                 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
 710                 if (v < 3 || v > 15) {
 711                         ret = -EINVAL;
 712                         goto exit_unlock;
 713                 } else {
 714                         /* Enable glitch filter and debouncer */
 715                         value0 |= PADCFG0_PREGFRXSEL;
 716                         value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
 717                         value2 |= PADCFG2_DEBEN;
 718                 }
 719         }
 720
 721         writel(value0, padcfg0);
 722         writel(value2, padcfg2);
 723
 724 exit_unlock:
 725         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 726
 727         return ret;
 728 }
 729
 730 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 731                           unsigned long *configs, unsigned int nconfigs)
 732 {
 733         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 734         int i, ret;
 735
 736         if (!intel_pad_usable(pctrl, pin))
 737                 return -ENOTSUPP;
 738
 739         for (i = 0; i < nconfigs; i++) {
 740                 switch (pinconf_to_config_param(configs[i])) {
 741                 case PIN_CONFIG_BIAS_DISABLE:
 742                 case PIN_CONFIG_BIAS_PULL_UP:
 743                 case PIN_CONFIG_BIAS_PULL_DOWN:
 744                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 745                         if (ret)
 746                                 return ret;
 747                         break;
 748
 749                 case PIN_CONFIG_INPUT_DEBOUNCE:
 750                         ret = intel_config_set_debounce(pctrl, pin,
 751                                 pinconf_to_config_argument(configs[i]));
 752                         if (ret)
 753                                 return ret;
 754                         break;
 755
 756                 default:
 757                         return -ENOTSUPP;
 758                 }
 759         }
 760
 761         return 0;
 762 }
 763
 764 static const struct pinconf_ops intel_pinconf_ops = {
 765         .is_generic = true,
 766         .pin_config_get = intel_config_get,
 767         .pin_config_set = intel_config_set,
 768 };
 769
 770 static const struct pinctrl_desc intel_pinctrl_desc = {
 771         .pctlops = &intel_pinctrl_ops,
 772         .pmxops = &intel_pinmux_ops,
 773         .confops = &intel_pinconf_ops,
 774         .owner = THIS_MODULE,
 775 };
 776
 777 /**
 778  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 779  * @pctrl: Pinctrl structure
 780  * @offset: GPIO offset from gpiolib
 781  * @community: Community is filled here if not %NULL
 782  * @padgrp: Pad group is filled here if not %NULL
 783  *
 784  * When coming through gpiolib irqchip, the GPIO offset is not
 785  * automatically translated to pinctrl pin number. This function can be
 786  * used to find out the corresponding pinctrl pin.
 787  */
 788 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
 789                              const struct intel_community **community,
 790                              const struct intel_padgroup **padgrp)
 791 {
 792         int i;
 793
 794         for (i = 0; i < pctrl->ncommunities; i++) {
 795                 const struct intel_community *comm = &pctrl->communities[i];
 796                 int j;
 797
 798                 for (j = 0; j < comm->ngpps; j++) {
 799                         const struct intel_padgroup *pgrp = &comm->gpps[j];
 800
 801                         if (pgrp->gpio_base < 0)
 802                                 continue;
 803
 804                         if (offset >= pgrp->gpio_base &&
 805                             offset < pgrp->gpio_base + pgrp->size) {
 806                                 int pin;
 807
 808                                 pin = pgrp->base + offset - pgrp->gpio_base;
 809                                 if (community)
 810                                         *community = comm;
 811                                 if (padgrp)
 812                                         *padgrp = pgrp;
 813
 814                                 return pin;
 815                         }
 816                 }
 817         }
 818
 819         return -EINVAL;
 820 }
 821
 822 /**
 823  * intel_pin_to_gpio() - Translate from pin number to GPIO offset
 824  * @pctrl: Pinctrl structure
 825  * @pin: pin number
 826  *
 827  * Translate the pin number of pinctrl to GPIO offset
 828  */
 829 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
 830 {
 831         const struct intel_community *community;
 832         const struct intel_padgroup *padgrp;
 833
 834         community = intel_get_community(pctrl, pin);
 835         if (!community)
 836                 return -EINVAL;
 837
 838         padgrp = intel_community_get_padgroup(community, pin);
 839         if (!padgrp)
 840                 return -EINVAL;
 841
 842         return pin - padgrp->base + padgrp->gpio_base;
 843 }
 844
 845 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
 846 {
 847         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 848         void __iomem *reg;
 849         u32 padcfg0;
 850         int pin;
 851
 852         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 853         if (pin < 0)
 854                 return -EINVAL;
 855
 856         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 857         if (!reg)
 858                 return -EINVAL;
 859
 860         padcfg0 = readl(reg);
 861         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
 862                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
 863
 864         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 865 }
 866
 867 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
 868                            int value)
 869 {
 870         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 871         unsigned long flags;
 872         void __iomem *reg;
 873         u32 padcfg0;
 874         int pin;
 875
 876         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 877         if (pin < 0)
 878                 return;
 879
 880         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 881         if (!reg)
 882                 return;
 883
 884         raw_spin_lock_irqsave(&pctrl->lock, flags);
 885         padcfg0 = readl(reg);
 886         if (value)
 887                 padcfg0 |= PADCFG0_GPIOTXSTATE;
 888         else
 889                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 890         writel(padcfg0, reg);
 891         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 892 }
 893
 894 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 895 {
 896         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 897         void __iomem *reg;
 898         u32 padcfg0;
 899         int pin;
 900
 901         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 902         if (pin < 0)
 903                 return -EINVAL;
 904
 905         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 906         if (!reg)
 907                 return -EINVAL;
 908
 909         padcfg0 = readl(reg);
 910
 911         if (padcfg0 & PADCFG0_PMODE_MASK)
 912                 return -EINVAL;
 913
 914         if (padcfg0 & PADCFG0_GPIOTXDIS)
 915                 return GPIO_LINE_DIRECTION_IN;
 916
 917         return GPIO_LINE_DIRECTION_OUT;
 918 }
 919
 920 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 921 {
 922         return pinctrl_gpio_direction_input(chip->base + offset);
 923 }
 924
 925 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
 926                                        int value)
 927 {
 928         intel_gpio_set(chip, offset, value);
 929         return pinctrl_gpio_direction_output(chip->base + offset);
 930 }
 931
 932 static const struct gpio_chip intel_gpio_chip = {
 933         .owner = THIS_MODULE,
 934         .request = gpiochip_generic_request,
 935         .free = gpiochip_generic_free,
 936         .get_direction = intel_gpio_get_direction,
 937         .direction_input = intel_gpio_direction_input,
 938         .direction_output = intel_gpio_direction_output,
 939         .get = intel_gpio_get,
 940         .set = intel_gpio_set,
 941         .set_config = gpiochip_generic_config,
 942 };
 943
 944 static void intel_gpio_irq_ack(struct irq_data *d)
 945 {
 946         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 947         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 948         const struct intel_community *community;
 949         const struct intel_padgroup *padgrp;
 950         int pin;
 951
 952         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 953         if (pin >= 0) {
 954                 unsigned int gpp, gpp_offset, is_offset;
 955
 956                 gpp = padgrp->reg_num;
 957                 gpp_offset = padgroup_offset(padgrp, pin);
 958                 is_offset = community->is_offset + gpp * 4;
 959
 960                 raw_spin_lock(&pctrl->lock);
 961                 writel(BIT(gpp_offset), community->regs + is_offset);
 962                 raw_spin_unlock(&pctrl->lock);
 963         }
 964 }
 965
 966 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
 967 {
 968         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 969         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 970         const struct intel_community *community;
 971         const struct intel_padgroup *padgrp;
 972         int pin;
 973
 974         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 975         if (pin >= 0) {
 976                 unsigned int gpp, gpp_offset;
 977                 unsigned long flags;
 978                 void __iomem *reg, *is;
 979                 u32 value;
 980
 981                 gpp = padgrp->reg_num;
 982                 gpp_offset = padgroup_offset(padgrp, pin);
 983
 984                 reg = community->regs + community->ie_offset + gpp * 4;
 985                 is = community->regs + community->is_offset + gpp * 4;
 986
 987                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 988
 989                 /* Clear interrupt status first to avoid unexpected interrupt */
 990                 writel(BIT(gpp_offset), is);
 991
 992                 value = readl(reg);
 993                 if (mask)
 994                         value &= ~BIT(gpp_offset);
 995                 else
 996                         value |= BIT(gpp_offset);
 997                 writel(value, reg);
 998                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 999         }
1000 }
1001
1002 static void intel_gpio_irq_mask(struct irq_data *d)
1003 {
1004         intel_gpio_irq_mask_unmask(d, true);
1005 }
1006
1007 static void intel_gpio_irq_unmask(struct irq_data *d)
1008 {
1009         intel_gpio_irq_mask_unmask(d, false);
1010 }
1011
1012 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1013 {
1014         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1015         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1016         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1017         unsigned long flags;
1018         void __iomem *reg;
1019         u32 value;
1020
1021         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1022         if (!reg)
1023                 return -EINVAL;
1024
1025         /*
1026          * If the pin is in ACPI mode it is still usable as a GPIO but it
1027          * cannot be used as IRQ because GPI_IS status bit will not be
1028          * updated by the host controller hardware.
1029          */
1030         if (intel_pad_acpi_mode(pctrl, pin)) {
1031                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1032                 return -EPERM;
1033         }
1034
1035         raw_spin_lock_irqsave(&pctrl->lock, flags);
1036
1037         intel_gpio_set_gpio_mode(reg);
1038
1039         value = readl(reg);
1040
1041         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1042
1043         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1044                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1045         } else if (type & IRQ_TYPE_EDGE_FALLING) {
1046                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1047                 value |= PADCFG0_RXINV;
1048         } else if (type & IRQ_TYPE_EDGE_RISING) {
1049                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1050         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1051                 if (type & IRQ_TYPE_LEVEL_LOW)
1052                         value |= PADCFG0_RXINV;
1053         } else {
1054                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1055         }
1056
1057         writel(value, reg);
1058
1059         if (type & IRQ_TYPE_EDGE_BOTH)
1060                 irq_set_handler_locked(d, handle_edge_irq);
1061         else if (type & IRQ_TYPE_LEVEL_MASK)
1062                 irq_set_handler_locked(d, handle_level_irq);
1063
1064         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1065
1066         return 0;
1067 }
1068
1069 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1070 {
1071         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1072         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1073         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1074
1075         if (on)
1076                 enable_irq_wake(pctrl->irq);
1077         else
1078                 disable_irq_wake(pctrl->irq);
1079
1080         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1081         return 0;
1082 }
1083
1084 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1085         const struct intel_community *community)
1086 {
1087         struct gpio_chip *gc = &pctrl->chip;
1088         irqreturn_t ret = IRQ_NONE;
1089         int gpp;
1090
1091         for (gpp = 0; gpp < community->ngpps; gpp++) {
1092                 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1093                 unsigned long pending, enabled, gpp_offset;
1094
1095                 pending = readl(community->regs + community->is_offset +
1096                                 padgrp->reg_num * 4);
1097                 enabled = readl(community->regs + community->ie_offset +
1098                                 padgrp->reg_num * 4);
1099
1100                 /* Only interrupts that are enabled */
1101                 pending &= enabled;
1102
1103                 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1104                         unsigned int irq;
1105
1106                         irq = irq_find_mapping(gc->irq.domain,
1107                                                padgrp->gpio_base + gpp_offset);
1108                         generic_handle_irq(irq);
1109
1110                         ret |= IRQ_HANDLED;
1111                 }
1112         }
1113
1114         return ret;
1115 }
1116
1117 static irqreturn_t intel_gpio_irq(int irq, void *data)
1118 {
1119         const struct intel_community *community;
1120         struct intel_pinctrl *pctrl = data;
1121         irqreturn_t ret = IRQ_NONE;
1122         int i;
1123
1124         /* Need to check all communities for pending interrupts */
1125         for (i = 0; i < pctrl->ncommunities; i++) {
1126                 community = &pctrl->communities[i];
1127                 ret |= intel_gpio_community_irq_handler(pctrl, community);
1128         }
1129
1130         return ret;
1131 }
1132
1133 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
1134                                 const struct intel_community *community)
1135 {
1136         int ret = 0, i;
1137
1138         for (i = 0; i < community->ngpps; i++) {
1139                 const struct intel_padgroup *gpp = &community->gpps[i];
1140
1141                 if (gpp->gpio_base < 0)
1142                         continue;
1143
1144                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1145                                              gpp->gpio_base, gpp->base,
1146                                              gpp->size);
1147                 if (ret)
1148                         return ret;
1149         }
1150
1151         return ret;
1152 }
1153
1154 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1155 {
1156         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1157         int ret, i;
1158
1159         for (i = 0; i < pctrl->ncommunities; i++) {
1160                 struct intel_community *community = &pctrl->communities[i];
1161
1162                 ret = intel_gpio_add_community_ranges(pctrl, community);
1163                 if (ret) {
1164                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1165                         return ret;
1166                 }
1167         }
1168
1169         return 0;
1170 }
1171
1172 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1173 {
1174         const struct intel_community *community;
1175         unsigned int ngpio = 0;
1176         int i, j;
1177
1178         for (i = 0; i < pctrl->ncommunities; i++) {
1179                 community = &pctrl->communities[i];
1180                 for (j = 0; j < community->ngpps; j++) {
1181                         const struct intel_padgroup *gpp = &community->gpps[j];
1182
1183                         if (gpp->gpio_base < 0)
1184                                 continue;
1185
1186                         if (gpp->gpio_base + gpp->size > ngpio)
1187                                 ngpio = gpp->gpio_base + gpp->size;
1188                 }
1189         }
1190
1191         return ngpio;
1192 }
1193
1194 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1195 {
1196         int ret;
1197         struct gpio_irq_chip *girq;
1198
1199         pctrl->chip = intel_gpio_chip;
1200
1201         /* Setup GPIO chip */
1202         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1203         pctrl->chip.label = dev_name(pctrl->dev);
1204         pctrl->chip.parent = pctrl->dev;
1205         pctrl->chip.base = -1;
1206         pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1207         pctrl->irq = irq;
1208
1209         /* Setup IRQ chip */
1210         pctrl->irqchip.name = dev_name(pctrl->dev);
1211         pctrl->irqchip.irq_ack = intel_gpio_irq_ack;
1212         pctrl->irqchip.irq_mask = intel_gpio_irq_mask;
1213         pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;
1214         pctrl->irqchip.irq_set_type = intel_gpio_irq_type;
1215         pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
1216         pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
1217
1218         /*
1219          * On some platforms several GPIO controllers share the same interrupt
1220          * line.
1221          */
1222         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1223                                IRQF_SHARED | IRQF_NO_THREAD,
1224                                dev_name(pctrl->dev), pctrl);
1225         if (ret) {
1226                 dev_err(pctrl->dev, "failed to request interrupt\n");
1227                 return ret;
1228         }
1229
1230         girq = &pctrl->chip.irq;
1231         girq->chip = &pctrl->irqchip;
1232         /* This will let us handle the IRQ in the driver */
1233         girq->parent_handler = NULL;
1234         girq->num_parents = 0;
1235         girq->default_type = IRQ_TYPE_NONE;
1236         girq->handler = handle_bad_irq;
1237
1238         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1239         if (ret) {
1240                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1241                 return ret;
1242         }
1243
1244         return 0;
1245 }
1246
1247 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1248                                        struct intel_community *community)
1249 {
1250         struct intel_padgroup *gpps;
1251         unsigned int npins = community->npins;
1252         unsigned int padown_num = 0;
1253         size_t ngpps, i;
1254
1255         if (community->gpps)
1256                 ngpps = community->ngpps;
1257         else
1258                 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1259
1260         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1261         if (!gpps)
1262                 return -ENOMEM;
1263
1264         for (i = 0; i < ngpps; i++) {
1265                 if (community->gpps) {
1266                         gpps[i] = community->gpps[i];
1267                 } else {
1268                         unsigned int gpp_size = community->gpp_size;
1269
1270                         gpps[i].reg_num = i;
1271                         gpps[i].base = community->pin_base + i * gpp_size;
1272                         gpps[i].size = min(gpp_size, npins);
1273                         npins -= gpps[i].size;
1274                 }
1275
1276                 if (gpps[i].size > 32)
1277                         return -EINVAL;
1278
1279                 if (!gpps[i].gpio_base)
1280                         gpps[i].gpio_base = gpps[i].base;
1281
1282                 gpps[i].padown_num = padown_num;
1283
1284                 /*
1285                  * In older hardware the number of padown registers per
1286                  * group is fixed regardless of the group size.
1287                  */
1288                 if (community->gpp_num_padown_regs)
1289                         padown_num += community->gpp_num_padown_regs;
1290                 else
1291                         padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1292         }
1293
1294         community->ngpps = ngpps;
1295         community->gpps = gpps;
1296
1297         return 0;
1298 }
1299
1300 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1301 {
1302 #ifdef CONFIG_PM_SLEEP
1303         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1304         struct intel_community_context *communities;
1305         struct intel_pad_context *pads;
1306         int i;
1307
1308         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1309         if (!pads)
1310                 return -ENOMEM;
1311
1312         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1313                                    sizeof(*communities), GFP_KERNEL);
1314         if (!communities)
1315                 return -ENOMEM;
1316
1317
1318         for (i = 0; i < pctrl->ncommunities; i++) {
1319                 struct intel_community *community = &pctrl->communities[i];
1320                 u32 *intmask, *hostown;
1321
1322                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1323                                        sizeof(*intmask), GFP_KERNEL);
1324                 if (!intmask)
1325                         return -ENOMEM;
1326
1327                 communities[i].intmask = intmask;
1328
1329                 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1330                                        sizeof(*hostown), GFP_KERNEL);
1331                 if (!hostown)
1332                         return -ENOMEM;
1333
1334                 communities[i].hostown = hostown;
1335         }
1336
1337         pctrl->context.pads = pads;
1338         pctrl->context.communities = communities;
1339 #endif
1340
1341         return 0;
1342 }
1343
1344 static int intel_pinctrl_probe(struct platform_device *pdev,
1345                                const struct intel_pinctrl_soc_data *soc_data)
1346 {
1347         struct intel_pinctrl *pctrl;
1348         int i, ret, irq;
1349
1350         if (!soc_data)
1351                 return -EINVAL;
1352
1353         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1354         if (!pctrl)
1355                 return -ENOMEM;
1356
1357         pctrl->dev = &pdev->dev;
1358         pctrl->soc = soc_data;
1359         raw_spin_lock_init(&pctrl->lock);
1360
1361         /*
1362          * Make a copy of the communities which we can use to hold pointers
1363          * to the registers.
1364          */
1365         pctrl->ncommunities = pctrl->soc->ncommunities;
1366         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1367                                   sizeof(*pctrl->communities), GFP_KERNEL);
1368         if (!pctrl->communities)
1369                 return -ENOMEM;
1370
1371         for (i = 0; i < pctrl->ncommunities; i++) {
1372                 struct intel_community *community = &pctrl->communities[i];
1373                 void __iomem *regs;
1374                 u32 padbar;
1375
1376                 *community = pctrl->soc->communities[i];
1377
1378                 regs = devm_platform_ioremap_resource(pdev, community->barno);
1379                 if (IS_ERR(regs))
1380                         return PTR_ERR(regs);
1381
1382                 /*
1383                  * Determine community features based on the revision if
1384                  * not specified already.
1385                  */
1386                 if (!community->features) {
1387                         u32 rev;
1388
1389                         rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1390                         if (rev >= 0x94) {
1391                                 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1392                                 community->features |= PINCTRL_FEATURE_1K_PD;
1393                         }
1394                 }
1395
1396                 /* Read offset of the pad configuration registers */
1397                 padbar = readl(regs + PADBAR);
1398
1399                 community->regs = regs;
1400                 community->pad_regs = regs + padbar;
1401
1402                 ret = intel_pinctrl_add_padgroups(pctrl, community);
1403                 if (ret)
1404                         return ret;
1405         }
1406
1407         irq = platform_get_irq(pdev, 0);
1408         if (irq < 0)
1409                 return irq;
1410
1411         ret = intel_pinctrl_pm_init(pctrl);
1412         if (ret)
1413                 return ret;
1414
1415         pctrl->pctldesc = intel_pinctrl_desc;
1416         pctrl->pctldesc.name = dev_name(&pdev->dev);
1417         pctrl->pctldesc.pins = pctrl->soc->pins;
1418         pctrl->pctldesc.npins = pctrl->soc->npins;
1419
1420         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1421                                                pctrl);
1422         if (IS_ERR(pctrl->pctldev)) {
1423                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1424                 return PTR_ERR(pctrl->pctldev);
1425         }
1426
1427         ret = intel_gpio_probe(pctrl, irq);
1428         if (ret)
1429                 return ret;
1430
1431         platform_set_drvdata(pdev, pctrl);
1432
1433         return 0;
1434 }
1435
1436 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1437 {
1438         const struct intel_pinctrl_soc_data *data;
1439
1440         data = device_get_match_data(&pdev->dev);
1441         return intel_pinctrl_probe(pdev, data);
1442 }
1443 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
1444
1445 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1446 {
1447         const struct intel_pinctrl_soc_data *data = NULL;
1448         const struct intel_pinctrl_soc_data **table;
1449         struct acpi_device *adev;
1450         unsigned int i;
1451
1452         adev = ACPI_COMPANION(&pdev->dev);
1453         if (adev) {
1454                 const void *match = device_get_match_data(&pdev->dev);
1455
1456                 table = (const struct intel_pinctrl_soc_data **)match;
1457                 for (i = 0; table[i]; i++) {
1458                         if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
1459                                 data = table[i];
1460                                 break;
1461                         }
1462                 }
1463         } else {
1464                 const struct platform_device_id *id;
1465
1466                 id = platform_get_device_id(pdev);
1467                 if (!id)
1468                         return -ENODEV;
1469
1470                 table = (const struct intel_pinctrl_soc_data **)id->driver_data;
1471                 data = table[pdev->id];
1472         }
1473
1474         return intel_pinctrl_probe(pdev, data);
1475 }
1476 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
1477
1478 #ifdef CONFIG_PM_SLEEP
1479 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1480 {
1481         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1482
1483         if (!pd || !intel_pad_usable(pctrl, pin))
1484                 return false;
1485
1486         /*
1487          * Only restore the pin if it is actually in use by the kernel (or
1488          * by userspace). It is possible that some pins are used by the
1489          * BIOS during resume and those are not always locked down so leave
1490          * them alone.
1491          */
1492         if (pd->mux_owner || pd->gpio_owner ||
1493             gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1494                 return true;
1495
1496         return false;
1497 }
1498
1499 int intel_pinctrl_suspend_noirq(struct device *dev)
1500 {
1501         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1502         struct intel_community_context *communities;
1503         struct intel_pad_context *pads;
1504         int i;
1505
1506         pads = pctrl->context.pads;
1507         for (i = 0; i < pctrl->soc->npins; i++) {
1508                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1509                 void __iomem *padcfg;
1510                 u32 val;
1511
1512                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1513                         continue;
1514
1515                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1516                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1517                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1518                 pads[i].padcfg1 = val;
1519
1520                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1521                 if (padcfg)
1522                         pads[i].padcfg2 = readl(padcfg);
1523         }
1524
1525         communities = pctrl->context.communities;
1526         for (i = 0; i < pctrl->ncommunities; i++) {
1527                 struct intel_community *community = &pctrl->communities[i];
1528                 void __iomem *base;
1529                 unsigned int gpp;
1530
1531                 base = community->regs + community->ie_offset;
1532                 for (gpp = 0; gpp < community->ngpps; gpp++)
1533                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1534
1535                 base = community->regs + community->hostown_offset;
1536                 for (gpp = 0; gpp < community->ngpps; gpp++)
1537                         communities[i].hostown[gpp] = readl(base + gpp * 4);
1538         }
1539
1540         return 0;
1541 }
1542 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1543
1544 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1545 {
1546         size_t i;
1547
1548         for (i = 0; i < pctrl->ncommunities; i++) {
1549                 const struct intel_community *community;
1550                 void __iomem *base;
1551                 unsigned int gpp;
1552
1553                 community = &pctrl->communities[i];
1554                 base = community->regs;
1555
1556                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1557                         /* Mask and clear all interrupts */
1558                         writel(0, base + community->ie_offset + gpp * 4);
1559                         writel(0xffff, base + community->is_offset + gpp * 4);
1560                 }
1561         }
1562 }
1563
1564 static u32
1565 intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size)
1566 {
1567         u32 requested = 0;
1568         unsigned int i;
1569
1570         for (i = 0; i < size; i++)
1571                 if (gpiochip_is_requested(chip, base + i))
1572                         requested |= BIT(i);
1573
1574         return requested;
1575 }
1576
1577 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1578 {
1579         u32 curr, updated;
1580
1581         curr = readl(reg);
1582
1583         updated = (curr & ~mask) | (value & mask);
1584         if (curr == updated)
1585                 return false;
1586
1587         writel(updated, reg);
1588         return true;
1589 }
1590
1591 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1592                                   void __iomem *base, unsigned int gpp, u32 saved)
1593 {
1594         const struct intel_community *community = &pctrl->communities[c];
1595         const struct intel_padgroup *padgrp = &community->gpps[gpp];
1596         struct device *dev = pctrl->dev;
1597         u32 requested;
1598
1599         if (padgrp->gpio_base < 0)
1600                 return;
1601
1602         requested = intel_gpio_is_requested(&pctrl->chip, padgrp->gpio_base, padgrp->size);
1603         if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1604                 return;
1605
1606         dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1607 }
1608
1609 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1610                                   void __iomem *base, unsigned int gpp, u32 saved)
1611 {
1612         struct device *dev = pctrl->dev;
1613
1614         if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1615                 return;
1616
1617         dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1618 }
1619
1620 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1621                                  unsigned int reg, u32 saved)
1622 {
1623         u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1624         unsigned int n = reg / sizeof(u32);
1625         struct device *dev = pctrl->dev;
1626         void __iomem *padcfg;
1627
1628         padcfg = intel_get_padcfg(pctrl, pin, reg);
1629         if (!padcfg)
1630                 return;
1631
1632         if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1633                 return;
1634
1635         dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1636 }
1637
1638 int intel_pinctrl_resume_noirq(struct device *dev)
1639 {
1640         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1641         const struct intel_community_context *communities;
1642         const struct intel_pad_context *pads;
1643         int i;
1644
1645         /* Mask all interrupts */
1646         intel_gpio_irq_init(pctrl);
1647
1648         pads = pctrl->context.pads;
1649         for (i = 0; i < pctrl->soc->npins; i++) {
1650                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1651
1652                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1653                         continue;
1654
1655                 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1656                 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1657                 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1658         }
1659
1660         communities = pctrl->context.communities;
1661         for (i = 0; i < pctrl->ncommunities; i++) {
1662                 struct intel_community *community = &pctrl->communities[i];
1663                 void __iomem *base;
1664                 unsigned int gpp;
1665
1666                 base = community->regs + community->ie_offset;
1667                 for (gpp = 0; gpp < community->ngpps; gpp++)
1668                         intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1669
1670                 base = community->regs + community->hostown_offset;
1671                 for (gpp = 0; gpp < community->ngpps; gpp++)
1672                         intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1673         }
1674
1675         return 0;
1676 }
1677 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1678 #endif
1679
1680 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1681 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1682 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1683 MODULE_LICENSE("GPL v2");