2 * Intel pinctrl/GPIO core driver.
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/platform_device.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinmux.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinconf-generic.h>
23 #include "pinctrl-intel.h"
25 /* Offset from regs */
28 #define GPI_GPE_STS 0x140
29 #define GPI_GPE_EN 0x160
32 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
33 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
34 #define PADOWN_GPP(p) ((p) / 8)
36 /* Offset from pad_regs */
38 #define PADCFG0_RXEVCFG_SHIFT 25
39 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
40 #define PADCFG0_RXEVCFG_LEVEL 0
41 #define PADCFG0_RXEVCFG_EDGE 1
42 #define PADCFG0_RXEVCFG_DISABLED 2
43 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
44 #define PADCFG0_RXINV BIT(23)
45 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
46 #define PADCFG0_GPIROUTSCI BIT(19)
47 #define PADCFG0_GPIROUTSMI BIT(18)
48 #define PADCFG0_GPIROUTNMI BIT(17)
49 #define PADCFG0_PMODE_SHIFT 10
50 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
51 #define PADCFG0_GPIORXDIS BIT(9)
52 #define PADCFG0_GPIOTXDIS BIT(8)
53 #define PADCFG0_GPIORXSTATE BIT(1)
54 #define PADCFG0_GPIOTXSTATE BIT(0)
57 #define PADCFG1_TERM_UP BIT(13)
58 #define PADCFG1_TERM_SHIFT 10
59 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
60 #define PADCFG1_TERM_20K 4
61 #define PADCFG1_TERM_2K 3
62 #define PADCFG1_TERM_5K 2
63 #define PADCFG1_TERM_1K 1
65 struct intel_pad_context {
70 struct intel_community_context {
74 struct intel_pinctrl_context {
75 struct intel_pad_context *pads;
76 struct intel_community_context *communities;
80 * struct intel_pinctrl - Intel pinctrl private structure
81 * @dev: Pointer to the device structure
82 * @lock: Lock to serialize register access
83 * @pctldesc: Pin controller description
84 * @pctldev: Pointer to the pin controller device
85 * @chip: GPIO chip in this pin controller
86 * @soc: SoC/PCH specific pin configuration data
87 * @communities: All communities in this pin controller
88 * @ncommunities: Number of communities in this pin controller
89 * @context: Configuration saved over system sleep
90 * @irq: pinctrl/GPIO chip irq number
92 struct intel_pinctrl {
95 struct pinctrl_desc pctldesc;
96 struct pinctrl_dev *pctldev;
97 struct gpio_chip chip;
98 const struct intel_pinctrl_soc_data *soc;
99 struct intel_community *communities;
101 struct intel_pinctrl_context context;
105 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
107 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
110 struct intel_community *community;
113 for (i = 0; i < pctrl->ncommunities; i++) {
114 community = &pctrl->communities[i];
115 if (pin >= community->pin_base &&
116 pin < community->pin_base + community->npins)
120 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
124 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
127 const struct intel_community *community;
130 community = intel_get_community(pctrl, pin);
134 padno = pin_to_padno(community, pin);
135 return community->pad_regs + reg + padno * 8;
138 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
140 const struct intel_community *community;
141 unsigned padno, gpp, offset, group;
142 void __iomem *padown;
144 community = intel_get_community(pctrl, pin);
147 if (!community->padown_offset)
150 padno = pin_to_padno(community, pin);
151 group = padno / community->gpp_size;
152 gpp = PADOWN_GPP(padno % community->gpp_size);
153 offset = community->padown_offset + 0x10 * group + gpp * 4;
154 padown = community->regs + offset;
156 return !(readl(padown) & PADOWN_MASK(padno));
159 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
161 const struct intel_community *community;
162 unsigned padno, gpp, offset;
163 void __iomem *hostown;
165 community = intel_get_community(pctrl, pin);
168 if (!community->hostown_offset)
171 padno = pin_to_padno(community, pin);
172 gpp = padno / community->gpp_size;
173 offset = community->hostown_offset + gpp * 4;
174 hostown = community->regs + offset;
176 return !(readl(hostown) & BIT(padno % community->gpp_size));
179 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
181 struct intel_community *community;
182 unsigned padno, gpp, offset;
185 community = intel_get_community(pctrl, pin);
188 if (!community->padcfglock_offset)
191 padno = pin_to_padno(community, pin);
192 gpp = padno / community->gpp_size;
195 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
196 * the pad is considered unlocked. Any other case means that it is
197 * either fully or partially locked and we don't touch it.
199 offset = community->padcfglock_offset + gpp * 8;
200 value = readl(community->regs + offset);
201 if (value & BIT(pin % community->gpp_size))
204 offset = community->padcfglock_offset + 4 + gpp * 8;
205 value = readl(community->regs + offset);
206 if (value & BIT(pin % community->gpp_size))
212 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
214 return intel_pad_owned_by_host(pctrl, pin) &&
215 !intel_pad_locked(pctrl, pin);
218 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
220 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
222 return pctrl->soc->ngroups;
225 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
228 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
230 return pctrl->soc->groups[group].name;
233 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
234 const unsigned **pins, unsigned *npins)
236 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
238 *pins = pctrl->soc->groups[group].pins;
239 *npins = pctrl->soc->groups[group].npins;
243 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
246 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
247 u32 cfg0, cfg1, mode;
250 if (!intel_pad_owned_by_host(pctrl, pin)) {
251 seq_puts(s, "not available");
255 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
256 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
258 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
260 seq_puts(s, "GPIO ");
262 seq_printf(s, "mode %d ", mode);
264 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
266 locked = intel_pad_locked(pctrl, pin);
267 acpi = intel_pad_acpi_mode(pctrl, pin);
269 if (locked || acpi) {
272 seq_puts(s, "LOCKED");
282 static const struct pinctrl_ops intel_pinctrl_ops = {
283 .get_groups_count = intel_get_groups_count,
284 .get_group_name = intel_get_group_name,
285 .get_group_pins = intel_get_group_pins,
286 .pin_dbg_show = intel_pin_dbg_show,
289 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
291 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
293 return pctrl->soc->nfunctions;
296 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
299 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
301 return pctrl->soc->functions[function].name;
304 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
306 const char * const **groups,
307 unsigned * const ngroups)
309 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
311 *groups = pctrl->soc->functions[function].groups;
312 *ngroups = pctrl->soc->functions[function].ngroups;
316 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
319 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
320 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
324 raw_spin_lock_irqsave(&pctrl->lock, flags);
327 * All pins in the groups needs to be accessible and writable
328 * before we can enable the mux for this group.
330 for (i = 0; i < grp->npins; i++) {
331 if (!intel_pad_usable(pctrl, grp->pins[i])) {
332 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
337 /* Now enable the mux setting for each pin in the group */
338 for (i = 0; i < grp->npins; i++) {
339 void __iomem *padcfg0;
342 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
343 value = readl(padcfg0);
345 value &= ~PADCFG0_PMODE_MASK;
346 value |= grp->mode << PADCFG0_PMODE_SHIFT;
348 writel(value, padcfg0);
351 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
356 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
360 value = readl(padcfg0);
362 value &= ~PADCFG0_GPIORXDIS;
363 value |= PADCFG0_GPIOTXDIS;
365 value &= ~PADCFG0_GPIOTXDIS;
366 value |= PADCFG0_GPIORXDIS;
368 writel(value, padcfg0);
371 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
372 struct pinctrl_gpio_range *range,
375 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
376 void __iomem *padcfg0;
380 raw_spin_lock_irqsave(&pctrl->lock, flags);
382 if (!intel_pad_usable(pctrl, pin)) {
383 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
387 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
388 /* Put the pad into GPIO mode */
389 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
390 /* Disable SCI/SMI/NMI generation */
391 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
392 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
393 writel(value, padcfg0);
395 /* Disable TX buffer and enable RX (this will be input) */
396 __intel_gpio_set_direction(padcfg0, true);
398 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
403 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
404 struct pinctrl_gpio_range *range,
405 unsigned pin, bool input)
407 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
408 void __iomem *padcfg0;
411 raw_spin_lock_irqsave(&pctrl->lock, flags);
413 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
414 __intel_gpio_set_direction(padcfg0, input);
416 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
421 static const struct pinmux_ops intel_pinmux_ops = {
422 .get_functions_count = intel_get_functions_count,
423 .get_function_name = intel_get_function_name,
424 .get_function_groups = intel_get_function_groups,
425 .set_mux = intel_pinmux_set_mux,
426 .gpio_request_enable = intel_gpio_request_enable,
427 .gpio_set_direction = intel_gpio_set_direction,
430 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
431 unsigned long *config)
433 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
434 enum pin_config_param param = pinconf_to_config_param(*config);
438 if (!intel_pad_owned_by_host(pctrl, pin))
441 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
442 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
445 case PIN_CONFIG_BIAS_DISABLE:
450 case PIN_CONFIG_BIAS_PULL_UP:
451 if (!term || !(value & PADCFG1_TERM_UP))
455 case PADCFG1_TERM_1K:
458 case PADCFG1_TERM_2K:
461 case PADCFG1_TERM_5K:
464 case PADCFG1_TERM_20K:
471 case PIN_CONFIG_BIAS_PULL_DOWN:
472 if (!term || value & PADCFG1_TERM_UP)
476 case PADCFG1_TERM_5K:
479 case PADCFG1_TERM_20K:
490 *config = pinconf_to_config_packed(param, arg);
494 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
495 unsigned long config)
497 unsigned param = pinconf_to_config_param(config);
498 unsigned arg = pinconf_to_config_argument(config);
499 void __iomem *padcfg1;
504 raw_spin_lock_irqsave(&pctrl->lock, flags);
506 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
507 value = readl(padcfg1);
510 case PIN_CONFIG_BIAS_DISABLE:
511 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
514 case PIN_CONFIG_BIAS_PULL_UP:
515 value &= ~PADCFG1_TERM_MASK;
517 value |= PADCFG1_TERM_UP;
521 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
524 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
527 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
530 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
538 case PIN_CONFIG_BIAS_PULL_DOWN:
539 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
543 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
546 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
556 writel(value, padcfg1);
558 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
563 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
564 unsigned long *configs, unsigned nconfigs)
566 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
569 if (!intel_pad_usable(pctrl, pin))
572 for (i = 0; i < nconfigs; i++) {
573 switch (pinconf_to_config_param(configs[i])) {
574 case PIN_CONFIG_BIAS_DISABLE:
575 case PIN_CONFIG_BIAS_PULL_UP:
576 case PIN_CONFIG_BIAS_PULL_DOWN:
577 ret = intel_config_set_pull(pctrl, pin, configs[i]);
590 static const struct pinconf_ops intel_pinconf_ops = {
592 .pin_config_get = intel_config_get,
593 .pin_config_set = intel_config_set,
596 static const struct pinctrl_desc intel_pinctrl_desc = {
597 .pctlops = &intel_pinctrl_ops,
598 .pmxops = &intel_pinmux_ops,
599 .confops = &intel_pinconf_ops,
600 .owner = THIS_MODULE,
603 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
605 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
608 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
612 return !!(readl(reg) & PADCFG0_GPIORXSTATE);
615 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
617 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
620 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
625 raw_spin_lock_irqsave(&pctrl->lock, flags);
626 padcfg0 = readl(reg);
628 padcfg0 |= PADCFG0_GPIOTXSTATE;
630 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
631 writel(padcfg0, reg);
632 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
636 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
638 return pinctrl_gpio_direction_input(chip->base + offset);
641 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
644 intel_gpio_set(chip, offset, value);
645 return pinctrl_gpio_direction_output(chip->base + offset);
648 static const struct gpio_chip intel_gpio_chip = {
649 .owner = THIS_MODULE,
650 .request = gpiochip_generic_request,
651 .free = gpiochip_generic_free,
652 .direction_input = intel_gpio_direction_input,
653 .direction_output = intel_gpio_direction_output,
654 .get = intel_gpio_get,
655 .set = intel_gpio_set,
658 static void intel_gpio_irq_ack(struct irq_data *d)
660 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
661 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
662 const struct intel_community *community;
663 unsigned pin = irqd_to_hwirq(d);
665 raw_spin_lock(&pctrl->lock);
667 community = intel_get_community(pctrl, pin);
669 unsigned padno = pin_to_padno(community, pin);
670 unsigned gpp_offset = padno % community->gpp_size;
671 unsigned gpp = padno / community->gpp_size;
673 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
676 raw_spin_unlock(&pctrl->lock);
679 static void intel_gpio_irq_enable(struct irq_data *d)
681 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
682 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
683 const struct intel_community *community;
684 unsigned pin = irqd_to_hwirq(d);
687 raw_spin_lock_irqsave(&pctrl->lock, flags);
689 community = intel_get_community(pctrl, pin);
691 unsigned padno = pin_to_padno(community, pin);
692 unsigned gpp_size = community->gpp_size;
693 unsigned gpp_offset = padno % gpp_size;
694 unsigned gpp = padno / gpp_size;
697 /* Clear interrupt status first to avoid unexpected interrupt */
698 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
700 value = readl(community->regs + community->ie_offset + gpp * 4);
701 value |= BIT(gpp_offset);
702 writel(value, community->regs + community->ie_offset + gpp * 4);
705 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
708 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
710 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
711 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
712 const struct intel_community *community;
713 unsigned pin = irqd_to_hwirq(d);
716 raw_spin_lock_irqsave(&pctrl->lock, flags);
718 community = intel_get_community(pctrl, pin);
720 unsigned padno = pin_to_padno(community, pin);
721 unsigned gpp_offset = padno % community->gpp_size;
722 unsigned gpp = padno / community->gpp_size;
726 reg = community->regs + community->ie_offset + gpp * 4;
729 value &= ~BIT(gpp_offset);
731 value |= BIT(gpp_offset);
735 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
738 static void intel_gpio_irq_mask(struct irq_data *d)
740 intel_gpio_irq_mask_unmask(d, true);
743 static void intel_gpio_irq_unmask(struct irq_data *d)
745 intel_gpio_irq_mask_unmask(d, false);
748 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
750 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
751 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
752 unsigned pin = irqd_to_hwirq(d);
757 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
762 * If the pin is in ACPI mode it is still usable as a GPIO but it
763 * cannot be used as IRQ because GPI_IS status bit will not be
764 * updated by the host controller hardware.
766 if (intel_pad_acpi_mode(pctrl, pin)) {
767 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
771 raw_spin_lock_irqsave(&pctrl->lock, flags);
775 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
777 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
778 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
779 } else if (type & IRQ_TYPE_EDGE_FALLING) {
780 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
781 value |= PADCFG0_RXINV;
782 } else if (type & IRQ_TYPE_EDGE_RISING) {
783 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
784 } else if (type & IRQ_TYPE_LEVEL_MASK) {
785 if (type & IRQ_TYPE_LEVEL_LOW)
786 value |= PADCFG0_RXINV;
788 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
793 if (type & IRQ_TYPE_EDGE_BOTH)
794 irq_set_handler_locked(d, handle_edge_irq);
795 else if (type & IRQ_TYPE_LEVEL_MASK)
796 irq_set_handler_locked(d, handle_level_irq);
798 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
803 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
805 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
806 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
807 unsigned pin = irqd_to_hwirq(d);
810 enable_irq_wake(pctrl->irq);
812 disable_irq_wake(pctrl->irq);
814 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
818 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
819 const struct intel_community *community)
821 struct gpio_chip *gc = &pctrl->chip;
822 irqreturn_t ret = IRQ_NONE;
825 for (gpp = 0; gpp < community->ngpps; gpp++) {
826 unsigned long pending, enabled, gpp_offset;
828 pending = readl(community->regs + GPI_IS + gpp * 4);
829 enabled = readl(community->regs + community->ie_offset +
832 /* Only interrupts that are enabled */
835 for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
839 * The last group in community can have less pins
842 padno = gpp_offset + gpp * community->gpp_size;
843 if (padno >= community->npins)
846 irq = irq_find_mapping(gc->irqdomain,
847 community->pin_base + padno);
848 generic_handle_irq(irq);
857 static irqreturn_t intel_gpio_irq(int irq, void *data)
859 const struct intel_community *community;
860 struct intel_pinctrl *pctrl = data;
861 irqreturn_t ret = IRQ_NONE;
864 /* Need to check all communities for pending interrupts */
865 for (i = 0; i < pctrl->ncommunities; i++) {
866 community = &pctrl->communities[i];
867 ret |= intel_gpio_community_irq_handler(pctrl, community);
873 static struct irq_chip intel_gpio_irqchip = {
874 .name = "intel-gpio",
875 .irq_enable = intel_gpio_irq_enable,
876 .irq_ack = intel_gpio_irq_ack,
877 .irq_mask = intel_gpio_irq_mask,
878 .irq_unmask = intel_gpio_irq_unmask,
879 .irq_set_type = intel_gpio_irq_type,
880 .irq_set_wake = intel_gpio_irq_wake,
883 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
887 pctrl->chip = intel_gpio_chip;
889 pctrl->chip.ngpio = pctrl->soc->npins;
890 pctrl->chip.label = dev_name(pctrl->dev);
891 pctrl->chip.parent = pctrl->dev;
892 pctrl->chip.base = -1;
895 ret = gpiochip_add_data(&pctrl->chip, pctrl);
897 dev_err(pctrl->dev, "failed to register gpiochip\n");
901 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
902 0, 0, pctrl->soc->npins);
904 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
909 * We need to request the interrupt here (instead of providing chip
910 * to the irq directly) because on some platforms several GPIO
911 * controllers share the same interrupt line.
913 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
914 IRQF_SHARED | IRQF_NO_THREAD,
915 dev_name(pctrl->dev), pctrl);
917 dev_err(pctrl->dev, "failed to request interrupt\n");
921 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
922 handle_bad_irq, IRQ_TYPE_NONE);
924 dev_err(pctrl->dev, "failed to add irqchip\n");
928 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
933 gpiochip_remove(&pctrl->chip);
938 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
940 #ifdef CONFIG_PM_SLEEP
941 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
942 struct intel_community_context *communities;
943 struct intel_pad_context *pads;
946 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
950 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
951 sizeof(*communities), GFP_KERNEL);
956 for (i = 0; i < pctrl->ncommunities; i++) {
957 struct intel_community *community = &pctrl->communities[i];
960 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
961 sizeof(*intmask), GFP_KERNEL);
965 communities[i].intmask = intmask;
968 pctrl->context.pads = pads;
969 pctrl->context.communities = communities;
975 int intel_pinctrl_probe(struct platform_device *pdev,
976 const struct intel_pinctrl_soc_data *soc_data)
978 struct intel_pinctrl *pctrl;
984 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
988 pctrl->dev = &pdev->dev;
989 pctrl->soc = soc_data;
990 raw_spin_lock_init(&pctrl->lock);
993 * Make a copy of the communities which we can use to hold pointers
996 pctrl->ncommunities = pctrl->soc->ncommunities;
997 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
998 sizeof(*pctrl->communities), GFP_KERNEL);
999 if (!pctrl->communities)
1002 for (i = 0; i < pctrl->ncommunities; i++) {
1003 struct intel_community *community = &pctrl->communities[i];
1004 struct resource *res;
1008 *community = pctrl->soc->communities[i];
1010 res = platform_get_resource(pdev, IORESOURCE_MEM,
1012 regs = devm_ioremap_resource(&pdev->dev, res);
1014 return PTR_ERR(regs);
1016 /* Read offset of the pad configuration registers */
1017 padbar = readl(regs + PADBAR);
1019 community->regs = regs;
1020 community->pad_regs = regs + padbar;
1021 community->ngpps = DIV_ROUND_UP(community->npins,
1022 community->gpp_size);
1025 irq = platform_get_irq(pdev, 0);
1027 dev_err(&pdev->dev, "failed to get interrupt number\n");
1031 ret = intel_pinctrl_pm_init(pctrl);
1035 pctrl->pctldesc = intel_pinctrl_desc;
1036 pctrl->pctldesc.name = dev_name(&pdev->dev);
1037 pctrl->pctldesc.pins = pctrl->soc->pins;
1038 pctrl->pctldesc.npins = pctrl->soc->npins;
1040 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1042 if (IS_ERR(pctrl->pctldev)) {
1043 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1044 return PTR_ERR(pctrl->pctldev);
1047 ret = intel_gpio_probe(pctrl, irq);
1051 platform_set_drvdata(pdev, pctrl);
1055 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1057 int intel_pinctrl_remove(struct platform_device *pdev)
1059 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1061 gpiochip_remove(&pctrl->chip);
1065 EXPORT_SYMBOL_GPL(intel_pinctrl_remove);
1067 #ifdef CONFIG_PM_SLEEP
1068 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1070 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1072 if (!pd || !intel_pad_usable(pctrl, pin))
1076 * Only restore the pin if it is actually in use by the kernel (or
1077 * by userspace). It is possible that some pins are used by the
1078 * BIOS during resume and those are not always locked down so leave
1081 if (pd->mux_owner || pd->gpio_owner ||
1082 gpiochip_line_is_irq(&pctrl->chip, pin))
1088 int intel_pinctrl_suspend(struct device *dev)
1090 struct platform_device *pdev = to_platform_device(dev);
1091 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1092 struct intel_community_context *communities;
1093 struct intel_pad_context *pads;
1096 pads = pctrl->context.pads;
1097 for (i = 0; i < pctrl->soc->npins; i++) {
1098 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1101 if (!intel_pinctrl_should_save(pctrl, desc->number))
1104 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1105 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1106 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1107 pads[i].padcfg1 = val;
1110 communities = pctrl->context.communities;
1111 for (i = 0; i < pctrl->ncommunities; i++) {
1112 struct intel_community *community = &pctrl->communities[i];
1116 base = community->regs + community->ie_offset;
1117 for (gpp = 0; gpp < community->ngpps; gpp++)
1118 communities[i].intmask[gpp] = readl(base + gpp * 4);
1123 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1125 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1129 for (i = 0; i < pctrl->ncommunities; i++) {
1130 const struct intel_community *community;
1134 community = &pctrl->communities[i];
1135 base = community->regs;
1137 for (gpp = 0; gpp < community->ngpps; gpp++) {
1138 /* Mask and clear all interrupts */
1139 writel(0, base + community->ie_offset + gpp * 4);
1140 writel(0xffff, base + GPI_IS + gpp * 4);
1145 int intel_pinctrl_resume(struct device *dev)
1147 struct platform_device *pdev = to_platform_device(dev);
1148 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1149 const struct intel_community_context *communities;
1150 const struct intel_pad_context *pads;
1153 /* Mask all interrupts */
1154 intel_gpio_irq_init(pctrl);
1156 pads = pctrl->context.pads;
1157 for (i = 0; i < pctrl->soc->npins; i++) {
1158 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1159 void __iomem *padcfg;
1162 if (!intel_pinctrl_should_save(pctrl, desc->number))
1165 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1166 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1167 if (val != pads[i].padcfg0) {
1168 writel(pads[i].padcfg0, padcfg);
1169 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1170 desc->number, readl(padcfg));
1173 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1174 val = readl(padcfg);
1175 if (val != pads[i].padcfg1) {
1176 writel(pads[i].padcfg1, padcfg);
1177 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1178 desc->number, readl(padcfg));
1182 communities = pctrl->context.communities;
1183 for (i = 0; i < pctrl->ncommunities; i++) {
1184 struct intel_community *community = &pctrl->communities[i];
1188 base = community->regs + community->ie_offset;
1189 for (gpp = 0; gpp < community->ngpps; gpp++) {
1190 writel(communities[i].intmask[gpp], base + gpp * 4);
1191 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1192 readl(base + gpp * 4));
1198 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1201 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1202 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1203 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1204 MODULE_LICENSE("GPL v2");