drivers/pinctrl/intel/pinctrl-intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel pinctrl/GPIO core driver.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/log2.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/property.h>
  17 #include <linux/time.h>
  18
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/pinctrl/pinconf.h>
  22 #include <linux/pinctrl/pinconf-generic.h>
  23
  24 #include "../core.h"
  25 #include "pinctrl-intel.h"
  26
  27 /* Offset from regs */
  28 #define REVID                           0x000
  29 #define REVID_SHIFT                     16
  30 #define REVID_MASK                      GENMASK(31, 16)
  31
  32 #define CAPLIST                         0x004
  33 #define CAPLIST_ID_SHIFT                16
  34 #define CAPLIST_ID_MASK                 GENMASK(23, 16)
  35 #define CAPLIST_ID_GPIO_HW_INFO         1
  36 #define CAPLIST_ID_PWM                  2
  37 #define CAPLIST_ID_BLINK                3
  38 #define CAPLIST_ID_EXP                  4
  39 #define CAPLIST_NEXT_SHIFT              0
  40 #define CAPLIST_NEXT_MASK               GENMASK(15, 0)
  41
  42 #define PADBAR                          0x00c
  43
  44 #define PADOWN_BITS                     4
  45 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  46 #define PADOWN_MASK(p)                  (GENMASK(3, 0) << PADOWN_SHIFT(p))
  47 #define PADOWN_GPP(p)                   ((p) / 8)
  48
  49 /* Offset from pad_regs */
  50 #define PADCFG0                         0x000
  51 #define PADCFG0_RXEVCFG_SHIFT           25
  52 #define PADCFG0_RXEVCFG_MASK            GENMASK(26, 25)
  53 #define PADCFG0_RXEVCFG_LEVEL           0
  54 #define PADCFG0_RXEVCFG_EDGE            1
  55 #define PADCFG0_RXEVCFG_DISABLED        2
  56 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  57 #define PADCFG0_PREGFRXSEL              BIT(24)
  58 #define PADCFG0_RXINV                   BIT(23)
  59 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  60 #define PADCFG0_GPIROUTSCI              BIT(19)
  61 #define PADCFG0_GPIROUTSMI              BIT(18)
  62 #define PADCFG0_GPIROUTNMI              BIT(17)
  63 #define PADCFG0_PMODE_SHIFT             10
  64 #define PADCFG0_PMODE_MASK              GENMASK(13, 10)
  65 #define PADCFG0_PMODE_GPIO              0
  66 #define PADCFG0_GPIORXDIS               BIT(9)
  67 #define PADCFG0_GPIOTXDIS               BIT(8)
  68 #define PADCFG0_GPIORXSTATE             BIT(1)
  69 #define PADCFG0_GPIOTXSTATE             BIT(0)
  70
  71 #define PADCFG1                         0x004
  72 #define PADCFG1_TERM_UP                 BIT(13)
  73 #define PADCFG1_TERM_SHIFT              10
  74 #define PADCFG1_TERM_MASK               GENMASK(12, 10)
  75 #define PADCFG1_TERM_20K                BIT(2)
  76 #define PADCFG1_TERM_5K                 BIT(1)
  77 #define PADCFG1_TERM_1K                 BIT(0)
  78 #define PADCFG1_TERM_833                (BIT(1) | BIT(0))
  79
  80 #define PADCFG2                         0x008
  81 #define PADCFG2_DEBEN                   BIT(0)
  82 #define PADCFG2_DEBOUNCE_SHIFT          1
  83 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
  84
  85 #define DEBOUNCE_PERIOD_NSEC            31250
  86
  87 struct intel_pad_context {
  88         u32 padcfg0;
  89         u32 padcfg1;
  90         u32 padcfg2;
  91 };
  92
  93 struct intel_community_context {
  94         u32 *intmask;
  95         u32 *hostown;
  96 };
  97
  98 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
  99 #define padgroup_offset(g, p)   ((p) - (g)->base)
 100
 101 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
 102                                                    unsigned int pin)
 103 {
 104         struct intel_community *community;
 105         int i;
 106
 107         for (i = 0; i < pctrl->ncommunities; i++) {
 108                 community = &pctrl->communities[i];
 109                 if (pin >= community->pin_base &&
 110                     pin < community->pin_base + community->npins)
 111                         return community;
 112         }
 113
 114         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 115         return NULL;
 116 }
 117
 118 static const struct intel_padgroup *
 119 intel_community_get_padgroup(const struct intel_community *community,
 120                              unsigned int pin)
 121 {
 122         int i;
 123
 124         for (i = 0; i < community->ngpps; i++) {
 125                 const struct intel_padgroup *padgrp = &community->gpps[i];
 126
 127                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 128                         return padgrp;
 129         }
 130
 131         return NULL;
 132 }
 133
 134 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
 135                                       unsigned int pin, unsigned int reg)
 136 {
 137         const struct intel_community *community;
 138         unsigned int padno;
 139         size_t nregs;
 140
 141         community = intel_get_community(pctrl, pin);
 142         if (!community)
 143                 return NULL;
 144
 145         padno = pin_to_padno(community, pin);
 146         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 147
 148         if (reg >= nregs * 4)
 149                 return NULL;
 150
 151         return community->pad_regs + reg + padno * nregs * 4;
 152 }
 153
 154 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
 155 {
 156         const struct intel_community *community;
 157         const struct intel_padgroup *padgrp;
 158         unsigned int gpp, offset, gpp_offset;
 159         void __iomem *padown;
 160
 161         community = intel_get_community(pctrl, pin);
 162         if (!community)
 163                 return false;
 164         if (!community->padown_offset)
 165                 return true;
 166
 167         padgrp = intel_community_get_padgroup(community, pin);
 168         if (!padgrp)
 169                 return false;
 170
 171         gpp_offset = padgroup_offset(padgrp, pin);
 172         gpp = PADOWN_GPP(gpp_offset);
 173         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 174         padown = community->regs + offset;
 175
 176         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 177 }
 178
 179 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
 180 {
 181         const struct intel_community *community;
 182         const struct intel_padgroup *padgrp;
 183         unsigned int offset, gpp_offset;
 184         void __iomem *hostown;
 185
 186         community = intel_get_community(pctrl, pin);
 187         if (!community)
 188                 return true;
 189         if (!community->hostown_offset)
 190                 return false;
 191
 192         padgrp = intel_community_get_padgroup(community, pin);
 193         if (!padgrp)
 194                 return true;
 195
 196         gpp_offset = padgroup_offset(padgrp, pin);
 197         offset = community->hostown_offset + padgrp->reg_num * 4;
 198         hostown = community->regs + offset;
 199
 200         return !(readl(hostown) & BIT(gpp_offset));
 201 }
 202
 203 /**
 204  * enum - Locking variants of the pad configuration
 205  *
 206  * @PAD_UNLOCKED:       pad is fully controlled by the configuration registers
 207  * @PAD_LOCKED:         pad configuration registers, except TX state, are locked
 208  * @PAD_LOCKED_TX:      pad configuration TX state is locked
 209  * @PAD_LOCKED_FULL:    pad configuration registers are locked completely
 210  *
 211  * Locking is considered as read-only mode for corresponding registers and
 212  * their respective fields. That said, TX state bit is locked separately from
 213  * the main locking scheme.
 214  */
 215 enum {
 216         PAD_UNLOCKED    = 0,
 217         PAD_LOCKED      = 1,
 218         PAD_LOCKED_TX   = 2,
 219         PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
 220 };
 221
 222 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
 223 {
 224         struct intel_community *community;
 225         const struct intel_padgroup *padgrp;
 226         unsigned int offset, gpp_offset;
 227         u32 value;
 228         int ret = PAD_UNLOCKED;
 229
 230         community = intel_get_community(pctrl, pin);
 231         if (!community)
 232                 return PAD_LOCKED_FULL;
 233         if (!community->padcfglock_offset)
 234                 return PAD_UNLOCKED;
 235
 236         padgrp = intel_community_get_padgroup(community, pin);
 237         if (!padgrp)
 238                 return PAD_LOCKED_FULL;
 239
 240         gpp_offset = padgroup_offset(padgrp, pin);
 241
 242         /*
 243          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 244          * the pad is considered unlocked. Any other case means that it is
 245          * either fully or partially locked.
 246          */
 247         offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
 248         value = readl(community->regs + offset);
 249         if (value & BIT(gpp_offset))
 250                 ret |= PAD_LOCKED;
 251
 252         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 253         value = readl(community->regs + offset);
 254         if (value & BIT(gpp_offset))
 255                 ret |= PAD_LOCKED_TX;
 256
 257         return ret;
 258 }
 259
 260 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
 261 {
 262         return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
 263 }
 264
 265 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
 266 {
 267         return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
 268 }
 269
 270 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 271 {
 272         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 273
 274         return pctrl->soc->ngroups;
 275 }
 276
 277 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 278                                       unsigned int group)
 279 {
 280         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 281
 282         return pctrl->soc->groups[group].grp.name;
 283 }
 284
 285 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 286                               const unsigned int **pins, unsigned int *npins)
 287 {
 288         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 289
 290         *pins = pctrl->soc->groups[group].grp.pins;
 291         *npins = pctrl->soc->groups[group].grp.npins;
 292         return 0;
 293 }
 294
 295 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 296                                unsigned int pin)
 297 {
 298         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 299         void __iomem *padcfg;
 300         u32 cfg0, cfg1, mode;
 301         int locked;
 302         bool acpi;
 303
 304         if (!intel_pad_owned_by_host(pctrl, pin)) {
 305                 seq_puts(s, "not available");
 306                 return;
 307         }
 308
 309         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 310         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 311
 312         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 313         if (mode == PADCFG0_PMODE_GPIO)
 314                 seq_puts(s, "GPIO ");
 315         else
 316                 seq_printf(s, "mode %d ", mode);
 317
 318         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 319
 320         /* Dump the additional PADCFG registers if available */
 321         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 322         if (padcfg)
 323                 seq_printf(s, " 0x%08x", readl(padcfg));
 324
 325         locked = intel_pad_locked(pctrl, pin);
 326         acpi = intel_pad_acpi_mode(pctrl, pin);
 327
 328         if (locked || acpi) {
 329                 seq_puts(s, " [");
 330                 if (locked)
 331                         seq_puts(s, "LOCKED");
 332                 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
 333                         seq_puts(s, " tx");
 334                 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
 335                         seq_puts(s, " full");
 336
 337                 if (locked && acpi)
 338                         seq_puts(s, ", ");
 339
 340                 if (acpi)
 341                         seq_puts(s, "ACPI");
 342                 seq_puts(s, "]");
 343         }
 344 }
 345
 346 static const struct pinctrl_ops intel_pinctrl_ops = {
 347         .get_groups_count = intel_get_groups_count,
 348         .get_group_name = intel_get_group_name,
 349         .get_group_pins = intel_get_group_pins,
 350         .pin_dbg_show = intel_pin_dbg_show,
 351 };
 352
 353 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 354 {
 355         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 356
 357         return pctrl->soc->nfunctions;
 358 }
 359
 360 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 361                                            unsigned int function)
 362 {
 363         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 364
 365         return pctrl->soc->functions[function].name;
 366 }
 367
 368 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 369                                      unsigned int function,
 370                                      const char * const **groups,
 371                                      unsigned int * const ngroups)
 372 {
 373         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 374
 375         *groups = pctrl->soc->functions[function].groups;
 376         *ngroups = pctrl->soc->functions[function].ngroups;
 377         return 0;
 378 }
 379
 380 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
 381                                 unsigned int function, unsigned int group)
 382 {
 383         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 384         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 385         unsigned long flags;
 386         int i;
 387
 388         raw_spin_lock_irqsave(&pctrl->lock, flags);
 389
 390         /*
 391          * All pins in the groups needs to be accessible and writable
 392          * before we can enable the mux for this group.
 393          */
 394         for (i = 0; i < grp->grp.npins; i++) {
 395                 if (!intel_pad_usable(pctrl, grp->grp.pins[i])) {
 396                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 397                         return -EBUSY;
 398                 }
 399         }
 400
 401         /* Now enable the mux setting for each pin in the group */
 402         for (i = 0; i < grp->grp.npins; i++) {
 403                 void __iomem *padcfg0;
 404                 u32 value;
 405
 406                 padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0);
 407                 value = readl(padcfg0);
 408
 409                 value &= ~PADCFG0_PMODE_MASK;
 410
 411                 if (grp->modes)
 412                         value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
 413                 else
 414                         value |= grp->mode << PADCFG0_PMODE_SHIFT;
 415
 416                 writel(value, padcfg0);
 417         }
 418
 419         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 420
 421         return 0;
 422 }
 423
 424 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 425 {
 426         u32 value;
 427
 428         value = readl(padcfg0);
 429         if (input) {
 430                 value &= ~PADCFG0_GPIORXDIS;
 431                 value |= PADCFG0_GPIOTXDIS;
 432         } else {
 433                 value &= ~PADCFG0_GPIOTXDIS;
 434                 value |= PADCFG0_GPIORXDIS;
 435         }
 436         writel(value, padcfg0);
 437 }
 438
 439 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
 440 {
 441         return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 442 }
 443
 444 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 445 {
 446         u32 value;
 447
 448         value = readl(padcfg0);
 449
 450         /* Put the pad into GPIO mode */
 451         value &= ~PADCFG0_PMODE_MASK;
 452         value |= PADCFG0_PMODE_GPIO;
 453
 454         /* Disable TX buffer and enable RX (this will be input) */
 455         value &= ~PADCFG0_GPIORXDIS;
 456         value |= PADCFG0_GPIOTXDIS;
 457
 458         /* Disable SCI/SMI/NMI generation */
 459         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 460         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 461
 462         writel(value, padcfg0);
 463 }
 464
 465 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 466                                      struct pinctrl_gpio_range *range,
 467                                      unsigned int pin)
 468 {
 469         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 470         void __iomem *padcfg0;
 471         unsigned long flags;
 472
 473         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 474
 475         raw_spin_lock_irqsave(&pctrl->lock, flags);
 476
 477         if (!intel_pad_owned_by_host(pctrl, pin)) {
 478                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 479                 return -EBUSY;
 480         }
 481
 482         if (!intel_pad_is_unlocked(pctrl, pin)) {
 483                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 484                 return 0;
 485         }
 486
 487         /*
 488          * If pin is already configured in GPIO mode, we assume that
 489          * firmware provides correct settings. In such case we avoid
 490          * potential glitches on the pin. Otherwise, for the pin in
 491          * alternative mode, consumer has to supply respective flags.
 492          */
 493         if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
 494                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 495                 return 0;
 496         }
 497
 498         intel_gpio_set_gpio_mode(padcfg0);
 499
 500         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 501
 502         return 0;
 503 }
 504
 505 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 506                                     struct pinctrl_gpio_range *range,
 507                                     unsigned int pin, bool input)
 508 {
 509         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 510         void __iomem *padcfg0;
 511         unsigned long flags;
 512
 513         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 514
 515         raw_spin_lock_irqsave(&pctrl->lock, flags);
 516         __intel_gpio_set_direction(padcfg0, input);
 517         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 518
 519         return 0;
 520 }
 521
 522 static const struct pinmux_ops intel_pinmux_ops = {
 523         .get_functions_count = intel_get_functions_count,
 524         .get_function_name = intel_get_function_name,
 525         .get_function_groups = intel_get_function_groups,
 526         .set_mux = intel_pinmux_set_mux,
 527         .gpio_request_enable = intel_gpio_request_enable,
 528         .gpio_set_direction = intel_gpio_set_direction,
 529 };
 530
 531 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 532                                  enum pin_config_param param, u32 *arg)
 533 {
 534         const struct intel_community *community;
 535         void __iomem *padcfg1;
 536         unsigned long flags;
 537         u32 value, term;
 538
 539         community = intel_get_community(pctrl, pin);
 540         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 541
 542         raw_spin_lock_irqsave(&pctrl->lock, flags);
 543         value = readl(padcfg1);
 544         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 545
 546         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 547
 548         switch (param) {
 549         case PIN_CONFIG_BIAS_DISABLE:
 550                 if (term)
 551                         return -EINVAL;
 552                 break;
 553
 554         case PIN_CONFIG_BIAS_PULL_UP:
 555                 if (!term || !(value & PADCFG1_TERM_UP))
 556                         return -EINVAL;
 557
 558                 switch (term) {
 559                 case PADCFG1_TERM_833:
 560                         *arg = 833;
 561                         break;
 562                 case PADCFG1_TERM_1K:
 563                         *arg = 1000;
 564                         break;
 565                 case PADCFG1_TERM_5K:
 566                         *arg = 5000;
 567                         break;
 568                 case PADCFG1_TERM_20K:
 569                         *arg = 20000;
 570                         break;
 571                 }
 572
 573                 break;
 574
 575         case PIN_CONFIG_BIAS_PULL_DOWN:
 576                 if (!term || value & PADCFG1_TERM_UP)
 577                         return -EINVAL;
 578
 579                 switch (term) {
 580                 case PADCFG1_TERM_833:
 581                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 582                                 return -EINVAL;
 583                         *arg = 833;
 584                         break;
 585                 case PADCFG1_TERM_1K:
 586                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 587                                 return -EINVAL;
 588                         *arg = 1000;
 589                         break;
 590                 case PADCFG1_TERM_5K:
 591                         *arg = 5000;
 592                         break;
 593                 case PADCFG1_TERM_20K:
 594                         *arg = 20000;
 595                         break;
 596                 }
 597
 598                 break;
 599
 600         default:
 601                 return -EINVAL;
 602         }
 603
 604         return 0;
 605 }
 606
 607 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
 608                                      enum pin_config_param param, u32 *arg)
 609 {
 610         void __iomem *padcfg2;
 611         unsigned long flags;
 612         unsigned long v;
 613         u32 value2;
 614
 615         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 616         if (!padcfg2)
 617                 return -ENOTSUPP;
 618
 619         raw_spin_lock_irqsave(&pctrl->lock, flags);
 620         value2 = readl(padcfg2);
 621         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 622         if (!(value2 & PADCFG2_DEBEN))
 623                 return -EINVAL;
 624
 625         v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 626         *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
 627
 628         return 0;
 629 }
 630
 631 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 632                             unsigned long *config)
 633 {
 634         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 635         enum pin_config_param param = pinconf_to_config_param(*config);
 636         u32 arg = 0;
 637         int ret;
 638
 639         if (!intel_pad_owned_by_host(pctrl, pin))
 640                 return -ENOTSUPP;
 641
 642         switch (param) {
 643         case PIN_CONFIG_BIAS_DISABLE:
 644         case PIN_CONFIG_BIAS_PULL_UP:
 645         case PIN_CONFIG_BIAS_PULL_DOWN:
 646                 ret = intel_config_get_pull(pctrl, pin, param, &arg);
 647                 if (ret)
 648                         return ret;
 649                 break;
 650
 651         case PIN_CONFIG_INPUT_DEBOUNCE:
 652                 ret = intel_config_get_debounce(pctrl, pin, param, &arg);
 653                 if (ret)
 654                         return ret;
 655                 break;
 656
 657         default:
 658                 return -ENOTSUPP;
 659         }
 660
 661         *config = pinconf_to_config_packed(param, arg);
 662         return 0;
 663 }
 664
 665 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 666                                  unsigned long config)
 667 {
 668         unsigned int param = pinconf_to_config_param(config);
 669         unsigned int arg = pinconf_to_config_argument(config);
 670         const struct intel_community *community;
 671         void __iomem *padcfg1;
 672         unsigned long flags;
 673         int ret = 0;
 674         u32 value;
 675
 676         community = intel_get_community(pctrl, pin);
 677         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 678
 679         raw_spin_lock_irqsave(&pctrl->lock, flags);
 680
 681         value = readl(padcfg1);
 682
 683         switch (param) {
 684         case PIN_CONFIG_BIAS_DISABLE:
 685                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 686                 break;
 687
 688         case PIN_CONFIG_BIAS_PULL_UP:
 689                 value &= ~PADCFG1_TERM_MASK;
 690
 691                 value |= PADCFG1_TERM_UP;
 692
 693                 /* Set default strength value in case none is given */
 694                 if (arg == 1)
 695                         arg = 5000;
 696
 697                 switch (arg) {
 698                 case 20000:
 699                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 700                         break;
 701                 case 5000:
 702                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 703                         break;
 704                 case 1000:
 705                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 706                         break;
 707                 case 833:
 708                         value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
 709                         break;
 710                 default:
 711                         ret = -EINVAL;
 712                 }
 713
 714                 break;
 715
 716         case PIN_CONFIG_BIAS_PULL_DOWN:
 717                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 718
 719                 /* Set default strength value in case none is given */
 720                 if (arg == 1)
 721                         arg = 5000;
 722
 723                 switch (arg) {
 724                 case 20000:
 725                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 726                         break;
 727                 case 5000:
 728                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 729                         break;
 730                 case 1000:
 731                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 732                                 ret = -EINVAL;
 733                                 break;
 734                         }
 735                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 736                         break;
 737                 case 833:
 738                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 739                                 ret = -EINVAL;
 740                                 break;
 741                         }
 742                         value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
 743                         break;
 744                 default:
 745                         ret = -EINVAL;
 746                 }
 747
 748                 break;
 749         }
 750
 751         if (!ret)
 752                 writel(value, padcfg1);
 753
 754         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 755
 756         return ret;
 757 }
 758
 759 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
 760                                      unsigned int pin, unsigned int debounce)
 761 {
 762         void __iomem *padcfg0, *padcfg2;
 763         unsigned long flags;
 764         u32 value0, value2;
 765
 766         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 767         if (!padcfg2)
 768                 return -ENOTSUPP;
 769
 770         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 771
 772         raw_spin_lock_irqsave(&pctrl->lock, flags);
 773
 774         value0 = readl(padcfg0);
 775         value2 = readl(padcfg2);
 776
 777         /* Disable glitch filter and debouncer */
 778         value0 &= ~PADCFG0_PREGFRXSEL;
 779         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
 780
 781         if (debounce) {
 782                 unsigned long v;
 783
 784                 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
 785                 if (v < 3 || v > 15) {
 786                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 787                         return -EINVAL;
 788                 }
 789
 790                 /* Enable glitch filter and debouncer */
 791                 value0 |= PADCFG0_PREGFRXSEL;
 792                 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
 793                 value2 |= PADCFG2_DEBEN;
 794         }
 795
 796         writel(value0, padcfg0);
 797         writel(value2, padcfg2);
 798
 799         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 800
 801         return 0;
 802 }
 803
 804 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 805                           unsigned long *configs, unsigned int nconfigs)
 806 {
 807         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 808         int i, ret;
 809
 810         if (!intel_pad_usable(pctrl, pin))
 811                 return -ENOTSUPP;
 812
 813         for (i = 0; i < nconfigs; i++) {
 814                 switch (pinconf_to_config_param(configs[i])) {
 815                 case PIN_CONFIG_BIAS_DISABLE:
 816                 case PIN_CONFIG_BIAS_PULL_UP:
 817                 case PIN_CONFIG_BIAS_PULL_DOWN:
 818                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 819                         if (ret)
 820                                 return ret;
 821                         break;
 822
 823                 case PIN_CONFIG_INPUT_DEBOUNCE:
 824                         ret = intel_config_set_debounce(pctrl, pin,
 825                                 pinconf_to_config_argument(configs[i]));
 826                         if (ret)
 827                                 return ret;
 828                         break;
 829
 830                 default:
 831                         return -ENOTSUPP;
 832                 }
 833         }
 834
 835         return 0;
 836 }
 837
 838 static const struct pinconf_ops intel_pinconf_ops = {
 839         .is_generic = true,
 840         .pin_config_get = intel_config_get,
 841         .pin_config_set = intel_config_set,
 842 };
 843
 844 static const struct pinctrl_desc intel_pinctrl_desc = {
 845         .pctlops = &intel_pinctrl_ops,
 846         .pmxops = &intel_pinmux_ops,
 847         .confops = &intel_pinconf_ops,
 848         .owner = THIS_MODULE,
 849 };
 850
 851 /**
 852  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 853  * @pctrl: Pinctrl structure
 854  * @offset: GPIO offset from gpiolib
 855  * @community: Community is filled here if not %NULL
 856  * @padgrp: Pad group is filled here if not %NULL
 857  *
 858  * When coming through gpiolib irqchip, the GPIO offset is not
 859  * automatically translated to pinctrl pin number. This function can be
 860  * used to find out the corresponding pinctrl pin.
 861  *
 862  * Return: a pin number and pointers to the community and pad group, which
 863  * the pin belongs to, or negative error code if translation can't be done.
 864  */
 865 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
 866                              const struct intel_community **community,
 867                              const struct intel_padgroup **padgrp)
 868 {
 869         int i;
 870
 871         for (i = 0; i < pctrl->ncommunities; i++) {
 872                 const struct intel_community *comm = &pctrl->communities[i];
 873                 int j;
 874
 875                 for (j = 0; j < comm->ngpps; j++) {
 876                         const struct intel_padgroup *pgrp = &comm->gpps[j];
 877
 878                         if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
 879                                 continue;
 880
 881                         if (offset >= pgrp->gpio_base &&
 882                             offset < pgrp->gpio_base + pgrp->size) {
 883                                 int pin;
 884
 885                                 pin = pgrp->base + offset - pgrp->gpio_base;
 886                                 if (community)
 887                                         *community = comm;
 888                                 if (padgrp)
 889                                         *padgrp = pgrp;
 890
 891                                 return pin;
 892                         }
 893                 }
 894         }
 895
 896         return -EINVAL;
 897 }
 898
 899 /**
 900  * intel_pin_to_gpio() - Translate from pin number to GPIO offset
 901  * @pctrl: Pinctrl structure
 902  * @pin: pin number
 903  *
 904  * Translate the pin number of pinctrl to GPIO offset
 905  *
 906  * Return: a GPIO offset, or negative error code if translation can't be done.
 907  */
 908 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
 909 {
 910         const struct intel_community *community;
 911         const struct intel_padgroup *padgrp;
 912
 913         community = intel_get_community(pctrl, pin);
 914         if (!community)
 915                 return -EINVAL;
 916
 917         padgrp = intel_community_get_padgroup(community, pin);
 918         if (!padgrp)
 919                 return -EINVAL;
 920
 921         return pin - padgrp->base + padgrp->gpio_base;
 922 }
 923
 924 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
 925 {
 926         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 927         void __iomem *reg;
 928         u32 padcfg0;
 929         int pin;
 930
 931         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 932         if (pin < 0)
 933                 return -EINVAL;
 934
 935         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 936         if (!reg)
 937                 return -EINVAL;
 938
 939         padcfg0 = readl(reg);
 940         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
 941                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
 942
 943         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 944 }
 945
 946 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
 947                            int value)
 948 {
 949         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 950         unsigned long flags;
 951         void __iomem *reg;
 952         u32 padcfg0;
 953         int pin;
 954
 955         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 956         if (pin < 0)
 957                 return;
 958
 959         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 960         if (!reg)
 961                 return;
 962
 963         raw_spin_lock_irqsave(&pctrl->lock, flags);
 964         padcfg0 = readl(reg);
 965         if (value)
 966                 padcfg0 |= PADCFG0_GPIOTXSTATE;
 967         else
 968                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 969         writel(padcfg0, reg);
 970         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 971 }
 972
 973 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 974 {
 975         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 976         unsigned long flags;
 977         void __iomem *reg;
 978         u32 padcfg0;
 979         int pin;
 980
 981         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 982         if (pin < 0)
 983                 return -EINVAL;
 984
 985         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 986         if (!reg)
 987                 return -EINVAL;
 988
 989         raw_spin_lock_irqsave(&pctrl->lock, flags);
 990         padcfg0 = readl(reg);
 991         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 992         if (padcfg0 & PADCFG0_PMODE_MASK)
 993                 return -EINVAL;
 994
 995         if (padcfg0 & PADCFG0_GPIOTXDIS)
 996                 return GPIO_LINE_DIRECTION_IN;
 997
 998         return GPIO_LINE_DIRECTION_OUT;
 999 }
1000
1001 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1002 {
1003         return pinctrl_gpio_direction_input(chip->base + offset);
1004 }
1005
1006 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1007                                        int value)
1008 {
1009         intel_gpio_set(chip, offset, value);
1010         return pinctrl_gpio_direction_output(chip->base + offset);
1011 }
1012
1013 static const struct gpio_chip intel_gpio_chip = {
1014         .owner = THIS_MODULE,
1015         .request = gpiochip_generic_request,
1016         .free = gpiochip_generic_free,
1017         .get_direction = intel_gpio_get_direction,
1018         .direction_input = intel_gpio_direction_input,
1019         .direction_output = intel_gpio_direction_output,
1020         .get = intel_gpio_get,
1021         .set = intel_gpio_set,
1022         .set_config = gpiochip_generic_config,
1023 };
1024
1025 static void intel_gpio_irq_ack(struct irq_data *d)
1026 {
1027         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1028         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1029         const struct intel_community *community;
1030         const struct intel_padgroup *padgrp;
1031         int pin;
1032
1033         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1034         if (pin >= 0) {
1035                 unsigned int gpp, gpp_offset, is_offset;
1036
1037                 gpp = padgrp->reg_num;
1038                 gpp_offset = padgroup_offset(padgrp, pin);
1039                 is_offset = community->is_offset + gpp * 4;
1040
1041                 raw_spin_lock(&pctrl->lock);
1042                 writel(BIT(gpp_offset), community->regs + is_offset);
1043                 raw_spin_unlock(&pctrl->lock);
1044         }
1045 }
1046
1047 static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
1048 {
1049         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1050         const struct intel_community *community;
1051         const struct intel_padgroup *padgrp;
1052         int pin;
1053
1054         pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp);
1055         if (pin >= 0) {
1056                 unsigned int gpp, gpp_offset;
1057                 unsigned long flags;
1058                 void __iomem *reg, *is;
1059                 u32 value;
1060
1061                 gpp = padgrp->reg_num;
1062                 gpp_offset = padgroup_offset(padgrp, pin);
1063
1064                 reg = community->regs + community->ie_offset + gpp * 4;
1065                 is = community->regs + community->is_offset + gpp * 4;
1066
1067                 raw_spin_lock_irqsave(&pctrl->lock, flags);
1068
1069                 /* Clear interrupt status first to avoid unexpected interrupt */
1070                 writel(BIT(gpp_offset), is);
1071
1072                 value = readl(reg);
1073                 if (mask)
1074                         value &= ~BIT(gpp_offset);
1075                 else
1076                         value |= BIT(gpp_offset);
1077                 writel(value, reg);
1078                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1079         }
1080 }
1081
1082 static void intel_gpio_irq_mask(struct irq_data *d)
1083 {
1084         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1085         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1086
1087         intel_gpio_irq_mask_unmask(gc, hwirq, true);
1088         gpiochip_disable_irq(gc, hwirq);
1089 }
1090
1091 static void intel_gpio_irq_unmask(struct irq_data *d)
1092 {
1093         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1094         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1095
1096         gpiochip_enable_irq(gc, hwirq);
1097         intel_gpio_irq_mask_unmask(gc, hwirq, false);
1098 }
1099
1100 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1101 {
1102         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1103         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1104         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1105         unsigned long flags;
1106         void __iomem *reg;
1107         u32 value;
1108
1109         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1110         if (!reg)
1111                 return -EINVAL;
1112
1113         /*
1114          * If the pin is in ACPI mode it is still usable as a GPIO but it
1115          * cannot be used as IRQ because GPI_IS status bit will not be
1116          * updated by the host controller hardware.
1117          */
1118         if (intel_pad_acpi_mode(pctrl, pin)) {
1119                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1120                 return -EPERM;
1121         }
1122
1123         raw_spin_lock_irqsave(&pctrl->lock, flags);
1124
1125         intel_gpio_set_gpio_mode(reg);
1126
1127         value = readl(reg);
1128
1129         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1130
1131         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1132                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1133         } else if (type & IRQ_TYPE_EDGE_FALLING) {
1134                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1135                 value |= PADCFG0_RXINV;
1136         } else if (type & IRQ_TYPE_EDGE_RISING) {
1137                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1138         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1139                 if (type & IRQ_TYPE_LEVEL_LOW)
1140                         value |= PADCFG0_RXINV;
1141         } else {
1142                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1143         }
1144
1145         writel(value, reg);
1146
1147         if (type & IRQ_TYPE_EDGE_BOTH)
1148                 irq_set_handler_locked(d, handle_edge_irq);
1149         else if (type & IRQ_TYPE_LEVEL_MASK)
1150                 irq_set_handler_locked(d, handle_level_irq);
1151
1152         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1153
1154         return 0;
1155 }
1156
1157 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1158 {
1159         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1160         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1161         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1162
1163         if (on)
1164                 enable_irq_wake(pctrl->irq);
1165         else
1166                 disable_irq_wake(pctrl->irq);
1167
1168         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1169         return 0;
1170 }
1171
1172 static const struct irq_chip intel_gpio_irq_chip = {
1173         .name = "intel-gpio",
1174         .irq_ack = intel_gpio_irq_ack,
1175         .irq_mask = intel_gpio_irq_mask,
1176         .irq_unmask = intel_gpio_irq_unmask,
1177         .irq_set_type = intel_gpio_irq_type,
1178         .irq_set_wake = intel_gpio_irq_wake,
1179         .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
1180         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1181 };
1182
1183 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1184                                             const struct intel_community *community)
1185 {
1186         struct gpio_chip *gc = &pctrl->chip;
1187         unsigned int gpp;
1188         int ret = 0;
1189
1190         for (gpp = 0; gpp < community->ngpps; gpp++) {
1191                 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1192                 unsigned long pending, enabled, gpp_offset;
1193
1194                 raw_spin_lock(&pctrl->lock);
1195
1196                 pending = readl(community->regs + community->is_offset +
1197                                 padgrp->reg_num * 4);
1198                 enabled = readl(community->regs + community->ie_offset +
1199                                 padgrp->reg_num * 4);
1200
1201                 raw_spin_unlock(&pctrl->lock);
1202
1203                 /* Only interrupts that are enabled */
1204                 pending &= enabled;
1205
1206                 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1207                         unsigned int irq;
1208
1209                         irq = irq_find_mapping(gc->irq.domain,
1210                                                padgrp->gpio_base + gpp_offset);
1211                         generic_handle_irq(irq);
1212                 }
1213
1214                 ret += pending ? 1 : 0;
1215         }
1216
1217         return ret;
1218 }
1219
1220 static irqreturn_t intel_gpio_irq(int irq, void *data)
1221 {
1222         const struct intel_community *community;
1223         struct intel_pinctrl *pctrl = data;
1224         unsigned int i;
1225         int ret = 0;
1226
1227         /* Need to check all communities for pending interrupts */
1228         for (i = 0; i < pctrl->ncommunities; i++) {
1229                 community = &pctrl->communities[i];
1230                 ret += intel_gpio_community_irq_handler(pctrl, community);
1231         }
1232
1233         return IRQ_RETVAL(ret);
1234 }
1235
1236 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1237 {
1238         int i;
1239
1240         for (i = 0; i < pctrl->ncommunities; i++) {
1241                 const struct intel_community *community;
1242                 void __iomem *base;
1243                 unsigned int gpp;
1244
1245                 community = &pctrl->communities[i];
1246                 base = community->regs;
1247
1248                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1249                         /* Mask and clear all interrupts */
1250                         writel(0, base + community->ie_offset + gpp * 4);
1251                         writel(0xffff, base + community->is_offset + gpp * 4);
1252                 }
1253         }
1254 }
1255
1256 static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
1257 {
1258         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1259
1260         /*
1261          * Make sure the interrupt lines are in a proper state before
1262          * further configuration.
1263          */
1264         intel_gpio_irq_init(pctrl);
1265
1266         return 0;
1267 }
1268
1269 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
1270                                 const struct intel_community *community)
1271 {
1272         int ret = 0, i;
1273
1274         for (i = 0; i < community->ngpps; i++) {
1275                 const struct intel_padgroup *gpp = &community->gpps[i];
1276
1277                 if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1278                         continue;
1279
1280                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1281                                              gpp->gpio_base, gpp->base,
1282                                              gpp->size);
1283                 if (ret)
1284                         return ret;
1285         }
1286
1287         return ret;
1288 }
1289
1290 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1291 {
1292         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1293         int ret, i;
1294
1295         for (i = 0; i < pctrl->ncommunities; i++) {
1296                 struct intel_community *community = &pctrl->communities[i];
1297
1298                 ret = intel_gpio_add_community_ranges(pctrl, community);
1299                 if (ret) {
1300                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1301                         return ret;
1302                 }
1303         }
1304
1305         return 0;
1306 }
1307
1308 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1309 {
1310         const struct intel_community *community;
1311         unsigned int ngpio = 0;
1312         int i, j;
1313
1314         for (i = 0; i < pctrl->ncommunities; i++) {
1315                 community = &pctrl->communities[i];
1316                 for (j = 0; j < community->ngpps; j++) {
1317                         const struct intel_padgroup *gpp = &community->gpps[j];
1318
1319                         if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1320                                 continue;
1321
1322                         if (gpp->gpio_base + gpp->size > ngpio)
1323                                 ngpio = gpp->gpio_base + gpp->size;
1324                 }
1325         }
1326
1327         return ngpio;
1328 }
1329
1330 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1331 {
1332         int ret;
1333         struct gpio_irq_chip *girq;
1334
1335         pctrl->chip = intel_gpio_chip;
1336
1337         /* Setup GPIO chip */
1338         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1339         pctrl->chip.label = dev_name(pctrl->dev);
1340         pctrl->chip.parent = pctrl->dev;
1341         pctrl->chip.base = -1;
1342         pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1343         pctrl->irq = irq;
1344
1345         /*
1346          * On some platforms several GPIO controllers share the same interrupt
1347          * line.
1348          */
1349         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1350                                IRQF_SHARED | IRQF_NO_THREAD,
1351                                dev_name(pctrl->dev), pctrl);
1352         if (ret) {
1353                 dev_err(pctrl->dev, "failed to request interrupt\n");
1354                 return ret;
1355         }
1356
1357         /* Setup IRQ chip */
1358         girq = &pctrl->chip.irq;
1359         gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip);
1360         /* This will let us handle the IRQ in the driver */
1361         girq->parent_handler = NULL;
1362         girq->num_parents = 0;
1363         girq->default_type = IRQ_TYPE_NONE;
1364         girq->handler = handle_bad_irq;
1365         girq->init_hw = intel_gpio_irq_init_hw;
1366
1367         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1368         if (ret) {
1369                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1370                 return ret;
1371         }
1372
1373         return 0;
1374 }
1375
1376 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
1377                                                struct intel_community *community)
1378 {
1379         struct intel_padgroup *gpps;
1380         unsigned int padown_num = 0;
1381         size_t i, ngpps = community->ngpps;
1382
1383         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1384         if (!gpps)
1385                 return -ENOMEM;
1386
1387         for (i = 0; i < ngpps; i++) {
1388                 gpps[i] = community->gpps[i];
1389
1390                 if (gpps[i].size > 32)
1391                         return -EINVAL;
1392
1393                 /* Special treatment for GPIO base */
1394                 switch (gpps[i].gpio_base) {
1395                         case INTEL_GPIO_BASE_MATCH:
1396                                 gpps[i].gpio_base = gpps[i].base;
1397                                 break;
1398                         case INTEL_GPIO_BASE_ZERO:
1399                                 gpps[i].gpio_base = 0;
1400                                 break;
1401                         case INTEL_GPIO_BASE_NOMAP:
1402                                 break;
1403                         default:
1404                                 break;
1405                 }
1406
1407                 gpps[i].padown_num = padown_num;
1408                 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1409         }
1410
1411         community->gpps = gpps;
1412
1413         return 0;
1414 }
1415
1416 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
1417                                                struct intel_community *community)
1418 {
1419         struct intel_padgroup *gpps;
1420         unsigned int npins = community->npins;
1421         unsigned int padown_num = 0;
1422         size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
1423
1424         if (community->gpp_size > 32)
1425                 return -EINVAL;
1426
1427         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1428         if (!gpps)
1429                 return -ENOMEM;
1430
1431         for (i = 0; i < ngpps; i++) {
1432                 unsigned int gpp_size = community->gpp_size;
1433
1434                 gpps[i].reg_num = i;
1435                 gpps[i].base = community->pin_base + i * gpp_size;
1436                 gpps[i].size = min(gpp_size, npins);
1437                 npins -= gpps[i].size;
1438
1439                 gpps[i].gpio_base = gpps[i].base;
1440                 gpps[i].padown_num = padown_num;
1441
1442                 /*
1443                  * In older hardware the number of padown registers per
1444                  * group is fixed regardless of the group size.
1445                  */
1446                 if (community->gpp_num_padown_regs)
1447                         padown_num += community->gpp_num_padown_regs;
1448                 else
1449                         padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1450         }
1451
1452         community->ngpps = ngpps;
1453         community->gpps = gpps;
1454
1455         return 0;
1456 }
1457
1458 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1459 {
1460 #ifdef CONFIG_PM_SLEEP
1461         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1462         struct intel_community_context *communities;
1463         struct intel_pad_context *pads;
1464         int i;
1465
1466         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1467         if (!pads)
1468                 return -ENOMEM;
1469
1470         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1471                                    sizeof(*communities), GFP_KERNEL);
1472         if (!communities)
1473                 return -ENOMEM;
1474
1475
1476         for (i = 0; i < pctrl->ncommunities; i++) {
1477                 struct intel_community *community = &pctrl->communities[i];
1478                 u32 *intmask, *hostown;
1479
1480                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1481                                        sizeof(*intmask), GFP_KERNEL);
1482                 if (!intmask)
1483                         return -ENOMEM;
1484
1485                 communities[i].intmask = intmask;
1486
1487                 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1488                                        sizeof(*hostown), GFP_KERNEL);
1489                 if (!hostown)
1490                         return -ENOMEM;
1491
1492                 communities[i].hostown = hostown;
1493         }
1494
1495         pctrl->context.pads = pads;
1496         pctrl->context.communities = communities;
1497 #endif
1498
1499         return 0;
1500 }
1501
1502 static int intel_pinctrl_probe(struct platform_device *pdev,
1503                                const struct intel_pinctrl_soc_data *soc_data)
1504 {
1505         struct intel_pinctrl *pctrl;
1506         int i, ret, irq;
1507
1508         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1509         if (!pctrl)
1510                 return -ENOMEM;
1511
1512         pctrl->dev = &pdev->dev;
1513         pctrl->soc = soc_data;
1514         raw_spin_lock_init(&pctrl->lock);
1515
1516         /*
1517          * Make a copy of the communities which we can use to hold pointers
1518          * to the registers.
1519          */
1520         pctrl->ncommunities = pctrl->soc->ncommunities;
1521         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1522                                   sizeof(*pctrl->communities), GFP_KERNEL);
1523         if (!pctrl->communities)
1524                 return -ENOMEM;
1525
1526         for (i = 0; i < pctrl->ncommunities; i++) {
1527                 struct intel_community *community = &pctrl->communities[i];
1528                 void __iomem *regs;
1529                 u32 offset;
1530                 u32 value;
1531
1532                 *community = pctrl->soc->communities[i];
1533
1534                 regs = devm_platform_ioremap_resource(pdev, community->barno);
1535                 if (IS_ERR(regs))
1536                         return PTR_ERR(regs);
1537
1538                 /*
1539                  * Determine community features based on the revision.
1540                  * A value of all ones means the device is not present.
1541                  */
1542                 value = readl(regs + REVID);
1543                 if (value == ~0u)
1544                         return -ENODEV;
1545                 if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
1546                         community->features |= PINCTRL_FEATURE_DEBOUNCE;
1547                         community->features |= PINCTRL_FEATURE_1K_PD;
1548                 }
1549
1550                 /* Determine community features based on the capabilities */
1551                 offset = CAPLIST;
1552                 do {
1553                         value = readl(regs + offset);
1554                         switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
1555                         case CAPLIST_ID_GPIO_HW_INFO:
1556                                 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;
1557                                 break;
1558                         case CAPLIST_ID_PWM:
1559                                 community->features |= PINCTRL_FEATURE_PWM;
1560                                 break;
1561                         case CAPLIST_ID_BLINK:
1562                                 community->features |= PINCTRL_FEATURE_BLINK;
1563                                 break;
1564                         case CAPLIST_ID_EXP:
1565                                 community->features |= PINCTRL_FEATURE_EXP;
1566                                 break;
1567                         default:
1568                                 break;
1569                         }
1570                         offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
1571                 } while (offset);
1572
1573                 dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features);
1574
1575                 /* Read offset of the pad configuration registers */
1576                 offset = readl(regs + PADBAR);
1577
1578                 community->regs = regs;
1579                 community->pad_regs = regs + offset;
1580
1581                 if (community->gpps)
1582                         ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community);
1583                 else
1584                         ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
1585                 if (ret)
1586                         return ret;
1587         }
1588
1589         irq = platform_get_irq(pdev, 0);
1590         if (irq < 0)
1591                 return irq;
1592
1593         ret = intel_pinctrl_pm_init(pctrl);
1594         if (ret)
1595                 return ret;
1596
1597         pctrl->pctldesc = intel_pinctrl_desc;
1598         pctrl->pctldesc.name = dev_name(&pdev->dev);
1599         pctrl->pctldesc.pins = pctrl->soc->pins;
1600         pctrl->pctldesc.npins = pctrl->soc->npins;
1601
1602         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1603                                                pctrl);
1604         if (IS_ERR(pctrl->pctldev)) {
1605                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1606                 return PTR_ERR(pctrl->pctldev);
1607         }
1608
1609         ret = intel_gpio_probe(pctrl, irq);
1610         if (ret)
1611                 return ret;
1612
1613         platform_set_drvdata(pdev, pctrl);
1614
1615         return 0;
1616 }
1617
1618 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1619 {
1620         const struct intel_pinctrl_soc_data *data;
1621
1622         data = device_get_match_data(&pdev->dev);
1623         if (!data)
1624                 return -ENODATA;
1625
1626         return intel_pinctrl_probe(pdev, data);
1627 }
1628 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
1629
1630 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1631 {
1632         const struct intel_pinctrl_soc_data *data;
1633
1634         data = intel_pinctrl_get_soc_data(pdev);
1635         if (IS_ERR(data))
1636                 return PTR_ERR(data);
1637
1638         return intel_pinctrl_probe(pdev, data);
1639 }
1640 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
1641
1642 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
1643 {
1644         const struct intel_pinctrl_soc_data * const *table;
1645         const struct intel_pinctrl_soc_data *data = NULL;
1646
1647         table = device_get_match_data(&pdev->dev);
1648         if (table) {
1649                 struct acpi_device *adev = ACPI_COMPANION(&pdev->dev);
1650                 unsigned int i;
1651
1652                 for (i = 0; table[i]; i++) {
1653                         if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
1654                                 data = table[i];
1655                                 break;
1656                         }
1657                 }
1658         } else {
1659                 const struct platform_device_id *id;
1660
1661                 id = platform_get_device_id(pdev);
1662                 if (!id)
1663                         return ERR_PTR(-ENODEV);
1664
1665                 table = (const struct intel_pinctrl_soc_data * const *)id->driver_data;
1666                 data = table[pdev->id];
1667         }
1668
1669         return data ?: ERR_PTR(-ENODATA);
1670 }
1671 EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data);
1672
1673 #ifdef CONFIG_PM_SLEEP
1674 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1675 {
1676         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1677
1678         if (!pd || !intel_pad_usable(pctrl, pin))
1679                 return false;
1680
1681         /*
1682          * Only restore the pin if it is actually in use by the kernel (or
1683          * by userspace). It is possible that some pins are used by the
1684          * BIOS during resume and those are not always locked down so leave
1685          * them alone.
1686          */
1687         if (pd->mux_owner || pd->gpio_owner ||
1688             gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1689                 return true;
1690
1691         return false;
1692 }
1693
1694 int intel_pinctrl_suspend_noirq(struct device *dev)
1695 {
1696         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1697         struct intel_community_context *communities;
1698         struct intel_pad_context *pads;
1699         int i;
1700
1701         pads = pctrl->context.pads;
1702         for (i = 0; i < pctrl->soc->npins; i++) {
1703                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1704                 void __iomem *padcfg;
1705                 u32 val;
1706
1707                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1708                         continue;
1709
1710                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1711                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1712                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1713                 pads[i].padcfg1 = val;
1714
1715                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1716                 if (padcfg)
1717                         pads[i].padcfg2 = readl(padcfg);
1718         }
1719
1720         communities = pctrl->context.communities;
1721         for (i = 0; i < pctrl->ncommunities; i++) {
1722                 struct intel_community *community = &pctrl->communities[i];
1723                 void __iomem *base;
1724                 unsigned int gpp;
1725
1726                 base = community->regs + community->ie_offset;
1727                 for (gpp = 0; gpp < community->ngpps; gpp++)
1728                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1729
1730                 base = community->regs + community->hostown_offset;
1731                 for (gpp = 0; gpp < community->ngpps; gpp++)
1732                         communities[i].hostown[gpp] = readl(base + gpp * 4);
1733         }
1734
1735         return 0;
1736 }
1737 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1738
1739 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1740 {
1741         u32 curr, updated;
1742
1743         curr = readl(reg);
1744
1745         updated = (curr & ~mask) | (value & mask);
1746         if (curr == updated)
1747                 return false;
1748
1749         writel(updated, reg);
1750         return true;
1751 }
1752
1753 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1754                                   void __iomem *base, unsigned int gpp, u32 saved)
1755 {
1756         const struct intel_community *community = &pctrl->communities[c];
1757         const struct intel_padgroup *padgrp = &community->gpps[gpp];
1758         struct device *dev = pctrl->dev;
1759         const char *dummy;
1760         u32 requested = 0;
1761         unsigned int i;
1762
1763         if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1764                 return;
1765
1766         for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
1767                 requested |= BIT(i);
1768
1769         if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1770                 return;
1771
1772         dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1773 }
1774
1775 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1776                                   void __iomem *base, unsigned int gpp, u32 saved)
1777 {
1778         struct device *dev = pctrl->dev;
1779
1780         if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1781                 return;
1782
1783         dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1784 }
1785
1786 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1787                                  unsigned int reg, u32 saved)
1788 {
1789         u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1790         unsigned int n = reg / sizeof(u32);
1791         struct device *dev = pctrl->dev;
1792         void __iomem *padcfg;
1793
1794         padcfg = intel_get_padcfg(pctrl, pin, reg);
1795         if (!padcfg)
1796                 return;
1797
1798         if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1799                 return;
1800
1801         dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1802 }
1803
1804 int intel_pinctrl_resume_noirq(struct device *dev)
1805 {
1806         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1807         const struct intel_community_context *communities;
1808         const struct intel_pad_context *pads;
1809         int i;
1810
1811         /* Mask all interrupts */
1812         intel_gpio_irq_init(pctrl);
1813
1814         pads = pctrl->context.pads;
1815         for (i = 0; i < pctrl->soc->npins; i++) {
1816                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1817
1818                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1819                         continue;
1820
1821                 intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1822                 intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1823                 intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1824         }
1825
1826         communities = pctrl->context.communities;
1827         for (i = 0; i < pctrl->ncommunities; i++) {
1828                 struct intel_community *community = &pctrl->communities[i];
1829                 void __iomem *base;
1830                 unsigned int gpp;
1831
1832                 base = community->regs + community->ie_offset;
1833                 for (gpp = 0; gpp < community->ngpps; gpp++)
1834                         intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1835
1836                 base = community->regs + community->hostown_offset;
1837                 for (gpp = 0; gpp < community->ngpps; gpp++)
1838                         intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1839         }
1840
1841         return 0;
1842 }
1843 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1844 #endif
1845
1846 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1847 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1848 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1849 MODULE_LICENSE("GPL v2");