2 * Intel pinctrl/GPIO core driver.
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/log2.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-intel.h"
26 /* Offset from regs */
28 #define REVID_SHIFT 16
29 #define REVID_MASK GENMASK(31, 16)
35 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
36 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
37 #define PADOWN_GPP(p) ((p) / 8)
39 /* Offset from pad_regs */
41 #define PADCFG0_RXEVCFG_SHIFT 25
42 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
43 #define PADCFG0_RXEVCFG_LEVEL 0
44 #define PADCFG0_RXEVCFG_EDGE 1
45 #define PADCFG0_RXEVCFG_DISABLED 2
46 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
47 #define PADCFG0_PREGFRXSEL BIT(24)
48 #define PADCFG0_RXINV BIT(23)
49 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
50 #define PADCFG0_GPIROUTSCI BIT(19)
51 #define PADCFG0_GPIROUTSMI BIT(18)
52 #define PADCFG0_GPIROUTNMI BIT(17)
53 #define PADCFG0_PMODE_SHIFT 10
54 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
55 #define PADCFG0_GPIORXDIS BIT(9)
56 #define PADCFG0_GPIOTXDIS BIT(8)
57 #define PADCFG0_GPIORXSTATE BIT(1)
58 #define PADCFG0_GPIOTXSTATE BIT(0)
61 #define PADCFG1_TERM_UP BIT(13)
62 #define PADCFG1_TERM_SHIFT 10
63 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
64 #define PADCFG1_TERM_20K 4
65 #define PADCFG1_TERM_2K 3
66 #define PADCFG1_TERM_5K 2
67 #define PADCFG1_TERM_1K 1
70 #define PADCFG2_DEBEN BIT(0)
71 #define PADCFG2_DEBOUNCE_SHIFT 1
72 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
74 #define DEBOUNCE_PERIOD 31250 /* ns */
76 struct intel_pad_context {
82 struct intel_community_context {
86 struct intel_pinctrl_context {
87 struct intel_pad_context *pads;
88 struct intel_community_context *communities;
92 * struct intel_pinctrl - Intel pinctrl private structure
93 * @dev: Pointer to the device structure
94 * @lock: Lock to serialize register access
95 * @pctldesc: Pin controller description
96 * @pctldev: Pointer to the pin controller device
97 * @chip: GPIO chip in this pin controller
98 * @soc: SoC/PCH specific pin configuration data
99 * @communities: All communities in this pin controller
100 * @ncommunities: Number of communities in this pin controller
101 * @context: Configuration saved over system sleep
102 * @irq: pinctrl/GPIO chip irq number
104 struct intel_pinctrl {
107 struct pinctrl_desc pctldesc;
108 struct pinctrl_dev *pctldev;
109 struct gpio_chip chip;
110 const struct intel_pinctrl_soc_data *soc;
111 struct intel_community *communities;
113 struct intel_pinctrl_context context;
117 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
118 #define padgroup_offset(g, p) ((p) - (g)->base)
120 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
123 struct intel_community *community;
126 for (i = 0; i < pctrl->ncommunities; i++) {
127 community = &pctrl->communities[i];
128 if (pin >= community->pin_base &&
129 pin < community->pin_base + community->npins)
133 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
137 static const struct intel_padgroup *
138 intel_community_get_padgroup(const struct intel_community *community,
143 for (i = 0; i < community->ngpps; i++) {
144 const struct intel_padgroup *padgrp = &community->gpps[i];
146 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
153 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
156 const struct intel_community *community;
160 community = intel_get_community(pctrl, pin);
164 padno = pin_to_padno(community, pin);
165 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
167 if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
170 return community->pad_regs + reg + padno * nregs * 4;
173 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
175 const struct intel_community *community;
176 const struct intel_padgroup *padgrp;
177 unsigned gpp, offset, gpp_offset;
178 void __iomem *padown;
180 community = intel_get_community(pctrl, pin);
183 if (!community->padown_offset)
186 padgrp = intel_community_get_padgroup(community, pin);
190 gpp_offset = padgroup_offset(padgrp, pin);
191 gpp = PADOWN_GPP(gpp_offset);
192 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
193 padown = community->regs + offset;
195 return !(readl(padown) & PADOWN_MASK(gpp_offset));
198 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
200 const struct intel_community *community;
201 const struct intel_padgroup *padgrp;
202 unsigned offset, gpp_offset;
203 void __iomem *hostown;
205 community = intel_get_community(pctrl, pin);
208 if (!community->hostown_offset)
211 padgrp = intel_community_get_padgroup(community, pin);
215 gpp_offset = padgroup_offset(padgrp, pin);
216 offset = community->hostown_offset + padgrp->reg_num * 4;
217 hostown = community->regs + offset;
219 return !(readl(hostown) & BIT(gpp_offset));
222 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
224 struct intel_community *community;
225 const struct intel_padgroup *padgrp;
226 unsigned offset, gpp_offset;
229 community = intel_get_community(pctrl, pin);
232 if (!community->padcfglock_offset)
235 padgrp = intel_community_get_padgroup(community, pin);
239 gpp_offset = padgroup_offset(padgrp, pin);
242 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
243 * the pad is considered unlocked. Any other case means that it is
244 * either fully or partially locked and we don't touch it.
246 offset = community->padcfglock_offset + padgrp->reg_num * 8;
247 value = readl(community->regs + offset);
248 if (value & BIT(gpp_offset))
251 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
252 value = readl(community->regs + offset);
253 if (value & BIT(gpp_offset))
259 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
261 return intel_pad_owned_by_host(pctrl, pin) &&
262 !intel_pad_locked(pctrl, pin);
265 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
267 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
269 return pctrl->soc->ngroups;
272 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
275 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
277 return pctrl->soc->groups[group].name;
280 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
281 const unsigned **pins, unsigned *npins)
283 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
285 *pins = pctrl->soc->groups[group].pins;
286 *npins = pctrl->soc->groups[group].npins;
290 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
293 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
294 void __iomem *padcfg;
295 u32 cfg0, cfg1, mode;
298 if (!intel_pad_owned_by_host(pctrl, pin)) {
299 seq_puts(s, "not available");
303 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
304 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
306 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
308 seq_puts(s, "GPIO ");
310 seq_printf(s, "mode %d ", mode);
312 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
314 /* Dump the additional PADCFG registers if available */
315 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
317 seq_printf(s, " 0x%08x", readl(padcfg));
319 locked = intel_pad_locked(pctrl, pin);
320 acpi = intel_pad_acpi_mode(pctrl, pin);
322 if (locked || acpi) {
325 seq_puts(s, "LOCKED");
335 static const struct pinctrl_ops intel_pinctrl_ops = {
336 .get_groups_count = intel_get_groups_count,
337 .get_group_name = intel_get_group_name,
338 .get_group_pins = intel_get_group_pins,
339 .pin_dbg_show = intel_pin_dbg_show,
342 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
344 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
346 return pctrl->soc->nfunctions;
349 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
352 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
354 return pctrl->soc->functions[function].name;
357 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
359 const char * const **groups,
360 unsigned * const ngroups)
362 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
364 *groups = pctrl->soc->functions[function].groups;
365 *ngroups = pctrl->soc->functions[function].ngroups;
369 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
372 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
373 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
377 raw_spin_lock_irqsave(&pctrl->lock, flags);
380 * All pins in the groups needs to be accessible and writable
381 * before we can enable the mux for this group.
383 for (i = 0; i < grp->npins; i++) {
384 if (!intel_pad_usable(pctrl, grp->pins[i])) {
385 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
390 /* Now enable the mux setting for each pin in the group */
391 for (i = 0; i < grp->npins; i++) {
392 void __iomem *padcfg0;
395 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
396 value = readl(padcfg0);
398 value &= ~PADCFG0_PMODE_MASK;
401 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
403 value |= grp->mode << PADCFG0_PMODE_SHIFT;
405 writel(value, padcfg0);
408 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
413 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
417 value = readl(padcfg0);
419 value &= ~PADCFG0_GPIORXDIS;
420 value |= PADCFG0_GPIOTXDIS;
422 value &= ~PADCFG0_GPIOTXDIS;
423 value |= PADCFG0_GPIORXDIS;
425 writel(value, padcfg0);
428 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
432 /* Put the pad into GPIO mode */
433 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
434 /* Disable SCI/SMI/NMI generation */
435 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
436 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
437 writel(value, padcfg0);
440 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
441 struct pinctrl_gpio_range *range,
444 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
445 void __iomem *padcfg0;
448 raw_spin_lock_irqsave(&pctrl->lock, flags);
450 if (!intel_pad_usable(pctrl, pin)) {
451 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
455 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
456 intel_gpio_set_gpio_mode(padcfg0);
457 /* Disable TX buffer and enable RX (this will be input) */
458 __intel_gpio_set_direction(padcfg0, true);
460 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
465 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
466 struct pinctrl_gpio_range *range,
467 unsigned pin, bool input)
469 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
470 void __iomem *padcfg0;
473 raw_spin_lock_irqsave(&pctrl->lock, flags);
475 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
476 __intel_gpio_set_direction(padcfg0, input);
478 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
483 static const struct pinmux_ops intel_pinmux_ops = {
484 .get_functions_count = intel_get_functions_count,
485 .get_function_name = intel_get_function_name,
486 .get_function_groups = intel_get_function_groups,
487 .set_mux = intel_pinmux_set_mux,
488 .gpio_request_enable = intel_gpio_request_enable,
489 .gpio_set_direction = intel_gpio_set_direction,
492 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
493 unsigned long *config)
495 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
496 enum pin_config_param param = pinconf_to_config_param(*config);
497 const struct intel_community *community;
501 if (!intel_pad_owned_by_host(pctrl, pin))
504 community = intel_get_community(pctrl, pin);
505 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
506 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
509 case PIN_CONFIG_BIAS_DISABLE:
514 case PIN_CONFIG_BIAS_PULL_UP:
515 if (!term || !(value & PADCFG1_TERM_UP))
519 case PADCFG1_TERM_1K:
522 case PADCFG1_TERM_2K:
525 case PADCFG1_TERM_5K:
528 case PADCFG1_TERM_20K:
535 case PIN_CONFIG_BIAS_PULL_DOWN:
536 if (!term || value & PADCFG1_TERM_UP)
540 case PADCFG1_TERM_1K:
541 if (!(community->features & PINCTRL_FEATURE_1K_PD))
545 case PADCFG1_TERM_5K:
548 case PADCFG1_TERM_20K:
555 case PIN_CONFIG_INPUT_DEBOUNCE: {
556 void __iomem *padcfg2;
559 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
564 if (!(v & PADCFG2_DEBEN))
567 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
568 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
577 *config = pinconf_to_config_packed(param, arg);
581 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
582 unsigned long config)
584 unsigned param = pinconf_to_config_param(config);
585 unsigned arg = pinconf_to_config_argument(config);
586 const struct intel_community *community;
587 void __iomem *padcfg1;
592 raw_spin_lock_irqsave(&pctrl->lock, flags);
594 community = intel_get_community(pctrl, pin);
595 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
596 value = readl(padcfg1);
599 case PIN_CONFIG_BIAS_DISABLE:
600 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
603 case PIN_CONFIG_BIAS_PULL_UP:
604 value &= ~PADCFG1_TERM_MASK;
606 value |= PADCFG1_TERM_UP;
610 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
613 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
616 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
619 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
627 case PIN_CONFIG_BIAS_PULL_DOWN:
628 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
632 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
635 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
638 if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
642 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
652 writel(value, padcfg1);
654 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
659 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
662 void __iomem *padcfg0, *padcfg2;
667 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
671 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
673 raw_spin_lock_irqsave(&pctrl->lock, flags);
675 value0 = readl(padcfg0);
676 value2 = readl(padcfg2);
678 /* Disable glitch filter and debouncer */
679 value0 &= ~PADCFG0_PREGFRXSEL;
680 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
685 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
686 if (v < 3 || v > 15) {
690 /* Enable glitch filter and debouncer */
691 value0 |= PADCFG0_PREGFRXSEL;
692 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
693 value2 |= PADCFG2_DEBEN;
697 writel(value0, padcfg0);
698 writel(value2, padcfg2);
701 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
706 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
707 unsigned long *configs, unsigned nconfigs)
709 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
712 if (!intel_pad_usable(pctrl, pin))
715 for (i = 0; i < nconfigs; i++) {
716 switch (pinconf_to_config_param(configs[i])) {
717 case PIN_CONFIG_BIAS_DISABLE:
718 case PIN_CONFIG_BIAS_PULL_UP:
719 case PIN_CONFIG_BIAS_PULL_DOWN:
720 ret = intel_config_set_pull(pctrl, pin, configs[i]);
725 case PIN_CONFIG_INPUT_DEBOUNCE:
726 ret = intel_config_set_debounce(pctrl, pin,
727 pinconf_to_config_argument(configs[i]));
740 static const struct pinconf_ops intel_pinconf_ops = {
742 .pin_config_get = intel_config_get,
743 .pin_config_set = intel_config_set,
746 static const struct pinctrl_desc intel_pinctrl_desc = {
747 .pctlops = &intel_pinctrl_ops,
748 .pmxops = &intel_pinmux_ops,
749 .confops = &intel_pinconf_ops,
750 .owner = THIS_MODULE,
753 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
755 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
759 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
763 padcfg0 = readl(reg);
764 if (!(padcfg0 & PADCFG0_GPIOTXDIS))
765 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
767 return !!(padcfg0 & PADCFG0_GPIORXSTATE);
770 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
772 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
777 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
781 raw_spin_lock_irqsave(&pctrl->lock, flags);
782 padcfg0 = readl(reg);
784 padcfg0 |= PADCFG0_GPIOTXSTATE;
786 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
787 writel(padcfg0, reg);
788 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
791 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
793 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
797 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
801 padcfg0 = readl(reg);
803 if (padcfg0 & PADCFG0_PMODE_MASK)
806 return !!(padcfg0 & PADCFG0_GPIOTXDIS);
809 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
811 return pinctrl_gpio_direction_input(chip->base + offset);
814 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
817 intel_gpio_set(chip, offset, value);
818 return pinctrl_gpio_direction_output(chip->base + offset);
821 static const struct gpio_chip intel_gpio_chip = {
822 .owner = THIS_MODULE,
823 .request = gpiochip_generic_request,
824 .free = gpiochip_generic_free,
825 .get_direction = intel_gpio_get_direction,
826 .direction_input = intel_gpio_direction_input,
827 .direction_output = intel_gpio_direction_output,
828 .get = intel_gpio_get,
829 .set = intel_gpio_set,
830 .set_config = gpiochip_generic_config,
834 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
835 * @pctrl: Pinctrl structure
836 * @offset: GPIO offset from gpiolib
837 * @commmunity: Community is filled here if not %NULL
838 * @padgrp: Pad group is filled here if not %NULL
840 * When coming through gpiolib irqchip, the GPIO offset is not
841 * automatically translated to pinctrl pin number. This function can be
842 * used to find out the corresponding pinctrl pin.
844 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
845 const struct intel_community **community,
846 const struct intel_padgroup **padgrp)
850 for (i = 0; i < pctrl->ncommunities; i++) {
851 const struct intel_community *comm = &pctrl->communities[i];
854 for (j = 0; j < comm->ngpps; j++) {
855 const struct intel_padgroup *pgrp = &comm->gpps[j];
857 if (pgrp->gpio_base < 0)
860 if (offset >= pgrp->gpio_base &&
861 offset < pgrp->gpio_base + pgrp->size) {
864 pin = pgrp->base + offset - pgrp->gpio_base;
878 static void intel_gpio_irq_ack(struct irq_data *d)
880 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
881 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
882 const struct intel_community *community;
883 const struct intel_padgroup *padgrp;
886 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
888 unsigned gpp, gpp_offset, is_offset;
890 gpp = padgrp->reg_num;
891 gpp_offset = padgroup_offset(padgrp, pin);
892 is_offset = community->is_offset + gpp * 4;
894 raw_spin_lock(&pctrl->lock);
895 writel(BIT(gpp_offset), community->regs + is_offset);
896 raw_spin_unlock(&pctrl->lock);
900 static void intel_gpio_irq_enable(struct irq_data *d)
902 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
903 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
904 const struct intel_community *community;
905 const struct intel_padgroup *padgrp;
908 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
910 unsigned gpp, gpp_offset, is_offset;
914 gpp = padgrp->reg_num;
915 gpp_offset = padgroup_offset(padgrp, pin);
916 is_offset = community->is_offset + gpp * 4;
918 raw_spin_lock_irqsave(&pctrl->lock, flags);
919 /* Clear interrupt status first to avoid unexpected interrupt */
920 writel(BIT(gpp_offset), community->regs + is_offset);
922 value = readl(community->regs + community->ie_offset + gpp * 4);
923 value |= BIT(gpp_offset);
924 writel(value, community->regs + community->ie_offset + gpp * 4);
925 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
929 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
931 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
932 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
933 const struct intel_community *community;
934 const struct intel_padgroup *padgrp;
937 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
939 unsigned gpp, gpp_offset;
944 gpp = padgrp->reg_num;
945 gpp_offset = padgroup_offset(padgrp, pin);
947 reg = community->regs + community->ie_offset + gpp * 4;
949 raw_spin_lock_irqsave(&pctrl->lock, flags);
952 value &= ~BIT(gpp_offset);
954 value |= BIT(gpp_offset);
956 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
960 static void intel_gpio_irq_mask(struct irq_data *d)
962 intel_gpio_irq_mask_unmask(d, true);
965 static void intel_gpio_irq_unmask(struct irq_data *d)
967 intel_gpio_irq_mask_unmask(d, false);
970 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
972 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
973 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
974 unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
979 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
984 * If the pin is in ACPI mode it is still usable as a GPIO but it
985 * cannot be used as IRQ because GPI_IS status bit will not be
986 * updated by the host controller hardware.
988 if (intel_pad_acpi_mode(pctrl, pin)) {
989 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
993 raw_spin_lock_irqsave(&pctrl->lock, flags);
995 intel_gpio_set_gpio_mode(reg);
999 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1001 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1002 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1003 } else if (type & IRQ_TYPE_EDGE_FALLING) {
1004 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1005 value |= PADCFG0_RXINV;
1006 } else if (type & IRQ_TYPE_EDGE_RISING) {
1007 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1008 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1009 if (type & IRQ_TYPE_LEVEL_LOW)
1010 value |= PADCFG0_RXINV;
1012 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1017 if (type & IRQ_TYPE_EDGE_BOTH)
1018 irq_set_handler_locked(d, handle_edge_irq);
1019 else if (type & IRQ_TYPE_LEVEL_MASK)
1020 irq_set_handler_locked(d, handle_level_irq);
1022 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1027 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1029 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1030 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1031 unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1034 enable_irq_wake(pctrl->irq);
1036 disable_irq_wake(pctrl->irq);
1038 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1042 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1043 const struct intel_community *community)
1045 struct gpio_chip *gc = &pctrl->chip;
1046 irqreturn_t ret = IRQ_NONE;
1049 for (gpp = 0; gpp < community->ngpps; gpp++) {
1050 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1051 unsigned long pending, enabled, gpp_offset;
1053 pending = readl(community->regs + community->is_offset +
1054 padgrp->reg_num * 4);
1055 enabled = readl(community->regs + community->ie_offset +
1056 padgrp->reg_num * 4);
1058 /* Only interrupts that are enabled */
1061 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1064 irq = irq_find_mapping(gc->irq.domain,
1065 padgrp->gpio_base + gpp_offset);
1066 generic_handle_irq(irq);
1075 static irqreturn_t intel_gpio_irq(int irq, void *data)
1077 const struct intel_community *community;
1078 struct intel_pinctrl *pctrl = data;
1079 irqreturn_t ret = IRQ_NONE;
1082 /* Need to check all communities for pending interrupts */
1083 for (i = 0; i < pctrl->ncommunities; i++) {
1084 community = &pctrl->communities[i];
1085 ret |= intel_gpio_community_irq_handler(pctrl, community);
1091 static struct irq_chip intel_gpio_irqchip = {
1092 .name = "intel-gpio",
1093 .irq_enable = intel_gpio_irq_enable,
1094 .irq_ack = intel_gpio_irq_ack,
1095 .irq_mask = intel_gpio_irq_mask,
1096 .irq_unmask = intel_gpio_irq_unmask,
1097 .irq_set_type = intel_gpio_irq_type,
1098 .irq_set_wake = intel_gpio_irq_wake,
1099 .flags = IRQCHIP_MASK_ON_SUSPEND,
1102 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1103 const struct intel_community *community)
1107 for (i = 0; i < community->ngpps; i++) {
1108 const struct intel_padgroup *gpp = &community->gpps[i];
1110 if (gpp->gpio_base < 0)
1113 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1114 gpp->gpio_base, gpp->base,
1123 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1125 const struct intel_community *community;
1129 for (i = 0; i < pctrl->ncommunities; i++) {
1130 community = &pctrl->communities[i];
1131 for (j = 0; j < community->ngpps; j++) {
1132 const struct intel_padgroup *gpp = &community->gpps[j];
1134 if (gpp->gpio_base < 0)
1137 if (gpp->gpio_base + gpp->size > ngpio)
1138 ngpio = gpp->gpio_base + gpp->size;
1145 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1149 pctrl->chip = intel_gpio_chip;
1151 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1152 pctrl->chip.label = dev_name(pctrl->dev);
1153 pctrl->chip.parent = pctrl->dev;
1154 pctrl->chip.base = -1;
1157 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1159 dev_err(pctrl->dev, "failed to register gpiochip\n");
1163 for (i = 0; i < pctrl->ncommunities; i++) {
1164 struct intel_community *community = &pctrl->communities[i];
1166 ret = intel_gpio_add_pin_ranges(pctrl, community);
1168 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1174 * We need to request the interrupt here (instead of providing chip
1175 * to the irq directly) because on some platforms several GPIO
1176 * controllers share the same interrupt line.
1178 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1179 IRQF_SHARED | IRQF_NO_THREAD,
1180 dev_name(pctrl->dev), pctrl);
1182 dev_err(pctrl->dev, "failed to request interrupt\n");
1186 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1187 handle_bad_irq, IRQ_TYPE_NONE);
1189 dev_err(pctrl->dev, "failed to add irqchip\n");
1193 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1198 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1199 struct intel_community *community)
1201 struct intel_padgroup *gpps;
1202 unsigned npins = community->npins;
1203 unsigned padown_num = 0;
1206 if (community->gpps)
1207 ngpps = community->ngpps;
1209 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1211 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1215 for (i = 0; i < ngpps; i++) {
1216 if (community->gpps) {
1217 gpps[i] = community->gpps[i];
1219 unsigned gpp_size = community->gpp_size;
1221 gpps[i].reg_num = i;
1222 gpps[i].base = community->pin_base + i * gpp_size;
1223 gpps[i].size = min(gpp_size, npins);
1224 npins -= gpps[i].size;
1227 if (gpps[i].size > 32)
1230 if (!gpps[i].gpio_base)
1231 gpps[i].gpio_base = gpps[i].base;
1233 gpps[i].padown_num = padown_num;
1236 * In older hardware the number of padown registers per
1237 * group is fixed regardless of the group size.
1239 if (community->gpp_num_padown_regs)
1240 padown_num += community->gpp_num_padown_regs;
1242 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1245 community->ngpps = ngpps;
1246 community->gpps = gpps;
1251 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1253 #ifdef CONFIG_PM_SLEEP
1254 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1255 struct intel_community_context *communities;
1256 struct intel_pad_context *pads;
1259 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1263 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1264 sizeof(*communities), GFP_KERNEL);
1269 for (i = 0; i < pctrl->ncommunities; i++) {
1270 struct intel_community *community = &pctrl->communities[i];
1273 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1274 sizeof(*intmask), GFP_KERNEL);
1278 communities[i].intmask = intmask;
1281 pctrl->context.pads = pads;
1282 pctrl->context.communities = communities;
1288 int intel_pinctrl_probe(struct platform_device *pdev,
1289 const struct intel_pinctrl_soc_data *soc_data)
1291 struct intel_pinctrl *pctrl;
1297 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1301 pctrl->dev = &pdev->dev;
1302 pctrl->soc = soc_data;
1303 raw_spin_lock_init(&pctrl->lock);
1306 * Make a copy of the communities which we can use to hold pointers
1309 pctrl->ncommunities = pctrl->soc->ncommunities;
1310 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1311 sizeof(*pctrl->communities), GFP_KERNEL);
1312 if (!pctrl->communities)
1315 for (i = 0; i < pctrl->ncommunities; i++) {
1316 struct intel_community *community = &pctrl->communities[i];
1317 struct resource *res;
1321 *community = pctrl->soc->communities[i];
1323 res = platform_get_resource(pdev, IORESOURCE_MEM,
1325 regs = devm_ioremap_resource(&pdev->dev, res);
1327 return PTR_ERR(regs);
1330 * Determine community features based on the revision if
1331 * not specified already.
1333 if (!community->features) {
1336 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1338 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1339 community->features |= PINCTRL_FEATURE_1K_PD;
1343 /* Read offset of the pad configuration registers */
1344 padbar = readl(regs + PADBAR);
1346 community->regs = regs;
1347 community->pad_regs = regs + padbar;
1349 if (!community->is_offset)
1350 community->is_offset = GPI_IS;
1352 ret = intel_pinctrl_add_padgroups(pctrl, community);
1357 irq = platform_get_irq(pdev, 0);
1359 dev_err(&pdev->dev, "failed to get interrupt number\n");
1363 ret = intel_pinctrl_pm_init(pctrl);
1367 pctrl->pctldesc = intel_pinctrl_desc;
1368 pctrl->pctldesc.name = dev_name(&pdev->dev);
1369 pctrl->pctldesc.pins = pctrl->soc->pins;
1370 pctrl->pctldesc.npins = pctrl->soc->npins;
1372 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1374 if (IS_ERR(pctrl->pctldev)) {
1375 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1376 return PTR_ERR(pctrl->pctldev);
1379 ret = intel_gpio_probe(pctrl, irq);
1383 platform_set_drvdata(pdev, pctrl);
1387 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1389 #ifdef CONFIG_PM_SLEEP
1390 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1392 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1394 if (!pd || !intel_pad_usable(pctrl, pin))
1398 * Only restore the pin if it is actually in use by the kernel (or
1399 * by userspace). It is possible that some pins are used by the
1400 * BIOS during resume and those are not always locked down so leave
1403 if (pd->mux_owner || pd->gpio_owner ||
1404 gpiochip_line_is_irq(&pctrl->chip, pin))
1410 int intel_pinctrl_suspend(struct device *dev)
1412 struct platform_device *pdev = to_platform_device(dev);
1413 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1414 struct intel_community_context *communities;
1415 struct intel_pad_context *pads;
1418 pads = pctrl->context.pads;
1419 for (i = 0; i < pctrl->soc->npins; i++) {
1420 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1421 void __iomem *padcfg;
1424 if (!intel_pinctrl_should_save(pctrl, desc->number))
1427 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1428 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1429 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1430 pads[i].padcfg1 = val;
1432 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1434 pads[i].padcfg2 = readl(padcfg);
1437 communities = pctrl->context.communities;
1438 for (i = 0; i < pctrl->ncommunities; i++) {
1439 struct intel_community *community = &pctrl->communities[i];
1443 base = community->regs + community->ie_offset;
1444 for (gpp = 0; gpp < community->ngpps; gpp++)
1445 communities[i].intmask[gpp] = readl(base + gpp * 4);
1450 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1452 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1456 for (i = 0; i < pctrl->ncommunities; i++) {
1457 const struct intel_community *community;
1461 community = &pctrl->communities[i];
1462 base = community->regs;
1464 for (gpp = 0; gpp < community->ngpps; gpp++) {
1465 /* Mask and clear all interrupts */
1466 writel(0, base + community->ie_offset + gpp * 4);
1467 writel(0xffff, base + community->is_offset + gpp * 4);
1472 int intel_pinctrl_resume(struct device *dev)
1474 struct platform_device *pdev = to_platform_device(dev);
1475 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1476 const struct intel_community_context *communities;
1477 const struct intel_pad_context *pads;
1480 /* Mask all interrupts */
1481 intel_gpio_irq_init(pctrl);
1483 pads = pctrl->context.pads;
1484 for (i = 0; i < pctrl->soc->npins; i++) {
1485 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1486 void __iomem *padcfg;
1489 if (!intel_pinctrl_should_save(pctrl, desc->number))
1492 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1493 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1494 if (val != pads[i].padcfg0) {
1495 writel(pads[i].padcfg0, padcfg);
1496 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1497 desc->number, readl(padcfg));
1500 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1501 val = readl(padcfg);
1502 if (val != pads[i].padcfg1) {
1503 writel(pads[i].padcfg1, padcfg);
1504 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1505 desc->number, readl(padcfg));
1508 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1510 val = readl(padcfg);
1511 if (val != pads[i].padcfg2) {
1512 writel(pads[i].padcfg2, padcfg);
1513 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1514 desc->number, readl(padcfg));
1519 communities = pctrl->context.communities;
1520 for (i = 0; i < pctrl->ncommunities; i++) {
1521 struct intel_community *community = &pctrl->communities[i];
1525 base = community->regs + community->ie_offset;
1526 for (gpp = 0; gpp < community->ngpps; gpp++) {
1527 writel(communities[i].intmask[gpp], base + gpp * 4);
1528 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1529 readl(base + gpp * 4));
1535 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1538 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1539 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1540 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1541 MODULE_LICENSE("GPL v2");