drivers/pinctrl/intel/pinctrl-intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel pinctrl/GPIO core driver.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/gpio/driver.h>
  13 #include <linux/log2.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/property.h>
  17 #include <linux/time.h>
  18
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/pinctrl/pinconf.h>
  22 #include <linux/pinctrl/pinconf-generic.h>
  23
  24 #include "../core.h"
  25 #include "pinctrl-intel.h"
  26
  27 /* Offset from regs */
  28 #define REVID                           0x000
  29 #define REVID_SHIFT                     16
  30 #define REVID_MASK                      GENMASK(31, 16)
  31
  32 #define PADBAR                          0x00c
  33
  34 #define PADOWN_BITS                     4
  35 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  36 #define PADOWN_MASK(p)                  (GENMASK(3, 0) << PADOWN_SHIFT(p))
  37 #define PADOWN_GPP(p)                   ((p) / 8)
  38
  39 /* Offset from pad_regs */
  40 #define PADCFG0                         0x000
  41 #define PADCFG0_RXEVCFG_SHIFT           25
  42 #define PADCFG0_RXEVCFG_MASK            GENMASK(26, 25)
  43 #define PADCFG0_RXEVCFG_LEVEL           0
  44 #define PADCFG0_RXEVCFG_EDGE            1
  45 #define PADCFG0_RXEVCFG_DISABLED        2
  46 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  47 #define PADCFG0_PREGFRXSEL              BIT(24)
  48 #define PADCFG0_RXINV                   BIT(23)
  49 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  50 #define PADCFG0_GPIROUTSCI              BIT(19)
  51 #define PADCFG0_GPIROUTSMI              BIT(18)
  52 #define PADCFG0_GPIROUTNMI              BIT(17)
  53 #define PADCFG0_PMODE_SHIFT             10
  54 #define PADCFG0_PMODE_MASK              GENMASK(13, 10)
  55 #define PADCFG0_GPIORXDIS               BIT(9)
  56 #define PADCFG0_GPIOTXDIS               BIT(8)
  57 #define PADCFG0_GPIORXSTATE             BIT(1)
  58 #define PADCFG0_GPIOTXSTATE             BIT(0)
  59
  60 #define PADCFG1                         0x004
  61 #define PADCFG1_TERM_UP                 BIT(13)
  62 #define PADCFG1_TERM_SHIFT              10
  63 #define PADCFG1_TERM_MASK               GENMASK(12, 10)
  64 #define PADCFG1_TERM_20K                4
  65 #define PADCFG1_TERM_2K                 3
  66 #define PADCFG1_TERM_5K                 2
  67 #define PADCFG1_TERM_1K                 1
  68
  69 #define PADCFG2                         0x008
  70 #define PADCFG2_DEBEN                   BIT(0)
  71 #define PADCFG2_DEBOUNCE_SHIFT          1
  72 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
  73
  74 #define DEBOUNCE_PERIOD_NSEC            31250
  75
  76 struct intel_pad_context {
  77         u32 padcfg0;
  78         u32 padcfg1;
  79         u32 padcfg2;
  80 };
  81
  82 struct intel_community_context {
  83         u32 *intmask;
  84         u32 *hostown;
  85 };
  86
  87 struct intel_pinctrl_context {
  88         struct intel_pad_context *pads;
  89         struct intel_community_context *communities;
  90 };
  91
  92 /**
  93  * struct intel_pinctrl - Intel pinctrl private structure
  94  * @dev: Pointer to the device structure
  95  * @lock: Lock to serialize register access
  96  * @pctldesc: Pin controller description
  97  * @pctldev: Pointer to the pin controller device
  98  * @chip: GPIO chip in this pin controller
  99  * @soc: SoC/PCH specific pin configuration data
 100  * @communities: All communities in this pin controller
 101  * @ncommunities: Number of communities in this pin controller
 102  * @context: Configuration saved over system sleep
 103  * @irq: pinctrl/GPIO chip irq number
 104  */
 105 struct intel_pinctrl {
 106         struct device *dev;
 107         raw_spinlock_t lock;
 108         struct pinctrl_desc pctldesc;
 109         struct pinctrl_dev *pctldev;
 110         struct gpio_chip chip;
 111         const struct intel_pinctrl_soc_data *soc;
 112         struct intel_community *communities;
 113         size_t ncommunities;
 114         struct intel_pinctrl_context context;
 115         int irq;
 116 };
 117
 118 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 119 #define padgroup_offset(g, p)   ((p) - (g)->base)
 120
 121 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
 122                                                    unsigned int pin)
 123 {
 124         struct intel_community *community;
 125         int i;
 126
 127         for (i = 0; i < pctrl->ncommunities; i++) {
 128                 community = &pctrl->communities[i];
 129                 if (pin >= community->pin_base &&
 130                     pin < community->pin_base + community->npins)
 131                         return community;
 132         }
 133
 134         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 135         return NULL;
 136 }
 137
 138 static const struct intel_padgroup *
 139 intel_community_get_padgroup(const struct intel_community *community,
 140                              unsigned int pin)
 141 {
 142         int i;
 143
 144         for (i = 0; i < community->ngpps; i++) {
 145                 const struct intel_padgroup *padgrp = &community->gpps[i];
 146
 147                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 148                         return padgrp;
 149         }
 150
 151         return NULL;
 152 }
 153
 154 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
 155                                       unsigned int pin, unsigned int reg)
 156 {
 157         const struct intel_community *community;
 158         unsigned int padno;
 159         size_t nregs;
 160
 161         community = intel_get_community(pctrl, pin);
 162         if (!community)
 163                 return NULL;
 164
 165         padno = pin_to_padno(community, pin);
 166         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 167
 168         if (reg >= nregs * 4)
 169                 return NULL;
 170
 171         return community->pad_regs + reg + padno * nregs * 4;
 172 }
 173
 174 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
 175 {
 176         const struct intel_community *community;
 177         const struct intel_padgroup *padgrp;
 178         unsigned int gpp, offset, gpp_offset;
 179         void __iomem *padown;
 180
 181         community = intel_get_community(pctrl, pin);
 182         if (!community)
 183                 return false;
 184         if (!community->padown_offset)
 185                 return true;
 186
 187         padgrp = intel_community_get_padgroup(community, pin);
 188         if (!padgrp)
 189                 return false;
 190
 191         gpp_offset = padgroup_offset(padgrp, pin);
 192         gpp = PADOWN_GPP(gpp_offset);
 193         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 194         padown = community->regs + offset;
 195
 196         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 197 }
 198
 199 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
 200 {
 201         const struct intel_community *community;
 202         const struct intel_padgroup *padgrp;
 203         unsigned int offset, gpp_offset;
 204         void __iomem *hostown;
 205
 206         community = intel_get_community(pctrl, pin);
 207         if (!community)
 208                 return true;
 209         if (!community->hostown_offset)
 210                 return false;
 211
 212         padgrp = intel_community_get_padgroup(community, pin);
 213         if (!padgrp)
 214                 return true;
 215
 216         gpp_offset = padgroup_offset(padgrp, pin);
 217         offset = community->hostown_offset + padgrp->reg_num * 4;
 218         hostown = community->regs + offset;
 219
 220         return !(readl(hostown) & BIT(gpp_offset));
 221 }
 222
 223 /**
 224  * enum - Locking variants of the pad configuration
 225  *
 226  * @PAD_UNLOCKED:       pad is fully controlled by the configuration registers
 227  * @PAD_LOCKED:         pad configuration registers, except TX state, are locked
 228  * @PAD_LOCKED_TX:      pad configuration TX state is locked
 229  * @PAD_LOCKED_FULL:    pad configuration registers are locked completely
 230  *
 231  * Locking is considered as read-only mode for corresponding registers and
 232  * their respective fields. That said, TX state bit is locked separately from
 233  * the main locking scheme.
 234  */
 235 enum {
 236         PAD_UNLOCKED    = 0,
 237         PAD_LOCKED      = 1,
 238         PAD_LOCKED_TX   = 2,
 239         PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
 240 };
 241
 242 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
 243 {
 244         struct intel_community *community;
 245         const struct intel_padgroup *padgrp;
 246         unsigned int offset, gpp_offset;
 247         u32 value;
 248         int ret = PAD_UNLOCKED;
 249
 250         community = intel_get_community(pctrl, pin);
 251         if (!community)
 252                 return PAD_LOCKED_FULL;
 253         if (!community->padcfglock_offset)
 254                 return PAD_UNLOCKED;
 255
 256         padgrp = intel_community_get_padgroup(community, pin);
 257         if (!padgrp)
 258                 return PAD_LOCKED_FULL;
 259
 260         gpp_offset = padgroup_offset(padgrp, pin);
 261
 262         /*
 263          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 264          * the pad is considered unlocked. Any other case means that it is
 265          * either fully or partially locked.
 266          */
 267         offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
 268         value = readl(community->regs + offset);
 269         if (value & BIT(gpp_offset))
 270                 ret |= PAD_LOCKED;
 271
 272         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 273         value = readl(community->regs + offset);
 274         if (value & BIT(gpp_offset))
 275                 ret |= PAD_LOCKED_TX;
 276
 277         return ret;
 278 }
 279
 280 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
 281 {
 282         return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
 283 }
 284
 285 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
 286 {
 287         return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
 288 }
 289
 290 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 291 {
 292         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 293
 294         return pctrl->soc->ngroups;
 295 }
 296
 297 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 298                                       unsigned int group)
 299 {
 300         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 301
 302         return pctrl->soc->groups[group].name;
 303 }
 304
 305 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 306                               const unsigned int **pins, unsigned int *npins)
 307 {
 308         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 309
 310         *pins = pctrl->soc->groups[group].pins;
 311         *npins = pctrl->soc->groups[group].npins;
 312         return 0;
 313 }
 314
 315 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 316                                unsigned int pin)
 317 {
 318         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 319         void __iomem *padcfg;
 320         u32 cfg0, cfg1, mode;
 321         int locked;
 322         bool acpi;
 323
 324         if (!intel_pad_owned_by_host(pctrl, pin)) {
 325                 seq_puts(s, "not available");
 326                 return;
 327         }
 328
 329         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 330         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 331
 332         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 333         if (!mode)
 334                 seq_puts(s, "GPIO ");
 335         else
 336                 seq_printf(s, "mode %d ", mode);
 337
 338         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 339
 340         /* Dump the additional PADCFG registers if available */
 341         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 342         if (padcfg)
 343                 seq_printf(s, " 0x%08x", readl(padcfg));
 344
 345         locked = intel_pad_locked(pctrl, pin);
 346         acpi = intel_pad_acpi_mode(pctrl, pin);
 347
 348         if (locked || acpi) {
 349                 seq_puts(s, " [");
 350                 if (locked)
 351                         seq_puts(s, "LOCKED");
 352                 if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
 353                         seq_puts(s, " tx");
 354                 else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
 355                         seq_puts(s, " full");
 356
 357                 if (locked && acpi)
 358                         seq_puts(s, ", ");
 359
 360                 if (acpi)
 361                         seq_puts(s, "ACPI");
 362                 seq_puts(s, "]");
 363         }
 364 }
 365
 366 static const struct pinctrl_ops intel_pinctrl_ops = {
 367         .get_groups_count = intel_get_groups_count,
 368         .get_group_name = intel_get_group_name,
 369         .get_group_pins = intel_get_group_pins,
 370         .pin_dbg_show = intel_pin_dbg_show,
 371 };
 372
 373 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 374 {
 375         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 376
 377         return pctrl->soc->nfunctions;
 378 }
 379
 380 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 381                                            unsigned int function)
 382 {
 383         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 384
 385         return pctrl->soc->functions[function].name;
 386 }
 387
 388 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 389                                      unsigned int function,
 390                                      const char * const **groups,
 391                                      unsigned int * const ngroups)
 392 {
 393         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 394
 395         *groups = pctrl->soc->functions[function].groups;
 396         *ngroups = pctrl->soc->functions[function].ngroups;
 397         return 0;
 398 }
 399
 400 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
 401                                 unsigned int function, unsigned int group)
 402 {
 403         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 404         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 405         unsigned long flags;
 406         int i;
 407
 408         raw_spin_lock_irqsave(&pctrl->lock, flags);
 409
 410         /*
 411          * All pins in the groups needs to be accessible and writable
 412          * before we can enable the mux for this group.
 413          */
 414         for (i = 0; i < grp->npins; i++) {
 415                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
 416                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 417                         return -EBUSY;
 418                 }
 419         }
 420
 421         /* Now enable the mux setting for each pin in the group */
 422         for (i = 0; i < grp->npins; i++) {
 423                 void __iomem *padcfg0;
 424                 u32 value;
 425
 426                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
 427                 value = readl(padcfg0);
 428
 429                 value &= ~PADCFG0_PMODE_MASK;
 430
 431                 if (grp->modes)
 432                         value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
 433                 else
 434                         value |= grp->mode << PADCFG0_PMODE_SHIFT;
 435
 436                 writel(value, padcfg0);
 437         }
 438
 439         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 440
 441         return 0;
 442 }
 443
 444 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 445 {
 446         u32 value;
 447
 448         value = readl(padcfg0);
 449         if (input) {
 450                 value &= ~PADCFG0_GPIORXDIS;
 451                 value |= PADCFG0_GPIOTXDIS;
 452         } else {
 453                 value &= ~PADCFG0_GPIOTXDIS;
 454                 value |= PADCFG0_GPIORXDIS;
 455         }
 456         writel(value, padcfg0);
 457 }
 458
 459 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 460 {
 461         u32 value;
 462
 463         /* Put the pad into GPIO mode */
 464         value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
 465         /* Disable SCI/SMI/NMI generation */
 466         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 467         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 468         writel(value, padcfg0);
 469 }
 470
 471 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 472                                      struct pinctrl_gpio_range *range,
 473                                      unsigned int pin)
 474 {
 475         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 476         void __iomem *padcfg0;
 477         unsigned long flags;
 478
 479         raw_spin_lock_irqsave(&pctrl->lock, flags);
 480
 481         if (!intel_pad_owned_by_host(pctrl, pin)) {
 482                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 483                 return -EBUSY;
 484         }
 485
 486         if (!intel_pad_is_unlocked(pctrl, pin)) {
 487                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 488                 return 0;
 489         }
 490
 491         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 492         intel_gpio_set_gpio_mode(padcfg0);
 493         /* Disable TX buffer and enable RX (this will be input) */
 494         __intel_gpio_set_direction(padcfg0, true);
 495
 496         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 497
 498         return 0;
 499 }
 500
 501 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 502                                     struct pinctrl_gpio_range *range,
 503                                     unsigned int pin, bool input)
 504 {
 505         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 506         void __iomem *padcfg0;
 507         unsigned long flags;
 508
 509         raw_spin_lock_irqsave(&pctrl->lock, flags);
 510
 511         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 512         __intel_gpio_set_direction(padcfg0, input);
 513
 514         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 515
 516         return 0;
 517 }
 518
 519 static const struct pinmux_ops intel_pinmux_ops = {
 520         .get_functions_count = intel_get_functions_count,
 521         .get_function_name = intel_get_function_name,
 522         .get_function_groups = intel_get_function_groups,
 523         .set_mux = intel_pinmux_set_mux,
 524         .gpio_request_enable = intel_gpio_request_enable,
 525         .gpio_set_direction = intel_gpio_set_direction,
 526 };
 527
 528 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 529                             unsigned long *config)
 530 {
 531         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 532         enum pin_config_param param = pinconf_to_config_param(*config);
 533         const struct intel_community *community;
 534         u32 value, term;
 535         u32 arg = 0;
 536
 537         if (!intel_pad_owned_by_host(pctrl, pin))
 538                 return -ENOTSUPP;
 539
 540         community = intel_get_community(pctrl, pin);
 541         value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 542         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 543
 544         switch (param) {
 545         case PIN_CONFIG_BIAS_DISABLE:
 546                 if (term)
 547                         return -EINVAL;
 548                 break;
 549
 550         case PIN_CONFIG_BIAS_PULL_UP:
 551                 if (!term || !(value & PADCFG1_TERM_UP))
 552                         return -EINVAL;
 553
 554                 switch (term) {
 555                 case PADCFG1_TERM_1K:
 556                         arg = 1000;
 557                         break;
 558                 case PADCFG1_TERM_2K:
 559                         arg = 2000;
 560                         break;
 561                 case PADCFG1_TERM_5K:
 562                         arg = 5000;
 563                         break;
 564                 case PADCFG1_TERM_20K:
 565                         arg = 20000;
 566                         break;
 567                 }
 568
 569                 break;
 570
 571         case PIN_CONFIG_BIAS_PULL_DOWN:
 572                 if (!term || value & PADCFG1_TERM_UP)
 573                         return -EINVAL;
 574
 575                 switch (term) {
 576                 case PADCFG1_TERM_1K:
 577                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 578                                 return -EINVAL;
 579                         arg = 1000;
 580                         break;
 581                 case PADCFG1_TERM_5K:
 582                         arg = 5000;
 583                         break;
 584                 case PADCFG1_TERM_20K:
 585                         arg = 20000;
 586                         break;
 587                 }
 588
 589                 break;
 590
 591         case PIN_CONFIG_INPUT_DEBOUNCE: {
 592                 void __iomem *padcfg2;
 593                 u32 v;
 594
 595                 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 596                 if (!padcfg2)
 597                         return -ENOTSUPP;
 598
 599                 v = readl(padcfg2);
 600                 if (!(v & PADCFG2_DEBEN))
 601                         return -EINVAL;
 602
 603                 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 604                 arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
 605
 606                 break;
 607         }
 608
 609         default:
 610                 return -ENOTSUPP;
 611         }
 612
 613         *config = pinconf_to_config_packed(param, arg);
 614         return 0;
 615 }
 616
 617 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
 618                                  unsigned long config)
 619 {
 620         unsigned int param = pinconf_to_config_param(config);
 621         unsigned int arg = pinconf_to_config_argument(config);
 622         const struct intel_community *community;
 623         void __iomem *padcfg1;
 624         unsigned long flags;
 625         int ret = 0;
 626         u32 value;
 627
 628         raw_spin_lock_irqsave(&pctrl->lock, flags);
 629
 630         community = intel_get_community(pctrl, pin);
 631         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 632         value = readl(padcfg1);
 633
 634         switch (param) {
 635         case PIN_CONFIG_BIAS_DISABLE:
 636                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 637                 break;
 638
 639         case PIN_CONFIG_BIAS_PULL_UP:
 640                 value &= ~PADCFG1_TERM_MASK;
 641
 642                 value |= PADCFG1_TERM_UP;
 643
 644                 switch (arg) {
 645                 case 20000:
 646                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 647                         break;
 648                 case 5000:
 649                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 650                         break;
 651                 case 2000:
 652                         value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
 653                         break;
 654                 case 1000:
 655                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 656                         break;
 657                 default:
 658                         ret = -EINVAL;
 659                 }
 660
 661                 break;
 662
 663         case PIN_CONFIG_BIAS_PULL_DOWN:
 664                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 665
 666                 switch (arg) {
 667                 case 20000:
 668                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 669                         break;
 670                 case 5000:
 671                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 672                         break;
 673                 case 1000:
 674                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 675                                 ret = -EINVAL;
 676                                 break;
 677                         }
 678                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 679                         break;
 680                 default:
 681                         ret = -EINVAL;
 682                 }
 683
 684                 break;
 685         }
 686
 687         if (!ret)
 688                 writel(value, padcfg1);
 689
 690         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 691
 692         return ret;
 693 }
 694
 695 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
 696                                      unsigned int pin, unsigned int debounce)
 697 {
 698         void __iomem *padcfg0, *padcfg2;
 699         unsigned long flags;
 700         u32 value0, value2;
 701         int ret = 0;
 702
 703         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 704         if (!padcfg2)
 705                 return -ENOTSUPP;
 706
 707         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 708
 709         raw_spin_lock_irqsave(&pctrl->lock, flags);
 710
 711         value0 = readl(padcfg0);
 712         value2 = readl(padcfg2);
 713
 714         /* Disable glitch filter and debouncer */
 715         value0 &= ~PADCFG0_PREGFRXSEL;
 716         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
 717
 718         if (debounce) {
 719                 unsigned long v;
 720
 721                 v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
 722                 if (v < 3 || v > 15) {
 723                         ret = -EINVAL;
 724                         goto exit_unlock;
 725                 } else {
 726                         /* Enable glitch filter and debouncer */
 727                         value0 |= PADCFG0_PREGFRXSEL;
 728                         value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
 729                         value2 |= PADCFG2_DEBEN;
 730                 }
 731         }
 732
 733         writel(value0, padcfg0);
 734         writel(value2, padcfg2);
 735
 736 exit_unlock:
 737         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 738
 739         return ret;
 740 }
 741
 742 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 743                           unsigned long *configs, unsigned int nconfigs)
 744 {
 745         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 746         int i, ret;
 747
 748         if (!intel_pad_usable(pctrl, pin))
 749                 return -ENOTSUPP;
 750
 751         for (i = 0; i < nconfigs; i++) {
 752                 switch (pinconf_to_config_param(configs[i])) {
 753                 case PIN_CONFIG_BIAS_DISABLE:
 754                 case PIN_CONFIG_BIAS_PULL_UP:
 755                 case PIN_CONFIG_BIAS_PULL_DOWN:
 756                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 757                         if (ret)
 758                                 return ret;
 759                         break;
 760
 761                 case PIN_CONFIG_INPUT_DEBOUNCE:
 762                         ret = intel_config_set_debounce(pctrl, pin,
 763                                 pinconf_to_config_argument(configs[i]));
 764                         if (ret)
 765                                 return ret;
 766                         break;
 767
 768                 default:
 769                         return -ENOTSUPP;
 770                 }
 771         }
 772
 773         return 0;
 774 }
 775
 776 static const struct pinconf_ops intel_pinconf_ops = {
 777         .is_generic = true,
 778         .pin_config_get = intel_config_get,
 779         .pin_config_set = intel_config_set,
 780 };
 781
 782 static const struct pinctrl_desc intel_pinctrl_desc = {
 783         .pctlops = &intel_pinctrl_ops,
 784         .pmxops = &intel_pinmux_ops,
 785         .confops = &intel_pinconf_ops,
 786         .owner = THIS_MODULE,
 787 };
 788
 789 /**
 790  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 791  * @pctrl: Pinctrl structure
 792  * @offset: GPIO offset from gpiolib
 793  * @community: Community is filled here if not %NULL
 794  * @padgrp: Pad group is filled here if not %NULL
 795  *
 796  * When coming through gpiolib irqchip, the GPIO offset is not
 797  * automatically translated to pinctrl pin number. This function can be
 798  * used to find out the corresponding pinctrl pin.
 799  */
 800 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
 801                              const struct intel_community **community,
 802                              const struct intel_padgroup **padgrp)
 803 {
 804         int i;
 805
 806         for (i = 0; i < pctrl->ncommunities; i++) {
 807                 const struct intel_community *comm = &pctrl->communities[i];
 808                 int j;
 809
 810                 for (j = 0; j < comm->ngpps; j++) {
 811                         const struct intel_padgroup *pgrp = &comm->gpps[j];
 812
 813                         if (pgrp->gpio_base < 0)
 814                                 continue;
 815
 816                         if (offset >= pgrp->gpio_base &&
 817                             offset < pgrp->gpio_base + pgrp->size) {
 818                                 int pin;
 819
 820                                 pin = pgrp->base + offset - pgrp->gpio_base;
 821                                 if (community)
 822                                         *community = comm;
 823                                 if (padgrp)
 824                                         *padgrp = pgrp;
 825
 826                                 return pin;
 827                         }
 828                 }
 829         }
 830
 831         return -EINVAL;
 832 }
 833
 834 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
 835 {
 836         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 837         void __iomem *reg;
 838         u32 padcfg0;
 839         int pin;
 840
 841         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 842         if (pin < 0)
 843                 return -EINVAL;
 844
 845         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 846         if (!reg)
 847                 return -EINVAL;
 848
 849         padcfg0 = readl(reg);
 850         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
 851                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
 852
 853         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 854 }
 855
 856 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
 857                            int value)
 858 {
 859         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 860         unsigned long flags;
 861         void __iomem *reg;
 862         u32 padcfg0;
 863         int pin;
 864
 865         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 866         if (pin < 0)
 867                 return;
 868
 869         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 870         if (!reg)
 871                 return;
 872
 873         raw_spin_lock_irqsave(&pctrl->lock, flags);
 874         padcfg0 = readl(reg);
 875         if (value)
 876                 padcfg0 |= PADCFG0_GPIOTXSTATE;
 877         else
 878                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 879         writel(padcfg0, reg);
 880         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 881 }
 882
 883 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 884 {
 885         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 886         void __iomem *reg;
 887         u32 padcfg0;
 888         int pin;
 889
 890         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 891         if (pin < 0)
 892                 return -EINVAL;
 893
 894         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 895         if (!reg)
 896                 return -EINVAL;
 897
 898         padcfg0 = readl(reg);
 899
 900         if (padcfg0 & PADCFG0_PMODE_MASK)
 901                 return -EINVAL;
 902
 903         return !!(padcfg0 & PADCFG0_GPIOTXDIS);
 904 }
 905
 906 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 907 {
 908         return pinctrl_gpio_direction_input(chip->base + offset);
 909 }
 910
 911 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
 912                                        int value)
 913 {
 914         intel_gpio_set(chip, offset, value);
 915         return pinctrl_gpio_direction_output(chip->base + offset);
 916 }
 917
 918 static const struct gpio_chip intel_gpio_chip = {
 919         .owner = THIS_MODULE,
 920         .request = gpiochip_generic_request,
 921         .free = gpiochip_generic_free,
 922         .get_direction = intel_gpio_get_direction,
 923         .direction_input = intel_gpio_direction_input,
 924         .direction_output = intel_gpio_direction_output,
 925         .get = intel_gpio_get,
 926         .set = intel_gpio_set,
 927         .set_config = gpiochip_generic_config,
 928 };
 929
 930 static void intel_gpio_irq_ack(struct irq_data *d)
 931 {
 932         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 933         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 934         const struct intel_community *community;
 935         const struct intel_padgroup *padgrp;
 936         int pin;
 937
 938         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 939         if (pin >= 0) {
 940                 unsigned int gpp, gpp_offset, is_offset;
 941
 942                 gpp = padgrp->reg_num;
 943                 gpp_offset = padgroup_offset(padgrp, pin);
 944                 is_offset = community->is_offset + gpp * 4;
 945
 946                 raw_spin_lock(&pctrl->lock);
 947                 writel(BIT(gpp_offset), community->regs + is_offset);
 948                 raw_spin_unlock(&pctrl->lock);
 949         }
 950 }
 951
 952 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
 953 {
 954         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 955         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 956         const struct intel_community *community;
 957         const struct intel_padgroup *padgrp;
 958         int pin;
 959
 960         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 961         if (pin >= 0) {
 962                 unsigned int gpp, gpp_offset;
 963                 unsigned long flags;
 964                 void __iomem *reg, *is;
 965                 u32 value;
 966
 967                 gpp = padgrp->reg_num;
 968                 gpp_offset = padgroup_offset(padgrp, pin);
 969
 970                 reg = community->regs + community->ie_offset + gpp * 4;
 971                 is = community->regs + community->is_offset + gpp * 4;
 972
 973                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 974
 975                 /* Clear interrupt status first to avoid unexpected interrupt */
 976                 writel(BIT(gpp_offset), is);
 977
 978                 value = readl(reg);
 979                 if (mask)
 980                         value &= ~BIT(gpp_offset);
 981                 else
 982                         value |= BIT(gpp_offset);
 983                 writel(value, reg);
 984                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 985         }
 986 }
 987
 988 static void intel_gpio_irq_mask(struct irq_data *d)
 989 {
 990         intel_gpio_irq_mask_unmask(d, true);
 991 }
 992
 993 static void intel_gpio_irq_unmask(struct irq_data *d)
 994 {
 995         intel_gpio_irq_mask_unmask(d, false);
 996 }
 997
 998 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
 999 {
1000         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1001         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1002         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1003         unsigned long flags;
1004         void __iomem *reg;
1005         u32 value;
1006
1007         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1008         if (!reg)
1009                 return -EINVAL;
1010
1011         /*
1012          * If the pin is in ACPI mode it is still usable as a GPIO but it
1013          * cannot be used as IRQ because GPI_IS status bit will not be
1014          * updated by the host controller hardware.
1015          */
1016         if (intel_pad_acpi_mode(pctrl, pin)) {
1017                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1018                 return -EPERM;
1019         }
1020
1021         raw_spin_lock_irqsave(&pctrl->lock, flags);
1022
1023         intel_gpio_set_gpio_mode(reg);
1024
1025         value = readl(reg);
1026
1027         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1028
1029         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1030                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1031         } else if (type & IRQ_TYPE_EDGE_FALLING) {
1032                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1033                 value |= PADCFG0_RXINV;
1034         } else if (type & IRQ_TYPE_EDGE_RISING) {
1035                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1036         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1037                 if (type & IRQ_TYPE_LEVEL_LOW)
1038                         value |= PADCFG0_RXINV;
1039         } else {
1040                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1041         }
1042
1043         writel(value, reg);
1044
1045         if (type & IRQ_TYPE_EDGE_BOTH)
1046                 irq_set_handler_locked(d, handle_edge_irq);
1047         else if (type & IRQ_TYPE_LEVEL_MASK)
1048                 irq_set_handler_locked(d, handle_level_irq);
1049
1050         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1051
1052         return 0;
1053 }
1054
1055 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1056 {
1057         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1058         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1059         unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1060
1061         if (on)
1062                 enable_irq_wake(pctrl->irq);
1063         else
1064                 disable_irq_wake(pctrl->irq);
1065
1066         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1067         return 0;
1068 }
1069
1070 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1071         const struct intel_community *community)
1072 {
1073         struct gpio_chip *gc = &pctrl->chip;
1074         irqreturn_t ret = IRQ_NONE;
1075         int gpp;
1076
1077         for (gpp = 0; gpp < community->ngpps; gpp++) {
1078                 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1079                 unsigned long pending, enabled, gpp_offset;
1080
1081                 pending = readl(community->regs + community->is_offset +
1082                                 padgrp->reg_num * 4);
1083                 enabled = readl(community->regs + community->ie_offset +
1084                                 padgrp->reg_num * 4);
1085
1086                 /* Only interrupts that are enabled */
1087                 pending &= enabled;
1088
1089                 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1090                         unsigned irq;
1091
1092                         irq = irq_find_mapping(gc->irq.domain,
1093                                                padgrp->gpio_base + gpp_offset);
1094                         generic_handle_irq(irq);
1095
1096                         ret |= IRQ_HANDLED;
1097                 }
1098         }
1099
1100         return ret;
1101 }
1102
1103 static irqreturn_t intel_gpio_irq(int irq, void *data)
1104 {
1105         const struct intel_community *community;
1106         struct intel_pinctrl *pctrl = data;
1107         irqreturn_t ret = IRQ_NONE;
1108         int i;
1109
1110         /* Need to check all communities for pending interrupts */
1111         for (i = 0; i < pctrl->ncommunities; i++) {
1112                 community = &pctrl->communities[i];
1113                 ret |= intel_gpio_community_irq_handler(pctrl, community);
1114         }
1115
1116         return ret;
1117 }
1118
1119 static struct irq_chip intel_gpio_irqchip = {
1120         .name = "intel-gpio",
1121         .irq_ack = intel_gpio_irq_ack,
1122         .irq_mask = intel_gpio_irq_mask,
1123         .irq_unmask = intel_gpio_irq_unmask,
1124         .irq_set_type = intel_gpio_irq_type,
1125         .irq_set_wake = intel_gpio_irq_wake,
1126         .flags = IRQCHIP_MASK_ON_SUSPEND,
1127 };
1128
1129 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1130                                      const struct intel_community *community)
1131 {
1132         int ret = 0, i;
1133
1134         for (i = 0; i < community->ngpps; i++) {
1135                 const struct intel_padgroup *gpp = &community->gpps[i];
1136
1137                 if (gpp->gpio_base < 0)
1138                         continue;
1139
1140                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1141                                              gpp->gpio_base, gpp->base,
1142                                              gpp->size);
1143                 if (ret)
1144                         return ret;
1145         }
1146
1147         return ret;
1148 }
1149
1150 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1151 {
1152         const struct intel_community *community;
1153         unsigned int ngpio = 0;
1154         int i, j;
1155
1156         for (i = 0; i < pctrl->ncommunities; i++) {
1157                 community = &pctrl->communities[i];
1158                 for (j = 0; j < community->ngpps; j++) {
1159                         const struct intel_padgroup *gpp = &community->gpps[j];
1160
1161                         if (gpp->gpio_base < 0)
1162                                 continue;
1163
1164                         if (gpp->gpio_base + gpp->size > ngpio)
1165                                 ngpio = gpp->gpio_base + gpp->size;
1166                 }
1167         }
1168
1169         return ngpio;
1170 }
1171
1172 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1173 {
1174         int ret, i;
1175
1176         pctrl->chip = intel_gpio_chip;
1177
1178         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1179         pctrl->chip.label = dev_name(pctrl->dev);
1180         pctrl->chip.parent = pctrl->dev;
1181         pctrl->chip.base = -1;
1182         pctrl->irq = irq;
1183
1184         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1185         if (ret) {
1186                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1187                 return ret;
1188         }
1189
1190         for (i = 0; i < pctrl->ncommunities; i++) {
1191                 struct intel_community *community = &pctrl->communities[i];
1192
1193                 ret = intel_gpio_add_pin_ranges(pctrl, community);
1194                 if (ret) {
1195                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1196                         return ret;
1197                 }
1198         }
1199
1200         /*
1201          * We need to request the interrupt here (instead of providing chip
1202          * to the irq directly) because on some platforms several GPIO
1203          * controllers share the same interrupt line.
1204          */
1205         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1206                                IRQF_SHARED | IRQF_NO_THREAD,
1207                                dev_name(pctrl->dev), pctrl);
1208         if (ret) {
1209                 dev_err(pctrl->dev, "failed to request interrupt\n");
1210                 return ret;
1211         }
1212
1213         ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1214                                    handle_bad_irq, IRQ_TYPE_NONE);
1215         if (ret) {
1216                 dev_err(pctrl->dev, "failed to add irqchip\n");
1217                 return ret;
1218         }
1219
1220         gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1221                                      NULL);
1222         return 0;
1223 }
1224
1225 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1226                                        struct intel_community *community)
1227 {
1228         struct intel_padgroup *gpps;
1229         unsigned int npins = community->npins;
1230         unsigned int padown_num = 0;
1231         size_t ngpps, i;
1232
1233         if (community->gpps)
1234                 ngpps = community->ngpps;
1235         else
1236                 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1237
1238         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1239         if (!gpps)
1240                 return -ENOMEM;
1241
1242         for (i = 0; i < ngpps; i++) {
1243                 if (community->gpps) {
1244                         gpps[i] = community->gpps[i];
1245                 } else {
1246                         unsigned int gpp_size = community->gpp_size;
1247
1248                         gpps[i].reg_num = i;
1249                         gpps[i].base = community->pin_base + i * gpp_size;
1250                         gpps[i].size = min(gpp_size, npins);
1251                         npins -= gpps[i].size;
1252                 }
1253
1254                 if (gpps[i].size > 32)
1255                         return -EINVAL;
1256
1257                 if (!gpps[i].gpio_base)
1258                         gpps[i].gpio_base = gpps[i].base;
1259
1260                 gpps[i].padown_num = padown_num;
1261
1262                 /*
1263                  * In older hardware the number of padown registers per
1264                  * group is fixed regardless of the group size.
1265                  */
1266                 if (community->gpp_num_padown_regs)
1267                         padown_num += community->gpp_num_padown_regs;
1268                 else
1269                         padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1270         }
1271
1272         community->ngpps = ngpps;
1273         community->gpps = gpps;
1274
1275         return 0;
1276 }
1277
1278 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1279 {
1280 #ifdef CONFIG_PM_SLEEP
1281         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1282         struct intel_community_context *communities;
1283         struct intel_pad_context *pads;
1284         int i;
1285
1286         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1287         if (!pads)
1288                 return -ENOMEM;
1289
1290         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1291                                    sizeof(*communities), GFP_KERNEL);
1292         if (!communities)
1293                 return -ENOMEM;
1294
1295
1296         for (i = 0; i < pctrl->ncommunities; i++) {
1297                 struct intel_community *community = &pctrl->communities[i];
1298                 u32 *intmask, *hostown;
1299
1300                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1301                                        sizeof(*intmask), GFP_KERNEL);
1302                 if (!intmask)
1303                         return -ENOMEM;
1304
1305                 communities[i].intmask = intmask;
1306
1307                 hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1308                                        sizeof(*hostown), GFP_KERNEL);
1309                 if (!hostown)
1310                         return -ENOMEM;
1311
1312                 communities[i].hostown = hostown;
1313         }
1314
1315         pctrl->context.pads = pads;
1316         pctrl->context.communities = communities;
1317 #endif
1318
1319         return 0;
1320 }
1321
1322 static int intel_pinctrl_probe(struct platform_device *pdev,
1323                                const struct intel_pinctrl_soc_data *soc_data)
1324 {
1325         struct intel_pinctrl *pctrl;
1326         int i, ret, irq;
1327
1328         if (!soc_data)
1329                 return -EINVAL;
1330
1331         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1332         if (!pctrl)
1333                 return -ENOMEM;
1334
1335         pctrl->dev = &pdev->dev;
1336         pctrl->soc = soc_data;
1337         raw_spin_lock_init(&pctrl->lock);
1338
1339         /*
1340          * Make a copy of the communities which we can use to hold pointers
1341          * to the registers.
1342          */
1343         pctrl->ncommunities = pctrl->soc->ncommunities;
1344         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1345                                   sizeof(*pctrl->communities), GFP_KERNEL);
1346         if (!pctrl->communities)
1347                 return -ENOMEM;
1348
1349         for (i = 0; i < pctrl->ncommunities; i++) {
1350                 struct intel_community *community = &pctrl->communities[i];
1351                 void __iomem *regs;
1352                 u32 padbar;
1353
1354                 *community = pctrl->soc->communities[i];
1355
1356                 regs = devm_platform_ioremap_resource(pdev, community->barno);
1357                 if (IS_ERR(regs))
1358                         return PTR_ERR(regs);
1359
1360                 /*
1361                  * Determine community features based on the revision if
1362                  * not specified already.
1363                  */
1364                 if (!community->features) {
1365                         u32 rev;
1366
1367                         rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1368                         if (rev >= 0x94) {
1369                                 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1370                                 community->features |= PINCTRL_FEATURE_1K_PD;
1371                         }
1372                 }
1373
1374                 /* Read offset of the pad configuration registers */
1375                 padbar = readl(regs + PADBAR);
1376
1377                 community->regs = regs;
1378                 community->pad_regs = regs + padbar;
1379
1380                 ret = intel_pinctrl_add_padgroups(pctrl, community);
1381                 if (ret)
1382                         return ret;
1383         }
1384
1385         irq = platform_get_irq(pdev, 0);
1386         if (irq < 0)
1387                 return irq;
1388
1389         ret = intel_pinctrl_pm_init(pctrl);
1390         if (ret)
1391                 return ret;
1392
1393         pctrl->pctldesc = intel_pinctrl_desc;
1394         pctrl->pctldesc.name = dev_name(&pdev->dev);
1395         pctrl->pctldesc.pins = pctrl->soc->pins;
1396         pctrl->pctldesc.npins = pctrl->soc->npins;
1397
1398         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1399                                                pctrl);
1400         if (IS_ERR(pctrl->pctldev)) {
1401                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1402                 return PTR_ERR(pctrl->pctldev);
1403         }
1404
1405         ret = intel_gpio_probe(pctrl, irq);
1406         if (ret)
1407                 return ret;
1408
1409         platform_set_drvdata(pdev, pctrl);
1410
1411         return 0;
1412 }
1413
1414 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1415 {
1416         const struct intel_pinctrl_soc_data *data;
1417
1418         data = device_get_match_data(&pdev->dev);
1419         return intel_pinctrl_probe(pdev, data);
1420 }
1421 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
1422
1423 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1424 {
1425         const struct intel_pinctrl_soc_data *data = NULL;
1426         const struct intel_pinctrl_soc_data **table;
1427         struct acpi_device *adev;
1428         unsigned int i;
1429
1430         adev = ACPI_COMPANION(&pdev->dev);
1431         if (adev) {
1432                 const void *match = device_get_match_data(&pdev->dev);
1433
1434                 table = (const struct intel_pinctrl_soc_data **)match;
1435                 for (i = 0; table[i]; i++) {
1436                         if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
1437                                 data = table[i];
1438                                 break;
1439                         }
1440                 }
1441         } else {
1442                 const struct platform_device_id *id;
1443
1444                 id = platform_get_device_id(pdev);
1445                 if (!id)
1446                         return -ENODEV;
1447
1448                 table = (const struct intel_pinctrl_soc_data **)id->driver_data;
1449                 data = table[pdev->id];
1450         }
1451
1452         return intel_pinctrl_probe(pdev, data);
1453 }
1454 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
1455
1456 #ifdef CONFIG_PM_SLEEP
1457 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1458 {
1459         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1460
1461         if (!pd || !intel_pad_usable(pctrl, pin))
1462                 return false;
1463
1464         /*
1465          * Only restore the pin if it is actually in use by the kernel (or
1466          * by userspace). It is possible that some pins are used by the
1467          * BIOS during resume and those are not always locked down so leave
1468          * them alone.
1469          */
1470         if (pd->mux_owner || pd->gpio_owner ||
1471             gpiochip_line_is_irq(&pctrl->chip, pin))
1472                 return true;
1473
1474         return false;
1475 }
1476
1477 int intel_pinctrl_suspend_noirq(struct device *dev)
1478 {
1479         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1480         struct intel_community_context *communities;
1481         struct intel_pad_context *pads;
1482         int i;
1483
1484         pads = pctrl->context.pads;
1485         for (i = 0; i < pctrl->soc->npins; i++) {
1486                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1487                 void __iomem *padcfg;
1488                 u32 val;
1489
1490                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1491                         continue;
1492
1493                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1494                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1495                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1496                 pads[i].padcfg1 = val;
1497
1498                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1499                 if (padcfg)
1500                         pads[i].padcfg2 = readl(padcfg);
1501         }
1502
1503         communities = pctrl->context.communities;
1504         for (i = 0; i < pctrl->ncommunities; i++) {
1505                 struct intel_community *community = &pctrl->communities[i];
1506                 void __iomem *base;
1507                 unsigned int gpp;
1508
1509                 base = community->regs + community->ie_offset;
1510                 for (gpp = 0; gpp < community->ngpps; gpp++)
1511                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1512
1513                 base = community->regs + community->hostown_offset;
1514                 for (gpp = 0; gpp < community->ngpps; gpp++)
1515                         communities[i].hostown[gpp] = readl(base + gpp * 4);
1516         }
1517
1518         return 0;
1519 }
1520 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1521
1522 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1523 {
1524         size_t i;
1525
1526         for (i = 0; i < pctrl->ncommunities; i++) {
1527                 const struct intel_community *community;
1528                 void __iomem *base;
1529                 unsigned int gpp;
1530
1531                 community = &pctrl->communities[i];
1532                 base = community->regs;
1533
1534                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1535                         /* Mask and clear all interrupts */
1536                         writel(0, base + community->ie_offset + gpp * 4);
1537                         writel(0xffff, base + community->is_offset + gpp * 4);
1538                 }
1539         }
1540 }
1541
1542 static u32
1543 intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size)
1544 {
1545         u32 requested = 0;
1546         unsigned int i;
1547
1548         for (i = 0; i < size; i++)
1549                 if (gpiochip_is_requested(chip, base + i))
1550                         requested |= BIT(i);
1551
1552         return requested;
1553 }
1554
1555 static u32
1556 intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value)
1557 {
1558         u32 curr, updated;
1559
1560         curr = readl(hostown);
1561         updated = (curr & ~mask) | (value & mask);
1562         writel(updated, hostown);
1563
1564         return curr;
1565 }
1566
1567 int intel_pinctrl_resume_noirq(struct device *dev)
1568 {
1569         struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1570         const struct intel_community_context *communities;
1571         const struct intel_pad_context *pads;
1572         int i;
1573
1574         /* Mask all interrupts */
1575         intel_gpio_irq_init(pctrl);
1576
1577         pads = pctrl->context.pads;
1578         for (i = 0; i < pctrl->soc->npins; i++) {
1579                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1580                 void __iomem *padcfg;
1581                 u32 val;
1582
1583                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1584                         continue;
1585
1586                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1587                 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1588                 if (val != pads[i].padcfg0) {
1589                         writel(pads[i].padcfg0, padcfg);
1590                         dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1591                                 desc->number, readl(padcfg));
1592                 }
1593
1594                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1595                 val = readl(padcfg);
1596                 if (val != pads[i].padcfg1) {
1597                         writel(pads[i].padcfg1, padcfg);
1598                         dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1599                                 desc->number, readl(padcfg));
1600                 }
1601
1602                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1603                 if (padcfg) {
1604                         val = readl(padcfg);
1605                         if (val != pads[i].padcfg2) {
1606                                 writel(pads[i].padcfg2, padcfg);
1607                                 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1608                                         desc->number, readl(padcfg));
1609                         }
1610                 }
1611         }
1612
1613         communities = pctrl->context.communities;
1614         for (i = 0; i < pctrl->ncommunities; i++) {
1615                 struct intel_community *community = &pctrl->communities[i];
1616                 void __iomem *base;
1617                 unsigned int gpp;
1618
1619                 base = community->regs + community->ie_offset;
1620                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1621                         writel(communities[i].intmask[gpp], base + gpp * 4);
1622                         dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1623                                 readl(base + gpp * 4));
1624                 }
1625
1626                 base = community->regs + community->hostown_offset;
1627                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1628                         const struct intel_padgroup *padgrp = &community->gpps[gpp];
1629                         u32 requested = 0, value = 0;
1630                         u32 saved = communities[i].hostown[gpp];
1631
1632                         if (padgrp->gpio_base < 0)
1633                                 continue;
1634
1635                         requested = intel_gpio_is_requested(&pctrl->chip,
1636                                         padgrp->gpio_base, padgrp->size);
1637                         value = intel_gpio_update_pad_mode(base + gpp * 4,
1638                                         requested, saved);
1639                         if ((value ^ saved) & requested) {
1640                                 dev_warn(dev, "restore hostown %d/%u %#8x->%#8x\n",
1641                                         i, gpp, value, saved);
1642                         }
1643                 }
1644         }
1645
1646         return 0;
1647 }
1648 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1649 #endif
1650
1651 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1652 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1653 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1654 MODULE_LICENSE("GPL v2");