drivers/pinctrl/intel/pinctrl-cherryview.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Cherryview/Braswell pinctrl driver
   4  *
   5  * Copyright (C) 2014, 2020 Intel Corporation
   6  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   7  *
   8  * This driver is based on the original Cherryview GPIO driver by
   9  *   Ning Li <ning.li@intel.com>
  10  *   Alan Cox <alan@linux.intel.com>
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/dmi.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/types.h>
  20
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25
  26 #include "pinctrl-intel.h"
  27
  28 #define CHV_INTSTAT                     0x300
  29 #define CHV_INTMASK                     0x380
  30
  31 #define FAMILY_PAD_REGS_OFF             0x4400
  32 #define FAMILY_PAD_REGS_SIZE            0x400
  33 #define MAX_FAMILY_PAD_GPIO_NO          15
  34 #define GPIO_REGS_SIZE                  8
  35
  36 #define CHV_PADCTRL0                    0x000
  37 #define CHV_PADCTRL0_INTSEL_SHIFT       28
  38 #define CHV_PADCTRL0_INTSEL_MASK        GENMASK(31, 28)
  39 #define CHV_PADCTRL0_TERM_UP            BIT(23)
  40 #define CHV_PADCTRL0_TERM_SHIFT         20
  41 #define CHV_PADCTRL0_TERM_MASK          GENMASK(22, 20)
  42 #define CHV_PADCTRL0_TERM_20K           1
  43 #define CHV_PADCTRL0_TERM_5K            2
  44 #define CHV_PADCTRL0_TERM_1K            4
  45 #define CHV_PADCTRL0_PMODE_SHIFT        16
  46 #define CHV_PADCTRL0_PMODE_MASK         GENMASK(19, 16)
  47 #define CHV_PADCTRL0_GPIOEN             BIT(15)
  48 #define CHV_PADCTRL0_GPIOCFG_SHIFT      8
  49 #define CHV_PADCTRL0_GPIOCFG_MASK       GENMASK(10, 8)
  50 #define CHV_PADCTRL0_GPIOCFG_GPIO       0
  51 #define CHV_PADCTRL0_GPIOCFG_GPO        1
  52 #define CHV_PADCTRL0_GPIOCFG_GPI        2
  53 #define CHV_PADCTRL0_GPIOCFG_HIZ        3
  54 #define CHV_PADCTRL0_GPIOTXSTATE        BIT(1)
  55 #define CHV_PADCTRL0_GPIORXSTATE        BIT(0)
  56
  57 #define CHV_PADCTRL1                    0x004
  58 #define CHV_PADCTRL1_CFGLOCK            BIT(31)
  59 #define CHV_PADCTRL1_INVRXTX_SHIFT      4
  60 #define CHV_PADCTRL1_INVRXTX_MASK       GENMASK(7, 4)
  61 #define CHV_PADCTRL1_INVRXTX_RXDATA     BIT(6)
  62 #define CHV_PADCTRL1_INVRXTX_TXENABLE   BIT(5)
  63 #define CHV_PADCTRL1_ODEN               BIT(3)
  64 #define CHV_PADCTRL1_INTWAKECFG_MASK    GENMASK(2, 0)
  65 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
  66 #define CHV_PADCTRL1_INTWAKECFG_RISING  2
  67 #define CHV_PADCTRL1_INTWAKECFG_BOTH    3
  68 #define CHV_PADCTRL1_INTWAKECFG_LEVEL   4
  69
  70 struct intel_pad_context {
  71         u32 padctrl0;
  72         u32 padctrl1;
  73 };
  74
  75 /**
  76  * struct chv_pinctrl - CHV pinctrl private structure
  77  * @dev: Pointer to the parent device
  78  * @pctldesc: Pin controller description
  79  * @pctldev: Pointer to the pin controller device
  80  * @chip: GPIO chip in this pin controller
  81  * @irqchip: IRQ chip in this pin controller
  82  * @soc: Community specific pin configuration data
  83  * @communities: All communities in this pin controller
  84  * @ncommunities: Number of communities in this pin controller
  85  * @context: Configuration saved over system sleep
  86  * @irq: Our parent irq
  87  * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
  88  * @saved_intmask: Interrupt mask saved for system sleep
  89  *
  90  * The first group in @groups is expected to contain all pins that can be
  91  * used as GPIOs.
  92  */
  93 struct chv_pinctrl {
  94         struct device *dev;
  95         struct pinctrl_desc pctldesc;
  96         struct pinctrl_dev *pctldev;
  97         struct gpio_chip chip;
  98         struct irq_chip irqchip;
  99         const struct intel_pinctrl_soc_data *soc;
 100         struct intel_community *communities;
 101         size_t ncommunities;
 102         struct intel_pinctrl_context context;
 103         int irq;
 104
 105         unsigned int intr_lines[16];
 106         u32 saved_intmask;
 107 };
 108
 109 #define PINMODE_INVERT_OE       BIT(15)
 110
 111 #define PINMODE(m, i)           ((m) | ((i) * PINMODE_INVERT_OE))
 112
 113 #define CHV_GPP(start, end)                     \
 114         {                                       \
 115                 .base = (start),                \
 116                 .size = (end) - (start) + 1,    \
 117         }
 118
 119 #define CHV_COMMUNITY(g, i, a)                  \
 120         {                                       \
 121                 .gpps = (g),                    \
 122                 .ngpps = ARRAY_SIZE(g),         \
 123                 .nirqs = (i),                   \
 124                 .acpi_space_id = (a),           \
 125         }
 126
 127 static const struct pinctrl_pin_desc southwest_pins[] = {
 128         PINCTRL_PIN(0, "FST_SPI_D2"),
 129         PINCTRL_PIN(1, "FST_SPI_D0"),
 130         PINCTRL_PIN(2, "FST_SPI_CLK"),
 131         PINCTRL_PIN(3, "FST_SPI_D3"),
 132         PINCTRL_PIN(4, "FST_SPI_CS1_B"),
 133         PINCTRL_PIN(5, "FST_SPI_D1"),
 134         PINCTRL_PIN(6, "FST_SPI_CS0_B"),
 135         PINCTRL_PIN(7, "FST_SPI_CS2_B"),
 136
 137         PINCTRL_PIN(15, "UART1_RTS_B"),
 138         PINCTRL_PIN(16, "UART1_RXD"),
 139         PINCTRL_PIN(17, "UART2_RXD"),
 140         PINCTRL_PIN(18, "UART1_CTS_B"),
 141         PINCTRL_PIN(19, "UART2_RTS_B"),
 142         PINCTRL_PIN(20, "UART1_TXD"),
 143         PINCTRL_PIN(21, "UART2_TXD"),
 144         PINCTRL_PIN(22, "UART2_CTS_B"),
 145
 146         PINCTRL_PIN(30, "MF_HDA_CLK"),
 147         PINCTRL_PIN(31, "MF_HDA_RSTB"),
 148         PINCTRL_PIN(32, "MF_HDA_SDIO"),
 149         PINCTRL_PIN(33, "MF_HDA_SDO"),
 150         PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
 151         PINCTRL_PIN(35, "MF_HDA_SYNC"),
 152         PINCTRL_PIN(36, "MF_HDA_SDI1"),
 153         PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
 154
 155         PINCTRL_PIN(45, "I2C5_SDA"),
 156         PINCTRL_PIN(46, "I2C4_SDA"),
 157         PINCTRL_PIN(47, "I2C6_SDA"),
 158         PINCTRL_PIN(48, "I2C5_SCL"),
 159         PINCTRL_PIN(49, "I2C_NFC_SDA"),
 160         PINCTRL_PIN(50, "I2C4_SCL"),
 161         PINCTRL_PIN(51, "I2C6_SCL"),
 162         PINCTRL_PIN(52, "I2C_NFC_SCL"),
 163
 164         PINCTRL_PIN(60, "I2C1_SDA"),
 165         PINCTRL_PIN(61, "I2C0_SDA"),
 166         PINCTRL_PIN(62, "I2C2_SDA"),
 167         PINCTRL_PIN(63, "I2C1_SCL"),
 168         PINCTRL_PIN(64, "I2C3_SDA"),
 169         PINCTRL_PIN(65, "I2C0_SCL"),
 170         PINCTRL_PIN(66, "I2C2_SCL"),
 171         PINCTRL_PIN(67, "I2C3_SCL"),
 172
 173         PINCTRL_PIN(75, "SATA_GP0"),
 174         PINCTRL_PIN(76, "SATA_GP1"),
 175         PINCTRL_PIN(77, "SATA_LEDN"),
 176         PINCTRL_PIN(78, "SATA_GP2"),
 177         PINCTRL_PIN(79, "MF_SMB_ALERTB"),
 178         PINCTRL_PIN(80, "SATA_GP3"),
 179         PINCTRL_PIN(81, "MF_SMB_CLK"),
 180         PINCTRL_PIN(82, "MF_SMB_DATA"),
 181
 182         PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
 183         PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
 184         PINCTRL_PIN(92, "GP_SSP_2_CLK"),
 185         PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
 186         PINCTRL_PIN(94, "GP_SSP_2_RXD"),
 187         PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
 188         PINCTRL_PIN(96, "GP_SSP_2_FS"),
 189         PINCTRL_PIN(97, "GP_SSP_2_TXD"),
 190 };
 191
 192 static const unsigned southwest_uart0_pins[] = { 16, 20 };
 193 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
 194 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
 195 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
 196 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
 197 static const unsigned southwest_lpe_pins[] = {
 198         30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
 199 };
 200 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
 201 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
 202 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
 203 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
 204 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
 205 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
 206 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
 207 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
 208
 209 /* Some of LPE I2S TXD pins need to have OE inversion set */
 210 static const unsigned int southwest_lpe_altfuncs[] = {
 211         PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */
 212         PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */
 213         PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */
 214 };
 215
 216 /*
 217  * Two spi3 chipselects are available in different mode than the main spi3
 218  * functionality, which is using mode 2.
 219  */
 220 static const unsigned int southwest_spi3_altfuncs[] = {
 221         PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */
 222         PINMODE(2, 0),                                              /* 82 */
 223 };
 224
 225 static const struct intel_pingroup southwest_groups[] = {
 226         PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)),
 227         PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)),
 228         PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)),
 229         PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)),
 230         PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)),
 231         PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)),
 232         PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)),
 233         PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)),
 234         PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)),
 235         PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)),
 236         PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)),
 237         PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)),
 238         PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs),
 239         PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs),
 240 };
 241
 242 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
 243 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
 244 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
 245 static const char * const southwest_hda_groups[] = { "hda_grp" };
 246 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
 247 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
 248 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
 249 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
 250 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
 251 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
 252 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
 253 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
 254 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
 255 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
 256
 257 /*
 258  * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
 259  * enabled only as GPIOs.
 260  */
 261 static const struct intel_function southwest_functions[] = {
 262         FUNCTION("uart0", southwest_uart0_groups),
 263         FUNCTION("uart1", southwest_uart1_groups),
 264         FUNCTION("uart2", southwest_uart2_groups),
 265         FUNCTION("hda", southwest_hda_groups),
 266         FUNCTION("lpe", southwest_lpe_groups),
 267         FUNCTION("i2c0", southwest_i2c0_groups),
 268         FUNCTION("i2c1", southwest_i2c1_groups),
 269         FUNCTION("i2c2", southwest_i2c2_groups),
 270         FUNCTION("i2c3", southwest_i2c3_groups),
 271         FUNCTION("i2c4", southwest_i2c4_groups),
 272         FUNCTION("i2c5", southwest_i2c5_groups),
 273         FUNCTION("i2c6", southwest_i2c6_groups),
 274         FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
 275         FUNCTION("spi3", southwest_spi3_groups),
 276 };
 277
 278 static const struct intel_padgroup southwest_gpps[] = {
 279         CHV_GPP(0, 7),
 280         CHV_GPP(15, 22),
 281         CHV_GPP(30, 37),
 282         CHV_GPP(45, 52),
 283         CHV_GPP(60, 67),
 284         CHV_GPP(75, 82),
 285         CHV_GPP(90, 97),
 286 };
 287
 288 /*
 289  * Southwest community can generate GPIO interrupts only for the first 8
 290  * interrupts. The upper half (8-15) can only be used to trigger GPEs.
 291  */
 292 static const struct intel_community southwest_communities[] = {
 293         CHV_COMMUNITY(southwest_gpps, 8, 0x91),
 294 };
 295
 296 static const struct intel_pinctrl_soc_data southwest_soc_data = {
 297         .uid = "1",
 298         .pins = southwest_pins,
 299         .npins = ARRAY_SIZE(southwest_pins),
 300         .groups = southwest_groups,
 301         .ngroups = ARRAY_SIZE(southwest_groups),
 302         .functions = southwest_functions,
 303         .nfunctions = ARRAY_SIZE(southwest_functions),
 304         .communities = southwest_communities,
 305         .ncommunities = ARRAY_SIZE(southwest_communities),
 306 };
 307
 308 static const struct pinctrl_pin_desc north_pins[] = {
 309         PINCTRL_PIN(0, "GPIO_DFX_0"),
 310         PINCTRL_PIN(1, "GPIO_DFX_3"),
 311         PINCTRL_PIN(2, "GPIO_DFX_7"),
 312         PINCTRL_PIN(3, "GPIO_DFX_1"),
 313         PINCTRL_PIN(4, "GPIO_DFX_5"),
 314         PINCTRL_PIN(5, "GPIO_DFX_4"),
 315         PINCTRL_PIN(6, "GPIO_DFX_8"),
 316         PINCTRL_PIN(7, "GPIO_DFX_2"),
 317         PINCTRL_PIN(8, "GPIO_DFX_6"),
 318
 319         PINCTRL_PIN(15, "GPIO_SUS0"),
 320         PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
 321         PINCTRL_PIN(17, "GPIO_SUS3"),
 322         PINCTRL_PIN(18, "GPIO_SUS7"),
 323         PINCTRL_PIN(19, "GPIO_SUS1"),
 324         PINCTRL_PIN(20, "GPIO_SUS5"),
 325         PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
 326         PINCTRL_PIN(22, "GPIO_SUS4"),
 327         PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
 328         PINCTRL_PIN(24, "GPIO_SUS2"),
 329         PINCTRL_PIN(25, "GPIO_SUS6"),
 330         PINCTRL_PIN(26, "CX_PREQ_B"),
 331         PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
 332
 333         PINCTRL_PIN(30, "TRST_B"),
 334         PINCTRL_PIN(31, "TCK"),
 335         PINCTRL_PIN(32, "PROCHOT_B"),
 336         PINCTRL_PIN(33, "SVIDO_DATA"),
 337         PINCTRL_PIN(34, "TMS"),
 338         PINCTRL_PIN(35, "CX_PRDY_B_2"),
 339         PINCTRL_PIN(36, "TDO_2"),
 340         PINCTRL_PIN(37, "CX_PRDY_B"),
 341         PINCTRL_PIN(38, "SVIDO_ALERT_B"),
 342         PINCTRL_PIN(39, "TDO"),
 343         PINCTRL_PIN(40, "SVIDO_CLK"),
 344         PINCTRL_PIN(41, "TDI"),
 345
 346         PINCTRL_PIN(45, "GP_CAMERASB_05"),
 347         PINCTRL_PIN(46, "GP_CAMERASB_02"),
 348         PINCTRL_PIN(47, "GP_CAMERASB_08"),
 349         PINCTRL_PIN(48, "GP_CAMERASB_00"),
 350         PINCTRL_PIN(49, "GP_CAMERASB_06"),
 351         PINCTRL_PIN(50, "GP_CAMERASB_10"),
 352         PINCTRL_PIN(51, "GP_CAMERASB_03"),
 353         PINCTRL_PIN(52, "GP_CAMERASB_09"),
 354         PINCTRL_PIN(53, "GP_CAMERASB_01"),
 355         PINCTRL_PIN(54, "GP_CAMERASB_07"),
 356         PINCTRL_PIN(55, "GP_CAMERASB_11"),
 357         PINCTRL_PIN(56, "GP_CAMERASB_04"),
 358
 359         PINCTRL_PIN(60, "PANEL0_BKLTEN"),
 360         PINCTRL_PIN(61, "HV_DDI0_HPD"),
 361         PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
 362         PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
 363         PINCTRL_PIN(64, "HV_DDI1_HPD"),
 364         PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
 365         PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
 366         PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
 367         PINCTRL_PIN(68, "HV_DDI2_HPD"),
 368         PINCTRL_PIN(69, "PANEL1_VDDEN"),
 369         PINCTRL_PIN(70, "PANEL1_BKLTEN"),
 370         PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
 371         PINCTRL_PIN(72, "PANEL0_VDDEN"),
 372 };
 373
 374 static const struct intel_padgroup north_gpps[] = {
 375         CHV_GPP(0, 8),
 376         CHV_GPP(15, 27),
 377         CHV_GPP(30, 41),
 378         CHV_GPP(45, 56),
 379         CHV_GPP(60, 72),
 380 };
 381
 382 /*
 383  * North community can generate GPIO interrupts only for the first 8
 384  * interrupts. The upper half (8-15) can only be used to trigger GPEs.
 385  */
 386 static const struct intel_community north_communities[] = {
 387         CHV_COMMUNITY(north_gpps, 8, 0x92),
 388 };
 389
 390 static const struct intel_pinctrl_soc_data north_soc_data = {
 391         .uid = "2",
 392         .pins = north_pins,
 393         .npins = ARRAY_SIZE(north_pins),
 394         .communities = north_communities,
 395         .ncommunities = ARRAY_SIZE(north_communities),
 396 };
 397
 398 static const struct pinctrl_pin_desc east_pins[] = {
 399         PINCTRL_PIN(0, "PMU_SLP_S3_B"),
 400         PINCTRL_PIN(1, "PMU_BATLOW_B"),
 401         PINCTRL_PIN(2, "SUS_STAT_B"),
 402         PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
 403         PINCTRL_PIN(4, "PMU_AC_PRESENT"),
 404         PINCTRL_PIN(5, "PMU_PLTRST_B"),
 405         PINCTRL_PIN(6, "PMU_SUSCLK"),
 406         PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
 407         PINCTRL_PIN(8, "PMU_PWRBTN_B"),
 408         PINCTRL_PIN(9, "PMU_SLP_S4_B"),
 409         PINCTRL_PIN(10, "PMU_WAKE_B"),
 410         PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
 411
 412         PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
 413         PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
 414         PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
 415         PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
 416         PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
 417         PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
 418         PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
 419         PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
 420         PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
 421         PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
 422         PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
 423         PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
 424 };
 425
 426 static const struct intel_padgroup east_gpps[] = {
 427         CHV_GPP(0, 11),
 428         CHV_GPP(15, 26),
 429 };
 430
 431 static const struct intel_community east_communities[] = {
 432         CHV_COMMUNITY(east_gpps, 16, 0x93),
 433 };
 434
 435 static const struct intel_pinctrl_soc_data east_soc_data = {
 436         .uid = "3",
 437         .pins = east_pins,
 438         .npins = ARRAY_SIZE(east_pins),
 439         .communities = east_communities,
 440         .ncommunities = ARRAY_SIZE(east_communities),
 441 };
 442
 443 static const struct pinctrl_pin_desc southeast_pins[] = {
 444         PINCTRL_PIN(0, "MF_PLT_CLK0"),
 445         PINCTRL_PIN(1, "PWM1"),
 446         PINCTRL_PIN(2, "MF_PLT_CLK1"),
 447         PINCTRL_PIN(3, "MF_PLT_CLK4"),
 448         PINCTRL_PIN(4, "MF_PLT_CLK3"),
 449         PINCTRL_PIN(5, "PWM0"),
 450         PINCTRL_PIN(6, "MF_PLT_CLK5"),
 451         PINCTRL_PIN(7, "MF_PLT_CLK2"),
 452
 453         PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
 454         PINCTRL_PIN(16, "SDMMC1_CLK"),
 455         PINCTRL_PIN(17, "SDMMC1_D0"),
 456         PINCTRL_PIN(18, "SDMMC2_D1"),
 457         PINCTRL_PIN(19, "SDMMC2_CLK"),
 458         PINCTRL_PIN(20, "SDMMC1_D2"),
 459         PINCTRL_PIN(21, "SDMMC2_D2"),
 460         PINCTRL_PIN(22, "SDMMC2_CMD"),
 461         PINCTRL_PIN(23, "SDMMC1_CMD"),
 462         PINCTRL_PIN(24, "SDMMC1_D1"),
 463         PINCTRL_PIN(25, "SDMMC2_D0"),
 464         PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
 465
 466         PINCTRL_PIN(30, "SDMMC3_D1"),
 467         PINCTRL_PIN(31, "SDMMC3_CLK"),
 468         PINCTRL_PIN(32, "SDMMC3_D3"),
 469         PINCTRL_PIN(33, "SDMMC3_D2"),
 470         PINCTRL_PIN(34, "SDMMC3_CMD"),
 471         PINCTRL_PIN(35, "SDMMC3_D0"),
 472
 473         PINCTRL_PIN(45, "MF_LPC_AD2"),
 474         PINCTRL_PIN(46, "LPC_CLKRUNB"),
 475         PINCTRL_PIN(47, "MF_LPC_AD0"),
 476         PINCTRL_PIN(48, "LPC_FRAMEB"),
 477         PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
 478         PINCTRL_PIN(50, "MF_LPC_AD3"),
 479         PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
 480         PINCTRL_PIN(52, "MF_LPC_AD1"),
 481
 482         PINCTRL_PIN(60, "SPI1_MISO"),
 483         PINCTRL_PIN(61, "SPI1_CSO_B"),
 484         PINCTRL_PIN(62, "SPI1_CLK"),
 485         PINCTRL_PIN(63, "MMC1_D6"),
 486         PINCTRL_PIN(64, "SPI1_MOSI"),
 487         PINCTRL_PIN(65, "MMC1_D5"),
 488         PINCTRL_PIN(66, "SPI1_CS1_B"),
 489         PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
 490         PINCTRL_PIN(68, "MMC1_D7"),
 491         PINCTRL_PIN(69, "MMC1_RCLK"),
 492
 493         PINCTRL_PIN(75, "USB_OC1_B"),
 494         PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
 495         PINCTRL_PIN(77, "GPIO_ALERT"),
 496         PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
 497         PINCTRL_PIN(79, "ILB_SERIRQ"),
 498         PINCTRL_PIN(80, "USB_OC0_B"),
 499         PINCTRL_PIN(81, "SDMMC3_CD_B"),
 500         PINCTRL_PIN(82, "SPKR"),
 501         PINCTRL_PIN(83, "SUSPWRDNACK"),
 502         PINCTRL_PIN(84, "SPARE_PIN"),
 503         PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
 504 };
 505
 506 static const unsigned southeast_pwm0_pins[] = { 5 };
 507 static const unsigned southeast_pwm1_pins[] = { 1 };
 508 static const unsigned southeast_sdmmc1_pins[] = {
 509         16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
 510 };
 511 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
 512 static const unsigned southeast_sdmmc3_pins[] = {
 513         30, 31, 32, 33, 34, 35, 78, 81, 85,
 514 };
 515 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
 516 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
 517
 518 static const struct intel_pingroup southeast_groups[] = {
 519         PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)),
 520         PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)),
 521         PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)),
 522         PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)),
 523         PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)),
 524         PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)),
 525         PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)),
 526 };
 527
 528 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
 529 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
 530 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
 531 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
 532 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
 533 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
 534 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
 535
 536 static const struct intel_function southeast_functions[] = {
 537         FUNCTION("pwm0", southeast_pwm0_groups),
 538         FUNCTION("pwm1", southeast_pwm1_groups),
 539         FUNCTION("sdmmc1", southeast_sdmmc1_groups),
 540         FUNCTION("sdmmc2", southeast_sdmmc2_groups),
 541         FUNCTION("sdmmc3", southeast_sdmmc3_groups),
 542         FUNCTION("spi1", southeast_spi1_groups),
 543         FUNCTION("spi2", southeast_spi2_groups),
 544 };
 545
 546 static const struct intel_padgroup southeast_gpps[] = {
 547         CHV_GPP(0, 7),
 548         CHV_GPP(15, 26),
 549         CHV_GPP(30, 35),
 550         CHV_GPP(45, 52),
 551         CHV_GPP(60, 69),
 552         CHV_GPP(75, 85),
 553 };
 554
 555 static const struct intel_community southeast_communities[] = {
 556         CHV_COMMUNITY(southeast_gpps, 16, 0x94),
 557 };
 558
 559 static const struct intel_pinctrl_soc_data southeast_soc_data = {
 560         .uid = "4",
 561         .pins = southeast_pins,
 562         .npins = ARRAY_SIZE(southeast_pins),
 563         .groups = southeast_groups,
 564         .ngroups = ARRAY_SIZE(southeast_groups),
 565         .functions = southeast_functions,
 566         .nfunctions = ARRAY_SIZE(southeast_functions),
 567         .communities = southeast_communities,
 568         .ncommunities = ARRAY_SIZE(southeast_communities),
 569 };
 570
 571 static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
 572         &southwest_soc_data,
 573         &north_soc_data,
 574         &east_soc_data,
 575         &southeast_soc_data,
 576         NULL
 577 };
 578
 579 /*
 580  * Lock to serialize register accesses
 581  *
 582  * Due to a silicon issue, a shared lock must be used to prevent
 583  * concurrent accesses across the 4 GPIO controllers.
 584  *
 585  * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
 586  * errata #CHT34, for further information.
 587  */
 588 static DEFINE_RAW_SPINLOCK(chv_lock);
 589
 590 static u32 chv_pctrl_readl(struct chv_pinctrl *pctrl, unsigned int offset)
 591 {
 592         const struct intel_community *community = &pctrl->communities[0];
 593
 594         return readl(community->regs + offset);
 595 }
 596
 597 static void chv_pctrl_writel(struct chv_pinctrl *pctrl, unsigned int offset, u32 value)
 598 {
 599         const struct intel_community *community = &pctrl->communities[0];
 600         void __iomem *reg = community->regs + offset;
 601
 602         /* Write and simple read back to confirm the bus transferring done */
 603         writel(value, reg);
 604         readl(reg);
 605 }
 606
 607 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
 608                                 unsigned int reg)
 609 {
 610         const struct intel_community *community = &pctrl->communities[0];
 611         unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
 612         unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
 613
 614         offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no;
 615
 616         return community->pad_regs + offset + reg;
 617 }
 618
 619 static u32 chv_readl(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int offset)
 620 {
 621         return readl(chv_padreg(pctrl, pin, offset));
 622 }
 623
 624 static void chv_writel(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
 625 {
 626         void __iomem *reg = chv_padreg(pctrl, pin, offset);
 627
 628         /* Write and simple read back to confirm the bus transferring done */
 629         writel(value, reg);
 630         readl(reg);
 631 }
 632
 633 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
 634 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset)
 635 {
 636         return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
 637 }
 638
 639 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
 640 {
 641         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 642
 643         return pctrl->soc->ngroups;
 644 }
 645
 646 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
 647                                       unsigned int group)
 648 {
 649         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 650
 651         return pctrl->soc->groups[group].name;
 652 }
 653
 654 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 655                               const unsigned int **pins, unsigned int *npins)
 656 {
 657         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 658
 659         *pins = pctrl->soc->groups[group].pins;
 660         *npins = pctrl->soc->groups[group].npins;
 661         return 0;
 662 }
 663
 664 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 665                              unsigned int offset)
 666 {
 667         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 668         unsigned long flags;
 669         u32 ctrl0, ctrl1;
 670         bool locked;
 671
 672         raw_spin_lock_irqsave(&chv_lock, flags);
 673
 674         ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
 675         ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
 676         locked = chv_pad_locked(pctrl, offset);
 677
 678         raw_spin_unlock_irqrestore(&chv_lock, flags);
 679
 680         if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
 681                 seq_puts(s, "GPIO ");
 682         } else {
 683                 u32 mode;
 684
 685                 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
 686                 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
 687
 688                 seq_printf(s, "mode %d ", mode);
 689         }
 690
 691         seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
 692
 693         if (locked)
 694                 seq_puts(s, " [LOCKED]");
 695 }
 696
 697 static const struct pinctrl_ops chv_pinctrl_ops = {
 698         .get_groups_count = chv_get_groups_count,
 699         .get_group_name = chv_get_group_name,
 700         .get_group_pins = chv_get_group_pins,
 701         .pin_dbg_show = chv_pin_dbg_show,
 702 };
 703
 704 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
 705 {
 706         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 707
 708         return pctrl->soc->nfunctions;
 709 }
 710
 711 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
 712                                          unsigned int function)
 713 {
 714         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 715
 716         return pctrl->soc->functions[function].name;
 717 }
 718
 719 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
 720                                    unsigned int function,
 721                                    const char * const **groups,
 722                                    unsigned int * const ngroups)
 723 {
 724         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 725
 726         *groups = pctrl->soc->functions[function].groups;
 727         *ngroups = pctrl->soc->functions[function].ngroups;
 728         return 0;
 729 }
 730
 731 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
 732                               unsigned int function, unsigned int group)
 733 {
 734         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 735         const struct intel_pingroup *grp;
 736         unsigned long flags;
 737         int i;
 738
 739         grp = &pctrl->soc->groups[group];
 740
 741         raw_spin_lock_irqsave(&chv_lock, flags);
 742
 743         /* Check first that the pad is not locked */
 744         for (i = 0; i < grp->npins; i++) {
 745                 if (chv_pad_locked(pctrl, grp->pins[i])) {
 746                         dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
 747                                  grp->pins[i]);
 748                         raw_spin_unlock_irqrestore(&chv_lock, flags);
 749                         return -EBUSY;
 750                 }
 751         }
 752
 753         for (i = 0; i < grp->npins; i++) {
 754                 int pin = grp->pins[i];
 755                 unsigned int mode;
 756                 bool invert_oe;
 757                 u32 value;
 758
 759                 /* Check if there is pin-specific config */
 760                 if (grp->modes)
 761                         mode = grp->modes[i];
 762                 else
 763                         mode = grp->mode;
 764
 765                 /* Extract OE inversion */
 766                 invert_oe = mode & PINMODE_INVERT_OE;
 767                 mode &= ~PINMODE_INVERT_OE;
 768
 769                 value = chv_readl(pctrl, pin, CHV_PADCTRL0);
 770                 /* Disable GPIO mode */
 771                 value &= ~CHV_PADCTRL0_GPIOEN;
 772                 /* Set to desired mode */
 773                 value &= ~CHV_PADCTRL0_PMODE_MASK;
 774                 value |= mode << CHV_PADCTRL0_PMODE_SHIFT;
 775                 chv_writel(pctrl, pin, CHV_PADCTRL0, value);
 776
 777                 /* Update for invert_oe */
 778                 value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK;
 779                 if (invert_oe)
 780                         value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
 781                 chv_writel(pctrl, pin, CHV_PADCTRL1, value);
 782
 783                 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
 784                         pin, mode, invert_oe ? "" : "not ");
 785         }
 786
 787         raw_spin_unlock_irqrestore(&chv_lock, flags);
 788
 789         return 0;
 790 }
 791
 792 static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl,
 793                                       unsigned int offset)
 794 {
 795         u32 value;
 796
 797         value = chv_readl(pctrl, offset, CHV_PADCTRL1);
 798         value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
 799         value &= ~CHV_PADCTRL1_INVRXTX_MASK;
 800         chv_writel(pctrl, offset, CHV_PADCTRL1, value);
 801 }
 802
 803 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
 804                                    struct pinctrl_gpio_range *range,
 805                                    unsigned int offset)
 806 {
 807         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 808         unsigned long flags;
 809         u32 value;
 810
 811         raw_spin_lock_irqsave(&chv_lock, flags);
 812
 813         if (chv_pad_locked(pctrl, offset)) {
 814                 value = chv_readl(pctrl, offset, CHV_PADCTRL0);
 815                 if (!(value & CHV_PADCTRL0_GPIOEN)) {
 816                         /* Locked so cannot enable */
 817                         raw_spin_unlock_irqrestore(&chv_lock, flags);
 818                         return -EBUSY;
 819                 }
 820         } else {
 821                 int i;
 822
 823                 /* Reset the interrupt mapping */
 824                 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
 825                         if (pctrl->intr_lines[i] == offset) {
 826                                 pctrl->intr_lines[i] = 0;
 827                                 break;
 828                         }
 829                 }
 830
 831                 /* Disable interrupt generation */
 832                 chv_gpio_clear_triggering(pctrl, offset);
 833
 834                 value = chv_readl(pctrl, offset, CHV_PADCTRL0);
 835
 836                 /*
 837                  * If the pin is in HiZ mode (both TX and RX buffers are
 838                  * disabled) we turn it to be input now.
 839                  */
 840                 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
 841                      (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
 842                         value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
 843                         value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
 844                 }
 845
 846                 /* Switch to a GPIO mode */
 847                 value |= CHV_PADCTRL0_GPIOEN;
 848                 chv_writel(pctrl, offset, CHV_PADCTRL0, value);
 849         }
 850
 851         raw_spin_unlock_irqrestore(&chv_lock, flags);
 852
 853         return 0;
 854 }
 855
 856 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
 857                                   struct pinctrl_gpio_range *range,
 858                                   unsigned int offset)
 859 {
 860         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 861         unsigned long flags;
 862
 863         raw_spin_lock_irqsave(&chv_lock, flags);
 864
 865         if (!chv_pad_locked(pctrl, offset))
 866                 chv_gpio_clear_triggering(pctrl, offset);
 867
 868         raw_spin_unlock_irqrestore(&chv_lock, flags);
 869 }
 870
 871 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
 872                                   struct pinctrl_gpio_range *range,
 873                                   unsigned int offset, bool input)
 874 {
 875         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 876         unsigned long flags;
 877         u32 ctrl0;
 878
 879         raw_spin_lock_irqsave(&chv_lock, flags);
 880
 881         ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;
 882         if (input)
 883                 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
 884         else
 885                 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
 886         chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
 887
 888         raw_spin_unlock_irqrestore(&chv_lock, flags);
 889
 890         return 0;
 891 }
 892
 893 static const struct pinmux_ops chv_pinmux_ops = {
 894         .get_functions_count = chv_get_functions_count,
 895         .get_function_name = chv_get_function_name,
 896         .get_function_groups = chv_get_function_groups,
 897         .set_mux = chv_pinmux_set_mux,
 898         .gpio_request_enable = chv_gpio_request_enable,
 899         .gpio_disable_free = chv_gpio_disable_free,
 900         .gpio_set_direction = chv_gpio_set_direction,
 901 };
 902
 903 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 904                           unsigned long *config)
 905 {
 906         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 907         enum pin_config_param param = pinconf_to_config_param(*config);
 908         unsigned long flags;
 909         u32 ctrl0, ctrl1;
 910         u16 arg = 0;
 911         u32 term;
 912
 913         raw_spin_lock_irqsave(&chv_lock, flags);
 914         ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
 915         ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
 916         raw_spin_unlock_irqrestore(&chv_lock, flags);
 917
 918         term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
 919
 920         switch (param) {
 921         case PIN_CONFIG_BIAS_DISABLE:
 922                 if (term)
 923                         return -EINVAL;
 924                 break;
 925
 926         case PIN_CONFIG_BIAS_PULL_UP:
 927                 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
 928                         return -EINVAL;
 929
 930                 switch (term) {
 931                 case CHV_PADCTRL0_TERM_20K:
 932                         arg = 20000;
 933                         break;
 934                 case CHV_PADCTRL0_TERM_5K:
 935                         arg = 5000;
 936                         break;
 937                 case CHV_PADCTRL0_TERM_1K:
 938                         arg = 1000;
 939                         break;
 940                 }
 941
 942                 break;
 943
 944         case PIN_CONFIG_BIAS_PULL_DOWN:
 945                 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
 946                         return -EINVAL;
 947
 948                 switch (term) {
 949                 case CHV_PADCTRL0_TERM_20K:
 950                         arg = 20000;
 951                         break;
 952                 case CHV_PADCTRL0_TERM_5K:
 953                         arg = 5000;
 954                         break;
 955                 }
 956
 957                 break;
 958
 959         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 960                 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
 961                         return -EINVAL;
 962                 break;
 963
 964         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
 965                 u32 cfg;
 966
 967                 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
 968                 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
 969                 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
 970                         return -EINVAL;
 971
 972                 break;
 973         }
 974
 975         default:
 976                 return -ENOTSUPP;
 977         }
 978
 979         *config = pinconf_to_config_packed(param, arg);
 980         return 0;
 981 }
 982
 983 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin,
 984                                enum pin_config_param param, u32 arg)
 985 {
 986         unsigned long flags;
 987         u32 ctrl0, pull;
 988
 989         raw_spin_lock_irqsave(&chv_lock, flags);
 990         ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
 991
 992         switch (param) {
 993         case PIN_CONFIG_BIAS_DISABLE:
 994                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
 995                 break;
 996
 997         case PIN_CONFIG_BIAS_PULL_UP:
 998                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
 999
1000                 switch (arg) {
1001                 case 1000:
1002                         /* For 1k there is only pull up */
1003                         pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1004                         break;
1005                 case 5000:
1006                         pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1007                         break;
1008                 case 20000:
1009                         pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1010                         break;
1011                 default:
1012                         raw_spin_unlock_irqrestore(&chv_lock, flags);
1013                         return -EINVAL;
1014                 }
1015
1016                 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1017                 break;
1018
1019         case PIN_CONFIG_BIAS_PULL_DOWN:
1020                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1021
1022                 switch (arg) {
1023                 case 5000:
1024                         pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1025                         break;
1026                 case 20000:
1027                         pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1028                         break;
1029                 default:
1030                         raw_spin_unlock_irqrestore(&chv_lock, flags);
1031                         return -EINVAL;
1032                 }
1033
1034                 ctrl0 |= pull;
1035                 break;
1036
1037         default:
1038                 raw_spin_unlock_irqrestore(&chv_lock, flags);
1039                 return -EINVAL;
1040         }
1041
1042         chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);
1043         raw_spin_unlock_irqrestore(&chv_lock, flags);
1044
1045         return 0;
1046 }
1047
1048 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1049                                bool enable)
1050 {
1051         unsigned long flags;
1052         u32 ctrl1;
1053
1054         raw_spin_lock_irqsave(&chv_lock, flags);
1055         ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
1056
1057         if (enable)
1058                 ctrl1 |= CHV_PADCTRL1_ODEN;
1059         else
1060                 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1061
1062         chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);
1063         raw_spin_unlock_irqrestore(&chv_lock, flags);
1064
1065         return 0;
1066 }
1067
1068 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1069                           unsigned long *configs, unsigned int nconfigs)
1070 {
1071         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1072         enum pin_config_param param;
1073         int i, ret;
1074         u32 arg;
1075
1076         if (chv_pad_locked(pctrl, pin))
1077                 return -EBUSY;
1078
1079         for (i = 0; i < nconfigs; i++) {
1080                 param = pinconf_to_config_param(configs[i]);
1081                 arg = pinconf_to_config_argument(configs[i]);
1082
1083                 switch (param) {
1084                 case PIN_CONFIG_BIAS_DISABLE:
1085                 case PIN_CONFIG_BIAS_PULL_UP:
1086                 case PIN_CONFIG_BIAS_PULL_DOWN:
1087                         ret = chv_config_set_pull(pctrl, pin, param, arg);
1088                         if (ret)
1089                                 return ret;
1090                         break;
1091
1092                 case PIN_CONFIG_DRIVE_PUSH_PULL:
1093                         ret = chv_config_set_oden(pctrl, pin, false);
1094                         if (ret)
1095                                 return ret;
1096                         break;
1097
1098                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1099                         ret = chv_config_set_oden(pctrl, pin, true);
1100                         if (ret)
1101                                 return ret;
1102                         break;
1103
1104                 default:
1105                         return -ENOTSUPP;
1106                 }
1107
1108                 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1109                         param, arg);
1110         }
1111
1112         return 0;
1113 }
1114
1115 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1116                                 unsigned int group,
1117                                 unsigned long *config)
1118 {
1119         const unsigned int *pins;
1120         unsigned int npins;
1121         int ret;
1122
1123         ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1124         if (ret)
1125                 return ret;
1126
1127         ret = chv_config_get(pctldev, pins[0], config);
1128         if (ret)
1129                 return ret;
1130
1131         return 0;
1132 }
1133
1134 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1135                                 unsigned int group, unsigned long *configs,
1136                                 unsigned int num_configs)
1137 {
1138         const unsigned int *pins;
1139         unsigned int npins;
1140         int i, ret;
1141
1142         ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1143         if (ret)
1144                 return ret;
1145
1146         for (i = 0; i < npins; i++) {
1147                 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1148                 if (ret)
1149                         return ret;
1150         }
1151
1152         return 0;
1153 }
1154
1155 static const struct pinconf_ops chv_pinconf_ops = {
1156         .is_generic = true,
1157         .pin_config_set = chv_config_set,
1158         .pin_config_get = chv_config_get,
1159         .pin_config_group_get = chv_config_group_get,
1160         .pin_config_group_set = chv_config_group_set,
1161 };
1162
1163 static struct pinctrl_desc chv_pinctrl_desc = {
1164         .pctlops = &chv_pinctrl_ops,
1165         .pmxops = &chv_pinmux_ops,
1166         .confops = &chv_pinconf_ops,
1167         .owner = THIS_MODULE,
1168 };
1169
1170 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
1171 {
1172         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1173         unsigned long flags;
1174         u32 ctrl0, cfg;
1175
1176         raw_spin_lock_irqsave(&chv_lock, flags);
1177         ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1178         raw_spin_unlock_irqrestore(&chv_lock, flags);
1179
1180         cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1181         cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1182
1183         if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1184                 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1185         return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1186 }
1187
1188 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1189 {
1190         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1191         unsigned long flags;
1192         u32 ctrl0;
1193
1194         raw_spin_lock_irqsave(&chv_lock, flags);
1195
1196         ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1197
1198         if (value)
1199                 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1200         else
1201                 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1202
1203         chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
1204
1205         raw_spin_unlock_irqrestore(&chv_lock, flags);
1206 }
1207
1208 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1209 {
1210         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1211         u32 ctrl0, direction;
1212         unsigned long flags;
1213
1214         raw_spin_lock_irqsave(&chv_lock, flags);
1215         ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1216         raw_spin_unlock_irqrestore(&chv_lock, flags);
1217
1218         direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1219         direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1220
1221         if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
1222                 return GPIO_LINE_DIRECTION_OUT;
1223
1224         return GPIO_LINE_DIRECTION_IN;
1225 }
1226
1227 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1228 {
1229         return pinctrl_gpio_direction_input(chip->base + offset);
1230 }
1231
1232 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1233                                      int value)
1234 {
1235         chv_gpio_set(chip, offset, value);
1236         return pinctrl_gpio_direction_output(chip->base + offset);
1237 }
1238
1239 static const struct gpio_chip chv_gpio_chip = {
1240         .owner = THIS_MODULE,
1241         .request = gpiochip_generic_request,
1242         .free = gpiochip_generic_free,
1243         .get_direction = chv_gpio_get_direction,
1244         .direction_input = chv_gpio_direction_input,
1245         .direction_output = chv_gpio_direction_output,
1246         .get = chv_gpio_get,
1247         .set = chv_gpio_set,
1248 };
1249
1250 static void chv_gpio_irq_ack(struct irq_data *d)
1251 {
1252         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1253         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1254         int pin = irqd_to_hwirq(d);
1255         u32 intr_line;
1256
1257         raw_spin_lock(&chv_lock);
1258
1259         intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
1260         intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1261         intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1262         chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
1263
1264         raw_spin_unlock(&chv_lock);
1265 }
1266
1267 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1268 {
1269         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1270         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1271         int pin = irqd_to_hwirq(d);
1272         u32 value, intr_line;
1273         unsigned long flags;
1274
1275         raw_spin_lock_irqsave(&chv_lock, flags);
1276
1277         intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
1278         intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1279         intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1280
1281         value = chv_pctrl_readl(pctrl, CHV_INTMASK);
1282         if (mask)
1283                 value &= ~BIT(intr_line);
1284         else
1285                 value |= BIT(intr_line);
1286         chv_pctrl_writel(pctrl, CHV_INTMASK, value);
1287
1288         raw_spin_unlock_irqrestore(&chv_lock, flags);
1289 }
1290
1291 static void chv_gpio_irq_mask(struct irq_data *d)
1292 {
1293         chv_gpio_irq_mask_unmask(d, true);
1294 }
1295
1296 static void chv_gpio_irq_unmask(struct irq_data *d)
1297 {
1298         chv_gpio_irq_mask_unmask(d, false);
1299 }
1300
1301 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1302 {
1303         /*
1304          * Check if the interrupt has been requested with 0 as triggering
1305          * type. In that case it is assumed that the current values
1306          * programmed to the hardware are used (e.g BIOS configured
1307          * defaults).
1308          *
1309          * In that case ->irq_set_type() will never be called so we need to
1310          * read back the values from hardware now, set correct flow handler
1311          * and update mappings before the interrupt is being used.
1312          */
1313         if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1314                 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1315                 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1316                 unsigned int pin = irqd_to_hwirq(d);
1317                 irq_flow_handler_t handler;
1318                 unsigned long flags;
1319                 u32 intsel, value;
1320
1321                 raw_spin_lock_irqsave(&chv_lock, flags);
1322                 intsel = chv_readl(pctrl, pin, CHV_PADCTRL0);
1323                 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1324                 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1325
1326                 value = chv_readl(pctrl, pin, CHV_PADCTRL1);
1327                 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1328                         handler = handle_level_irq;
1329                 else
1330                         handler = handle_edge_irq;
1331
1332                 if (!pctrl->intr_lines[intsel]) {
1333                         irq_set_handler_locked(d, handler);
1334                         pctrl->intr_lines[intsel] = pin;
1335                 }
1336                 raw_spin_unlock_irqrestore(&chv_lock, flags);
1337         }
1338
1339         chv_gpio_irq_unmask(d);
1340         return 0;
1341 }
1342
1343 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
1344 {
1345         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1346         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1347         unsigned int pin = irqd_to_hwirq(d);
1348         unsigned long flags;
1349         u32 value;
1350
1351         raw_spin_lock_irqsave(&chv_lock, flags);
1352
1353         /*
1354          * Pins which can be used as shared interrupt are configured in
1355          * BIOS. Driver trusts BIOS configurations and assigns different
1356          * handler according to the irq type.
1357          *
1358          * Driver needs to save the mapping between each pin and
1359          * its interrupt line.
1360          * 1. If the pin cfg is locked in BIOS:
1361          *      Trust BIOS has programmed IntWakeCfg bits correctly,
1362          *      driver just needs to save the mapping.
1363          * 2. If the pin cfg is not locked in BIOS:
1364          *      Driver programs the IntWakeCfg bits and save the mapping.
1365          */
1366         if (!chv_pad_locked(pctrl, pin)) {
1367                 value = chv_readl(pctrl, pin, CHV_PADCTRL1);
1368                 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1369                 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1370
1371                 if (type & IRQ_TYPE_EDGE_BOTH) {
1372                         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1373                                 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1374                         else if (type & IRQ_TYPE_EDGE_RISING)
1375                                 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1376                         else if (type & IRQ_TYPE_EDGE_FALLING)
1377                                 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1378                 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1379                         value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1380                         if (type & IRQ_TYPE_LEVEL_LOW)
1381                                 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1382                 }
1383
1384                 chv_writel(pctrl, pin, CHV_PADCTRL1, value);
1385         }
1386
1387         value = chv_readl(pctrl, pin, CHV_PADCTRL0);
1388         value &= CHV_PADCTRL0_INTSEL_MASK;
1389         value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1390
1391         pctrl->intr_lines[value] = pin;
1392
1393         if (type & IRQ_TYPE_EDGE_BOTH)
1394                 irq_set_handler_locked(d, handle_edge_irq);
1395         else if (type & IRQ_TYPE_LEVEL_MASK)
1396                 irq_set_handler_locked(d, handle_level_irq);
1397
1398         raw_spin_unlock_irqrestore(&chv_lock, flags);
1399
1400         return 0;
1401 }
1402
1403 static void chv_gpio_irq_handler(struct irq_desc *desc)
1404 {
1405         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1406         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1407         const struct intel_community *community = &pctrl->communities[0];
1408         struct irq_chip *chip = irq_desc_get_chip(desc);
1409         unsigned long pending;
1410         unsigned long flags;
1411         u32 intr_line;
1412
1413         chained_irq_enter(chip, desc);
1414
1415         raw_spin_lock_irqsave(&chv_lock, flags);
1416         pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
1417         raw_spin_unlock_irqrestore(&chv_lock, flags);
1418
1419         for_each_set_bit(intr_line, &pending, community->nirqs) {
1420                 unsigned int irq, offset;
1421
1422                 offset = pctrl->intr_lines[intr_line];
1423                 irq = irq_find_mapping(gc->irq.domain, offset);
1424                 generic_handle_irq(irq);
1425         }
1426
1427         chained_irq_exit(chip, desc);
1428 }
1429
1430 /*
1431  * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1432  * tables. Since we leave GPIOs that are not capable of generating
1433  * interrupts out of the irqdomain the numbering will be different and
1434  * cause devices using the hardcoded IRQ numbers fail. In order not to
1435  * break such machines we will only mask pins from irqdomain if the machine
1436  * is not listed below.
1437  */
1438 static const struct dmi_system_id chv_no_valid_mask[] = {
1439         /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1440         {
1441                 .ident = "Intel_Strago based Chromebooks (All models)",
1442                 .matches = {
1443                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1444                         DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1445                 },
1446         },
1447         {
1448                 .ident = "HP Chromebook 11 G5 (Setzer)",
1449                 .matches = {
1450                         DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1451                         DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1452                 },
1453         },
1454         {
1455                 .ident = "Acer Chromebook R11 (Cyan)",
1456                 .matches = {
1457                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1458                         DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1459                 },
1460         },
1461         {
1462                 .ident = "Samsung Chromebook 3 (Celes)",
1463                 .matches = {
1464                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1465                         DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
1466                 },
1467         },
1468         {}
1469 };
1470
1471 static void chv_init_irq_valid_mask(struct gpio_chip *chip,
1472                                     unsigned long *valid_mask,
1473                                     unsigned int ngpios)
1474 {
1475         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1476         const struct intel_community *community = &pctrl->communities[0];
1477         int i;
1478
1479         /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1480         for (i = 0; i < pctrl->soc->npins; i++) {
1481                 const struct pinctrl_pin_desc *desc;
1482                 u32 intsel;
1483
1484                 desc = &pctrl->soc->pins[i];
1485
1486                 intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1487                 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1488                 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1489
1490                 if (intsel >= community->nirqs)
1491                         clear_bit(desc->number, valid_mask);
1492         }
1493 }
1494
1495 static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
1496 {
1497         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1498         const struct intel_community *community = &pctrl->communities[0];
1499
1500         /*
1501          * The same set of machines in chv_no_valid_mask[] have incorrectly
1502          * configured GPIOs that generate spurious interrupts so we use
1503          * this same list to apply another quirk for them.
1504          *
1505          * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1506          */
1507         if (!pctrl->chip.irq.init_valid_mask) {
1508                 /*
1509                  * Mask all interrupts the community is able to generate
1510                  * but leave the ones that can only generate GPEs unmasked.
1511                  */
1512                 chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs));
1513         }
1514
1515         /* Clear all interrupts */
1516         chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
1517
1518         return 0;
1519 }
1520
1521 static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
1522 {
1523         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1524         const struct intel_community *community = &pctrl->communities[0];
1525         const struct intel_padgroup *gpp;
1526         int ret, i;
1527
1528         for (i = 0; i < community->ngpps; i++) {
1529                 gpp = &community->gpps[i];
1530                 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1531                                              gpp->base, gpp->base,
1532                                              gpp->size);
1533                 if (ret) {
1534                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1535                         return ret;
1536                 }
1537         }
1538
1539         return 0;
1540 }
1541
1542 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1543 {
1544         const struct intel_community *community = &pctrl->communities[0];
1545         const struct intel_padgroup *gpp;
1546         struct gpio_chip *chip = &pctrl->chip;
1547         bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1548         int ret, i, irq_base;
1549
1550         *chip = chv_gpio_chip;
1551
1552         chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
1553         chip->label = dev_name(pctrl->dev);
1554         chip->add_pin_ranges = chv_gpio_add_pin_ranges;
1555         chip->parent = pctrl->dev;
1556         chip->base = -1;
1557
1558         pctrl->irq = irq;
1559         pctrl->irqchip.name = "chv-gpio";
1560         pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
1561         pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
1562         pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
1563         pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
1564         pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
1565         pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
1566
1567         chip->irq.chip = &pctrl->irqchip;
1568         chip->irq.init_hw = chv_gpio_irq_init_hw;
1569         chip->irq.parent_handler = chv_gpio_irq_handler;
1570         chip->irq.num_parents = 1;
1571         chip->irq.parents = &pctrl->irq;
1572         chip->irq.default_type = IRQ_TYPE_NONE;
1573         chip->irq.handler = handle_bad_irq;
1574         if (need_valid_mask) {
1575                 chip->irq.init_valid_mask = chv_init_irq_valid_mask;
1576         } else {
1577                 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1578                                                 pctrl->soc->npins, NUMA_NO_NODE);
1579                 if (irq_base < 0) {
1580                         dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1581                         return irq_base;
1582                 }
1583         }
1584
1585         ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1586         if (ret) {
1587                 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1588                 return ret;
1589         }
1590
1591         if (!need_valid_mask) {
1592                 for (i = 0; i < community->ngpps; i++) {
1593                         gpp = &community->gpps[i];
1594
1595                         irq_domain_associate_many(chip->irq.domain, irq_base,
1596                                                   gpp->base, gpp->size);
1597                         irq_base += gpp->size;
1598                 }
1599         }
1600
1601         return 0;
1602 }
1603
1604 static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1605         acpi_physical_address address, u32 bits, u64 *value,
1606         void *handler_context, void *region_context)
1607 {
1608         struct chv_pinctrl *pctrl = region_context;
1609         unsigned long flags;
1610         acpi_status ret = AE_OK;
1611
1612         raw_spin_lock_irqsave(&chv_lock, flags);
1613
1614         if (function == ACPI_WRITE)
1615                 chv_pctrl_writel(pctrl, address, *value);
1616         else if (function == ACPI_READ)
1617                 *value = chv_pctrl_readl(pctrl, address);
1618         else
1619                 ret = AE_BAD_PARAMETER;
1620
1621         raw_spin_unlock_irqrestore(&chv_lock, flags);
1622
1623         return ret;
1624 }
1625
1626 static int chv_pinctrl_probe(struct platform_device *pdev)
1627 {
1628         const struct intel_pinctrl_soc_data *soc_data = NULL;
1629         const struct intel_pinctrl_soc_data **soc_table;
1630         struct intel_community *community;
1631         struct device *dev = &pdev->dev;
1632         struct chv_pinctrl *pctrl;
1633         struct acpi_device *adev;
1634         acpi_status status;
1635         int ret, irq, i;
1636
1637         adev = ACPI_COMPANION(&pdev->dev);
1638         if (!adev)
1639                 return -ENODEV;
1640
1641         soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev);
1642         for (i = 0; soc_table[i]; i++) {
1643                 if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
1644                         soc_data = soc_table[i];
1645                         break;
1646                 }
1647         }
1648         if (!soc_data)
1649                 return -ENODEV;
1650
1651         pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1652         if (!pctrl)
1653                 return -ENOMEM;
1654
1655         pctrl->dev = &pdev->dev;
1656         pctrl->soc = soc_data;
1657
1658         pctrl->ncommunities = pctrl->soc->ncommunities;
1659         pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities,
1660                                           pctrl->ncommunities * sizeof(*pctrl->communities),
1661                                           GFP_KERNEL);
1662         if (!pctrl->communities)
1663                 return -ENOMEM;
1664
1665         community = &pctrl->communities[0];
1666         community->regs = devm_platform_ioremap_resource(pdev, 0);
1667         if (IS_ERR(community->regs))
1668                 return PTR_ERR(community->regs);
1669
1670         community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF;
1671
1672 #ifdef CONFIG_PM_SLEEP
1673         pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins,
1674                                            sizeof(*pctrl->context.pads),
1675                                            GFP_KERNEL);
1676         if (!pctrl->context.pads)
1677                 return -ENOMEM;
1678 #endif
1679
1680         irq = platform_get_irq(pdev, 0);
1681         if (irq < 0)
1682                 return irq;
1683
1684         pctrl->pctldesc = chv_pinctrl_desc;
1685         pctrl->pctldesc.name = dev_name(&pdev->dev);
1686         pctrl->pctldesc.pins = pctrl->soc->pins;
1687         pctrl->pctldesc.npins = pctrl->soc->npins;
1688
1689         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1690                                                pctrl);
1691         if (IS_ERR(pctrl->pctldev)) {
1692                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1693                 return PTR_ERR(pctrl->pctldev);
1694         }
1695
1696         ret = chv_gpio_probe(pctrl, irq);
1697         if (ret)
1698                 return ret;
1699
1700         status = acpi_install_address_space_handler(adev->handle,
1701                                         community->acpi_space_id,
1702                                         chv_pinctrl_mmio_access_handler,
1703                                         NULL, pctrl);
1704         if (ACPI_FAILURE(status))
1705                 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
1706
1707         platform_set_drvdata(pdev, pctrl);
1708
1709         return 0;
1710 }
1711
1712 static int chv_pinctrl_remove(struct platform_device *pdev)
1713 {
1714         struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1715         const struct intel_community *community = &pctrl->communities[0];
1716
1717         acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
1718                                           community->acpi_space_id,
1719                                           chv_pinctrl_mmio_access_handler);
1720
1721         return 0;
1722 }
1723
1724 #ifdef CONFIG_PM_SLEEP
1725 static int chv_pinctrl_suspend_noirq(struct device *dev)
1726 {
1727         struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
1728         unsigned long flags;
1729         int i;
1730
1731         raw_spin_lock_irqsave(&chv_lock, flags);
1732
1733         pctrl->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
1734
1735         for (i = 0; i < pctrl->soc->npins; i++) {
1736                 const struct pinctrl_pin_desc *desc;
1737                 struct intel_pad_context *ctx = &pctrl->context.pads[i];
1738
1739                 desc = &pctrl->soc->pins[i];
1740                 if (chv_pad_locked(pctrl, desc->number))
1741                         continue;
1742
1743                 ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1744                 ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE;
1745
1746                 ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
1747         }
1748
1749         raw_spin_unlock_irqrestore(&chv_lock, flags);
1750
1751         return 0;
1752 }
1753
1754 static int chv_pinctrl_resume_noirq(struct device *dev)
1755 {
1756         struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
1757         unsigned long flags;
1758         int i;
1759
1760         raw_spin_lock_irqsave(&chv_lock, flags);
1761
1762         /*
1763          * Mask all interrupts before restoring per-pin configuration
1764          * registers because we don't know in which state BIOS left them
1765          * upon exiting suspend.
1766          */
1767         chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000);
1768
1769         for (i = 0; i < pctrl->soc->npins; i++) {
1770                 const struct pinctrl_pin_desc *desc;
1771                 struct intel_pad_context *ctx = &pctrl->context.pads[i];
1772                 u32 val;
1773
1774                 desc = &pctrl->soc->pins[i];
1775                 if (chv_pad_locked(pctrl, desc->number))
1776                         continue;
1777
1778                 /* Only restore if our saved state differs from the current */
1779                 val = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1780                 val &= ~CHV_PADCTRL0_GPIORXSTATE;
1781                 if (ctx->padctrl0 != val) {
1782                         chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0);
1783                         dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1784                                 desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL0));
1785                 }
1786
1787                 val = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
1788                 if (ctx->padctrl1 != val) {
1789                         chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1);
1790                         dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1791                                 desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL1));
1792                 }
1793         }
1794
1795         /*
1796          * Now that all pins are restored to known state, we can restore
1797          * the interrupt mask register as well.
1798          */
1799         chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
1800         chv_pctrl_writel(pctrl, CHV_INTMASK, pctrl->saved_intmask);
1801
1802         raw_spin_unlock_irqrestore(&chv_lock, flags);
1803
1804         return 0;
1805 }
1806 #endif
1807
1808 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1809         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1810                                       chv_pinctrl_resume_noirq)
1811 };
1812
1813 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1814         { "INT33FF", (kernel_ulong_t)chv_soc_data },
1815         { }
1816 };
1817 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1818
1819 static struct platform_driver chv_pinctrl_driver = {
1820         .probe = chv_pinctrl_probe,
1821         .remove = chv_pinctrl_remove,
1822         .driver = {
1823                 .name = "cherryview-pinctrl",
1824                 .pm = &chv_pinctrl_pm_ops,
1825                 .acpi_match_table = chv_pinctrl_acpi_match,
1826         },
1827 };
1828
1829 static int __init chv_pinctrl_init(void)
1830 {
1831         return platform_driver_register(&chv_pinctrl_driver);
1832 }
1833 subsys_initcall(chv_pinctrl_init);
1834
1835 static void __exit chv_pinctrl_exit(void)
1836 {
1837         platform_driver_unregister(&chv_pinctrl_driver);
1838 }
1839 module_exit(chv_pinctrl_exit);
1840
1841 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1842 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1843 MODULE_LICENSE("GPL v2");