drivers/pinctrl/intel/pinctrl-cherryview.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Cherryview/Braswell pinctrl driver
   4  *
   5  * Copyright (C) 2014, Intel Corporation
   6  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
   7  *
   8  * This driver is based on the original Cherryview GPIO driver by
   9  *   Ning Li <ning.li@intel.com>
  10  *   Alan Cox <alan@linux.intel.com>
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/dmi.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/types.h>
  20
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25
  26 #include "pinctrl-intel.h"
  27
  28 #define CHV_INTSTAT                     0x300
  29 #define CHV_INTMASK                     0x380
  30
  31 #define FAMILY_PAD_REGS_OFF             0x4400
  32 #define FAMILY_PAD_REGS_SIZE            0x400
  33 #define MAX_FAMILY_PAD_GPIO_NO          15
  34 #define GPIO_REGS_SIZE                  8
  35
  36 #define CHV_PADCTRL0                    0x000
  37 #define CHV_PADCTRL0_INTSEL_SHIFT       28
  38 #define CHV_PADCTRL0_INTSEL_MASK        GENMASK(31, 28)
  39 #define CHV_PADCTRL0_TERM_UP            BIT(23)
  40 #define CHV_PADCTRL0_TERM_SHIFT         20
  41 #define CHV_PADCTRL0_TERM_MASK          GENMASK(22, 20)
  42 #define CHV_PADCTRL0_TERM_20K           1
  43 #define CHV_PADCTRL0_TERM_5K            2
  44 #define CHV_PADCTRL0_TERM_1K            4
  45 #define CHV_PADCTRL0_PMODE_SHIFT        16
  46 #define CHV_PADCTRL0_PMODE_MASK         GENMASK(19, 16)
  47 #define CHV_PADCTRL0_GPIOEN             BIT(15)
  48 #define CHV_PADCTRL0_GPIOCFG_SHIFT      8
  49 #define CHV_PADCTRL0_GPIOCFG_MASK       GENMASK(10, 8)
  50 #define CHV_PADCTRL0_GPIOCFG_GPIO       0
  51 #define CHV_PADCTRL0_GPIOCFG_GPO        1
  52 #define CHV_PADCTRL0_GPIOCFG_GPI        2
  53 #define CHV_PADCTRL0_GPIOCFG_HIZ        3
  54 #define CHV_PADCTRL0_GPIOTXSTATE        BIT(1)
  55 #define CHV_PADCTRL0_GPIORXSTATE        BIT(0)
  56
  57 #define CHV_PADCTRL1                    0x004
  58 #define CHV_PADCTRL1_CFGLOCK            BIT(31)
  59 #define CHV_PADCTRL1_INVRXTX_SHIFT      4
  60 #define CHV_PADCTRL1_INVRXTX_MASK       GENMASK(7, 4)
  61 #define CHV_PADCTRL1_INVRXTX_RXDATA     BIT(6)
  62 #define CHV_PADCTRL1_INVRXTX_TXENABLE   BIT(5)
  63 #define CHV_PADCTRL1_ODEN               BIT(3)
  64 #define CHV_PADCTRL1_INTWAKECFG_MASK    GENMASK(2, 0)
  65 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
  66 #define CHV_PADCTRL1_INTWAKECFG_RISING  2
  67 #define CHV_PADCTRL1_INTWAKECFG_BOTH    3
  68 #define CHV_PADCTRL1_INTWAKECFG_LEVEL   4
  69
  70 /**
  71  * struct chv_community - A community specific configuration
  72  * @uid: ACPI _UID used to match the community
  73  * @pins: All pins in this community
  74  * @npins: Number of pins
  75  * @groups: All groups in this community
  76  * @ngroups: Number of groups
  77  * @functions: All functions in this community
  78  * @nfunctions: Number of functions
  79  * @gpps: Pad groups
  80  * @ngpps: Number of pad groups in this community
  81  * @nirqs: Total number of IRQs this community can generate
  82  * @acpi_space_id: An address space ID for ACPI OpRegion handler
  83  */
  84 struct chv_community {
  85         const char *uid;
  86         const struct pinctrl_pin_desc *pins;
  87         size_t npins;
  88         const struct intel_pingroup *groups;
  89         size_t ngroups;
  90         const struct intel_function *functions;
  91         size_t nfunctions;
  92         const struct intel_padgroup *gpps;
  93         size_t ngpps;
  94         size_t nirqs;
  95         acpi_adr_space_type acpi_space_id;
  96 };
  97
  98 struct chv_pin_context {
  99         u32 padctrl0;
 100         u32 padctrl1;
 101 };
 102
 103 /**
 104  * struct chv_pinctrl - CHV pinctrl private structure
 105  * @dev: Pointer to the parent device
 106  * @pctldesc: Pin controller description
 107  * @pctldev: Pointer to the pin controller device
 108  * @chip: GPIO chip in this pin controller
 109  * @irqchip: IRQ chip in this pin controller
 110  * @regs: MMIO registers
 111  * @irq: Our parent irq
 112  * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
 113  *              offset (in GPIO number space)
 114  * @community: Community this pinctrl instance represents
 115  * @saved_intmask: Interrupt mask saved for system sleep
 116  * @saved_pin_context: Pointer to a context of the pins saved for system sleep
 117  *
 118  * The first group in @groups is expected to contain all pins that can be
 119  * used as GPIOs.
 120  */
 121 struct chv_pinctrl {
 122         struct device *dev;
 123         struct pinctrl_desc pctldesc;
 124         struct pinctrl_dev *pctldev;
 125         struct gpio_chip chip;
 126         struct irq_chip irqchip;
 127         void __iomem *regs;
 128         unsigned int irq;
 129         unsigned int intr_lines[16];
 130         const struct chv_community *community;
 131         u32 saved_intmask;
 132         struct chv_pin_context *saved_pin_context;
 133 };
 134
 135 #define PINMODE_INVERT_OE       BIT(15)
 136
 137 #define PINMODE(m, i)           ((m) | ((i) * PINMODE_INVERT_OE))
 138
 139 #define CHV_GPP(start, end)             \
 140         {                                       \
 141                 .base = (start),                \
 142                 .size = (end) - (start) + 1,    \
 143         }
 144
 145 static const struct pinctrl_pin_desc southwest_pins[] = {
 146         PINCTRL_PIN(0, "FST_SPI_D2"),
 147         PINCTRL_PIN(1, "FST_SPI_D0"),
 148         PINCTRL_PIN(2, "FST_SPI_CLK"),
 149         PINCTRL_PIN(3, "FST_SPI_D3"),
 150         PINCTRL_PIN(4, "FST_SPI_CS1_B"),
 151         PINCTRL_PIN(5, "FST_SPI_D1"),
 152         PINCTRL_PIN(6, "FST_SPI_CS0_B"),
 153         PINCTRL_PIN(7, "FST_SPI_CS2_B"),
 154
 155         PINCTRL_PIN(15, "UART1_RTS_B"),
 156         PINCTRL_PIN(16, "UART1_RXD"),
 157         PINCTRL_PIN(17, "UART2_RXD"),
 158         PINCTRL_PIN(18, "UART1_CTS_B"),
 159         PINCTRL_PIN(19, "UART2_RTS_B"),
 160         PINCTRL_PIN(20, "UART1_TXD"),
 161         PINCTRL_PIN(21, "UART2_TXD"),
 162         PINCTRL_PIN(22, "UART2_CTS_B"),
 163
 164         PINCTRL_PIN(30, "MF_HDA_CLK"),
 165         PINCTRL_PIN(31, "MF_HDA_RSTB"),
 166         PINCTRL_PIN(32, "MF_HDA_SDIO"),
 167         PINCTRL_PIN(33, "MF_HDA_SDO"),
 168         PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
 169         PINCTRL_PIN(35, "MF_HDA_SYNC"),
 170         PINCTRL_PIN(36, "MF_HDA_SDI1"),
 171         PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
 172
 173         PINCTRL_PIN(45, "I2C5_SDA"),
 174         PINCTRL_PIN(46, "I2C4_SDA"),
 175         PINCTRL_PIN(47, "I2C6_SDA"),
 176         PINCTRL_PIN(48, "I2C5_SCL"),
 177         PINCTRL_PIN(49, "I2C_NFC_SDA"),
 178         PINCTRL_PIN(50, "I2C4_SCL"),
 179         PINCTRL_PIN(51, "I2C6_SCL"),
 180         PINCTRL_PIN(52, "I2C_NFC_SCL"),
 181
 182         PINCTRL_PIN(60, "I2C1_SDA"),
 183         PINCTRL_PIN(61, "I2C0_SDA"),
 184         PINCTRL_PIN(62, "I2C2_SDA"),
 185         PINCTRL_PIN(63, "I2C1_SCL"),
 186         PINCTRL_PIN(64, "I2C3_SDA"),
 187         PINCTRL_PIN(65, "I2C0_SCL"),
 188         PINCTRL_PIN(66, "I2C2_SCL"),
 189         PINCTRL_PIN(67, "I2C3_SCL"),
 190
 191         PINCTRL_PIN(75, "SATA_GP0"),
 192         PINCTRL_PIN(76, "SATA_GP1"),
 193         PINCTRL_PIN(77, "SATA_LEDN"),
 194         PINCTRL_PIN(78, "SATA_GP2"),
 195         PINCTRL_PIN(79, "MF_SMB_ALERTB"),
 196         PINCTRL_PIN(80, "SATA_GP3"),
 197         PINCTRL_PIN(81, "MF_SMB_CLK"),
 198         PINCTRL_PIN(82, "MF_SMB_DATA"),
 199
 200         PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
 201         PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
 202         PINCTRL_PIN(92, "GP_SSP_2_CLK"),
 203         PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
 204         PINCTRL_PIN(94, "GP_SSP_2_RXD"),
 205         PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
 206         PINCTRL_PIN(96, "GP_SSP_2_FS"),
 207         PINCTRL_PIN(97, "GP_SSP_2_TXD"),
 208 };
 209
 210 static const unsigned southwest_uart0_pins[] = { 16, 20 };
 211 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
 212 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
 213 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
 214 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
 215 static const unsigned southwest_lpe_pins[] = {
 216         30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
 217 };
 218 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
 219 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
 220 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
 221 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
 222 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
 223 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
 224 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
 225 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
 226
 227 /* Some of LPE I2S TXD pins need to have OE inversion set */
 228 static const unsigned int southwest_lpe_altfuncs[] = {
 229         PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */
 230         PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */
 231         PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */
 232 };
 233
 234 /*
 235  * Two spi3 chipselects are available in different mode than the main spi3
 236  * functionality, which is using mode 2.
 237  */
 238 static const unsigned int southwest_spi3_altfuncs[] = {
 239         PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */
 240         PINMODE(2, 0),                                              /* 82 */
 241 };
 242
 243 static const struct intel_pingroup southwest_groups[] = {
 244         PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)),
 245         PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)),
 246         PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)),
 247         PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)),
 248         PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)),
 249         PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)),
 250         PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)),
 251         PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)),
 252         PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)),
 253         PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)),
 254         PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)),
 255         PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)),
 256         PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs),
 257         PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs),
 258 };
 259
 260 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
 261 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
 262 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
 263 static const char * const southwest_hda_groups[] = { "hda_grp" };
 264 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
 265 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
 266 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
 267 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
 268 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
 269 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
 270 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
 271 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
 272 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
 273 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
 274
 275 /*
 276  * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
 277  * enabled only as GPIOs.
 278  */
 279 static const struct intel_function southwest_functions[] = {
 280         FUNCTION("uart0", southwest_uart0_groups),
 281         FUNCTION("uart1", southwest_uart1_groups),
 282         FUNCTION("uart2", southwest_uart2_groups),
 283         FUNCTION("hda", southwest_hda_groups),
 284         FUNCTION("lpe", southwest_lpe_groups),
 285         FUNCTION("i2c0", southwest_i2c0_groups),
 286         FUNCTION("i2c1", southwest_i2c1_groups),
 287         FUNCTION("i2c2", southwest_i2c2_groups),
 288         FUNCTION("i2c3", southwest_i2c3_groups),
 289         FUNCTION("i2c4", southwest_i2c4_groups),
 290         FUNCTION("i2c5", southwest_i2c5_groups),
 291         FUNCTION("i2c6", southwest_i2c6_groups),
 292         FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
 293         FUNCTION("spi3", southwest_spi3_groups),
 294 };
 295
 296 static const struct intel_padgroup southwest_gpps[] = {
 297         CHV_GPP(0, 7),
 298         CHV_GPP(15, 22),
 299         CHV_GPP(30, 37),
 300         CHV_GPP(45, 52),
 301         CHV_GPP(60, 67),
 302         CHV_GPP(75, 82),
 303         CHV_GPP(90, 97),
 304 };
 305
 306 static const struct chv_community southwest_community = {
 307         .uid = "1",
 308         .pins = southwest_pins,
 309         .npins = ARRAY_SIZE(southwest_pins),
 310         .groups = southwest_groups,
 311         .ngroups = ARRAY_SIZE(southwest_groups),
 312         .functions = southwest_functions,
 313         .nfunctions = ARRAY_SIZE(southwest_functions),
 314         .gpps = southwest_gpps,
 315         .ngpps = ARRAY_SIZE(southwest_gpps),
 316         /*
 317          * Southwest community can generate GPIO interrupts only for the
 318          * first 8 interrupts. The upper half (8-15) can only be used to
 319          * trigger GPEs.
 320          */
 321         .nirqs = 8,
 322         .acpi_space_id = 0x91,
 323 };
 324
 325 static const struct pinctrl_pin_desc north_pins[] = {
 326         PINCTRL_PIN(0, "GPIO_DFX_0"),
 327         PINCTRL_PIN(1, "GPIO_DFX_3"),
 328         PINCTRL_PIN(2, "GPIO_DFX_7"),
 329         PINCTRL_PIN(3, "GPIO_DFX_1"),
 330         PINCTRL_PIN(4, "GPIO_DFX_5"),
 331         PINCTRL_PIN(5, "GPIO_DFX_4"),
 332         PINCTRL_PIN(6, "GPIO_DFX_8"),
 333         PINCTRL_PIN(7, "GPIO_DFX_2"),
 334         PINCTRL_PIN(8, "GPIO_DFX_6"),
 335
 336         PINCTRL_PIN(15, "GPIO_SUS0"),
 337         PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
 338         PINCTRL_PIN(17, "GPIO_SUS3"),
 339         PINCTRL_PIN(18, "GPIO_SUS7"),
 340         PINCTRL_PIN(19, "GPIO_SUS1"),
 341         PINCTRL_PIN(20, "GPIO_SUS5"),
 342         PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
 343         PINCTRL_PIN(22, "GPIO_SUS4"),
 344         PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
 345         PINCTRL_PIN(24, "GPIO_SUS2"),
 346         PINCTRL_PIN(25, "GPIO_SUS6"),
 347         PINCTRL_PIN(26, "CX_PREQ_B"),
 348         PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
 349
 350         PINCTRL_PIN(30, "TRST_B"),
 351         PINCTRL_PIN(31, "TCK"),
 352         PINCTRL_PIN(32, "PROCHOT_B"),
 353         PINCTRL_PIN(33, "SVIDO_DATA"),
 354         PINCTRL_PIN(34, "TMS"),
 355         PINCTRL_PIN(35, "CX_PRDY_B_2"),
 356         PINCTRL_PIN(36, "TDO_2"),
 357         PINCTRL_PIN(37, "CX_PRDY_B"),
 358         PINCTRL_PIN(38, "SVIDO_ALERT_B"),
 359         PINCTRL_PIN(39, "TDO"),
 360         PINCTRL_PIN(40, "SVIDO_CLK"),
 361         PINCTRL_PIN(41, "TDI"),
 362
 363         PINCTRL_PIN(45, "GP_CAMERASB_05"),
 364         PINCTRL_PIN(46, "GP_CAMERASB_02"),
 365         PINCTRL_PIN(47, "GP_CAMERASB_08"),
 366         PINCTRL_PIN(48, "GP_CAMERASB_00"),
 367         PINCTRL_PIN(49, "GP_CAMERASB_06"),
 368         PINCTRL_PIN(50, "GP_CAMERASB_10"),
 369         PINCTRL_PIN(51, "GP_CAMERASB_03"),
 370         PINCTRL_PIN(52, "GP_CAMERASB_09"),
 371         PINCTRL_PIN(53, "GP_CAMERASB_01"),
 372         PINCTRL_PIN(54, "GP_CAMERASB_07"),
 373         PINCTRL_PIN(55, "GP_CAMERASB_11"),
 374         PINCTRL_PIN(56, "GP_CAMERASB_04"),
 375
 376         PINCTRL_PIN(60, "PANEL0_BKLTEN"),
 377         PINCTRL_PIN(61, "HV_DDI0_HPD"),
 378         PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
 379         PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
 380         PINCTRL_PIN(64, "HV_DDI1_HPD"),
 381         PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
 382         PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
 383         PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
 384         PINCTRL_PIN(68, "HV_DDI2_HPD"),
 385         PINCTRL_PIN(69, "PANEL1_VDDEN"),
 386         PINCTRL_PIN(70, "PANEL1_BKLTEN"),
 387         PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
 388         PINCTRL_PIN(72, "PANEL0_VDDEN"),
 389 };
 390
 391 static const struct intel_padgroup north_gpps[] = {
 392         CHV_GPP(0, 8),
 393         CHV_GPP(15, 27),
 394         CHV_GPP(30, 41),
 395         CHV_GPP(45, 56),
 396         CHV_GPP(60, 72),
 397 };
 398
 399 static const struct chv_community north_community = {
 400         .uid = "2",
 401         .pins = north_pins,
 402         .npins = ARRAY_SIZE(north_pins),
 403         .gpps = north_gpps,
 404         .ngpps = ARRAY_SIZE(north_gpps),
 405         /*
 406          * North community can generate GPIO interrupts only for the first
 407          * 8 interrupts. The upper half (8-15) can only be used to trigger
 408          * GPEs.
 409          */
 410         .nirqs = 8,
 411         .acpi_space_id = 0x92,
 412 };
 413
 414 static const struct pinctrl_pin_desc east_pins[] = {
 415         PINCTRL_PIN(0, "PMU_SLP_S3_B"),
 416         PINCTRL_PIN(1, "PMU_BATLOW_B"),
 417         PINCTRL_PIN(2, "SUS_STAT_B"),
 418         PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
 419         PINCTRL_PIN(4, "PMU_AC_PRESENT"),
 420         PINCTRL_PIN(5, "PMU_PLTRST_B"),
 421         PINCTRL_PIN(6, "PMU_SUSCLK"),
 422         PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
 423         PINCTRL_PIN(8, "PMU_PWRBTN_B"),
 424         PINCTRL_PIN(9, "PMU_SLP_S4_B"),
 425         PINCTRL_PIN(10, "PMU_WAKE_B"),
 426         PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
 427
 428         PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
 429         PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
 430         PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
 431         PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
 432         PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
 433         PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
 434         PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
 435         PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
 436         PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
 437         PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
 438         PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
 439         PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
 440 };
 441
 442 static const struct intel_padgroup east_gpps[] = {
 443         CHV_GPP(0, 11),
 444         CHV_GPP(15, 26),
 445 };
 446
 447 static const struct chv_community east_community = {
 448         .uid = "3",
 449         .pins = east_pins,
 450         .npins = ARRAY_SIZE(east_pins),
 451         .gpps = east_gpps,
 452         .ngpps = ARRAY_SIZE(east_gpps),
 453         .nirqs = 16,
 454         .acpi_space_id = 0x93,
 455 };
 456
 457 static const struct pinctrl_pin_desc southeast_pins[] = {
 458         PINCTRL_PIN(0, "MF_PLT_CLK0"),
 459         PINCTRL_PIN(1, "PWM1"),
 460         PINCTRL_PIN(2, "MF_PLT_CLK1"),
 461         PINCTRL_PIN(3, "MF_PLT_CLK4"),
 462         PINCTRL_PIN(4, "MF_PLT_CLK3"),
 463         PINCTRL_PIN(5, "PWM0"),
 464         PINCTRL_PIN(6, "MF_PLT_CLK5"),
 465         PINCTRL_PIN(7, "MF_PLT_CLK2"),
 466
 467         PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
 468         PINCTRL_PIN(16, "SDMMC1_CLK"),
 469         PINCTRL_PIN(17, "SDMMC1_D0"),
 470         PINCTRL_PIN(18, "SDMMC2_D1"),
 471         PINCTRL_PIN(19, "SDMMC2_CLK"),
 472         PINCTRL_PIN(20, "SDMMC1_D2"),
 473         PINCTRL_PIN(21, "SDMMC2_D2"),
 474         PINCTRL_PIN(22, "SDMMC2_CMD"),
 475         PINCTRL_PIN(23, "SDMMC1_CMD"),
 476         PINCTRL_PIN(24, "SDMMC1_D1"),
 477         PINCTRL_PIN(25, "SDMMC2_D0"),
 478         PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
 479
 480         PINCTRL_PIN(30, "SDMMC3_D1"),
 481         PINCTRL_PIN(31, "SDMMC3_CLK"),
 482         PINCTRL_PIN(32, "SDMMC3_D3"),
 483         PINCTRL_PIN(33, "SDMMC3_D2"),
 484         PINCTRL_PIN(34, "SDMMC3_CMD"),
 485         PINCTRL_PIN(35, "SDMMC3_D0"),
 486
 487         PINCTRL_PIN(45, "MF_LPC_AD2"),
 488         PINCTRL_PIN(46, "LPC_CLKRUNB"),
 489         PINCTRL_PIN(47, "MF_LPC_AD0"),
 490         PINCTRL_PIN(48, "LPC_FRAMEB"),
 491         PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
 492         PINCTRL_PIN(50, "MF_LPC_AD3"),
 493         PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
 494         PINCTRL_PIN(52, "MF_LPC_AD1"),
 495
 496         PINCTRL_PIN(60, "SPI1_MISO"),
 497         PINCTRL_PIN(61, "SPI1_CSO_B"),
 498         PINCTRL_PIN(62, "SPI1_CLK"),
 499         PINCTRL_PIN(63, "MMC1_D6"),
 500         PINCTRL_PIN(64, "SPI1_MOSI"),
 501         PINCTRL_PIN(65, "MMC1_D5"),
 502         PINCTRL_PIN(66, "SPI1_CS1_B"),
 503         PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
 504         PINCTRL_PIN(68, "MMC1_D7"),
 505         PINCTRL_PIN(69, "MMC1_RCLK"),
 506
 507         PINCTRL_PIN(75, "USB_OC1_B"),
 508         PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
 509         PINCTRL_PIN(77, "GPIO_ALERT"),
 510         PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
 511         PINCTRL_PIN(79, "ILB_SERIRQ"),
 512         PINCTRL_PIN(80, "USB_OC0_B"),
 513         PINCTRL_PIN(81, "SDMMC3_CD_B"),
 514         PINCTRL_PIN(82, "SPKR"),
 515         PINCTRL_PIN(83, "SUSPWRDNACK"),
 516         PINCTRL_PIN(84, "SPARE_PIN"),
 517         PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
 518 };
 519
 520 static const unsigned southeast_pwm0_pins[] = { 5 };
 521 static const unsigned southeast_pwm1_pins[] = { 1 };
 522 static const unsigned southeast_sdmmc1_pins[] = {
 523         16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
 524 };
 525 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
 526 static const unsigned southeast_sdmmc3_pins[] = {
 527         30, 31, 32, 33, 34, 35, 78, 81, 85,
 528 };
 529 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
 530 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
 531
 532 static const struct intel_pingroup southeast_groups[] = {
 533         PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)),
 534         PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)),
 535         PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)),
 536         PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)),
 537         PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)),
 538         PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)),
 539         PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)),
 540 };
 541
 542 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
 543 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
 544 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
 545 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
 546 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
 547 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
 548 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
 549
 550 static const struct intel_function southeast_functions[] = {
 551         FUNCTION("pwm0", southeast_pwm0_groups),
 552         FUNCTION("pwm1", southeast_pwm1_groups),
 553         FUNCTION("sdmmc1", southeast_sdmmc1_groups),
 554         FUNCTION("sdmmc2", southeast_sdmmc2_groups),
 555         FUNCTION("sdmmc3", southeast_sdmmc3_groups),
 556         FUNCTION("spi1", southeast_spi1_groups),
 557         FUNCTION("spi2", southeast_spi2_groups),
 558 };
 559
 560 static const struct intel_padgroup southeast_gpps[] = {
 561         CHV_GPP(0, 7),
 562         CHV_GPP(15, 26),
 563         CHV_GPP(30, 35),
 564         CHV_GPP(45, 52),
 565         CHV_GPP(60, 69),
 566         CHV_GPP(75, 85),
 567 };
 568
 569 static const struct chv_community southeast_community = {
 570         .uid = "4",
 571         .pins = southeast_pins,
 572         .npins = ARRAY_SIZE(southeast_pins),
 573         .groups = southeast_groups,
 574         .ngroups = ARRAY_SIZE(southeast_groups),
 575         .functions = southeast_functions,
 576         .nfunctions = ARRAY_SIZE(southeast_functions),
 577         .gpps = southeast_gpps,
 578         .ngpps = ARRAY_SIZE(southeast_gpps),
 579         .nirqs = 16,
 580         .acpi_space_id = 0x94,
 581 };
 582
 583 static const struct chv_community *chv_communities[] = {
 584         &southwest_community,
 585         &north_community,
 586         &east_community,
 587         &southeast_community,
 588 };
 589
 590 /*
 591  * Lock to serialize register accesses
 592  *
 593  * Due to a silicon issue, a shared lock must be used to prevent
 594  * concurrent accesses across the 4 GPIO controllers.
 595  *
 596  * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
 597  * errata #CHT34, for further information.
 598  */
 599 static DEFINE_RAW_SPINLOCK(chv_lock);
 600
 601 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
 602                                 unsigned int reg)
 603 {
 604         unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
 605         unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
 606
 607         offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
 608                  GPIO_REGS_SIZE * pad_no;
 609
 610         return pctrl->regs + offset + reg;
 611 }
 612
 613 static void chv_writel(u32 value, void __iomem *reg)
 614 {
 615         writel(value, reg);
 616         /* simple readback to confirm the bus transferring done */
 617         readl(reg);
 618 }
 619
 620 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
 621 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset)
 622 {
 623         void __iomem *reg;
 624
 625         reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
 626         return readl(reg) & CHV_PADCTRL1_CFGLOCK;
 627 }
 628
 629 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
 630 {
 631         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 632
 633         return pctrl->community->ngroups;
 634 }
 635
 636 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
 637                                       unsigned int group)
 638 {
 639         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 640
 641         return pctrl->community->groups[group].name;
 642 }
 643
 644 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 645                               const unsigned int **pins, unsigned int *npins)
 646 {
 647         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 648
 649         *pins = pctrl->community->groups[group].pins;
 650         *npins = pctrl->community->groups[group].npins;
 651         return 0;
 652 }
 653
 654 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 655                              unsigned int offset)
 656 {
 657         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 658         unsigned long flags;
 659         u32 ctrl0, ctrl1;
 660         bool locked;
 661
 662         raw_spin_lock_irqsave(&chv_lock, flags);
 663
 664         ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
 665         ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
 666         locked = chv_pad_locked(pctrl, offset);
 667
 668         raw_spin_unlock_irqrestore(&chv_lock, flags);
 669
 670         if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
 671                 seq_puts(s, "GPIO ");
 672         } else {
 673                 u32 mode;
 674
 675                 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
 676                 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
 677
 678                 seq_printf(s, "mode %d ", mode);
 679         }
 680
 681         seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
 682
 683         if (locked)
 684                 seq_puts(s, " [LOCKED]");
 685 }
 686
 687 static const struct pinctrl_ops chv_pinctrl_ops = {
 688         .get_groups_count = chv_get_groups_count,
 689         .get_group_name = chv_get_group_name,
 690         .get_group_pins = chv_get_group_pins,
 691         .pin_dbg_show = chv_pin_dbg_show,
 692 };
 693
 694 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
 695 {
 696         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 697
 698         return pctrl->community->nfunctions;
 699 }
 700
 701 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
 702                                          unsigned int function)
 703 {
 704         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 705
 706         return pctrl->community->functions[function].name;
 707 }
 708
 709 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
 710                                    unsigned int function,
 711                                    const char * const **groups,
 712                                    unsigned int * const ngroups)
 713 {
 714         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 715
 716         *groups = pctrl->community->functions[function].groups;
 717         *ngroups = pctrl->community->functions[function].ngroups;
 718         return 0;
 719 }
 720
 721 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
 722                               unsigned int function, unsigned int group)
 723 {
 724         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 725         const struct intel_pingroup *grp;
 726         unsigned long flags;
 727         int i;
 728
 729         grp = &pctrl->community->groups[group];
 730
 731         raw_spin_lock_irqsave(&chv_lock, flags);
 732
 733         /* Check first that the pad is not locked */
 734         for (i = 0; i < grp->npins; i++) {
 735                 if (chv_pad_locked(pctrl, grp->pins[i])) {
 736                         dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
 737                                  grp->pins[i]);
 738                         raw_spin_unlock_irqrestore(&chv_lock, flags);
 739                         return -EBUSY;
 740                 }
 741         }
 742
 743         for (i = 0; i < grp->npins; i++) {
 744                 int pin = grp->pins[i];
 745                 void __iomem *reg;
 746                 unsigned int mode;
 747                 bool invert_oe;
 748                 u32 value;
 749
 750                 /* Check if there is pin-specific config */
 751                 if (grp->modes)
 752                         mode = grp->modes[i];
 753                 else
 754                         mode = grp->mode;
 755
 756                 /* Extract OE inversion */
 757                 invert_oe = mode & PINMODE_INVERT_OE;
 758                 mode &= ~PINMODE_INVERT_OE;
 759
 760                 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
 761                 value = readl(reg);
 762                 /* Disable GPIO mode */
 763                 value &= ~CHV_PADCTRL0_GPIOEN;
 764                 /* Set to desired mode */
 765                 value &= ~CHV_PADCTRL0_PMODE_MASK;
 766                 value |= mode << CHV_PADCTRL0_PMODE_SHIFT;
 767                 chv_writel(value, reg);
 768
 769                 /* Update for invert_oe */
 770                 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
 771                 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
 772                 if (invert_oe)
 773                         value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
 774                 chv_writel(value, reg);
 775
 776                 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
 777                         pin, mode, invert_oe ? "" : "not ");
 778         }
 779
 780         raw_spin_unlock_irqrestore(&chv_lock, flags);
 781
 782         return 0;
 783 }
 784
 785 static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl,
 786                                       unsigned int offset)
 787 {
 788         void __iomem *reg;
 789         u32 value;
 790
 791         reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
 792         value = readl(reg);
 793         value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
 794         value &= ~CHV_PADCTRL1_INVRXTX_MASK;
 795         chv_writel(value, reg);
 796 }
 797
 798 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
 799                                    struct pinctrl_gpio_range *range,
 800                                    unsigned int offset)
 801 {
 802         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 803         unsigned long flags;
 804         void __iomem *reg;
 805         u32 value;
 806
 807         raw_spin_lock_irqsave(&chv_lock, flags);
 808
 809         if (chv_pad_locked(pctrl, offset)) {
 810                 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
 811                 if (!(value & CHV_PADCTRL0_GPIOEN)) {
 812                         /* Locked so cannot enable */
 813                         raw_spin_unlock_irqrestore(&chv_lock, flags);
 814                         return -EBUSY;
 815                 }
 816         } else {
 817                 int i;
 818
 819                 /* Reset the interrupt mapping */
 820                 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
 821                         if (pctrl->intr_lines[i] == offset) {
 822                                 pctrl->intr_lines[i] = 0;
 823                                 break;
 824                         }
 825                 }
 826
 827                 /* Disable interrupt generation */
 828                 chv_gpio_clear_triggering(pctrl, offset);
 829
 830                 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
 831                 value = readl(reg);
 832
 833                 /*
 834                  * If the pin is in HiZ mode (both TX and RX buffers are
 835                  * disabled) we turn it to be input now.
 836                  */
 837                 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
 838                      (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
 839                         value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
 840                         value |= CHV_PADCTRL0_GPIOCFG_GPI <<
 841                                 CHV_PADCTRL0_GPIOCFG_SHIFT;
 842                 }
 843
 844                 /* Switch to a GPIO mode */
 845                 value |= CHV_PADCTRL0_GPIOEN;
 846                 chv_writel(value, reg);
 847         }
 848
 849         raw_spin_unlock_irqrestore(&chv_lock, flags);
 850
 851         return 0;
 852 }
 853
 854 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
 855                                   struct pinctrl_gpio_range *range,
 856                                   unsigned int offset)
 857 {
 858         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 859         unsigned long flags;
 860
 861         raw_spin_lock_irqsave(&chv_lock, flags);
 862
 863         if (!chv_pad_locked(pctrl, offset))
 864                 chv_gpio_clear_triggering(pctrl, offset);
 865
 866         raw_spin_unlock_irqrestore(&chv_lock, flags);
 867 }
 868
 869 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
 870                                   struct pinctrl_gpio_range *range,
 871                                   unsigned int offset, bool input)
 872 {
 873         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 874         void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
 875         unsigned long flags;
 876         u32 ctrl0;
 877
 878         raw_spin_lock_irqsave(&chv_lock, flags);
 879
 880         ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
 881         if (input)
 882                 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
 883         else
 884                 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
 885         chv_writel(ctrl0, reg);
 886
 887         raw_spin_unlock_irqrestore(&chv_lock, flags);
 888
 889         return 0;
 890 }
 891
 892 static const struct pinmux_ops chv_pinmux_ops = {
 893         .get_functions_count = chv_get_functions_count,
 894         .get_function_name = chv_get_function_name,
 895         .get_function_groups = chv_get_function_groups,
 896         .set_mux = chv_pinmux_set_mux,
 897         .gpio_request_enable = chv_gpio_request_enable,
 898         .gpio_disable_free = chv_gpio_disable_free,
 899         .gpio_set_direction = chv_gpio_set_direction,
 900 };
 901
 902 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 903                           unsigned long *config)
 904 {
 905         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 906         enum pin_config_param param = pinconf_to_config_param(*config);
 907         unsigned long flags;
 908         u32 ctrl0, ctrl1;
 909         u16 arg = 0;
 910         u32 term;
 911
 912         raw_spin_lock_irqsave(&chv_lock, flags);
 913         ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
 914         ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
 915         raw_spin_unlock_irqrestore(&chv_lock, flags);
 916
 917         term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
 918
 919         switch (param) {
 920         case PIN_CONFIG_BIAS_DISABLE:
 921                 if (term)
 922                         return -EINVAL;
 923                 break;
 924
 925         case PIN_CONFIG_BIAS_PULL_UP:
 926                 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
 927                         return -EINVAL;
 928
 929                 switch (term) {
 930                 case CHV_PADCTRL0_TERM_20K:
 931                         arg = 20000;
 932                         break;
 933                 case CHV_PADCTRL0_TERM_5K:
 934                         arg = 5000;
 935                         break;
 936                 case CHV_PADCTRL0_TERM_1K:
 937                         arg = 1000;
 938                         break;
 939                 }
 940
 941                 break;
 942
 943         case PIN_CONFIG_BIAS_PULL_DOWN:
 944                 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
 945                         return -EINVAL;
 946
 947                 switch (term) {
 948                 case CHV_PADCTRL0_TERM_20K:
 949                         arg = 20000;
 950                         break;
 951                 case CHV_PADCTRL0_TERM_5K:
 952                         arg = 5000;
 953                         break;
 954                 }
 955
 956                 break;
 957
 958         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 959                 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
 960                         return -EINVAL;
 961                 break;
 962
 963         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
 964                 u32 cfg;
 965
 966                 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
 967                 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
 968                 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
 969                         return -EINVAL;
 970
 971                 break;
 972         }
 973
 974         default:
 975                 return -ENOTSUPP;
 976         }
 977
 978         *config = pinconf_to_config_packed(param, arg);
 979         return 0;
 980 }
 981
 982 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin,
 983                                enum pin_config_param param, u32 arg)
 984 {
 985         void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
 986         unsigned long flags;
 987         u32 ctrl0, pull;
 988
 989         raw_spin_lock_irqsave(&chv_lock, flags);
 990         ctrl0 = readl(reg);
 991
 992         switch (param) {
 993         case PIN_CONFIG_BIAS_DISABLE:
 994                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
 995                 break;
 996
 997         case PIN_CONFIG_BIAS_PULL_UP:
 998                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
 999
1000                 switch (arg) {
1001                 case 1000:
1002                         /* For 1k there is only pull up */
1003                         pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1004                         break;
1005                 case 5000:
1006                         pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1007                         break;
1008                 case 20000:
1009                         pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1010                         break;
1011                 default:
1012                         raw_spin_unlock_irqrestore(&chv_lock, flags);
1013                         return -EINVAL;
1014                 }
1015
1016                 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1017                 break;
1018
1019         case PIN_CONFIG_BIAS_PULL_DOWN:
1020                 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1021
1022                 switch (arg) {
1023                 case 5000:
1024                         pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1025                         break;
1026                 case 20000:
1027                         pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1028                         break;
1029                 default:
1030                         raw_spin_unlock_irqrestore(&chv_lock, flags);
1031                         return -EINVAL;
1032                 }
1033
1034                 ctrl0 |= pull;
1035                 break;
1036
1037         default:
1038                 raw_spin_unlock_irqrestore(&chv_lock, flags);
1039                 return -EINVAL;
1040         }
1041
1042         chv_writel(ctrl0, reg);
1043         raw_spin_unlock_irqrestore(&chv_lock, flags);
1044
1045         return 0;
1046 }
1047
1048 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1049                                bool enable)
1050 {
1051         void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1052         unsigned long flags;
1053         u32 ctrl1;
1054
1055         raw_spin_lock_irqsave(&chv_lock, flags);
1056         ctrl1 = readl(reg);
1057
1058         if (enable)
1059                 ctrl1 |= CHV_PADCTRL1_ODEN;
1060         else
1061                 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1062
1063         chv_writel(ctrl1, reg);
1064         raw_spin_unlock_irqrestore(&chv_lock, flags);
1065
1066         return 0;
1067 }
1068
1069 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1070                           unsigned long *configs, unsigned int nconfigs)
1071 {
1072         struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1073         enum pin_config_param param;
1074         int i, ret;
1075         u32 arg;
1076
1077         if (chv_pad_locked(pctrl, pin))
1078                 return -EBUSY;
1079
1080         for (i = 0; i < nconfigs; i++) {
1081                 param = pinconf_to_config_param(configs[i]);
1082                 arg = pinconf_to_config_argument(configs[i]);
1083
1084                 switch (param) {
1085                 case PIN_CONFIG_BIAS_DISABLE:
1086                 case PIN_CONFIG_BIAS_PULL_UP:
1087                 case PIN_CONFIG_BIAS_PULL_DOWN:
1088                         ret = chv_config_set_pull(pctrl, pin, param, arg);
1089                         if (ret)
1090                                 return ret;
1091                         break;
1092
1093                 case PIN_CONFIG_DRIVE_PUSH_PULL:
1094                         ret = chv_config_set_oden(pctrl, pin, false);
1095                         if (ret)
1096                                 return ret;
1097                         break;
1098
1099                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1100                         ret = chv_config_set_oden(pctrl, pin, true);
1101                         if (ret)
1102                                 return ret;
1103                         break;
1104
1105                 default:
1106                         return -ENOTSUPP;
1107                 }
1108
1109                 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1110                         param, arg);
1111         }
1112
1113         return 0;
1114 }
1115
1116 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1117                                 unsigned int group,
1118                                 unsigned long *config)
1119 {
1120         const unsigned int *pins;
1121         unsigned int npins;
1122         int ret;
1123
1124         ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1125         if (ret)
1126                 return ret;
1127
1128         ret = chv_config_get(pctldev, pins[0], config);
1129         if (ret)
1130                 return ret;
1131
1132         return 0;
1133 }
1134
1135 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1136                                 unsigned int group, unsigned long *configs,
1137                                 unsigned int num_configs)
1138 {
1139         const unsigned int *pins;
1140         unsigned int npins;
1141         int i, ret;
1142
1143         ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1144         if (ret)
1145                 return ret;
1146
1147         for (i = 0; i < npins; i++) {
1148                 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1149                 if (ret)
1150                         return ret;
1151         }
1152
1153         return 0;
1154 }
1155
1156 static const struct pinconf_ops chv_pinconf_ops = {
1157         .is_generic = true,
1158         .pin_config_set = chv_config_set,
1159         .pin_config_get = chv_config_get,
1160         .pin_config_group_get = chv_config_group_get,
1161         .pin_config_group_set = chv_config_group_set,
1162 };
1163
1164 static struct pinctrl_desc chv_pinctrl_desc = {
1165         .pctlops = &chv_pinctrl_ops,
1166         .pmxops = &chv_pinmux_ops,
1167         .confops = &chv_pinconf_ops,
1168         .owner = THIS_MODULE,
1169 };
1170
1171 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
1172 {
1173         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1174         unsigned long flags;
1175         u32 ctrl0, cfg;
1176
1177         raw_spin_lock_irqsave(&chv_lock, flags);
1178         ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1179         raw_spin_unlock_irqrestore(&chv_lock, flags);
1180
1181         cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1182         cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1183
1184         if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1185                 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1186         return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1187 }
1188
1189 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1190 {
1191         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1192         unsigned long flags;
1193         void __iomem *reg;
1194         u32 ctrl0;
1195
1196         raw_spin_lock_irqsave(&chv_lock, flags);
1197
1198         reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
1199         ctrl0 = readl(reg);
1200
1201         if (value)
1202                 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1203         else
1204                 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1205
1206         chv_writel(ctrl0, reg);
1207
1208         raw_spin_unlock_irqrestore(&chv_lock, flags);
1209 }
1210
1211 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1212 {
1213         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1214         u32 ctrl0, direction;
1215         unsigned long flags;
1216
1217         raw_spin_lock_irqsave(&chv_lock, flags);
1218         ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1219         raw_spin_unlock_irqrestore(&chv_lock, flags);
1220
1221         direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1222         direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1223
1224         if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
1225                 return GPIO_LINE_DIRECTION_OUT;
1226
1227         return GPIO_LINE_DIRECTION_IN;
1228 }
1229
1230 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1231 {
1232         return pinctrl_gpio_direction_input(chip->base + offset);
1233 }
1234
1235 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1236                                      int value)
1237 {
1238         chv_gpio_set(chip, offset, value);
1239         return pinctrl_gpio_direction_output(chip->base + offset);
1240 }
1241
1242 static const struct gpio_chip chv_gpio_chip = {
1243         .owner = THIS_MODULE,
1244         .request = gpiochip_generic_request,
1245         .free = gpiochip_generic_free,
1246         .get_direction = chv_gpio_get_direction,
1247         .direction_input = chv_gpio_direction_input,
1248         .direction_output = chv_gpio_direction_output,
1249         .get = chv_gpio_get,
1250         .set = chv_gpio_set,
1251 };
1252
1253 static void chv_gpio_irq_ack(struct irq_data *d)
1254 {
1255         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1256         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1257         int pin = irqd_to_hwirq(d);
1258         u32 intr_line;
1259
1260         raw_spin_lock(&chv_lock);
1261
1262         intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1263         intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1264         intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1265         chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1266
1267         raw_spin_unlock(&chv_lock);
1268 }
1269
1270 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1271 {
1272         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1273         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1274         int pin = irqd_to_hwirq(d);
1275         u32 value, intr_line;
1276         unsigned long flags;
1277
1278         raw_spin_lock_irqsave(&chv_lock, flags);
1279
1280         intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1281         intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1282         intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1283
1284         value = readl(pctrl->regs + CHV_INTMASK);
1285         if (mask)
1286                 value &= ~BIT(intr_line);
1287         else
1288                 value |= BIT(intr_line);
1289         chv_writel(value, pctrl->regs + CHV_INTMASK);
1290
1291         raw_spin_unlock_irqrestore(&chv_lock, flags);
1292 }
1293
1294 static void chv_gpio_irq_mask(struct irq_data *d)
1295 {
1296         chv_gpio_irq_mask_unmask(d, true);
1297 }
1298
1299 static void chv_gpio_irq_unmask(struct irq_data *d)
1300 {
1301         chv_gpio_irq_mask_unmask(d, false);
1302 }
1303
1304 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1305 {
1306         /*
1307          * Check if the interrupt has been requested with 0 as triggering
1308          * type. In that case it is assumed that the current values
1309          * programmed to the hardware are used (e.g BIOS configured
1310          * defaults).
1311          *
1312          * In that case ->irq_set_type() will never be called so we need to
1313          * read back the values from hardware now, set correct flow handler
1314          * and update mappings before the interrupt is being used.
1315          */
1316         if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1317                 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1318                 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1319                 unsigned int pin = irqd_to_hwirq(d);
1320                 irq_flow_handler_t handler;
1321                 unsigned long flags;
1322                 u32 intsel, value;
1323
1324                 raw_spin_lock_irqsave(&chv_lock, flags);
1325                 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1326                 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1327                 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1328
1329                 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1330                 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1331                         handler = handle_level_irq;
1332                 else
1333                         handler = handle_edge_irq;
1334
1335                 if (!pctrl->intr_lines[intsel]) {
1336                         irq_set_handler_locked(d, handler);
1337                         pctrl->intr_lines[intsel] = pin;
1338                 }
1339                 raw_spin_unlock_irqrestore(&chv_lock, flags);
1340         }
1341
1342         chv_gpio_irq_unmask(d);
1343         return 0;
1344 }
1345
1346 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
1347 {
1348         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1349         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1350         unsigned int pin = irqd_to_hwirq(d);
1351         unsigned long flags;
1352         u32 value;
1353
1354         raw_spin_lock_irqsave(&chv_lock, flags);
1355
1356         /*
1357          * Pins which can be used as shared interrupt are configured in
1358          * BIOS. Driver trusts BIOS configurations and assigns different
1359          * handler according to the irq type.
1360          *
1361          * Driver needs to save the mapping between each pin and
1362          * its interrupt line.
1363          * 1. If the pin cfg is locked in BIOS:
1364          *      Trust BIOS has programmed IntWakeCfg bits correctly,
1365          *      driver just needs to save the mapping.
1366          * 2. If the pin cfg is not locked in BIOS:
1367          *      Driver programs the IntWakeCfg bits and save the mapping.
1368          */
1369         if (!chv_pad_locked(pctrl, pin)) {
1370                 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1371
1372                 value = readl(reg);
1373                 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1374                 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1375
1376                 if (type & IRQ_TYPE_EDGE_BOTH) {
1377                         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1378                                 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1379                         else if (type & IRQ_TYPE_EDGE_RISING)
1380                                 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1381                         else if (type & IRQ_TYPE_EDGE_FALLING)
1382                                 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1383                 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1384                         value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1385                         if (type & IRQ_TYPE_LEVEL_LOW)
1386                                 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1387                 }
1388
1389                 chv_writel(value, reg);
1390         }
1391
1392         value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1393         value &= CHV_PADCTRL0_INTSEL_MASK;
1394         value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1395
1396         pctrl->intr_lines[value] = pin;
1397
1398         if (type & IRQ_TYPE_EDGE_BOTH)
1399                 irq_set_handler_locked(d, handle_edge_irq);
1400         else if (type & IRQ_TYPE_LEVEL_MASK)
1401                 irq_set_handler_locked(d, handle_level_irq);
1402
1403         raw_spin_unlock_irqrestore(&chv_lock, flags);
1404
1405         return 0;
1406 }
1407
1408 static void chv_gpio_irq_handler(struct irq_desc *desc)
1409 {
1410         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1411         struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1412         struct irq_chip *chip = irq_desc_get_chip(desc);
1413         unsigned long pending;
1414         unsigned long flags;
1415         u32 intr_line;
1416
1417         chained_irq_enter(chip, desc);
1418
1419         raw_spin_lock_irqsave(&chv_lock, flags);
1420         pending = readl(pctrl->regs + CHV_INTSTAT);
1421         raw_spin_unlock_irqrestore(&chv_lock, flags);
1422
1423         for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
1424                 unsigned int irq, offset;
1425
1426                 offset = pctrl->intr_lines[intr_line];
1427                 irq = irq_find_mapping(gc->irq.domain, offset);
1428                 generic_handle_irq(irq);
1429         }
1430
1431         chained_irq_exit(chip, desc);
1432 }
1433
1434 /*
1435  * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1436  * tables. Since we leave GPIOs that are not capable of generating
1437  * interrupts out of the irqdomain the numbering will be different and
1438  * cause devices using the hardcoded IRQ numbers fail. In order not to
1439  * break such machines we will only mask pins from irqdomain if the machine
1440  * is not listed below.
1441  */
1442 static const struct dmi_system_id chv_no_valid_mask[] = {
1443         /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1444         {
1445                 .ident = "Intel_Strago based Chromebooks (All models)",
1446                 .matches = {
1447                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1448                         DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1449                 },
1450         },
1451         {
1452                 .ident = "HP Chromebook 11 G5 (Setzer)",
1453                 .matches = {
1454                         DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1455                         DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1456                 },
1457         },
1458         {
1459                 .ident = "Acer Chromebook R11 (Cyan)",
1460                 .matches = {
1461                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1462                         DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1463                 },
1464         },
1465         {
1466                 .ident = "Samsung Chromebook 3 (Celes)",
1467                 .matches = {
1468                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1469                         DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
1470                 },
1471         },
1472         {}
1473 };
1474
1475 static void chv_init_irq_valid_mask(struct gpio_chip *chip,
1476                                     unsigned long *valid_mask,
1477                                     unsigned int ngpios)
1478 {
1479         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1480         const struct chv_community *community = pctrl->community;
1481         int i;
1482
1483         /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1484         for (i = 0; i < community->npins; i++) {
1485                 const struct pinctrl_pin_desc *desc;
1486                 u32 intsel;
1487
1488                 desc = &community->pins[i];
1489
1490                 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1491                 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1492                 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1493
1494                 if (intsel >= community->nirqs)
1495                         clear_bit(desc->number, valid_mask);
1496         }
1497 }
1498
1499 static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
1500 {
1501         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1502
1503         /*
1504          * The same set of machines in chv_no_valid_mask[] have incorrectly
1505          * configured GPIOs that generate spurious interrupts so we use
1506          * this same list to apply another quirk for them.
1507          *
1508          * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1509          */
1510         if (!pctrl->chip.irq.init_valid_mask) {
1511                 /*
1512                  * Mask all interrupts the community is able to generate
1513                  * but leave the ones that can only generate GPEs unmasked.
1514                  */
1515                 chv_writel(GENMASK(31, pctrl->community->nirqs),
1516                            pctrl->regs + CHV_INTMASK);
1517         }
1518
1519         /* Clear all interrupts */
1520         chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1521
1522         return 0;
1523 }
1524
1525 static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
1526 {
1527         struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1528         const struct chv_community *community = pctrl->community;
1529         const struct intel_padgroup *gpp;
1530         int ret, i;
1531
1532         for (i = 0; i < community->ngpps; i++) {
1533                 gpp = &community->gpps[i];
1534                 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1535                                              gpp->base, gpp->base,
1536                                              gpp->size);
1537                 if (ret) {
1538                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1539                         return ret;
1540                 }
1541         }
1542
1543         return 0;
1544 }
1545
1546 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1547 {
1548         const struct intel_padgroup *gpp;
1549         struct gpio_chip *chip = &pctrl->chip;
1550         bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1551         const struct chv_community *community = pctrl->community;
1552         int ret, i, irq_base;
1553
1554         *chip = chv_gpio_chip;
1555
1556         chip->ngpio = community->pins[community->npins - 1].number + 1;
1557         chip->label = dev_name(pctrl->dev);
1558         chip->add_pin_ranges = chv_gpio_add_pin_ranges;
1559         chip->parent = pctrl->dev;
1560         chip->base = -1;
1561
1562         pctrl->irq = irq;
1563         pctrl->irqchip.name = "chv-gpio";
1564         pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
1565         pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
1566         pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
1567         pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
1568         pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
1569         pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
1570
1571         chip->irq.chip = &pctrl->irqchip;
1572         chip->irq.init_hw = chv_gpio_irq_init_hw;
1573         chip->irq.parent_handler = chv_gpio_irq_handler;
1574         chip->irq.num_parents = 1;
1575         chip->irq.parents = &pctrl->irq;
1576         chip->irq.default_type = IRQ_TYPE_NONE;
1577         chip->irq.handler = handle_bad_irq;
1578         if (need_valid_mask) {
1579                 chip->irq.init_valid_mask = chv_init_irq_valid_mask;
1580         } else {
1581                 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1582                                                 community->npins, NUMA_NO_NODE);
1583                 if (irq_base < 0) {
1584                         dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1585                         return irq_base;
1586                 }
1587         }
1588
1589         ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1590         if (ret) {
1591                 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1592                 return ret;
1593         }
1594
1595         if (!need_valid_mask) {
1596                 for (i = 0; i < community->ngpps; i++) {
1597                         gpp = &community->gpps[i];
1598
1599                         irq_domain_associate_many(chip->irq.domain, irq_base,
1600                                                   gpp->base, gpp->size);
1601                         irq_base += gpp->size;
1602                 }
1603         }
1604
1605         return 0;
1606 }
1607
1608 static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1609         acpi_physical_address address, u32 bits, u64 *value,
1610         void *handler_context, void *region_context)
1611 {
1612         struct chv_pinctrl *pctrl = region_context;
1613         unsigned long flags;
1614         acpi_status ret = AE_OK;
1615
1616         raw_spin_lock_irqsave(&chv_lock, flags);
1617
1618         if (function == ACPI_WRITE)
1619                 chv_writel((u32)(*value), pctrl->regs + (u32)address);
1620         else if (function == ACPI_READ)
1621                 *value = readl(pctrl->regs + (u32)address);
1622         else
1623                 ret = AE_BAD_PARAMETER;
1624
1625         raw_spin_unlock_irqrestore(&chv_lock, flags);
1626
1627         return ret;
1628 }
1629
1630 static int chv_pinctrl_probe(struct platform_device *pdev)
1631 {
1632         struct chv_pinctrl *pctrl;
1633         struct acpi_device *adev;
1634         acpi_status status;
1635         int ret, irq, i;
1636
1637         adev = ACPI_COMPANION(&pdev->dev);
1638         if (!adev)
1639                 return -ENODEV;
1640
1641         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1642         if (!pctrl)
1643                 return -ENOMEM;
1644
1645         for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1646                 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1647                         pctrl->community = chv_communities[i];
1648                         break;
1649                 }
1650         if (i == ARRAY_SIZE(chv_communities))
1651                 return -ENODEV;
1652
1653         pctrl->dev = &pdev->dev;
1654
1655 #ifdef CONFIG_PM_SLEEP
1656         pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1657                 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1658                 GFP_KERNEL);
1659         if (!pctrl->saved_pin_context)
1660                 return -ENOMEM;
1661 #endif
1662
1663         pctrl->regs = devm_platform_ioremap_resource(pdev, 0);
1664         if (IS_ERR(pctrl->regs))
1665                 return PTR_ERR(pctrl->regs);
1666
1667         irq = platform_get_irq(pdev, 0);
1668         if (irq < 0)
1669                 return irq;
1670
1671         pctrl->pctldesc = chv_pinctrl_desc;
1672         pctrl->pctldesc.name = dev_name(&pdev->dev);
1673         pctrl->pctldesc.pins = pctrl->community->pins;
1674         pctrl->pctldesc.npins = pctrl->community->npins;
1675
1676         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1677                                                pctrl);
1678         if (IS_ERR(pctrl->pctldev)) {
1679                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1680                 return PTR_ERR(pctrl->pctldev);
1681         }
1682
1683         ret = chv_gpio_probe(pctrl, irq);
1684         if (ret)
1685                 return ret;
1686
1687         status = acpi_install_address_space_handler(adev->handle,
1688                                         pctrl->community->acpi_space_id,
1689                                         chv_pinctrl_mmio_access_handler,
1690                                         NULL, pctrl);
1691         if (ACPI_FAILURE(status))
1692                 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
1693
1694         platform_set_drvdata(pdev, pctrl);
1695
1696         return 0;
1697 }
1698
1699 static int chv_pinctrl_remove(struct platform_device *pdev)
1700 {
1701         struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1702
1703         acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
1704                                           pctrl->community->acpi_space_id,
1705                                           chv_pinctrl_mmio_access_handler);
1706
1707         return 0;
1708 }
1709
1710 #ifdef CONFIG_PM_SLEEP
1711 static int chv_pinctrl_suspend_noirq(struct device *dev)
1712 {
1713         struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
1714         unsigned long flags;
1715         int i;
1716
1717         raw_spin_lock_irqsave(&chv_lock, flags);
1718
1719         pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1720
1721         for (i = 0; i < pctrl->community->npins; i++) {
1722                 const struct pinctrl_pin_desc *desc;
1723                 struct chv_pin_context *ctx;
1724                 void __iomem *reg;
1725
1726                 desc = &pctrl->community->pins[i];
1727                 if (chv_pad_locked(pctrl, desc->number))
1728                         continue;
1729
1730                 ctx = &pctrl->saved_pin_context[i];
1731
1732                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1733                 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1734
1735                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1736                 ctx->padctrl1 = readl(reg);
1737         }
1738
1739         raw_spin_unlock_irqrestore(&chv_lock, flags);
1740
1741         return 0;
1742 }
1743
1744 static int chv_pinctrl_resume_noirq(struct device *dev)
1745 {
1746         struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
1747         unsigned long flags;
1748         int i;
1749
1750         raw_spin_lock_irqsave(&chv_lock, flags);
1751
1752         /*
1753          * Mask all interrupts before restoring per-pin configuration
1754          * registers because we don't know in which state BIOS left them
1755          * upon exiting suspend.
1756          */
1757         chv_writel(0, pctrl->regs + CHV_INTMASK);
1758
1759         for (i = 0; i < pctrl->community->npins; i++) {
1760                 const struct pinctrl_pin_desc *desc;
1761                 const struct chv_pin_context *ctx;
1762                 void __iomem *reg;
1763                 u32 val;
1764
1765                 desc = &pctrl->community->pins[i];
1766                 if (chv_pad_locked(pctrl, desc->number))
1767                         continue;
1768
1769                 ctx = &pctrl->saved_pin_context[i];
1770
1771                 /* Only restore if our saved state differs from the current */
1772                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1773                 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1774                 if (ctx->padctrl0 != val) {
1775                         chv_writel(ctx->padctrl0, reg);
1776                         dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1777                                 desc->number, readl(reg));
1778                 }
1779
1780                 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1781                 val = readl(reg);
1782                 if (ctx->padctrl1 != val) {
1783                         chv_writel(ctx->padctrl1, reg);
1784                         dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1785                                 desc->number, readl(reg));
1786                 }
1787         }
1788
1789         /*
1790          * Now that all pins are restored to known state, we can restore
1791          * the interrupt mask register as well.
1792          */
1793         chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1794         chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1795
1796         raw_spin_unlock_irqrestore(&chv_lock, flags);
1797
1798         return 0;
1799 }
1800 #endif
1801
1802 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1803         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1804                                       chv_pinctrl_resume_noirq)
1805 };
1806
1807 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1808         { "INT33FF" },
1809         { }
1810 };
1811 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1812
1813 static struct platform_driver chv_pinctrl_driver = {
1814         .probe = chv_pinctrl_probe,
1815         .remove = chv_pinctrl_remove,
1816         .driver = {
1817                 .name = "cherryview-pinctrl",
1818                 .pm = &chv_pinctrl_pm_ops,
1819                 .acpi_match_table = chv_pinctrl_acpi_match,
1820         },
1821 };
1822
1823 static int __init chv_pinctrl_init(void)
1824 {
1825         return platform_driver_register(&chv_pinctrl_driver);
1826 }
1827 subsys_initcall(chv_pinctrl_init);
1828
1829 static void __exit chv_pinctrl_exit(void)
1830 {
1831         platform_driver_unregister(&chv_pinctrl_driver);
1832 }
1833 module_exit(chv_pinctrl_exit);
1834
1835 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1836 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1837 MODULE_LICENSE("GPL v2");