drivers/pinctrl/intel/pinctrl-baytrail.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pinctrl GPIO driver for Intel Baytrail
   4  *
   5  * Copyright (c) 2012-2013, Intel Corporation
   6  * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/bitops.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/kernel.h>
  16 #include <linux/types.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/property.h>
  20 #include <linux/seq_file.h>
  21
  22 #include <linux/pinctrl/pinctrl.h>
  23 #include <linux/pinctrl/pinmux.h>
  24 #include <linux/pinctrl/pinconf.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26
  27 #include "pinctrl-intel.h"
  28
  29 /* memory mapped register offsets */
  30 #define BYT_CONF0_REG           0x000
  31 #define BYT_CONF1_REG           0x004
  32 #define BYT_VAL_REG             0x008
  33 #define BYT_DFT_REG             0x00c
  34 #define BYT_INT_STAT_REG        0x800
  35 #define BYT_DEBOUNCE_REG        0x9d0
  36
  37 /* BYT_CONF0_REG register bits */
  38 #define BYT_IODEN               BIT(31)
  39 #define BYT_DIRECT_IRQ_EN       BIT(27)
  40 #define BYT_TRIG_MASK           GENMASK(26, 24)
  41 #define BYT_TRIG_NEG            BIT(26)
  42 #define BYT_TRIG_POS            BIT(25)
  43 #define BYT_TRIG_LVL            BIT(24)
  44 #define BYT_DEBOUNCE_EN         BIT(20)
  45 #define BYT_GLITCH_FILTER_EN    BIT(19)
  46 #define BYT_GLITCH_F_SLOW_CLK   BIT(17)
  47 #define BYT_GLITCH_F_FAST_CLK   BIT(16)
  48 #define BYT_PULL_STR_SHIFT      9
  49 #define BYT_PULL_STR_MASK       GENMASK(10, 9)
  50 #define BYT_PULL_STR_2K         (0 << BYT_PULL_STR_SHIFT)
  51 #define BYT_PULL_STR_10K        (1 << BYT_PULL_STR_SHIFT)
  52 #define BYT_PULL_STR_20K        (2 << BYT_PULL_STR_SHIFT)
  53 #define BYT_PULL_STR_40K        (3 << BYT_PULL_STR_SHIFT)
  54 #define BYT_PULL_ASSIGN_SHIFT   7
  55 #define BYT_PULL_ASSIGN_MASK    GENMASK(8, 7)
  56 #define BYT_PULL_ASSIGN_UP      (1 << BYT_PULL_ASSIGN_SHIFT)
  57 #define BYT_PULL_ASSIGN_DOWN    (2 << BYT_PULL_ASSIGN_SHIFT)
  58 #define BYT_PIN_MUX             GENMASK(2, 0)
  59
  60 /* BYT_VAL_REG register bits */
  61 #define BYT_DIR_MASK            GENMASK(2, 1)
  62 #define BYT_INPUT_EN            BIT(2)  /* 0: input enabled (active low)*/
  63 #define BYT_OUTPUT_EN           BIT(1)  /* 0: output enabled (active low)*/
  64 #define BYT_LEVEL               BIT(0)
  65
  66 #define BYT_CONF0_RESTORE_MASK  (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
  67 #define BYT_VAL_RESTORE_MASK    (BYT_DIR_MASK | BYT_LEVEL)
  68
  69 /* BYT_DEBOUNCE_REG bits */
  70 #define BYT_DEBOUNCE_PULSE_MASK         GENMASK(2, 0)
  71 #define BYT_DEBOUNCE_PULSE_375US        1
  72 #define BYT_DEBOUNCE_PULSE_750US        2
  73 #define BYT_DEBOUNCE_PULSE_1500US       3
  74 #define BYT_DEBOUNCE_PULSE_3MS          4
  75 #define BYT_DEBOUNCE_PULSE_6MS          5
  76 #define BYT_DEBOUNCE_PULSE_12MS         6
  77 #define BYT_DEBOUNCE_PULSE_24MS         7
  78
  79 #define BYT_NGPIO_SCORE         102
  80 #define BYT_NGPIO_NCORE         28
  81 #define BYT_NGPIO_SUS           44
  82
  83 #define BYT_SCORE_ACPI_UID      "1"
  84 #define BYT_NCORE_ACPI_UID      "2"
  85 #define BYT_SUS_ACPI_UID        "3"
  86
  87 /*
  88  * This is the function value most pins have for GPIO muxing. If the value
  89  * differs from the default one, it must be explicitly mentioned. Otherwise, the
  90  * pin control implementation will set the muxing value to default GPIO if it
  91  * does not find a match for the requested function.
  92  */
  93 #define BYT_DEFAULT_GPIO_MUX    0
  94 #define BYT_ALTER_GPIO_MUX      1
  95
  96 struct intel_pad_context {
  97         u32 conf0;
  98         u32 val;
  99 };
 100
 101 #define COMMUNITY(p, n, map)            \
 102         {                               \
 103                 .pin_base       = (p),  \
 104                 .npins          = (n),  \
 105                 .pad_map        = (map),\
 106         }
 107
 108 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
 109 static const struct pinctrl_pin_desc byt_score_pins[] = {
 110         PINCTRL_PIN(0, "SATA_GP0"),
 111         PINCTRL_PIN(1, "SATA_GP1"),
 112         PINCTRL_PIN(2, "SATA_LED#"),
 113         PINCTRL_PIN(3, "PCIE_CLKREQ0"),
 114         PINCTRL_PIN(4, "PCIE_CLKREQ1"),
 115         PINCTRL_PIN(5, "PCIE_CLKREQ2"),
 116         PINCTRL_PIN(6, "PCIE_CLKREQ3"),
 117         PINCTRL_PIN(7, "SD3_WP"),
 118         PINCTRL_PIN(8, "HDA_RST"),
 119         PINCTRL_PIN(9, "HDA_SYNC"),
 120         PINCTRL_PIN(10, "HDA_CLK"),
 121         PINCTRL_PIN(11, "HDA_SDO"),
 122         PINCTRL_PIN(12, "HDA_SDI0"),
 123         PINCTRL_PIN(13, "HDA_SDI1"),
 124         PINCTRL_PIN(14, "GPIO_S0_SC14"),
 125         PINCTRL_PIN(15, "GPIO_S0_SC15"),
 126         PINCTRL_PIN(16, "MMC1_CLK"),
 127         PINCTRL_PIN(17, "MMC1_D0"),
 128         PINCTRL_PIN(18, "MMC1_D1"),
 129         PINCTRL_PIN(19, "MMC1_D2"),
 130         PINCTRL_PIN(20, "MMC1_D3"),
 131         PINCTRL_PIN(21, "MMC1_D4"),
 132         PINCTRL_PIN(22, "MMC1_D5"),
 133         PINCTRL_PIN(23, "MMC1_D6"),
 134         PINCTRL_PIN(24, "MMC1_D7"),
 135         PINCTRL_PIN(25, "MMC1_CMD"),
 136         PINCTRL_PIN(26, "MMC1_RST"),
 137         PINCTRL_PIN(27, "SD2_CLK"),
 138         PINCTRL_PIN(28, "SD2_D0"),
 139         PINCTRL_PIN(29, "SD2_D1"),
 140         PINCTRL_PIN(30, "SD2_D2"),
 141         PINCTRL_PIN(31, "SD2_D3_CD"),
 142         PINCTRL_PIN(32, "SD2_CMD"),
 143         PINCTRL_PIN(33, "SD3_CLK"),
 144         PINCTRL_PIN(34, "SD3_D0"),
 145         PINCTRL_PIN(35, "SD3_D1"),
 146         PINCTRL_PIN(36, "SD3_D2"),
 147         PINCTRL_PIN(37, "SD3_D3"),
 148         PINCTRL_PIN(38, "SD3_CD"),
 149         PINCTRL_PIN(39, "SD3_CMD"),
 150         PINCTRL_PIN(40, "SD3_1P8EN"),
 151         PINCTRL_PIN(41, "SD3_PWREN#"),
 152         PINCTRL_PIN(42, "ILB_LPC_AD0"),
 153         PINCTRL_PIN(43, "ILB_LPC_AD1"),
 154         PINCTRL_PIN(44, "ILB_LPC_AD2"),
 155         PINCTRL_PIN(45, "ILB_LPC_AD3"),
 156         PINCTRL_PIN(46, "ILB_LPC_FRAME"),
 157         PINCTRL_PIN(47, "ILB_LPC_CLK0"),
 158         PINCTRL_PIN(48, "ILB_LPC_CLK1"),
 159         PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
 160         PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
 161         PINCTRL_PIN(51, "PCU_SMB_DATA"),
 162         PINCTRL_PIN(52, "PCU_SMB_CLK"),
 163         PINCTRL_PIN(53, "PCU_SMB_ALERT"),
 164         PINCTRL_PIN(54, "ILB_8254_SPKR"),
 165         PINCTRL_PIN(55, "GPIO_S0_SC55"),
 166         PINCTRL_PIN(56, "GPIO_S0_SC56"),
 167         PINCTRL_PIN(57, "GPIO_S0_SC57"),
 168         PINCTRL_PIN(58, "GPIO_S0_SC58"),
 169         PINCTRL_PIN(59, "GPIO_S0_SC59"),
 170         PINCTRL_PIN(60, "GPIO_S0_SC60"),
 171         PINCTRL_PIN(61, "GPIO_S0_SC61"),
 172         PINCTRL_PIN(62, "LPE_I2S2_CLK"),
 173         PINCTRL_PIN(63, "LPE_I2S2_FRM"),
 174         PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
 175         PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
 176         PINCTRL_PIN(66, "SIO_SPI_CS"),
 177         PINCTRL_PIN(67, "SIO_SPI_MISO"),
 178         PINCTRL_PIN(68, "SIO_SPI_MOSI"),
 179         PINCTRL_PIN(69, "SIO_SPI_CLK"),
 180         PINCTRL_PIN(70, "SIO_UART1_RXD"),
 181         PINCTRL_PIN(71, "SIO_UART1_TXD"),
 182         PINCTRL_PIN(72, "SIO_UART1_RTS"),
 183         PINCTRL_PIN(73, "SIO_UART1_CTS"),
 184         PINCTRL_PIN(74, "SIO_UART2_RXD"),
 185         PINCTRL_PIN(75, "SIO_UART2_TXD"),
 186         PINCTRL_PIN(76, "SIO_UART2_RTS"),
 187         PINCTRL_PIN(77, "SIO_UART2_CTS"),
 188         PINCTRL_PIN(78, "SIO_I2C0_DATA"),
 189         PINCTRL_PIN(79, "SIO_I2C0_CLK"),
 190         PINCTRL_PIN(80, "SIO_I2C1_DATA"),
 191         PINCTRL_PIN(81, "SIO_I2C1_CLK"),
 192         PINCTRL_PIN(82, "SIO_I2C2_DATA"),
 193         PINCTRL_PIN(83, "SIO_I2C2_CLK"),
 194         PINCTRL_PIN(84, "SIO_I2C3_DATA"),
 195         PINCTRL_PIN(85, "SIO_I2C3_CLK"),
 196         PINCTRL_PIN(86, "SIO_I2C4_DATA"),
 197         PINCTRL_PIN(87, "SIO_I2C4_CLK"),
 198         PINCTRL_PIN(88, "SIO_I2C5_DATA"),
 199         PINCTRL_PIN(89, "SIO_I2C5_CLK"),
 200         PINCTRL_PIN(90, "SIO_I2C6_DATA"),
 201         PINCTRL_PIN(91, "SIO_I2C6_CLK"),
 202         PINCTRL_PIN(92, "GPIO_S0_SC92"),
 203         PINCTRL_PIN(93, "GPIO_S0_SC93"),
 204         PINCTRL_PIN(94, "SIO_PWM0"),
 205         PINCTRL_PIN(95, "SIO_PWM1"),
 206         PINCTRL_PIN(96, "PMC_PLT_CLK0"),
 207         PINCTRL_PIN(97, "PMC_PLT_CLK1"),
 208         PINCTRL_PIN(98, "PMC_PLT_CLK2"),
 209         PINCTRL_PIN(99, "PMC_PLT_CLK3"),
 210         PINCTRL_PIN(100, "PMC_PLT_CLK4"),
 211         PINCTRL_PIN(101, "PMC_PLT_CLK5"),
 212 };
 213
 214 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
 215         85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
 216         36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
 217         54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
 218         52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
 219         95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
 220         86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
 221         80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
 222         2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
 223         31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
 224         24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
 225         97, 100,
 226 };
 227
 228 /* SCORE groups */
 229 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
 230 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
 231
 232 static const unsigned int byt_score_pwm0_pins[] = { 94 };
 233 static const unsigned int byt_score_pwm1_pins[] = { 95 };
 234
 235 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
 236
 237 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
 238 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
 239 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
 240 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
 241 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
 242 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
 243 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
 244
 245 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
 246 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
 247 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
 248
 249 static const unsigned int byt_score_sdcard_pins[] = {
 250         7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
 251 };
 252 static const unsigned int byt_score_sdcard_mux_values[] = {
 253         2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 254 };
 255
 256 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
 257
 258 static const unsigned int byt_score_emmc_pins[] = {
 259         16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
 260 };
 261
 262 static const unsigned int byt_score_ilb_lpc_pins[] = {
 263         42, 43, 44, 45, 46, 47, 48, 49, 50,
 264 };
 265
 266 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
 267
 268 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
 269 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
 270 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
 271 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
 272 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
 273 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
 274
 275 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
 276
 277 static const struct intel_pingroup byt_score_groups[] = {
 278         PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
 279         PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
 280         PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
 281         PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
 282         PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
 283         PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
 284         PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
 285         PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
 286         PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
 287         PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
 288         PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
 289         PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
 290         PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
 291         PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
 292         PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
 293         PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
 294         PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
 295         PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
 296         PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
 297         PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
 298         PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
 299         PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
 300         PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
 301         PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
 302         PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
 303         PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
 304         PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
 305 };
 306
 307 static const char * const byt_score_uart_groups[] = {
 308         "uart1_grp", "uart2_grp",
 309 };
 310 static const char * const byt_score_pwm_groups[] = {
 311         "pwm0_grp", "pwm1_grp",
 312 };
 313 static const char * const byt_score_ssp_groups[] = {
 314         "ssp0_grp", "ssp1_grp", "ssp2_grp",
 315 };
 316 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
 317 static const char * const byt_score_i2c_groups[] = {
 318         "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
 319         "i2c6_grp",
 320 };
 321 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
 322 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
 323 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
 324 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
 325 static const char * const byt_score_sata_groups[] = { "sata_grp" };
 326 static const char * const byt_score_plt_clk_groups[] = {
 327         "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
 328         "plt_clk4_grp", "plt_clk5_grp",
 329 };
 330 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
 331 static const char * const byt_score_gpio_groups[] = {
 332         "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
 333         "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
 334         "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
 335         "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
 336         "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
 337         "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
 338 };
 339
 340 static const struct intel_function byt_score_functions[] = {
 341         FUNCTION("uart", byt_score_uart_groups),
 342         FUNCTION("pwm", byt_score_pwm_groups),
 343         FUNCTION("ssp", byt_score_ssp_groups),
 344         FUNCTION("spi", byt_score_spi_groups),
 345         FUNCTION("i2c", byt_score_i2c_groups),
 346         FUNCTION("sdcard", byt_score_sdcard_groups),
 347         FUNCTION("sdio", byt_score_sdio_groups),
 348         FUNCTION("emmc", byt_score_emmc_groups),
 349         FUNCTION("lpc", byt_score_lpc_groups),
 350         FUNCTION("sata", byt_score_sata_groups),
 351         FUNCTION("plt_clk", byt_score_plt_clk_groups),
 352         FUNCTION("smbus", byt_score_smbus_groups),
 353         FUNCTION("gpio", byt_score_gpio_groups),
 354 };
 355
 356 static const struct intel_community byt_score_communities[] = {
 357         COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
 358 };
 359
 360 static const struct intel_pinctrl_soc_data byt_score_soc_data = {
 361         .uid            = BYT_SCORE_ACPI_UID,
 362         .pins           = byt_score_pins,
 363         .npins          = ARRAY_SIZE(byt_score_pins),
 364         .groups         = byt_score_groups,
 365         .ngroups        = ARRAY_SIZE(byt_score_groups),
 366         .functions      = byt_score_functions,
 367         .nfunctions     = ARRAY_SIZE(byt_score_functions),
 368         .communities    = byt_score_communities,
 369         .ncommunities   = ARRAY_SIZE(byt_score_communities),
 370 };
 371
 372 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>]  */
 373 static const struct pinctrl_pin_desc byt_sus_pins[] = {
 374         PINCTRL_PIN(0, "GPIO_S50"),
 375         PINCTRL_PIN(1, "GPIO_S51"),
 376         PINCTRL_PIN(2, "GPIO_S52"),
 377         PINCTRL_PIN(3, "GPIO_S53"),
 378         PINCTRL_PIN(4, "GPIO_S54"),
 379         PINCTRL_PIN(5, "GPIO_S55"),
 380         PINCTRL_PIN(6, "GPIO_S56"),
 381         PINCTRL_PIN(7, "GPIO_S57"),
 382         PINCTRL_PIN(8, "GPIO_S58"),
 383         PINCTRL_PIN(9, "GPIO_S59"),
 384         PINCTRL_PIN(10, "GPIO_S510"),
 385         PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
 386         PINCTRL_PIN(12, "PMC_SUSCLK0"),
 387         PINCTRL_PIN(13, "GPIO_S513"),
 388         PINCTRL_PIN(14, "USB_ULPI_RST"),
 389         PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
 390         PINCTRL_PIN(16, "PMC_PWRBTN"),
 391         PINCTRL_PIN(17, "GPIO_S517"),
 392         PINCTRL_PIN(18, "PMC_SUS_STAT"),
 393         PINCTRL_PIN(19, "USB_OC0"),
 394         PINCTRL_PIN(20, "USB_OC1"),
 395         PINCTRL_PIN(21, "PCU_SPI_CS1"),
 396         PINCTRL_PIN(22, "GPIO_S522"),
 397         PINCTRL_PIN(23, "GPIO_S523"),
 398         PINCTRL_PIN(24, "GPIO_S524"),
 399         PINCTRL_PIN(25, "GPIO_S525"),
 400         PINCTRL_PIN(26, "GPIO_S526"),
 401         PINCTRL_PIN(27, "GPIO_S527"),
 402         PINCTRL_PIN(28, "GPIO_S528"),
 403         PINCTRL_PIN(29, "GPIO_S529"),
 404         PINCTRL_PIN(30, "GPIO_S530"),
 405         PINCTRL_PIN(31, "USB_ULPI_CLK"),
 406         PINCTRL_PIN(32, "USB_ULPI_DATA0"),
 407         PINCTRL_PIN(33, "USB_ULPI_DATA1"),
 408         PINCTRL_PIN(34, "USB_ULPI_DATA2"),
 409         PINCTRL_PIN(35, "USB_ULPI_DATA3"),
 410         PINCTRL_PIN(36, "USB_ULPI_DATA4"),
 411         PINCTRL_PIN(37, "USB_ULPI_DATA5"),
 412         PINCTRL_PIN(38, "USB_ULPI_DATA6"),
 413         PINCTRL_PIN(39, "USB_ULPI_DATA7"),
 414         PINCTRL_PIN(40, "USB_ULPI_DIR"),
 415         PINCTRL_PIN(41, "USB_ULPI_NXT"),
 416         PINCTRL_PIN(42, "USB_ULPI_STP"),
 417         PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
 418 };
 419
 420 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
 421         29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
 422         18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
 423         0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
 424         26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
 425         52, 53, 59, 40,
 426 };
 427
 428 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
 429 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
 430 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
 431
 432 static const unsigned int byt_sus_usb_ulpi_pins[] = {
 433         14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
 434 };
 435 static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
 436         2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 437 };
 438 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
 439         1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 440 };
 441
 442 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
 443 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
 444 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
 445
 446 static const struct intel_pingroup byt_sus_groups[] = {
 447         PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
 448         PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
 449         PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
 450         PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
 451         PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
 452         PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
 453 };
 454
 455 static const char * const byt_sus_usb_groups[] = {
 456         "usb_oc_grp", "usb_ulpi_grp",
 457 };
 458 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
 459 static const char * const byt_sus_gpio_groups[] = {
 460         "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
 461 };
 462
 463 static const struct intel_function byt_sus_functions[] = {
 464         FUNCTION("usb", byt_sus_usb_groups),
 465         FUNCTION("spi", byt_sus_spi_groups),
 466         FUNCTION("gpio", byt_sus_gpio_groups),
 467 };
 468
 469 static const struct intel_community byt_sus_communities[] = {
 470         COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
 471 };
 472
 473 static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
 474         .uid            = BYT_SUS_ACPI_UID,
 475         .pins           = byt_sus_pins,
 476         .npins          = ARRAY_SIZE(byt_sus_pins),
 477         .groups         = byt_sus_groups,
 478         .ngroups        = ARRAY_SIZE(byt_sus_groups),
 479         .functions      = byt_sus_functions,
 480         .nfunctions     = ARRAY_SIZE(byt_sus_functions),
 481         .communities    = byt_sus_communities,
 482         .ncommunities   = ARRAY_SIZE(byt_sus_communities),
 483 };
 484
 485 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
 486         PINCTRL_PIN(0, "HV_DDI0_HPD"),
 487         PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"),
 488         PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"),
 489         PINCTRL_PIN(3, "PANEL0_VDDEN"),
 490         PINCTRL_PIN(4, "PANEL0_BKLTEN"),
 491         PINCTRL_PIN(5, "PANEL0_BKLTCTL"),
 492         PINCTRL_PIN(6, "HV_DDI1_HPD"),
 493         PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"),
 494         PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"),
 495         PINCTRL_PIN(9, "PANEL1_VDDEN"),
 496         PINCTRL_PIN(10, "PANEL1_BKLTEN"),
 497         PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
 498         PINCTRL_PIN(12, "GP_INTD_DSI_TE1"),
 499         PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"),
 500         PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"),
 501         PINCTRL_PIN(15, "GP_CAMERASB00"),
 502         PINCTRL_PIN(16, "GP_CAMERASB01"),
 503         PINCTRL_PIN(17, "GP_CAMERASB02"),
 504         PINCTRL_PIN(18, "GP_CAMERASB03"),
 505         PINCTRL_PIN(19, "GP_CAMERASB04"),
 506         PINCTRL_PIN(20, "GP_CAMERASB05"),
 507         PINCTRL_PIN(21, "GP_CAMERASB06"),
 508         PINCTRL_PIN(22, "GP_CAMERASB07"),
 509         PINCTRL_PIN(23, "GP_CAMERASB08"),
 510         PINCTRL_PIN(24, "GP_CAMERASB09"),
 511         PINCTRL_PIN(25, "GP_CAMERASB10"),
 512         PINCTRL_PIN(26, "GP_CAMERASB11"),
 513         PINCTRL_PIN(27, "GP_INTD_DSI_TE2"),
 514 };
 515
 516 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
 517         19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
 518         14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
 519         3, 6, 10, 13, 2, 5, 9, 7,
 520 };
 521
 522 static const struct intel_community byt_ncore_communities[] = {
 523         COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
 524 };
 525
 526 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
 527         .uid            = BYT_NCORE_ACPI_UID,
 528         .pins           = byt_ncore_pins,
 529         .npins          = ARRAY_SIZE(byt_ncore_pins),
 530         .communities    = byt_ncore_communities,
 531         .ncommunities   = ARRAY_SIZE(byt_ncore_communities),
 532 };
 533
 534 static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
 535         &byt_score_soc_data,
 536         &byt_sus_soc_data,
 537         &byt_ncore_soc_data,
 538         NULL
 539 };
 540
 541 static DEFINE_RAW_SPINLOCK(byt_lock);
 542
 543 static struct intel_community *byt_get_community(struct intel_pinctrl *vg,
 544                                                  unsigned int pin)
 545 {
 546         struct intel_community *comm;
 547         int i;
 548
 549         for (i = 0; i < vg->ncommunities; i++) {
 550                 comm = vg->communities + i;
 551                 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
 552                         return comm;
 553         }
 554
 555         return NULL;
 556 }
 557
 558 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
 559                                   int reg)
 560 {
 561         struct intel_community *comm = byt_get_community(vg, offset);
 562         u32 reg_offset;
 563
 564         if (!comm)
 565                 return NULL;
 566
 567         offset -= comm->pin_base;
 568         switch (reg) {
 569         case BYT_INT_STAT_REG:
 570                 reg_offset = (offset / 32) * 4;
 571                 break;
 572         case BYT_DEBOUNCE_REG:
 573                 reg_offset = 0;
 574                 break;
 575         default:
 576                 reg_offset = comm->pad_map[offset] * 16;
 577                 break;
 578         }
 579
 580         return comm->pad_regs + reg_offset + reg;
 581 }
 582
 583 static int byt_get_groups_count(struct pinctrl_dev *pctldev)
 584 {
 585         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 586
 587         return vg->soc->ngroups;
 588 }
 589
 590 static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
 591                                       unsigned int selector)
 592 {
 593         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 594
 595         return vg->soc->groups[selector].name;
 596 }
 597
 598 static int byt_get_group_pins(struct pinctrl_dev *pctldev,
 599                               unsigned int selector,
 600                               const unsigned int **pins,
 601                               unsigned int *num_pins)
 602 {
 603         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 604
 605         *pins           = vg->soc->groups[selector].pins;
 606         *num_pins       = vg->soc->groups[selector].npins;
 607
 608         return 0;
 609 }
 610
 611 static const struct pinctrl_ops byt_pinctrl_ops = {
 612         .get_groups_count       = byt_get_groups_count,
 613         .get_group_name         = byt_get_group_name,
 614         .get_group_pins         = byt_get_group_pins,
 615 };
 616
 617 static int byt_get_functions_count(struct pinctrl_dev *pctldev)
 618 {
 619         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 620
 621         return vg->soc->nfunctions;
 622 }
 623
 624 static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
 625                                          unsigned int selector)
 626 {
 627         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 628
 629         return vg->soc->functions[selector].name;
 630 }
 631
 632 static int byt_get_function_groups(struct pinctrl_dev *pctldev,
 633                                    unsigned int selector,
 634                                    const char * const **groups,
 635                                    unsigned int *num_groups)
 636 {
 637         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 638
 639         *groups         = vg->soc->functions[selector].groups;
 640         *num_groups     = vg->soc->functions[selector].ngroups;
 641
 642         return 0;
 643 }
 644
 645 static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
 646                                      const struct intel_pingroup group,
 647                                      unsigned int func)
 648 {
 649         unsigned long flags;
 650         int i;
 651
 652         raw_spin_lock_irqsave(&byt_lock, flags);
 653
 654         for (i = 0; i < group.npins; i++) {
 655                 void __iomem *padcfg0;
 656                 u32 value;
 657
 658                 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
 659                 if (!padcfg0) {
 660                         dev_warn(vg->dev,
 661                                  "Group %s, pin %i not muxed (no padcfg0)\n",
 662                                  group.name, i);
 663                         continue;
 664                 }
 665
 666                 value = readl(padcfg0);
 667                 value &= ~BYT_PIN_MUX;
 668                 value |= func;
 669                 writel(value, padcfg0);
 670         }
 671
 672         raw_spin_unlock_irqrestore(&byt_lock, flags);
 673 }
 674
 675 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
 676                                     const struct intel_pingroup group,
 677                                     const unsigned int *func)
 678 {
 679         unsigned long flags;
 680         int i;
 681
 682         raw_spin_lock_irqsave(&byt_lock, flags);
 683
 684         for (i = 0; i < group.npins; i++) {
 685                 void __iomem *padcfg0;
 686                 u32 value;
 687
 688                 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
 689                 if (!padcfg0) {
 690                         dev_warn(vg->dev,
 691                                  "Group %s, pin %i not muxed (no padcfg0)\n",
 692                                  group.name, i);
 693                         continue;
 694                 }
 695
 696                 value = readl(padcfg0);
 697                 value &= ~BYT_PIN_MUX;
 698                 value |= func[i];
 699                 writel(value, padcfg0);
 700         }
 701
 702         raw_spin_unlock_irqrestore(&byt_lock, flags);
 703 }
 704
 705 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
 706                        unsigned int group_selector)
 707 {
 708         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 709         const struct intel_function func = vg->soc->functions[func_selector];
 710         const struct intel_pingroup group = vg->soc->groups[group_selector];
 711
 712         if (group.modes)
 713                 byt_set_group_mixed_mux(vg, group, group.modes);
 714         else if (!strcmp(func.name, "gpio"))
 715                 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
 716         else
 717                 byt_set_group_simple_mux(vg, group, group.mode);
 718
 719         return 0;
 720 }
 721
 722 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
 723 {
 724         /* SCORE pin 92-93 */
 725         if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&
 726             offset >= 92 && offset <= 93)
 727                 return BYT_ALTER_GPIO_MUX;
 728
 729         /* SUS pin 11-21 */
 730         if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&
 731             offset >= 11 && offset <= 21)
 732                 return BYT_ALTER_GPIO_MUX;
 733
 734         return BYT_DEFAULT_GPIO_MUX;
 735 }
 736
 737 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
 738 {
 739         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 740         unsigned long flags;
 741         u32 value;
 742
 743         raw_spin_lock_irqsave(&byt_lock, flags);
 744         value = readl(reg);
 745
 746         /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
 747         if (value & BYT_DIRECT_IRQ_EN)
 748                 /* nothing to do */ ;
 749         else
 750                 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
 751
 752         writel(value, reg);
 753         raw_spin_unlock_irqrestore(&byt_lock, flags);
 754 }
 755
 756 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
 757                                    struct pinctrl_gpio_range *range,
 758                                    unsigned int offset)
 759 {
 760         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 761         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 762         u32 value, gpio_mux;
 763         unsigned long flags;
 764
 765         raw_spin_lock_irqsave(&byt_lock, flags);
 766
 767         /*
 768          * In most cases, func pin mux 000 means GPIO function.
 769          * But, some pins may have func pin mux 001 represents
 770          * GPIO function.
 771          *
 772          * Because there are devices out there where some pins were not
 773          * configured correctly we allow changing the mux value from
 774          * request (but print out warning about that).
 775          */
 776         value = readl(reg) & BYT_PIN_MUX;
 777         gpio_mux = byt_get_gpio_mux(vg, offset);
 778         if (gpio_mux != value) {
 779                 value = readl(reg) & ~BYT_PIN_MUX;
 780                 value |= gpio_mux;
 781                 writel(value, reg);
 782
 783                 dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset);
 784         }
 785
 786         raw_spin_unlock_irqrestore(&byt_lock, flags);
 787
 788         pm_runtime_get(vg->dev);
 789
 790         return 0;
 791 }
 792
 793 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
 794                                   struct pinctrl_gpio_range *range,
 795                                   unsigned int offset)
 796 {
 797         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 798
 799         byt_gpio_clear_triggering(vg, offset);
 800         pm_runtime_put(vg->dev);
 801 }
 802
 803 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
 804                                   struct pinctrl_gpio_range *range,
 805                                   unsigned int offset,
 806                                   bool input)
 807 {
 808         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 809         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 810         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 811         unsigned long flags;
 812         u32 value;
 813
 814         raw_spin_lock_irqsave(&byt_lock, flags);
 815
 816         value = readl(val_reg);
 817         value &= ~BYT_DIR_MASK;
 818         if (input)
 819                 value |= BYT_OUTPUT_EN;
 820         else if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
 821                 /*
 822                  * Before making any direction modifications, do a check if gpio
 823                  * is set for direct IRQ.  On baytrail, setting GPIO to output
 824                  * does not make sense, so let's at least inform the caller before
 825                  * they shoot themselves in the foot.
 826                  */
 827                 dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
 828
 829         writel(value, val_reg);
 830
 831         raw_spin_unlock_irqrestore(&byt_lock, flags);
 832
 833         return 0;
 834 }
 835
 836 static const struct pinmux_ops byt_pinmux_ops = {
 837         .get_functions_count    = byt_get_functions_count,
 838         .get_function_name      = byt_get_function_name,
 839         .get_function_groups    = byt_get_function_groups,
 840         .set_mux                = byt_set_mux,
 841         .gpio_request_enable    = byt_gpio_request_enable,
 842         .gpio_disable_free      = byt_gpio_disable_free,
 843         .gpio_set_direction     = byt_gpio_set_direction,
 844 };
 845
 846 static void byt_get_pull_strength(u32 reg, u16 *strength)
 847 {
 848         switch (reg & BYT_PULL_STR_MASK) {
 849         case BYT_PULL_STR_2K:
 850                 *strength = 2000;
 851                 break;
 852         case BYT_PULL_STR_10K:
 853                 *strength = 10000;
 854                 break;
 855         case BYT_PULL_STR_20K:
 856                 *strength = 20000;
 857                 break;
 858         case BYT_PULL_STR_40K:
 859                 *strength = 40000;
 860                 break;
 861         }
 862 }
 863
 864 static int byt_set_pull_strength(u32 *reg, u16 strength)
 865 {
 866         *reg &= ~BYT_PULL_STR_MASK;
 867
 868         switch (strength) {
 869         case 2000:
 870                 *reg |= BYT_PULL_STR_2K;
 871                 break;
 872         case 10000:
 873                 *reg |= BYT_PULL_STR_10K;
 874                 break;
 875         case 20000:
 876                 *reg |= BYT_PULL_STR_20K;
 877                 break;
 878         case 40000:
 879                 *reg |= BYT_PULL_STR_40K;
 880                 break;
 881         default:
 882                 return -EINVAL;
 883         }
 884
 885         return 0;
 886 }
 887
 888 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
 889                               unsigned long *config)
 890 {
 891         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 892         enum pin_config_param param = pinconf_to_config_param(*config);
 893         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 894         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 895         void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
 896         unsigned long flags;
 897         u32 conf, pull, val, debounce;
 898         u16 arg = 0;
 899
 900         raw_spin_lock_irqsave(&byt_lock, flags);
 901         conf = readl(conf_reg);
 902         pull = conf & BYT_PULL_ASSIGN_MASK;
 903         val = readl(val_reg);
 904         raw_spin_unlock_irqrestore(&byt_lock, flags);
 905
 906         switch (param) {
 907         case PIN_CONFIG_BIAS_DISABLE:
 908                 if (pull)
 909                         return -EINVAL;
 910                 break;
 911         case PIN_CONFIG_BIAS_PULL_DOWN:
 912                 /* Pull assignment is only applicable in input mode */
 913                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
 914                         return -EINVAL;
 915
 916                 byt_get_pull_strength(conf, &arg);
 917
 918                 break;
 919         case PIN_CONFIG_BIAS_PULL_UP:
 920                 /* Pull assignment is only applicable in input mode */
 921                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
 922                         return -EINVAL;
 923
 924                 byt_get_pull_strength(conf, &arg);
 925
 926                 break;
 927         case PIN_CONFIG_INPUT_DEBOUNCE:
 928                 if (!(conf & BYT_DEBOUNCE_EN))
 929                         return -EINVAL;
 930
 931                 raw_spin_lock_irqsave(&byt_lock, flags);
 932                 debounce = readl(db_reg);
 933                 raw_spin_unlock_irqrestore(&byt_lock, flags);
 934
 935                 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
 936                 case BYT_DEBOUNCE_PULSE_375US:
 937                         arg = 375;
 938                         break;
 939                 case BYT_DEBOUNCE_PULSE_750US:
 940                         arg = 750;
 941                         break;
 942                 case BYT_DEBOUNCE_PULSE_1500US:
 943                         arg = 1500;
 944                         break;
 945                 case BYT_DEBOUNCE_PULSE_3MS:
 946                         arg = 3000;
 947                         break;
 948                 case BYT_DEBOUNCE_PULSE_6MS:
 949                         arg = 6000;
 950                         break;
 951                 case BYT_DEBOUNCE_PULSE_12MS:
 952                         arg = 12000;
 953                         break;
 954                 case BYT_DEBOUNCE_PULSE_24MS:
 955                         arg = 24000;
 956                         break;
 957                 default:
 958                         return -EINVAL;
 959                 }
 960
 961                 break;
 962         default:
 963                 return -ENOTSUPP;
 964         }
 965
 966         *config = pinconf_to_config_packed(param, arg);
 967
 968         return 0;
 969 }
 970
 971 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
 972                               unsigned int offset,
 973                               unsigned long *configs,
 974                               unsigned int num_configs)
 975 {
 976         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 977         unsigned int param, arg;
 978         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 979         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 980         void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
 981         unsigned long flags;
 982         u32 conf, val, debounce;
 983         int i, ret = 0;
 984
 985         raw_spin_lock_irqsave(&byt_lock, flags);
 986
 987         conf = readl(conf_reg);
 988         val = readl(val_reg);
 989
 990         for (i = 0; i < num_configs; i++) {
 991                 param = pinconf_to_config_param(configs[i]);
 992                 arg = pinconf_to_config_argument(configs[i]);
 993
 994                 switch (param) {
 995                 case PIN_CONFIG_BIAS_DISABLE:
 996                         conf &= ~BYT_PULL_ASSIGN_MASK;
 997                         break;
 998                 case PIN_CONFIG_BIAS_PULL_DOWN:
 999                         /* Set default strength value in case none is given */
1000                         if (arg == 1)
1001                                 arg = 2000;
1002
1003                         /*
1004                          * Pull assignment is only applicable in input mode. If
1005                          * chip is not in input mode, set it and warn about it.
1006                          */
1007                         if (val & BYT_INPUT_EN) {
1008                                 val &= ~BYT_INPUT_EN;
1009                                 writel(val, val_reg);
1010                                 dev_warn(vg->dev,
1011                                          "pin %u forcibly set to input mode\n",
1012                                          offset);
1013                         }
1014
1015                         conf &= ~BYT_PULL_ASSIGN_MASK;
1016                         conf |= BYT_PULL_ASSIGN_DOWN;
1017                         ret = byt_set_pull_strength(&conf, arg);
1018
1019                         break;
1020                 case PIN_CONFIG_BIAS_PULL_UP:
1021                         /* Set default strength value in case none is given */
1022                         if (arg == 1)
1023                                 arg = 2000;
1024
1025                         /*
1026                          * Pull assignment is only applicable in input mode. If
1027                          * chip is not in input mode, set it and warn about it.
1028                          */
1029                         if (val & BYT_INPUT_EN) {
1030                                 val &= ~BYT_INPUT_EN;
1031                                 writel(val, val_reg);
1032                                 dev_warn(vg->dev,
1033                                          "pin %u forcibly set to input mode\n",
1034                                          offset);
1035                         }
1036
1037                         conf &= ~BYT_PULL_ASSIGN_MASK;
1038                         conf |= BYT_PULL_ASSIGN_UP;
1039                         ret = byt_set_pull_strength(&conf, arg);
1040
1041                         break;
1042                 case PIN_CONFIG_INPUT_DEBOUNCE:
1043                         debounce = readl(db_reg);
1044                         debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1045
1046                         if (arg)
1047                                 conf |= BYT_DEBOUNCE_EN;
1048                         else
1049                                 conf &= ~BYT_DEBOUNCE_EN;
1050
1051                         switch (arg) {
1052                         case 375:
1053                                 debounce |= BYT_DEBOUNCE_PULSE_375US;
1054                                 break;
1055                         case 750:
1056                                 debounce |= BYT_DEBOUNCE_PULSE_750US;
1057                                 break;
1058                         case 1500:
1059                                 debounce |= BYT_DEBOUNCE_PULSE_1500US;
1060                                 break;
1061                         case 3000:
1062                                 debounce |= BYT_DEBOUNCE_PULSE_3MS;
1063                                 break;
1064                         case 6000:
1065                                 debounce |= BYT_DEBOUNCE_PULSE_6MS;
1066                                 break;
1067                         case 12000:
1068                                 debounce |= BYT_DEBOUNCE_PULSE_12MS;
1069                                 break;
1070                         case 24000:
1071                                 debounce |= BYT_DEBOUNCE_PULSE_24MS;
1072                                 break;
1073                         default:
1074                                 if (arg)
1075                                         ret = -EINVAL;
1076                                 break;
1077                         }
1078
1079                         if (!ret)
1080                                 writel(debounce, db_reg);
1081                         break;
1082                 default:
1083                         ret = -ENOTSUPP;
1084                 }
1085
1086                 if (ret)
1087                         break;
1088         }
1089
1090         if (!ret)
1091                 writel(conf, conf_reg);
1092
1093         raw_spin_unlock_irqrestore(&byt_lock, flags);
1094
1095         return ret;
1096 }
1097
1098 static const struct pinconf_ops byt_pinconf_ops = {
1099         .is_generic     = true,
1100         .pin_config_get = byt_pin_config_get,
1101         .pin_config_set = byt_pin_config_set,
1102 };
1103
1104 static const struct pinctrl_desc byt_pinctrl_desc = {
1105         .pctlops        = &byt_pinctrl_ops,
1106         .pmxops         = &byt_pinmux_ops,
1107         .confops        = &byt_pinconf_ops,
1108         .owner          = THIS_MODULE,
1109 };
1110
1111 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1112 {
1113         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1114         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1115         unsigned long flags;
1116         u32 val;
1117
1118         raw_spin_lock_irqsave(&byt_lock, flags);
1119         val = readl(reg);
1120         raw_spin_unlock_irqrestore(&byt_lock, flags);
1121
1122         return !!(val & BYT_LEVEL);
1123 }
1124
1125 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1126 {
1127         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1128         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1129         unsigned long flags;
1130         u32 old_val;
1131
1132         if (!reg)
1133                 return;
1134
1135         raw_spin_lock_irqsave(&byt_lock, flags);
1136         old_val = readl(reg);
1137         if (value)
1138                 writel(old_val | BYT_LEVEL, reg);
1139         else
1140                 writel(old_val & ~BYT_LEVEL, reg);
1141         raw_spin_unlock_irqrestore(&byt_lock, flags);
1142 }
1143
1144 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1145 {
1146         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1147         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1148         unsigned long flags;
1149         u32 value;
1150
1151         if (!reg)
1152                 return -EINVAL;
1153
1154         raw_spin_lock_irqsave(&byt_lock, flags);
1155         value = readl(reg);
1156         raw_spin_unlock_irqrestore(&byt_lock, flags);
1157
1158         if (!(value & BYT_OUTPUT_EN))
1159                 return GPIO_LINE_DIRECTION_OUT;
1160         if (!(value & BYT_INPUT_EN))
1161                 return GPIO_LINE_DIRECTION_IN;
1162
1163         return -EINVAL;
1164 }
1165
1166 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1167 {
1168         return pinctrl_gpio_direction_input(chip->base + offset);
1169 }
1170
1171 static int byt_gpio_direction_output(struct gpio_chip *chip,
1172                                      unsigned int offset, int value)
1173 {
1174         int ret = pinctrl_gpio_direction_output(chip->base + offset);
1175
1176         if (ret)
1177                 return ret;
1178
1179         byt_gpio_set(chip, offset, value);
1180
1181         return 0;
1182 }
1183
1184 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1185 {
1186         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1187         int i;
1188         u32 conf0, val;
1189
1190         for (i = 0; i < vg->soc->npins; i++) {
1191                 const struct intel_community *comm;
1192                 const char *pull_str = NULL;
1193                 const char *pull = NULL;
1194                 void __iomem *reg;
1195                 unsigned long flags;
1196                 const char *label;
1197                 unsigned int pin;
1198
1199                 raw_spin_lock_irqsave(&byt_lock, flags);
1200                 pin = vg->soc->pins[i].number;
1201                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1202                 if (!reg) {
1203                         seq_printf(s,
1204                                    "Could not retrieve pin %i conf0 reg\n",
1205                                    pin);
1206                         raw_spin_unlock_irqrestore(&byt_lock, flags);
1207                         continue;
1208                 }
1209                 conf0 = readl(reg);
1210
1211                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1212                 if (!reg) {
1213                         seq_printf(s,
1214                                    "Could not retrieve pin %i val reg\n", pin);
1215                         raw_spin_unlock_irqrestore(&byt_lock, flags);
1216                         continue;
1217                 }
1218                 val = readl(reg);
1219                 raw_spin_unlock_irqrestore(&byt_lock, flags);
1220
1221                 comm = byt_get_community(vg, pin);
1222                 if (!comm) {
1223                         seq_printf(s,
1224                                    "Could not get community for pin %i\n", pin);
1225                         continue;
1226                 }
1227                 label = gpiochip_is_requested(chip, i);
1228                 if (!label)
1229                         label = "Unrequested";
1230
1231                 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1232                 case BYT_PULL_ASSIGN_UP:
1233                         pull = "up";
1234                         break;
1235                 case BYT_PULL_ASSIGN_DOWN:
1236                         pull = "down";
1237                         break;
1238                 }
1239
1240                 switch (conf0 & BYT_PULL_STR_MASK) {
1241                 case BYT_PULL_STR_2K:
1242                         pull_str = "2k";
1243                         break;
1244                 case BYT_PULL_STR_10K:
1245                         pull_str = "10k";
1246                         break;
1247                 case BYT_PULL_STR_20K:
1248                         pull_str = "20k";
1249                         break;
1250                 case BYT_PULL_STR_40K:
1251                         pull_str = "40k";
1252                         break;
1253                 }
1254
1255                 seq_printf(s,
1256                            " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1257                            pin,
1258                            label,
1259                            val & BYT_INPUT_EN ? "  " : "in",
1260                            val & BYT_OUTPUT_EN ? "   " : "out",
1261                            val & BYT_LEVEL ? "hi" : "lo",
1262                            comm->pad_map[i], comm->pad_map[i] * 16,
1263                            conf0 & 0x7,
1264                            conf0 & BYT_TRIG_NEG ? " fall" : "     ",
1265                            conf0 & BYT_TRIG_POS ? " rise" : "     ",
1266                            conf0 & BYT_TRIG_LVL ? " level" : "      ");
1267
1268                 if (pull && pull_str)
1269                         seq_printf(s, " %-4s %-3s", pull, pull_str);
1270                 else
1271                         seq_puts(s, "          ");
1272
1273                 if (conf0 & BYT_IODEN)
1274                         seq_puts(s, " open-drain");
1275
1276                 seq_puts(s, "\n");
1277         }
1278 }
1279
1280 static const struct gpio_chip byt_gpio_chip = {
1281         .owner                  = THIS_MODULE,
1282         .request                = gpiochip_generic_request,
1283         .free                   = gpiochip_generic_free,
1284         .get_direction          = byt_gpio_get_direction,
1285         .direction_input        = byt_gpio_direction_input,
1286         .direction_output       = byt_gpio_direction_output,
1287         .get                    = byt_gpio_get,
1288         .set                    = byt_gpio_set,
1289         .set_config             = gpiochip_generic_config,
1290         .dbg_show               = byt_gpio_dbg_show,
1291 };
1292
1293 static void byt_irq_ack(struct irq_data *d)
1294 {
1295         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1296         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1297         unsigned int offset = irqd_to_hwirq(d);
1298         void __iomem *reg;
1299
1300         reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1301         if (!reg)
1302                 return;
1303
1304         raw_spin_lock(&byt_lock);
1305         writel(BIT(offset % 32), reg);
1306         raw_spin_unlock(&byt_lock);
1307 }
1308
1309 static void byt_irq_mask(struct irq_data *d)
1310 {
1311         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1312         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1313
1314         byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1315 }
1316
1317 static void byt_irq_unmask(struct irq_data *d)
1318 {
1319         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1320         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1321         unsigned int offset = irqd_to_hwirq(d);
1322         unsigned long flags;
1323         void __iomem *reg;
1324         u32 value;
1325
1326         reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1327         if (!reg)
1328                 return;
1329
1330         raw_spin_lock_irqsave(&byt_lock, flags);
1331         value = readl(reg);
1332
1333         switch (irqd_get_trigger_type(d)) {
1334         case IRQ_TYPE_LEVEL_HIGH:
1335                 value |= BYT_TRIG_LVL;
1336                 /* fall through */
1337         case IRQ_TYPE_EDGE_RISING:
1338                 value |= BYT_TRIG_POS;
1339                 break;
1340         case IRQ_TYPE_LEVEL_LOW:
1341                 value |= BYT_TRIG_LVL;
1342                 /* fall through */
1343         case IRQ_TYPE_EDGE_FALLING:
1344                 value |= BYT_TRIG_NEG;
1345                 break;
1346         case IRQ_TYPE_EDGE_BOTH:
1347                 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1348                 break;
1349         }
1350
1351         writel(value, reg);
1352
1353         raw_spin_unlock_irqrestore(&byt_lock, flags);
1354 }
1355
1356 static int byt_irq_type(struct irq_data *d, unsigned int type)
1357 {
1358         struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1359         u32 offset = irqd_to_hwirq(d);
1360         u32 value;
1361         unsigned long flags;
1362         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1363
1364         if (!reg || offset >= vg->chip.ngpio)
1365                 return -EINVAL;
1366
1367         raw_spin_lock_irqsave(&byt_lock, flags);
1368         value = readl(reg);
1369
1370         WARN(value & BYT_DIRECT_IRQ_EN,
1371              "Bad pad config for io mode, force direct_irq_en bit clearing");
1372
1373         /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1374          * are used to indicate high and low level triggering
1375          */
1376         value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1377                    BYT_TRIG_LVL);
1378         /* Enable glitch filtering */
1379         value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1380                  BYT_GLITCH_F_FAST_CLK;
1381
1382         writel(value, reg);
1383
1384         if (type & IRQ_TYPE_EDGE_BOTH)
1385                 irq_set_handler_locked(d, handle_edge_irq);
1386         else if (type & IRQ_TYPE_LEVEL_MASK)
1387                 irq_set_handler_locked(d, handle_level_irq);
1388
1389         raw_spin_unlock_irqrestore(&byt_lock, flags);
1390
1391         return 0;
1392 }
1393
1394 static void byt_gpio_irq_handler(struct irq_desc *desc)
1395 {
1396         struct irq_data *data = irq_desc_get_irq_data(desc);
1397         struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
1398         struct irq_chip *chip = irq_data_get_irq_chip(data);
1399         u32 base, pin;
1400         void __iomem *reg;
1401         unsigned long pending;
1402         unsigned int virq;
1403
1404         /* check from GPIO controller which pin triggered the interrupt */
1405         for (base = 0; base < vg->chip.ngpio; base += 32) {
1406                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1407
1408                 if (!reg) {
1409                         dev_warn(vg->dev,
1410                                  "Pin %i: could not retrieve interrupt status register\n",
1411                                  base);
1412                         continue;
1413                 }
1414
1415                 raw_spin_lock(&byt_lock);
1416                 pending = readl(reg);
1417                 raw_spin_unlock(&byt_lock);
1418                 for_each_set_bit(pin, &pending, 32) {
1419                         virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
1420                         generic_handle_irq(virq);
1421                 }
1422         }
1423         chip->irq_eoi(data);
1424 }
1425
1426 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
1427                                     unsigned long *valid_mask,
1428                                     unsigned int ngpios)
1429 {
1430         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1431         void __iomem *reg;
1432         u32 value;
1433         int i;
1434
1435         /*
1436          * Clear interrupt triggers for all pins that are GPIOs and
1437          * do not use direct IRQ mode. This will prevent spurious
1438          * interrupts from misconfigured pins.
1439          */
1440         for (i = 0; i < vg->soc->npins; i++) {
1441                 unsigned int pin = vg->soc->pins[i].number;
1442
1443                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1444                 if (!reg) {
1445                         dev_warn(vg->dev,
1446                                  "Pin %i: could not retrieve conf0 register\n",
1447                                  i);
1448                         continue;
1449                 }
1450
1451                 value = readl(reg);
1452                 if (value & BYT_DIRECT_IRQ_EN) {
1453                         clear_bit(i, valid_mask);
1454                         dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i);
1455                 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1456                         byt_gpio_clear_triggering(vg, i);
1457                         dev_dbg(vg->dev, "disabling GPIO %d\n", i);
1458                 }
1459         }
1460 }
1461
1462 static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
1463 {
1464         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1465         void __iomem *reg;
1466         u32 base, value;
1467
1468         /* clear interrupt status trigger registers */
1469         for (base = 0; base < vg->soc->npins; base += 32) {
1470                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1471
1472                 if (!reg) {
1473                         dev_warn(vg->dev,
1474                                  "Pin %i: could not retrieve irq status reg\n",
1475                                  base);
1476                         continue;
1477                 }
1478
1479                 writel(0xffffffff, reg);
1480                 /* make sure trigger bits are cleared, if not then a pin
1481                    might be misconfigured in bios */
1482                 value = readl(reg);
1483                 if (value)
1484                         dev_err(vg->dev,
1485                                 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
1486                                 base / 32, value);
1487         }
1488
1489         return 0;
1490 }
1491
1492 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
1493 {
1494         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1495         struct device *dev = vg->dev;
1496         int ret;
1497
1498         ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
1499         if (ret)
1500                 dev_err(dev, "failed to add GPIO pin range\n");
1501
1502         return ret;
1503 }
1504
1505 static int byt_gpio_probe(struct intel_pinctrl *vg)
1506 {
1507         struct platform_device *pdev = to_platform_device(vg->dev);
1508         struct gpio_chip *gc;
1509         int irq, ret;
1510
1511         /* Set up gpio chip */
1512         vg->chip        = byt_gpio_chip;
1513         gc              = &vg->chip;
1514         gc->label       = dev_name(vg->dev);
1515         gc->base        = -1;
1516         gc->can_sleep   = false;
1517         gc->add_pin_ranges = byt_gpio_add_pin_ranges;
1518         gc->parent      = vg->dev;
1519         gc->ngpio       = vg->soc->npins;
1520
1521 #ifdef CONFIG_PM_SLEEP
1522         vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),
1523                                         GFP_KERNEL);
1524         if (!vg->context.pads)
1525                 return -ENOMEM;
1526 #endif
1527
1528         /* set up interrupts  */
1529         irq = platform_get_irq_optional(pdev, 0);
1530         if (irq > 0) {
1531                 struct gpio_irq_chip *girq;
1532
1533                 vg->irqchip.name = "BYT-GPIO",
1534                 vg->irqchip.irq_ack = byt_irq_ack,
1535                 vg->irqchip.irq_mask = byt_irq_mask,
1536                 vg->irqchip.irq_unmask = byt_irq_unmask,
1537                 vg->irqchip.irq_set_type = byt_irq_type,
1538                 vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE,
1539
1540                 girq = &gc->irq;
1541                 girq->chip = &vg->irqchip;
1542                 girq->init_hw = byt_gpio_irq_init_hw;
1543                 girq->init_valid_mask = byt_init_irq_valid_mask;
1544                 girq->parent_handler = byt_gpio_irq_handler;
1545                 girq->num_parents = 1;
1546                 girq->parents = devm_kcalloc(vg->dev, girq->num_parents,
1547                                              sizeof(*girq->parents), GFP_KERNEL);
1548                 if (!girq->parents)
1549                         return -ENOMEM;
1550                 girq->parents[0] = irq;
1551                 girq->default_type = IRQ_TYPE_NONE;
1552                 girq->handler = handle_bad_irq;
1553         }
1554
1555         ret = devm_gpiochip_add_data(vg->dev, gc, vg);
1556         if (ret) {
1557                 dev_err(vg->dev, "failed adding byt-gpio chip\n");
1558                 return ret;
1559         }
1560
1561         return ret;
1562 }
1563
1564 static int byt_set_soc_data(struct intel_pinctrl *vg,
1565                             const struct intel_pinctrl_soc_data *soc)
1566 {
1567         struct platform_device *pdev = to_platform_device(vg->dev);
1568         int i;
1569
1570         vg->soc = soc;
1571
1572         vg->ncommunities = vg->soc->ncommunities;
1573         vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,
1574                                        sizeof(*vg->communities), GFP_KERNEL);
1575         if (!vg->communities)
1576                 return -ENOMEM;
1577
1578         for (i = 0; i < vg->soc->ncommunities; i++) {
1579                 struct intel_community *comm = vg->communities + i;
1580
1581                 *comm = vg->soc->communities[i];
1582
1583                 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0);
1584                 if (IS_ERR(comm->pad_regs))
1585                         return PTR_ERR(comm->pad_regs);
1586         }
1587
1588         return 0;
1589 }
1590
1591 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1592         { "INT33B2", (kernel_ulong_t)byt_soc_data },
1593         { "INT33FC", (kernel_ulong_t)byt_soc_data },
1594         { }
1595 };
1596
1597 static int byt_pinctrl_probe(struct platform_device *pdev)
1598 {
1599         const struct intel_pinctrl_soc_data *soc_data = NULL;
1600         const struct intel_pinctrl_soc_data **soc_table;
1601         struct device *dev = &pdev->dev;
1602         struct acpi_device *acpi_dev;
1603         struct intel_pinctrl *vg;
1604         int i, ret;
1605
1606         acpi_dev = ACPI_COMPANION(dev);
1607         if (!acpi_dev)
1608                 return -ENODEV;
1609
1610         soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev);
1611
1612         for (i = 0; soc_table[i]; i++) {
1613                 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
1614                         soc_data = soc_table[i];
1615                         break;
1616                 }
1617         }
1618
1619         if (!soc_data)
1620                 return -ENODEV;
1621
1622         vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
1623         if (!vg)
1624                 return -ENOMEM;
1625
1626         vg->dev = dev;
1627         ret = byt_set_soc_data(vg, soc_data);
1628         if (ret) {
1629                 dev_err(dev, "failed to set soc data\n");
1630                 return ret;
1631         }
1632
1633         vg->pctldesc            = byt_pinctrl_desc;
1634         vg->pctldesc.name       = dev_name(dev);
1635         vg->pctldesc.pins       = vg->soc->pins;
1636         vg->pctldesc.npins      = vg->soc->npins;
1637
1638         vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
1639         if (IS_ERR(vg->pctldev)) {
1640                 dev_err(dev, "failed to register pinctrl driver\n");
1641                 return PTR_ERR(vg->pctldev);
1642         }
1643
1644         ret = byt_gpio_probe(vg);
1645         if (ret)
1646                 return ret;
1647
1648         platform_set_drvdata(pdev, vg);
1649         pm_runtime_enable(dev);
1650
1651         return 0;
1652 }
1653
1654 #ifdef CONFIG_PM_SLEEP
1655 static int byt_gpio_suspend(struct device *dev)
1656 {
1657         struct intel_pinctrl *vg = dev_get_drvdata(dev);
1658         unsigned long flags;
1659         int i;
1660
1661         raw_spin_lock_irqsave(&byt_lock, flags);
1662
1663         for (i = 0; i < vg->soc->npins; i++) {
1664                 void __iomem *reg;
1665                 u32 value;
1666                 unsigned int pin = vg->soc->pins[i].number;
1667
1668                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1669                 if (!reg) {
1670                         dev_warn(vg->dev,
1671                                  "Pin %i: could not retrieve conf0 register\n",
1672                                  i);
1673                         continue;
1674                 }
1675                 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1676                 vg->context.pads[i].conf0 = value;
1677
1678                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1679                 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1680                 vg->context.pads[i].val = value;
1681         }
1682
1683         raw_spin_unlock_irqrestore(&byt_lock, flags);
1684         return 0;
1685 }
1686
1687 static int byt_gpio_resume(struct device *dev)
1688 {
1689         struct intel_pinctrl *vg = dev_get_drvdata(dev);
1690         unsigned long flags;
1691         int i;
1692
1693         raw_spin_lock_irqsave(&byt_lock, flags);
1694
1695         for (i = 0; i < vg->soc->npins; i++) {
1696                 void __iomem *reg;
1697                 u32 value;
1698                 unsigned int pin = vg->soc->pins[i].number;
1699
1700                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1701                 if (!reg) {
1702                         dev_warn(vg->dev,
1703                                  "Pin %i: could not retrieve conf0 register\n",
1704                                  i);
1705                         continue;
1706                 }
1707                 value = readl(reg);
1708                 if ((value & BYT_CONF0_RESTORE_MASK) !=
1709                      vg->context.pads[i].conf0) {
1710                         value &= ~BYT_CONF0_RESTORE_MASK;
1711                         value |= vg->context.pads[i].conf0;
1712                         writel(value, reg);
1713                         dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1714                 }
1715
1716                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1717                 value = readl(reg);
1718                 if ((value & BYT_VAL_RESTORE_MASK) !=
1719                      vg->context.pads[i].val) {
1720                         u32 v;
1721
1722                         v = value & ~BYT_VAL_RESTORE_MASK;
1723                         v |= vg->context.pads[i].val;
1724                         if (v != value) {
1725                                 writel(v, reg);
1726                                 dev_dbg(dev, "restored pin %d val %#08x\n",
1727                                         i, v);
1728                         }
1729                 }
1730         }
1731
1732         raw_spin_unlock_irqrestore(&byt_lock, flags);
1733         return 0;
1734 }
1735 #endif
1736
1737 #ifdef CONFIG_PM
1738 static int byt_gpio_runtime_suspend(struct device *dev)
1739 {
1740         return 0;
1741 }
1742
1743 static int byt_gpio_runtime_resume(struct device *dev)
1744 {
1745         return 0;
1746 }
1747 #endif
1748
1749 static const struct dev_pm_ops byt_gpio_pm_ops = {
1750         SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1751         SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1752                            NULL)
1753 };
1754
1755 static struct platform_driver byt_gpio_driver = {
1756         .probe          = byt_pinctrl_probe,
1757         .driver         = {
1758                 .name                   = "byt_gpio",
1759                 .pm                     = &byt_gpio_pm_ops,
1760                 .suppress_bind_attrs    = true,
1761
1762                 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
1763         },
1764 };
1765
1766 static int __init byt_gpio_init(void)
1767 {
1768         return platform_driver_register(&byt_gpio_driver);
1769 }
1770 subsys_initcall(byt_gpio_init);