drivers/pinctrl/intel/pinctrl-baytrail.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pinctrl GPIO driver for Intel Baytrail
   4  *
   5  * Copyright (c) 2012-2013, Intel Corporation
   6  * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/bitops.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/kernel.h>
  16 #include <linux/types.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/property.h>
  20 #include <linux/seq_file.h>
  21
  22 #include <linux/pinctrl/pinctrl.h>
  23 #include <linux/pinctrl/pinmux.h>
  24 #include <linux/pinctrl/pinconf.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26
  27 #include "pinctrl-intel.h"
  28
  29 /* memory mapped register offsets */
  30 #define BYT_CONF0_REG           0x000
  31 #define BYT_CONF1_REG           0x004
  32 #define BYT_VAL_REG             0x008
  33 #define BYT_DFT_REG             0x00c
  34 #define BYT_INT_STAT_REG        0x800
  35 #define BYT_DIRECT_IRQ_REG      0x980
  36 #define BYT_DEBOUNCE_REG        0x9d0
  37
  38 /* BYT_CONF0_REG register bits */
  39 #define BYT_IODEN               BIT(31)
  40 #define BYT_DIRECT_IRQ_EN       BIT(27)
  41 #define BYT_TRIG_MASK           GENMASK(26, 24)
  42 #define BYT_TRIG_NEG            BIT(26)
  43 #define BYT_TRIG_POS            BIT(25)
  44 #define BYT_TRIG_LVL            BIT(24)
  45 #define BYT_DEBOUNCE_EN         BIT(20)
  46 #define BYT_GLITCH_FILTER_EN    BIT(19)
  47 #define BYT_GLITCH_F_SLOW_CLK   BIT(17)
  48 #define BYT_GLITCH_F_FAST_CLK   BIT(16)
  49 #define BYT_PULL_STR_SHIFT      9
  50 #define BYT_PULL_STR_MASK       GENMASK(10, 9)
  51 #define BYT_PULL_STR_2K         (0 << BYT_PULL_STR_SHIFT)
  52 #define BYT_PULL_STR_10K        (1 << BYT_PULL_STR_SHIFT)
  53 #define BYT_PULL_STR_20K        (2 << BYT_PULL_STR_SHIFT)
  54 #define BYT_PULL_STR_40K        (3 << BYT_PULL_STR_SHIFT)
  55 #define BYT_PULL_ASSIGN_SHIFT   7
  56 #define BYT_PULL_ASSIGN_MASK    GENMASK(8, 7)
  57 #define BYT_PULL_ASSIGN_UP      (1 << BYT_PULL_ASSIGN_SHIFT)
  58 #define BYT_PULL_ASSIGN_DOWN    (2 << BYT_PULL_ASSIGN_SHIFT)
  59 #define BYT_PIN_MUX             GENMASK(2, 0)
  60
  61 /* BYT_VAL_REG register bits */
  62 #define BYT_DIR_MASK            GENMASK(2, 1)
  63 #define BYT_INPUT_EN            BIT(2)  /* 0: input enabled (active low)*/
  64 #define BYT_OUTPUT_EN           BIT(1)  /* 0: output enabled (active low)*/
  65 #define BYT_LEVEL               BIT(0)
  66
  67 #define BYT_CONF0_RESTORE_MASK  (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
  68 #define BYT_VAL_RESTORE_MASK    (BYT_DIR_MASK | BYT_LEVEL)
  69
  70 /* BYT_DEBOUNCE_REG bits */
  71 #define BYT_DEBOUNCE_PULSE_MASK         GENMASK(2, 0)
  72 #define BYT_DEBOUNCE_PULSE_375US        1
  73 #define BYT_DEBOUNCE_PULSE_750US        2
  74 #define BYT_DEBOUNCE_PULSE_1500US       3
  75 #define BYT_DEBOUNCE_PULSE_3MS          4
  76 #define BYT_DEBOUNCE_PULSE_6MS          5
  77 #define BYT_DEBOUNCE_PULSE_12MS         6
  78 #define BYT_DEBOUNCE_PULSE_24MS         7
  79
  80 #define BYT_NGPIO_SCORE         102
  81 #define BYT_NGPIO_NCORE         28
  82 #define BYT_NGPIO_SUS           44
  83
  84 #define BYT_SCORE_ACPI_UID      "1"
  85 #define BYT_NCORE_ACPI_UID      "2"
  86 #define BYT_SUS_ACPI_UID        "3"
  87
  88 /*
  89  * This is the function value most pins have for GPIO muxing. If the value
  90  * differs from the default one, it must be explicitly mentioned. Otherwise, the
  91  * pin control implementation will set the muxing value to default GPIO if it
  92  * does not find a match for the requested function.
  93  */
  94 #define BYT_DEFAULT_GPIO_MUX    0
  95 #define BYT_ALTER_GPIO_MUX      1
  96
  97 struct intel_pad_context {
  98         u32 conf0;
  99         u32 val;
 100 };
 101
 102 #define COMMUNITY(p, n, map)            \
 103         {                               \
 104                 .pin_base       = (p),  \
 105                 .npins          = (n),  \
 106                 .pad_map        = (map),\
 107         }
 108
 109 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
 110 static const struct pinctrl_pin_desc byt_score_pins[] = {
 111         PINCTRL_PIN(0, "SATA_GP0"),
 112         PINCTRL_PIN(1, "SATA_GP1"),
 113         PINCTRL_PIN(2, "SATA_LED#"),
 114         PINCTRL_PIN(3, "PCIE_CLKREQ0"),
 115         PINCTRL_PIN(4, "PCIE_CLKREQ1"),
 116         PINCTRL_PIN(5, "PCIE_CLKREQ2"),
 117         PINCTRL_PIN(6, "PCIE_CLKREQ3"),
 118         PINCTRL_PIN(7, "SD3_WP"),
 119         PINCTRL_PIN(8, "HDA_RST"),
 120         PINCTRL_PIN(9, "HDA_SYNC"),
 121         PINCTRL_PIN(10, "HDA_CLK"),
 122         PINCTRL_PIN(11, "HDA_SDO"),
 123         PINCTRL_PIN(12, "HDA_SDI0"),
 124         PINCTRL_PIN(13, "HDA_SDI1"),
 125         PINCTRL_PIN(14, "GPIO_S0_SC14"),
 126         PINCTRL_PIN(15, "GPIO_S0_SC15"),
 127         PINCTRL_PIN(16, "MMC1_CLK"),
 128         PINCTRL_PIN(17, "MMC1_D0"),
 129         PINCTRL_PIN(18, "MMC1_D1"),
 130         PINCTRL_PIN(19, "MMC1_D2"),
 131         PINCTRL_PIN(20, "MMC1_D3"),
 132         PINCTRL_PIN(21, "MMC1_D4"),
 133         PINCTRL_PIN(22, "MMC1_D5"),
 134         PINCTRL_PIN(23, "MMC1_D6"),
 135         PINCTRL_PIN(24, "MMC1_D7"),
 136         PINCTRL_PIN(25, "MMC1_CMD"),
 137         PINCTRL_PIN(26, "MMC1_RST"),
 138         PINCTRL_PIN(27, "SD2_CLK"),
 139         PINCTRL_PIN(28, "SD2_D0"),
 140         PINCTRL_PIN(29, "SD2_D1"),
 141         PINCTRL_PIN(30, "SD2_D2"),
 142         PINCTRL_PIN(31, "SD2_D3_CD"),
 143         PINCTRL_PIN(32, "SD2_CMD"),
 144         PINCTRL_PIN(33, "SD3_CLK"),
 145         PINCTRL_PIN(34, "SD3_D0"),
 146         PINCTRL_PIN(35, "SD3_D1"),
 147         PINCTRL_PIN(36, "SD3_D2"),
 148         PINCTRL_PIN(37, "SD3_D3"),
 149         PINCTRL_PIN(38, "SD3_CD"),
 150         PINCTRL_PIN(39, "SD3_CMD"),
 151         PINCTRL_PIN(40, "SD3_1P8EN"),
 152         PINCTRL_PIN(41, "SD3_PWREN#"),
 153         PINCTRL_PIN(42, "ILB_LPC_AD0"),
 154         PINCTRL_PIN(43, "ILB_LPC_AD1"),
 155         PINCTRL_PIN(44, "ILB_LPC_AD2"),
 156         PINCTRL_PIN(45, "ILB_LPC_AD3"),
 157         PINCTRL_PIN(46, "ILB_LPC_FRAME"),
 158         PINCTRL_PIN(47, "ILB_LPC_CLK0"),
 159         PINCTRL_PIN(48, "ILB_LPC_CLK1"),
 160         PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
 161         PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
 162         PINCTRL_PIN(51, "PCU_SMB_DATA"),
 163         PINCTRL_PIN(52, "PCU_SMB_CLK"),
 164         PINCTRL_PIN(53, "PCU_SMB_ALERT"),
 165         PINCTRL_PIN(54, "ILB_8254_SPKR"),
 166         PINCTRL_PIN(55, "GPIO_S0_SC55"),
 167         PINCTRL_PIN(56, "GPIO_S0_SC56"),
 168         PINCTRL_PIN(57, "GPIO_S0_SC57"),
 169         PINCTRL_PIN(58, "GPIO_S0_SC58"),
 170         PINCTRL_PIN(59, "GPIO_S0_SC59"),
 171         PINCTRL_PIN(60, "GPIO_S0_SC60"),
 172         PINCTRL_PIN(61, "GPIO_S0_SC61"),
 173         PINCTRL_PIN(62, "LPE_I2S2_CLK"),
 174         PINCTRL_PIN(63, "LPE_I2S2_FRM"),
 175         PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
 176         PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
 177         PINCTRL_PIN(66, "SIO_SPI_CS"),
 178         PINCTRL_PIN(67, "SIO_SPI_MISO"),
 179         PINCTRL_PIN(68, "SIO_SPI_MOSI"),
 180         PINCTRL_PIN(69, "SIO_SPI_CLK"),
 181         PINCTRL_PIN(70, "SIO_UART1_RXD"),
 182         PINCTRL_PIN(71, "SIO_UART1_TXD"),
 183         PINCTRL_PIN(72, "SIO_UART1_RTS"),
 184         PINCTRL_PIN(73, "SIO_UART1_CTS"),
 185         PINCTRL_PIN(74, "SIO_UART2_RXD"),
 186         PINCTRL_PIN(75, "SIO_UART2_TXD"),
 187         PINCTRL_PIN(76, "SIO_UART2_RTS"),
 188         PINCTRL_PIN(77, "SIO_UART2_CTS"),
 189         PINCTRL_PIN(78, "SIO_I2C0_DATA"),
 190         PINCTRL_PIN(79, "SIO_I2C0_CLK"),
 191         PINCTRL_PIN(80, "SIO_I2C1_DATA"),
 192         PINCTRL_PIN(81, "SIO_I2C1_CLK"),
 193         PINCTRL_PIN(82, "SIO_I2C2_DATA"),
 194         PINCTRL_PIN(83, "SIO_I2C2_CLK"),
 195         PINCTRL_PIN(84, "SIO_I2C3_DATA"),
 196         PINCTRL_PIN(85, "SIO_I2C3_CLK"),
 197         PINCTRL_PIN(86, "SIO_I2C4_DATA"),
 198         PINCTRL_PIN(87, "SIO_I2C4_CLK"),
 199         PINCTRL_PIN(88, "SIO_I2C5_DATA"),
 200         PINCTRL_PIN(89, "SIO_I2C5_CLK"),
 201         PINCTRL_PIN(90, "SIO_I2C6_DATA"),
 202         PINCTRL_PIN(91, "SIO_I2C6_CLK"),
 203         PINCTRL_PIN(92, "GPIO_S0_SC92"),
 204         PINCTRL_PIN(93, "GPIO_S0_SC93"),
 205         PINCTRL_PIN(94, "SIO_PWM0"),
 206         PINCTRL_PIN(95, "SIO_PWM1"),
 207         PINCTRL_PIN(96, "PMC_PLT_CLK0"),
 208         PINCTRL_PIN(97, "PMC_PLT_CLK1"),
 209         PINCTRL_PIN(98, "PMC_PLT_CLK2"),
 210         PINCTRL_PIN(99, "PMC_PLT_CLK3"),
 211         PINCTRL_PIN(100, "PMC_PLT_CLK4"),
 212         PINCTRL_PIN(101, "PMC_PLT_CLK5"),
 213 };
 214
 215 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
 216         85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
 217         36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
 218         54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
 219         52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
 220         95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
 221         86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
 222         80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
 223         2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
 224         31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
 225         24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
 226         97, 100,
 227 };
 228
 229 /* SCORE groups */
 230 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
 231 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
 232
 233 static const unsigned int byt_score_pwm0_pins[] = { 94 };
 234 static const unsigned int byt_score_pwm1_pins[] = { 95 };
 235
 236 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
 237
 238 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
 239 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
 240 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
 241 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
 242 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
 243 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
 244 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
 245
 246 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
 247 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
 248 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
 249
 250 static const unsigned int byt_score_sdcard_pins[] = {
 251         7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
 252 };
 253 static const unsigned int byt_score_sdcard_mux_values[] = {
 254         2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 255 };
 256
 257 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
 258
 259 static const unsigned int byt_score_emmc_pins[] = {
 260         16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
 261 };
 262
 263 static const unsigned int byt_score_ilb_lpc_pins[] = {
 264         42, 43, 44, 45, 46, 47, 48, 49, 50,
 265 };
 266
 267 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
 268
 269 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
 270 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
 271 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
 272 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
 273 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
 274 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
 275
 276 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
 277
 278 static const struct intel_pingroup byt_score_groups[] = {
 279         PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
 280         PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
 281         PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
 282         PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
 283         PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
 284         PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
 285         PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
 286         PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
 287         PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
 288         PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
 289         PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
 290         PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
 291         PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
 292         PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
 293         PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
 294         PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
 295         PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
 296         PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
 297         PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
 298         PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
 299         PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
 300         PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
 301         PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
 302         PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
 303         PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
 304         PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
 305         PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
 306 };
 307
 308 static const char * const byt_score_uart_groups[] = {
 309         "uart1_grp", "uart2_grp",
 310 };
 311 static const char * const byt_score_pwm_groups[] = {
 312         "pwm0_grp", "pwm1_grp",
 313 };
 314 static const char * const byt_score_ssp_groups[] = {
 315         "ssp0_grp", "ssp1_grp", "ssp2_grp",
 316 };
 317 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
 318 static const char * const byt_score_i2c_groups[] = {
 319         "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
 320         "i2c6_grp",
 321 };
 322 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
 323 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
 324 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
 325 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
 326 static const char * const byt_score_sata_groups[] = { "sata_grp" };
 327 static const char * const byt_score_plt_clk_groups[] = {
 328         "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
 329         "plt_clk4_grp", "plt_clk5_grp",
 330 };
 331 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
 332 static const char * const byt_score_gpio_groups[] = {
 333         "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
 334         "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
 335         "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
 336         "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
 337         "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
 338         "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
 339 };
 340
 341 static const struct intel_function byt_score_functions[] = {
 342         FUNCTION("uart", byt_score_uart_groups),
 343         FUNCTION("pwm", byt_score_pwm_groups),
 344         FUNCTION("ssp", byt_score_ssp_groups),
 345         FUNCTION("spi", byt_score_spi_groups),
 346         FUNCTION("i2c", byt_score_i2c_groups),
 347         FUNCTION("sdcard", byt_score_sdcard_groups),
 348         FUNCTION("sdio", byt_score_sdio_groups),
 349         FUNCTION("emmc", byt_score_emmc_groups),
 350         FUNCTION("lpc", byt_score_lpc_groups),
 351         FUNCTION("sata", byt_score_sata_groups),
 352         FUNCTION("plt_clk", byt_score_plt_clk_groups),
 353         FUNCTION("smbus", byt_score_smbus_groups),
 354         FUNCTION("gpio", byt_score_gpio_groups),
 355 };
 356
 357 static const struct intel_community byt_score_communities[] = {
 358         COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
 359 };
 360
 361 static const struct intel_pinctrl_soc_data byt_score_soc_data = {
 362         .uid            = BYT_SCORE_ACPI_UID,
 363         .pins           = byt_score_pins,
 364         .npins          = ARRAY_SIZE(byt_score_pins),
 365         .groups         = byt_score_groups,
 366         .ngroups        = ARRAY_SIZE(byt_score_groups),
 367         .functions      = byt_score_functions,
 368         .nfunctions     = ARRAY_SIZE(byt_score_functions),
 369         .communities    = byt_score_communities,
 370         .ncommunities   = ARRAY_SIZE(byt_score_communities),
 371 };
 372
 373 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>]  */
 374 static const struct pinctrl_pin_desc byt_sus_pins[] = {
 375         PINCTRL_PIN(0, "GPIO_S50"),
 376         PINCTRL_PIN(1, "GPIO_S51"),
 377         PINCTRL_PIN(2, "GPIO_S52"),
 378         PINCTRL_PIN(3, "GPIO_S53"),
 379         PINCTRL_PIN(4, "GPIO_S54"),
 380         PINCTRL_PIN(5, "GPIO_S55"),
 381         PINCTRL_PIN(6, "GPIO_S56"),
 382         PINCTRL_PIN(7, "GPIO_S57"),
 383         PINCTRL_PIN(8, "GPIO_S58"),
 384         PINCTRL_PIN(9, "GPIO_S59"),
 385         PINCTRL_PIN(10, "GPIO_S510"),
 386         PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
 387         PINCTRL_PIN(12, "PMC_SUSCLK0"),
 388         PINCTRL_PIN(13, "GPIO_S513"),
 389         PINCTRL_PIN(14, "USB_ULPI_RST"),
 390         PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
 391         PINCTRL_PIN(16, "PMC_PWRBTN"),
 392         PINCTRL_PIN(17, "GPIO_S517"),
 393         PINCTRL_PIN(18, "PMC_SUS_STAT"),
 394         PINCTRL_PIN(19, "USB_OC0"),
 395         PINCTRL_PIN(20, "USB_OC1"),
 396         PINCTRL_PIN(21, "PCU_SPI_CS1"),
 397         PINCTRL_PIN(22, "GPIO_S522"),
 398         PINCTRL_PIN(23, "GPIO_S523"),
 399         PINCTRL_PIN(24, "GPIO_S524"),
 400         PINCTRL_PIN(25, "GPIO_S525"),
 401         PINCTRL_PIN(26, "GPIO_S526"),
 402         PINCTRL_PIN(27, "GPIO_S527"),
 403         PINCTRL_PIN(28, "GPIO_S528"),
 404         PINCTRL_PIN(29, "GPIO_S529"),
 405         PINCTRL_PIN(30, "GPIO_S530"),
 406         PINCTRL_PIN(31, "USB_ULPI_CLK"),
 407         PINCTRL_PIN(32, "USB_ULPI_DATA0"),
 408         PINCTRL_PIN(33, "USB_ULPI_DATA1"),
 409         PINCTRL_PIN(34, "USB_ULPI_DATA2"),
 410         PINCTRL_PIN(35, "USB_ULPI_DATA3"),
 411         PINCTRL_PIN(36, "USB_ULPI_DATA4"),
 412         PINCTRL_PIN(37, "USB_ULPI_DATA5"),
 413         PINCTRL_PIN(38, "USB_ULPI_DATA6"),
 414         PINCTRL_PIN(39, "USB_ULPI_DATA7"),
 415         PINCTRL_PIN(40, "USB_ULPI_DIR"),
 416         PINCTRL_PIN(41, "USB_ULPI_NXT"),
 417         PINCTRL_PIN(42, "USB_ULPI_STP"),
 418         PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
 419 };
 420
 421 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
 422         29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
 423         18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
 424         0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
 425         26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
 426         52, 53, 59, 40,
 427 };
 428
 429 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
 430 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
 431 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
 432
 433 static const unsigned int byt_sus_usb_ulpi_pins[] = {
 434         14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
 435 };
 436 static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
 437         2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 438 };
 439 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
 440         1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 441 };
 442
 443 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
 444 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
 445 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
 446
 447 static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 };
 448 static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 };
 449
 450 static const struct intel_pingroup byt_sus_groups[] = {
 451         PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
 452         PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
 453         PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
 454         PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
 455         PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
 456         PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
 457         PIN_GROUP("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1),
 458         PIN_GROUP("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1),
 459 };
 460
 461 static const char * const byt_sus_usb_groups[] = {
 462         "usb_oc_grp", "usb_ulpi_grp",
 463 };
 464 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
 465 static const char * const byt_sus_pmu_clk_groups[] = {
 466         "pmu_clk1_grp", "pmu_clk2_grp",
 467 };
 468 static const char * const byt_sus_gpio_groups[] = {
 469         "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
 470         "pmu_clk1_grp", "pmu_clk2_grp",
 471 };
 472
 473 static const struct intel_function byt_sus_functions[] = {
 474         FUNCTION("usb", byt_sus_usb_groups),
 475         FUNCTION("spi", byt_sus_spi_groups),
 476         FUNCTION("gpio", byt_sus_gpio_groups),
 477         FUNCTION("pmu_clk", byt_sus_pmu_clk_groups),
 478 };
 479
 480 static const struct intel_community byt_sus_communities[] = {
 481         COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
 482 };
 483
 484 static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
 485         .uid            = BYT_SUS_ACPI_UID,
 486         .pins           = byt_sus_pins,
 487         .npins          = ARRAY_SIZE(byt_sus_pins),
 488         .groups         = byt_sus_groups,
 489         .ngroups        = ARRAY_SIZE(byt_sus_groups),
 490         .functions      = byt_sus_functions,
 491         .nfunctions     = ARRAY_SIZE(byt_sus_functions),
 492         .communities    = byt_sus_communities,
 493         .ncommunities   = ARRAY_SIZE(byt_sus_communities),
 494 };
 495
 496 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
 497         PINCTRL_PIN(0, "HV_DDI0_HPD"),
 498         PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"),
 499         PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"),
 500         PINCTRL_PIN(3, "PANEL0_VDDEN"),
 501         PINCTRL_PIN(4, "PANEL0_BKLTEN"),
 502         PINCTRL_PIN(5, "PANEL0_BKLTCTL"),
 503         PINCTRL_PIN(6, "HV_DDI1_HPD"),
 504         PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"),
 505         PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"),
 506         PINCTRL_PIN(9, "PANEL1_VDDEN"),
 507         PINCTRL_PIN(10, "PANEL1_BKLTEN"),
 508         PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
 509         PINCTRL_PIN(12, "GP_INTD_DSI_TE1"),
 510         PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"),
 511         PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"),
 512         PINCTRL_PIN(15, "GP_CAMERASB00"),
 513         PINCTRL_PIN(16, "GP_CAMERASB01"),
 514         PINCTRL_PIN(17, "GP_CAMERASB02"),
 515         PINCTRL_PIN(18, "GP_CAMERASB03"),
 516         PINCTRL_PIN(19, "GP_CAMERASB04"),
 517         PINCTRL_PIN(20, "GP_CAMERASB05"),
 518         PINCTRL_PIN(21, "GP_CAMERASB06"),
 519         PINCTRL_PIN(22, "GP_CAMERASB07"),
 520         PINCTRL_PIN(23, "GP_CAMERASB08"),
 521         PINCTRL_PIN(24, "GP_CAMERASB09"),
 522         PINCTRL_PIN(25, "GP_CAMERASB10"),
 523         PINCTRL_PIN(26, "GP_CAMERASB11"),
 524         PINCTRL_PIN(27, "GP_INTD_DSI_TE2"),
 525 };
 526
 527 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
 528         19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
 529         14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
 530         3, 6, 10, 13, 2, 5, 9, 7,
 531 };
 532
 533 static const struct intel_community byt_ncore_communities[] = {
 534         COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
 535 };
 536
 537 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
 538         .uid            = BYT_NCORE_ACPI_UID,
 539         .pins           = byt_ncore_pins,
 540         .npins          = ARRAY_SIZE(byt_ncore_pins),
 541         .communities    = byt_ncore_communities,
 542         .ncommunities   = ARRAY_SIZE(byt_ncore_communities),
 543 };
 544
 545 static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
 546         &byt_score_soc_data,
 547         &byt_sus_soc_data,
 548         &byt_ncore_soc_data,
 549         NULL
 550 };
 551
 552 static DEFINE_RAW_SPINLOCK(byt_lock);
 553
 554 static struct intel_community *byt_get_community(struct intel_pinctrl *vg,
 555                                                  unsigned int pin)
 556 {
 557         struct intel_community *comm;
 558         int i;
 559
 560         for (i = 0; i < vg->ncommunities; i++) {
 561                 comm = vg->communities + i;
 562                 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
 563                         return comm;
 564         }
 565
 566         return NULL;
 567 }
 568
 569 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
 570                                   int reg)
 571 {
 572         struct intel_community *comm = byt_get_community(vg, offset);
 573         u32 reg_offset;
 574
 575         if (!comm)
 576                 return NULL;
 577
 578         offset -= comm->pin_base;
 579         switch (reg) {
 580         case BYT_INT_STAT_REG:
 581                 reg_offset = (offset / 32) * 4;
 582                 break;
 583         case BYT_DEBOUNCE_REG:
 584                 reg_offset = 0;
 585                 break;
 586         default:
 587                 reg_offset = comm->pad_map[offset] * 16;
 588                 break;
 589         }
 590
 591         return comm->pad_regs + reg_offset + reg;
 592 }
 593
 594 static int byt_get_groups_count(struct pinctrl_dev *pctldev)
 595 {
 596         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 597
 598         return vg->soc->ngroups;
 599 }
 600
 601 static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
 602                                       unsigned int selector)
 603 {
 604         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 605
 606         return vg->soc->groups[selector].grp.name;
 607 }
 608
 609 static int byt_get_group_pins(struct pinctrl_dev *pctldev,
 610                               unsigned int selector,
 611                               const unsigned int **pins,
 612                               unsigned int *num_pins)
 613 {
 614         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 615
 616         *pins           = vg->soc->groups[selector].grp.pins;
 617         *num_pins       = vg->soc->groups[selector].grp.npins;
 618
 619         return 0;
 620 }
 621
 622 static const struct pinctrl_ops byt_pinctrl_ops = {
 623         .get_groups_count       = byt_get_groups_count,
 624         .get_group_name         = byt_get_group_name,
 625         .get_group_pins         = byt_get_group_pins,
 626 };
 627
 628 static int byt_get_functions_count(struct pinctrl_dev *pctldev)
 629 {
 630         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 631
 632         return vg->soc->nfunctions;
 633 }
 634
 635 static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
 636                                          unsigned int selector)
 637 {
 638         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 639
 640         return vg->soc->functions[selector].func.name;
 641 }
 642
 643 static int byt_get_function_groups(struct pinctrl_dev *pctldev,
 644                                    unsigned int selector,
 645                                    const char * const **groups,
 646                                    unsigned int *ngroups)
 647 {
 648         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 649
 650         *groups         = vg->soc->functions[selector].func.groups;
 651         *ngroups        = vg->soc->functions[selector].func.ngroups;
 652
 653         return 0;
 654 }
 655
 656 static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
 657                                      const struct intel_pingroup group,
 658                                      unsigned int func)
 659 {
 660         unsigned long flags;
 661         int i;
 662
 663         raw_spin_lock_irqsave(&byt_lock, flags);
 664
 665         for (i = 0; i < group.grp.npins; i++) {
 666                 void __iomem *padcfg0;
 667                 u32 value;
 668
 669                 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
 670                 if (!padcfg0) {
 671                         dev_warn(vg->dev,
 672                                  "Group %s, pin %i not muxed (no padcfg0)\n",
 673                                  group.grp.name, i);
 674                         continue;
 675                 }
 676
 677                 value = readl(padcfg0);
 678                 value &= ~BYT_PIN_MUX;
 679                 value |= func;
 680                 writel(value, padcfg0);
 681         }
 682
 683         raw_spin_unlock_irqrestore(&byt_lock, flags);
 684 }
 685
 686 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
 687                                     const struct intel_pingroup group,
 688                                     const unsigned int *func)
 689 {
 690         unsigned long flags;
 691         int i;
 692
 693         raw_spin_lock_irqsave(&byt_lock, flags);
 694
 695         for (i = 0; i < group.grp.npins; i++) {
 696                 void __iomem *padcfg0;
 697                 u32 value;
 698
 699                 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
 700                 if (!padcfg0) {
 701                         dev_warn(vg->dev,
 702                                  "Group %s, pin %i not muxed (no padcfg0)\n",
 703                                  group.grp.name, i);
 704                         continue;
 705                 }
 706
 707                 value = readl(padcfg0);
 708                 value &= ~BYT_PIN_MUX;
 709                 value |= func[i];
 710                 writel(value, padcfg0);
 711         }
 712
 713         raw_spin_unlock_irqrestore(&byt_lock, flags);
 714 }
 715
 716 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
 717                        unsigned int group_selector)
 718 {
 719         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 720         const struct intel_function func = vg->soc->functions[func_selector];
 721         const struct intel_pingroup group = vg->soc->groups[group_selector];
 722
 723         if (group.modes)
 724                 byt_set_group_mixed_mux(vg, group, group.modes);
 725         else if (!strcmp(func.func.name, "gpio"))
 726                 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
 727         else
 728                 byt_set_group_simple_mux(vg, group, group.mode);
 729
 730         return 0;
 731 }
 732
 733 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
 734 {
 735         /* SCORE pin 92-93 */
 736         if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&
 737             offset >= 92 && offset <= 93)
 738                 return BYT_ALTER_GPIO_MUX;
 739
 740         /* SUS pin 11-21 */
 741         if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&
 742             offset >= 11 && offset <= 21)
 743                 return BYT_ALTER_GPIO_MUX;
 744
 745         return BYT_DEFAULT_GPIO_MUX;
 746 }
 747
 748 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
 749 {
 750         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 751         unsigned long flags;
 752         u32 value;
 753
 754         raw_spin_lock_irqsave(&byt_lock, flags);
 755         value = readl(reg);
 756
 757         /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
 758         if (value & BYT_DIRECT_IRQ_EN)
 759                 /* nothing to do */ ;
 760         else
 761                 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
 762
 763         writel(value, reg);
 764         raw_spin_unlock_irqrestore(&byt_lock, flags);
 765 }
 766
 767 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
 768                                    struct pinctrl_gpio_range *range,
 769                                    unsigned int offset)
 770 {
 771         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 772         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 773         u32 value, gpio_mux;
 774         unsigned long flags;
 775
 776         raw_spin_lock_irqsave(&byt_lock, flags);
 777
 778         /*
 779          * In most cases, func pin mux 000 means GPIO function.
 780          * But, some pins may have func pin mux 001 represents
 781          * GPIO function.
 782          *
 783          * Because there are devices out there where some pins were not
 784          * configured correctly we allow changing the mux value from
 785          * request (but print out warning about that).
 786          */
 787         value = readl(reg) & BYT_PIN_MUX;
 788         gpio_mux = byt_get_gpio_mux(vg, offset);
 789         if (gpio_mux != value) {
 790                 value = readl(reg) & ~BYT_PIN_MUX;
 791                 value |= gpio_mux;
 792                 writel(value, reg);
 793
 794                 dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset);
 795         }
 796
 797         raw_spin_unlock_irqrestore(&byt_lock, flags);
 798
 799         pm_runtime_get(vg->dev);
 800
 801         return 0;
 802 }
 803
 804 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
 805                                   struct pinctrl_gpio_range *range,
 806                                   unsigned int offset)
 807 {
 808         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 809
 810         byt_gpio_clear_triggering(vg, offset);
 811         pm_runtime_put(vg->dev);
 812 }
 813
 814 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
 815                                       unsigned int offset)
 816 {
 817         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 818
 819         /*
 820          * Before making any direction modifications, do a check if gpio is set
 821          * for direct IRQ. On Bay Trail, setting GPIO to output does not make
 822          * sense, so let's at least inform the caller before they shoot
 823          * themselves in the foot.
 824          */
 825         if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
 826                 dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
 827 }
 828
 829 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
 830                                   struct pinctrl_gpio_range *range,
 831                                   unsigned int offset,
 832                                   bool input)
 833 {
 834         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 835         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 836         unsigned long flags;
 837         u32 value;
 838
 839         raw_spin_lock_irqsave(&byt_lock, flags);
 840
 841         value = readl(val_reg);
 842         value &= ~BYT_DIR_MASK;
 843         if (input)
 844                 value |= BYT_OUTPUT_EN;
 845         else
 846                 byt_gpio_direct_irq_check(vg, offset);
 847
 848         writel(value, val_reg);
 849
 850         raw_spin_unlock_irqrestore(&byt_lock, flags);
 851
 852         return 0;
 853 }
 854
 855 static const struct pinmux_ops byt_pinmux_ops = {
 856         .get_functions_count    = byt_get_functions_count,
 857         .get_function_name      = byt_get_function_name,
 858         .get_function_groups    = byt_get_function_groups,
 859         .set_mux                = byt_set_mux,
 860         .gpio_request_enable    = byt_gpio_request_enable,
 861         .gpio_disable_free      = byt_gpio_disable_free,
 862         .gpio_set_direction     = byt_gpio_set_direction,
 863 };
 864
 865 static void byt_get_pull_strength(u32 reg, u16 *strength)
 866 {
 867         switch (reg & BYT_PULL_STR_MASK) {
 868         case BYT_PULL_STR_2K:
 869                 *strength = 2000;
 870                 break;
 871         case BYT_PULL_STR_10K:
 872                 *strength = 10000;
 873                 break;
 874         case BYT_PULL_STR_20K:
 875                 *strength = 20000;
 876                 break;
 877         case BYT_PULL_STR_40K:
 878                 *strength = 40000;
 879                 break;
 880         }
 881 }
 882
 883 static int byt_set_pull_strength(u32 *reg, u16 strength)
 884 {
 885         *reg &= ~BYT_PULL_STR_MASK;
 886
 887         switch (strength) {
 888         case 2000:
 889                 *reg |= BYT_PULL_STR_2K;
 890                 break;
 891         case 10000:
 892                 *reg |= BYT_PULL_STR_10K;
 893                 break;
 894         case 20000:
 895                 *reg |= BYT_PULL_STR_20K;
 896                 break;
 897         case 40000:
 898                 *reg |= BYT_PULL_STR_40K;
 899                 break;
 900         default:
 901                 return -EINVAL;
 902         }
 903
 904         return 0;
 905 }
 906
 907 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
 908                               unsigned long *config)
 909 {
 910         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 911         enum pin_config_param param = pinconf_to_config_param(*config);
 912         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 913         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 914         void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
 915         unsigned long flags;
 916         u32 conf, pull, val, debounce;
 917         u16 arg = 0;
 918
 919         raw_spin_lock_irqsave(&byt_lock, flags);
 920         conf = readl(conf_reg);
 921         pull = conf & BYT_PULL_ASSIGN_MASK;
 922         val = readl(val_reg);
 923         raw_spin_unlock_irqrestore(&byt_lock, flags);
 924
 925         switch (param) {
 926         case PIN_CONFIG_BIAS_DISABLE:
 927                 if (pull)
 928                         return -EINVAL;
 929                 break;
 930         case PIN_CONFIG_BIAS_PULL_DOWN:
 931                 /* Pull assignment is only applicable in input mode */
 932                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
 933                         return -EINVAL;
 934
 935                 byt_get_pull_strength(conf, &arg);
 936
 937                 break;
 938         case PIN_CONFIG_BIAS_PULL_UP:
 939                 /* Pull assignment is only applicable in input mode */
 940                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
 941                         return -EINVAL;
 942
 943                 byt_get_pull_strength(conf, &arg);
 944
 945                 break;
 946         case PIN_CONFIG_INPUT_DEBOUNCE:
 947                 if (!(conf & BYT_DEBOUNCE_EN))
 948                         return -EINVAL;
 949
 950                 raw_spin_lock_irqsave(&byt_lock, flags);
 951                 debounce = readl(db_reg);
 952                 raw_spin_unlock_irqrestore(&byt_lock, flags);
 953
 954                 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
 955                 case BYT_DEBOUNCE_PULSE_375US:
 956                         arg = 375;
 957                         break;
 958                 case BYT_DEBOUNCE_PULSE_750US:
 959                         arg = 750;
 960                         break;
 961                 case BYT_DEBOUNCE_PULSE_1500US:
 962                         arg = 1500;
 963                         break;
 964                 case BYT_DEBOUNCE_PULSE_3MS:
 965                         arg = 3000;
 966                         break;
 967                 case BYT_DEBOUNCE_PULSE_6MS:
 968                         arg = 6000;
 969                         break;
 970                 case BYT_DEBOUNCE_PULSE_12MS:
 971                         arg = 12000;
 972                         break;
 973                 case BYT_DEBOUNCE_PULSE_24MS:
 974                         arg = 24000;
 975                         break;
 976                 default:
 977                         return -EINVAL;
 978                 }
 979
 980                 break;
 981         default:
 982                 return -ENOTSUPP;
 983         }
 984
 985         *config = pinconf_to_config_packed(param, arg);
 986
 987         return 0;
 988 }
 989
 990 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
 991                               unsigned int offset,
 992                               unsigned long *configs,
 993                               unsigned int num_configs)
 994 {
 995         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 996         unsigned int param, arg;
 997         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 998         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 999         void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1000         unsigned long flags;
1001         u32 conf, val, debounce;
1002         int i, ret = 0;
1003
1004         raw_spin_lock_irqsave(&byt_lock, flags);
1005
1006         conf = readl(conf_reg);
1007         val = readl(val_reg);
1008
1009         for (i = 0; i < num_configs; i++) {
1010                 param = pinconf_to_config_param(configs[i]);
1011                 arg = pinconf_to_config_argument(configs[i]);
1012
1013                 switch (param) {
1014                 case PIN_CONFIG_BIAS_DISABLE:
1015                         conf &= ~BYT_PULL_ASSIGN_MASK;
1016                         break;
1017                 case PIN_CONFIG_BIAS_PULL_DOWN:
1018                         /* Set default strength value in case none is given */
1019                         if (arg == 1)
1020                                 arg = 2000;
1021
1022                         /*
1023                          * Pull assignment is only applicable in input mode. If
1024                          * chip is not in input mode, set it and warn about it.
1025                          */
1026                         if (val & BYT_INPUT_EN) {
1027                                 val &= ~BYT_INPUT_EN;
1028                                 writel(val, val_reg);
1029                                 dev_warn(vg->dev,
1030                                          "pin %u forcibly set to input mode\n",
1031                                          offset);
1032                         }
1033
1034                         conf &= ~BYT_PULL_ASSIGN_MASK;
1035                         conf |= BYT_PULL_ASSIGN_DOWN;
1036                         ret = byt_set_pull_strength(&conf, arg);
1037
1038                         break;
1039                 case PIN_CONFIG_BIAS_PULL_UP:
1040                         /* Set default strength value in case none is given */
1041                         if (arg == 1)
1042                                 arg = 2000;
1043
1044                         /*
1045                          * Pull assignment is only applicable in input mode. If
1046                          * chip is not in input mode, set it and warn about it.
1047                          */
1048                         if (val & BYT_INPUT_EN) {
1049                                 val &= ~BYT_INPUT_EN;
1050                                 writel(val, val_reg);
1051                                 dev_warn(vg->dev,
1052                                          "pin %u forcibly set to input mode\n",
1053                                          offset);
1054                         }
1055
1056                         conf &= ~BYT_PULL_ASSIGN_MASK;
1057                         conf |= BYT_PULL_ASSIGN_UP;
1058                         ret = byt_set_pull_strength(&conf, arg);
1059
1060                         break;
1061                 case PIN_CONFIG_INPUT_DEBOUNCE:
1062                         debounce = readl(db_reg);
1063
1064                         if (arg)
1065                                 conf |= BYT_DEBOUNCE_EN;
1066                         else
1067                                 conf &= ~BYT_DEBOUNCE_EN;
1068
1069                         switch (arg) {
1070                         case 375:
1071                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1072                                 debounce |= BYT_DEBOUNCE_PULSE_375US;
1073                                 break;
1074                         case 750:
1075                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1076                                 debounce |= BYT_DEBOUNCE_PULSE_750US;
1077                                 break;
1078                         case 1500:
1079                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1080                                 debounce |= BYT_DEBOUNCE_PULSE_1500US;
1081                                 break;
1082                         case 3000:
1083                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1084                                 debounce |= BYT_DEBOUNCE_PULSE_3MS;
1085                                 break;
1086                         case 6000:
1087                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1088                                 debounce |= BYT_DEBOUNCE_PULSE_6MS;
1089                                 break;
1090                         case 12000:
1091                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1092                                 debounce |= BYT_DEBOUNCE_PULSE_12MS;
1093                                 break;
1094                         case 24000:
1095                                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1096                                 debounce |= BYT_DEBOUNCE_PULSE_24MS;
1097                                 break;
1098                         default:
1099                                 if (arg)
1100                                         ret = -EINVAL;
1101                                 break;
1102                         }
1103
1104                         if (!ret)
1105                                 writel(debounce, db_reg);
1106                         break;
1107                 default:
1108                         ret = -ENOTSUPP;
1109                 }
1110
1111                 if (ret)
1112                         break;
1113         }
1114
1115         if (!ret)
1116                 writel(conf, conf_reg);
1117
1118         raw_spin_unlock_irqrestore(&byt_lock, flags);
1119
1120         return ret;
1121 }
1122
1123 static const struct pinconf_ops byt_pinconf_ops = {
1124         .is_generic     = true,
1125         .pin_config_get = byt_pin_config_get,
1126         .pin_config_set = byt_pin_config_set,
1127 };
1128
1129 static const struct pinctrl_desc byt_pinctrl_desc = {
1130         .pctlops        = &byt_pinctrl_ops,
1131         .pmxops         = &byt_pinmux_ops,
1132         .confops        = &byt_pinconf_ops,
1133         .owner          = THIS_MODULE,
1134 };
1135
1136 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1137 {
1138         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1139         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1140         unsigned long flags;
1141         u32 val;
1142
1143         raw_spin_lock_irqsave(&byt_lock, flags);
1144         val = readl(reg);
1145         raw_spin_unlock_irqrestore(&byt_lock, flags);
1146
1147         return !!(val & BYT_LEVEL);
1148 }
1149
1150 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1151 {
1152         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1153         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1154         unsigned long flags;
1155         u32 old_val;
1156
1157         if (!reg)
1158                 return;
1159
1160         raw_spin_lock_irqsave(&byt_lock, flags);
1161         old_val = readl(reg);
1162         if (value)
1163                 writel(old_val | BYT_LEVEL, reg);
1164         else
1165                 writel(old_val & ~BYT_LEVEL, reg);
1166         raw_spin_unlock_irqrestore(&byt_lock, flags);
1167 }
1168
1169 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1170 {
1171         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1172         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1173         unsigned long flags;
1174         u32 value;
1175
1176         if (!reg)
1177                 return -EINVAL;
1178
1179         raw_spin_lock_irqsave(&byt_lock, flags);
1180         value = readl(reg);
1181         raw_spin_unlock_irqrestore(&byt_lock, flags);
1182
1183         if (!(value & BYT_OUTPUT_EN))
1184                 return GPIO_LINE_DIRECTION_OUT;
1185         if (!(value & BYT_INPUT_EN))
1186                 return GPIO_LINE_DIRECTION_IN;
1187
1188         return -EINVAL;
1189 }
1190
1191 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1192 {
1193         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1194         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1195         unsigned long flags;
1196         u32 reg;
1197
1198         raw_spin_lock_irqsave(&byt_lock, flags);
1199
1200         reg = readl(val_reg);
1201         reg &= ~BYT_DIR_MASK;
1202         reg |= BYT_OUTPUT_EN;
1203         writel(reg, val_reg);
1204
1205         raw_spin_unlock_irqrestore(&byt_lock, flags);
1206         return 0;
1207 }
1208
1209 /*
1210  * Note despite the temptation this MUST NOT be converted into a call to
1211  * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this
1212  * MUST be done as a single BYT_VAL_REG register write.
1213  * See the commit message of the commit adding this comment for details.
1214  */
1215 static int byt_gpio_direction_output(struct gpio_chip *chip,
1216                                      unsigned int offset, int value)
1217 {
1218         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1219         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1220         unsigned long flags;
1221         u32 reg;
1222
1223         raw_spin_lock_irqsave(&byt_lock, flags);
1224
1225         byt_gpio_direct_irq_check(vg, offset);
1226
1227         reg = readl(val_reg);
1228         reg &= ~BYT_DIR_MASK;
1229         if (value)
1230                 reg |= BYT_LEVEL;
1231         else
1232                 reg &= ~BYT_LEVEL;
1233
1234         writel(reg, val_reg);
1235
1236         raw_spin_unlock_irqrestore(&byt_lock, flags);
1237         return 0;
1238 }
1239
1240 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1241 {
1242         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1243         int i;
1244         u32 conf0, val;
1245
1246         for (i = 0; i < vg->soc->npins; i++) {
1247                 const struct intel_community *comm;
1248                 const char *pull_str = NULL;
1249                 const char *pull = NULL;
1250                 void __iomem *reg;
1251                 unsigned long flags;
1252                 const char *label;
1253                 unsigned int pin;
1254
1255                 raw_spin_lock_irqsave(&byt_lock, flags);
1256                 pin = vg->soc->pins[i].number;
1257                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1258                 if (!reg) {
1259                         seq_printf(s,
1260                                    "Could not retrieve pin %i conf0 reg\n",
1261                                    pin);
1262                         raw_spin_unlock_irqrestore(&byt_lock, flags);
1263                         continue;
1264                 }
1265                 conf0 = readl(reg);
1266
1267                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1268                 if (!reg) {
1269                         seq_printf(s,
1270                                    "Could not retrieve pin %i val reg\n", pin);
1271                         raw_spin_unlock_irqrestore(&byt_lock, flags);
1272                         continue;
1273                 }
1274                 val = readl(reg);
1275                 raw_spin_unlock_irqrestore(&byt_lock, flags);
1276
1277                 comm = byt_get_community(vg, pin);
1278                 if (!comm) {
1279                         seq_printf(s,
1280                                    "Could not get community for pin %i\n", pin);
1281                         continue;
1282                 }
1283                 label = gpiochip_is_requested(chip, i);
1284                 if (!label)
1285                         label = "Unrequested";
1286
1287                 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1288                 case BYT_PULL_ASSIGN_UP:
1289                         pull = "up";
1290                         break;
1291                 case BYT_PULL_ASSIGN_DOWN:
1292                         pull = "down";
1293                         break;
1294                 }
1295
1296                 switch (conf0 & BYT_PULL_STR_MASK) {
1297                 case BYT_PULL_STR_2K:
1298                         pull_str = "2k";
1299                         break;
1300                 case BYT_PULL_STR_10K:
1301                         pull_str = "10k";
1302                         break;
1303                 case BYT_PULL_STR_20K:
1304                         pull_str = "20k";
1305                         break;
1306                 case BYT_PULL_STR_40K:
1307                         pull_str = "40k";
1308                         break;
1309                 }
1310
1311                 seq_printf(s,
1312                            " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1313                            pin,
1314                            label,
1315                            val & BYT_INPUT_EN ? "  " : "in",
1316                            val & BYT_OUTPUT_EN ? "   " : "out",
1317                            val & BYT_LEVEL ? "hi" : "lo",
1318                            comm->pad_map[i], comm->pad_map[i] * 16,
1319                            conf0 & 0x7,
1320                            conf0 & BYT_TRIG_NEG ? " fall" : "     ",
1321                            conf0 & BYT_TRIG_POS ? " rise" : "     ",
1322                            conf0 & BYT_TRIG_LVL ? " level" : "      ");
1323
1324                 if (pull && pull_str)
1325                         seq_printf(s, " %-4s %-3s", pull, pull_str);
1326                 else
1327                         seq_puts(s, "          ");
1328
1329                 if (conf0 & BYT_IODEN)
1330                         seq_puts(s, " open-drain");
1331
1332                 seq_puts(s, "\n");
1333         }
1334 }
1335
1336 static const struct gpio_chip byt_gpio_chip = {
1337         .owner                  = THIS_MODULE,
1338         .request                = gpiochip_generic_request,
1339         .free                   = gpiochip_generic_free,
1340         .get_direction          = byt_gpio_get_direction,
1341         .direction_input        = byt_gpio_direction_input,
1342         .direction_output       = byt_gpio_direction_output,
1343         .get                    = byt_gpio_get,
1344         .set                    = byt_gpio_set,
1345         .set_config             = gpiochip_generic_config,
1346         .dbg_show               = byt_gpio_dbg_show,
1347 };
1348
1349 static void byt_irq_ack(struct irq_data *d)
1350 {
1351         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1352         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1353         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1354         void __iomem *reg;
1355
1356         reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG);
1357         if (!reg)
1358                 return;
1359
1360         raw_spin_lock(&byt_lock);
1361         writel(BIT(hwirq % 32), reg);
1362         raw_spin_unlock(&byt_lock);
1363 }
1364
1365 static void byt_irq_mask(struct irq_data *d)
1366 {
1367         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1368         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1369         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1370
1371         byt_gpio_clear_triggering(vg, hwirq);
1372         gpiochip_disable_irq(gc, hwirq);
1373 }
1374
1375 static void byt_irq_unmask(struct irq_data *d)
1376 {
1377         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1378         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1379         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1380         unsigned long flags;
1381         void __iomem *reg;
1382         u32 value;
1383
1384         gpiochip_enable_irq(gc, hwirq);
1385
1386         reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1387         if (!reg)
1388                 return;
1389
1390         raw_spin_lock_irqsave(&byt_lock, flags);
1391         value = readl(reg);
1392
1393         switch (irqd_get_trigger_type(d)) {
1394         case IRQ_TYPE_LEVEL_HIGH:
1395                 value |= BYT_TRIG_LVL;
1396                 fallthrough;
1397         case IRQ_TYPE_EDGE_RISING:
1398                 value |= BYT_TRIG_POS;
1399                 break;
1400         case IRQ_TYPE_LEVEL_LOW:
1401                 value |= BYT_TRIG_LVL;
1402                 fallthrough;
1403         case IRQ_TYPE_EDGE_FALLING:
1404                 value |= BYT_TRIG_NEG;
1405                 break;
1406         case IRQ_TYPE_EDGE_BOTH:
1407                 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1408                 break;
1409         }
1410
1411         writel(value, reg);
1412
1413         raw_spin_unlock_irqrestore(&byt_lock, flags);
1414 }
1415
1416 static int byt_irq_type(struct irq_data *d, unsigned int type)
1417 {
1418         struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1419         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1420         u32 value;
1421         unsigned long flags;
1422         void __iomem *reg;
1423
1424         reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1425         if (!reg)
1426                 return -EINVAL;
1427
1428         raw_spin_lock_irqsave(&byt_lock, flags);
1429         value = readl(reg);
1430
1431         WARN(value & BYT_DIRECT_IRQ_EN,
1432              "Bad pad config for io mode, force direct_irq_en bit clearing");
1433
1434         /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1435          * are used to indicate high and low level triggering
1436          */
1437         value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1438                    BYT_TRIG_LVL);
1439         /* Enable glitch filtering */
1440         value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1441                  BYT_GLITCH_F_FAST_CLK;
1442
1443         writel(value, reg);
1444
1445         if (type & IRQ_TYPE_EDGE_BOTH)
1446                 irq_set_handler_locked(d, handle_edge_irq);
1447         else if (type & IRQ_TYPE_LEVEL_MASK)
1448                 irq_set_handler_locked(d, handle_level_irq);
1449
1450         raw_spin_unlock_irqrestore(&byt_lock, flags);
1451
1452         return 0;
1453 }
1454
1455 static const struct irq_chip byt_gpio_irq_chip = {
1456         .name           = "BYT-GPIO",
1457         .irq_ack        = byt_irq_ack,
1458         .irq_mask       = byt_irq_mask,
1459         .irq_unmask     = byt_irq_unmask,
1460         .irq_set_type   = byt_irq_type,
1461         .flags          = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
1462         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1463 };
1464
1465 static void byt_gpio_irq_handler(struct irq_desc *desc)
1466 {
1467         struct irq_data *data = irq_desc_get_irq_data(desc);
1468         struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
1469         struct irq_chip *chip = irq_data_get_irq_chip(data);
1470         u32 base, pin;
1471         void __iomem *reg;
1472         unsigned long pending;
1473
1474         /* check from GPIO controller which pin triggered the interrupt */
1475         for (base = 0; base < vg->chip.ngpio; base += 32) {
1476                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1477
1478                 if (!reg) {
1479                         dev_warn(vg->dev,
1480                                  "Pin %i: could not retrieve interrupt status register\n",
1481                                  base);
1482                         continue;
1483                 }
1484
1485                 raw_spin_lock(&byt_lock);
1486                 pending = readl(reg);
1487                 raw_spin_unlock(&byt_lock);
1488                 for_each_set_bit(pin, &pending, 32)
1489                         generic_handle_domain_irq(vg->chip.irq.domain, base + pin);
1490         }
1491         chip->irq_eoi(data);
1492 }
1493
1494 static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0)
1495 {
1496         int direct_irq, ioapic_direct_irq_base;
1497         u8 *match, direct_irq_mux[16];
1498         u32 trig;
1499
1500         memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG,
1501                       sizeof(direct_irq_mux));
1502         match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
1503         if (!match) {
1504                 dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin);
1505                 return false;
1506         }
1507
1508         direct_irq = match - direct_irq_mux;
1509         /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */
1510         ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67;
1511         dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin,
1512                 direct_irq, direct_irq + ioapic_direct_irq_base);
1513
1514         /*
1515          * Testing has shown that the way direct IRQs work is that the combination of the
1516          * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ
1517          * trigger block, which normally sets the status flag in the IRQ status reg at
1518          * 0x800, to one of the IO-APIC pins according to the mux registers.
1519          *
1520          * This means that:
1521          * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block
1522          * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly
1523          *    passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set,
1524          *    selecting edge mode operation then on the first edge the IO-APIC pin goes
1525          *    high, but since no write-to-clear write will be done to the IRQ status reg
1526          *    at 0x800, the detected edge condition will never get cleared.
1527          */
1528         trig = conf0 & BYT_TRIG_MASK;
1529         if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
1530             trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
1531                 dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n",
1532                          pin, conf0);
1533                 return false;
1534         }
1535
1536         return true;
1537 }
1538
1539 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
1540                                     unsigned long *valid_mask,
1541                                     unsigned int ngpios)
1542 {
1543         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1544         void __iomem *reg;
1545         u32 value;
1546         int i;
1547
1548         /*
1549          * Clear interrupt triggers for all pins that are GPIOs and
1550          * do not use direct IRQ mode. This will prevent spurious
1551          * interrupts from misconfigured pins.
1552          */
1553         for (i = 0; i < vg->soc->npins; i++) {
1554                 unsigned int pin = vg->soc->pins[i].number;
1555
1556                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1557                 if (!reg) {
1558                         dev_warn(vg->dev,
1559                                  "Pin %i: could not retrieve conf0 register\n",
1560                                  i);
1561                         continue;
1562                 }
1563
1564                 value = readl(reg);
1565                 if (value & BYT_DIRECT_IRQ_EN) {
1566                         if (byt_direct_irq_sanity_check(vg, i, value)) {
1567                                 clear_bit(i, valid_mask);
1568                         } else {
1569                                 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS |
1570                                            BYT_TRIG_NEG | BYT_TRIG_LVL);
1571                                 writel(value, reg);
1572                         }
1573                 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1574                         byt_gpio_clear_triggering(vg, i);
1575                         dev_dbg(vg->dev, "disabling GPIO %d\n", i);
1576                 }
1577         }
1578 }
1579
1580 static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
1581 {
1582         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1583         void __iomem *reg;
1584         u32 base, value;
1585
1586         /* clear interrupt status trigger registers */
1587         for (base = 0; base < vg->soc->npins; base += 32) {
1588                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1589
1590                 if (!reg) {
1591                         dev_warn(vg->dev,
1592                                  "Pin %i: could not retrieve irq status reg\n",
1593                                  base);
1594                         continue;
1595                 }
1596
1597                 writel(0xffffffff, reg);
1598                 /* make sure trigger bits are cleared, if not then a pin
1599                    might be misconfigured in bios */
1600                 value = readl(reg);
1601                 if (value)
1602                         dev_err(vg->dev,
1603                                 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
1604                                 base / 32, value);
1605         }
1606
1607         return 0;
1608 }
1609
1610 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
1611 {
1612         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1613         struct device *dev = vg->dev;
1614         int ret;
1615
1616         ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
1617         if (ret)
1618                 dev_err(dev, "failed to add GPIO pin range\n");
1619
1620         return ret;
1621 }
1622
1623 static int byt_gpio_probe(struct intel_pinctrl *vg)
1624 {
1625         struct platform_device *pdev = to_platform_device(vg->dev);
1626         struct gpio_chip *gc;
1627         int irq, ret;
1628
1629         /* Set up gpio chip */
1630         vg->chip        = byt_gpio_chip;
1631         gc              = &vg->chip;
1632         gc->label       = dev_name(vg->dev);
1633         gc->base        = -1;
1634         gc->can_sleep   = false;
1635         gc->add_pin_ranges = byt_gpio_add_pin_ranges;
1636         gc->parent      = vg->dev;
1637         gc->ngpio       = vg->soc->npins;
1638
1639 #ifdef CONFIG_PM_SLEEP
1640         vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),
1641                                         GFP_KERNEL);
1642         if (!vg->context.pads)
1643                 return -ENOMEM;
1644 #endif
1645
1646         /* set up interrupts  */
1647         irq = platform_get_irq_optional(pdev, 0);
1648         if (irq > 0) {
1649                 struct gpio_irq_chip *girq;
1650
1651                 girq = &gc->irq;
1652                 gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip);
1653                 girq->init_hw = byt_gpio_irq_init_hw;
1654                 girq->init_valid_mask = byt_init_irq_valid_mask;
1655                 girq->parent_handler = byt_gpio_irq_handler;
1656                 girq->num_parents = 1;
1657                 girq->parents = devm_kcalloc(vg->dev, girq->num_parents,
1658                                              sizeof(*girq->parents), GFP_KERNEL);
1659                 if (!girq->parents)
1660                         return -ENOMEM;
1661                 girq->parents[0] = irq;
1662                 girq->default_type = IRQ_TYPE_NONE;
1663                 girq->handler = handle_bad_irq;
1664         }
1665
1666         ret = devm_gpiochip_add_data(vg->dev, gc, vg);
1667         if (ret) {
1668                 dev_err(vg->dev, "failed adding byt-gpio chip\n");
1669                 return ret;
1670         }
1671
1672         return ret;
1673 }
1674
1675 static int byt_set_soc_data(struct intel_pinctrl *vg,
1676                             const struct intel_pinctrl_soc_data *soc)
1677 {
1678         struct platform_device *pdev = to_platform_device(vg->dev);
1679         int i;
1680
1681         vg->soc = soc;
1682
1683         vg->ncommunities = vg->soc->ncommunities;
1684         vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,
1685                                        sizeof(*vg->communities), GFP_KERNEL);
1686         if (!vg->communities)
1687                 return -ENOMEM;
1688
1689         for (i = 0; i < vg->soc->ncommunities; i++) {
1690                 struct intel_community *comm = vg->communities + i;
1691
1692                 *comm = vg->soc->communities[i];
1693
1694                 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0);
1695                 if (IS_ERR(comm->pad_regs))
1696                         return PTR_ERR(comm->pad_regs);
1697         }
1698
1699         return 0;
1700 }
1701
1702 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1703         { "INT33B2", (kernel_ulong_t)byt_soc_data },
1704         { "INT33FC", (kernel_ulong_t)byt_soc_data },
1705         { }
1706 };
1707
1708 static int byt_pinctrl_probe(struct platform_device *pdev)
1709 {
1710         const struct intel_pinctrl_soc_data *soc_data;
1711         struct device *dev = &pdev->dev;
1712         struct intel_pinctrl *vg;
1713         int ret;
1714
1715         soc_data = intel_pinctrl_get_soc_data(pdev);
1716         if (IS_ERR(soc_data))
1717                 return PTR_ERR(soc_data);
1718
1719         vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
1720         if (!vg)
1721                 return -ENOMEM;
1722
1723         vg->dev = dev;
1724         ret = byt_set_soc_data(vg, soc_data);
1725         if (ret) {
1726                 dev_err(dev, "failed to set soc data\n");
1727                 return ret;
1728         }
1729
1730         vg->pctldesc            = byt_pinctrl_desc;
1731         vg->pctldesc.name       = dev_name(dev);
1732         vg->pctldesc.pins       = vg->soc->pins;
1733         vg->pctldesc.npins      = vg->soc->npins;
1734
1735         vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
1736         if (IS_ERR(vg->pctldev)) {
1737                 dev_err(dev, "failed to register pinctrl driver\n");
1738                 return PTR_ERR(vg->pctldev);
1739         }
1740
1741         ret = byt_gpio_probe(vg);
1742         if (ret)
1743                 return ret;
1744
1745         platform_set_drvdata(pdev, vg);
1746         pm_runtime_enable(dev);
1747
1748         return 0;
1749 }
1750
1751 #ifdef CONFIG_PM_SLEEP
1752 static int byt_gpio_suspend(struct device *dev)
1753 {
1754         struct intel_pinctrl *vg = dev_get_drvdata(dev);
1755         unsigned long flags;
1756         int i;
1757
1758         raw_spin_lock_irqsave(&byt_lock, flags);
1759
1760         for (i = 0; i < vg->soc->npins; i++) {
1761                 void __iomem *reg;
1762                 u32 value;
1763                 unsigned int pin = vg->soc->pins[i].number;
1764
1765                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1766                 if (!reg) {
1767                         dev_warn(vg->dev,
1768                                  "Pin %i: could not retrieve conf0 register\n",
1769                                  i);
1770                         continue;
1771                 }
1772                 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1773                 vg->context.pads[i].conf0 = value;
1774
1775                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1776                 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1777                 vg->context.pads[i].val = value;
1778         }
1779
1780         raw_spin_unlock_irqrestore(&byt_lock, flags);
1781         return 0;
1782 }
1783
1784 static int byt_gpio_resume(struct device *dev)
1785 {
1786         struct intel_pinctrl *vg = dev_get_drvdata(dev);
1787         unsigned long flags;
1788         int i;
1789
1790         raw_spin_lock_irqsave(&byt_lock, flags);
1791
1792         for (i = 0; i < vg->soc->npins; i++) {
1793                 void __iomem *reg;
1794                 u32 value;
1795                 unsigned int pin = vg->soc->pins[i].number;
1796
1797                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1798                 if (!reg) {
1799                         dev_warn(vg->dev,
1800                                  "Pin %i: could not retrieve conf0 register\n",
1801                                  i);
1802                         continue;
1803                 }
1804                 value = readl(reg);
1805                 if ((value & BYT_CONF0_RESTORE_MASK) !=
1806                      vg->context.pads[i].conf0) {
1807                         value &= ~BYT_CONF0_RESTORE_MASK;
1808                         value |= vg->context.pads[i].conf0;
1809                         writel(value, reg);
1810                         dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1811                 }
1812
1813                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1814                 value = readl(reg);
1815                 if ((value & BYT_VAL_RESTORE_MASK) !=
1816                      vg->context.pads[i].val) {
1817                         u32 v;
1818
1819                         v = value & ~BYT_VAL_RESTORE_MASK;
1820                         v |= vg->context.pads[i].val;
1821                         if (v != value) {
1822                                 writel(v, reg);
1823                                 dev_dbg(dev, "restored pin %d val %#08x\n",
1824                                         i, v);
1825                         }
1826                 }
1827         }
1828
1829         raw_spin_unlock_irqrestore(&byt_lock, flags);
1830         return 0;
1831 }
1832 #endif
1833
1834 #ifdef CONFIG_PM
1835 static int byt_gpio_runtime_suspend(struct device *dev)
1836 {
1837         return 0;
1838 }
1839
1840 static int byt_gpio_runtime_resume(struct device *dev)
1841 {
1842         return 0;
1843 }
1844 #endif
1845
1846 static const struct dev_pm_ops byt_gpio_pm_ops = {
1847         SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1848         SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1849                            NULL)
1850 };
1851
1852 static struct platform_driver byt_gpio_driver = {
1853         .probe          = byt_pinctrl_probe,
1854         .driver         = {
1855                 .name                   = "byt_gpio",
1856                 .pm                     = &byt_gpio_pm_ops,
1857                 .acpi_match_table       = byt_gpio_acpi_match,
1858                 .suppress_bind_attrs    = true,
1859         },
1860 };
1861
1862 static int __init byt_gpio_init(void)
1863 {
1864         return platform_driver_register(&byt_gpio_driver);
1865 }
1866 subsys_initcall(byt_gpio_init);