drivers/pinctrl/intel/pinctrl-baytrail.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pinctrl GPIO driver for Intel Baytrail
   4  *
   5  * Copyright (c) 2012-2013, Intel Corporation
   6  * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/array_size.h>
  11 #include <linux/bitops.h>
  12 #include <linux/cleanup.h>
  13 #include <linux/gpio/driver.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm.h>
  21 #include <linux/property.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/string_helpers.h>
  24
  25 #include <linux/pinctrl/pinctrl.h>
  26 #include <linux/pinctrl/pinmux.h>
  27 #include <linux/pinctrl/pinconf.h>
  28 #include <linux/pinctrl/pinconf-generic.h>
  29
  30 #include "pinctrl-intel.h"
  31
  32 /* memory mapped register offsets */
  33 #define BYT_CONF0_REG           0x000
  34 #define BYT_CONF1_REG           0x004
  35 #define BYT_VAL_REG             0x008
  36 #define BYT_DFT_REG             0x00c
  37 #define BYT_INT_STAT_REG        0x800
  38 #define BYT_DIRECT_IRQ_REG      0x980
  39 #define BYT_DEBOUNCE_REG        0x9d0
  40
  41 /* BYT_CONF0_REG register bits */
  42 #define BYT_IODEN               BIT(31)
  43 #define BYT_DIRECT_IRQ_EN       BIT(27)
  44 #define BYT_TRIG_MASK           GENMASK(26, 24)
  45 #define BYT_TRIG_NEG            BIT(26)
  46 #define BYT_TRIG_POS            BIT(25)
  47 #define BYT_TRIG_LVL            BIT(24)
  48 #define BYT_DEBOUNCE_EN         BIT(20)
  49 #define BYT_GLITCH_FILTER_EN    BIT(19)
  50 #define BYT_GLITCH_F_SLOW_CLK   BIT(17)
  51 #define BYT_GLITCH_F_FAST_CLK   BIT(16)
  52 #define BYT_PULL_STR_SHIFT      9
  53 #define BYT_PULL_STR_MASK       GENMASK(10, 9)
  54 #define BYT_PULL_STR_2K         (0 << BYT_PULL_STR_SHIFT)
  55 #define BYT_PULL_STR_10K        (1 << BYT_PULL_STR_SHIFT)
  56 #define BYT_PULL_STR_20K        (2 << BYT_PULL_STR_SHIFT)
  57 #define BYT_PULL_STR_40K        (3 << BYT_PULL_STR_SHIFT)
  58 #define BYT_PULL_ASSIGN_MASK    GENMASK(8, 7)
  59 #define BYT_PULL_ASSIGN_DOWN    BIT(8)
  60 #define BYT_PULL_ASSIGN_UP      BIT(7)
  61 #define BYT_PIN_MUX             GENMASK(2, 0)
  62
  63 /* BYT_VAL_REG register bits */
  64 #define BYT_DIR_MASK            GENMASK(2, 1)
  65 #define BYT_INPUT_EN            BIT(2)  /* 0: input enabled (active low)*/
  66 #define BYT_OUTPUT_EN           BIT(1)  /* 0: output enabled (active low)*/
  67 #define BYT_LEVEL               BIT(0)
  68
  69 #define BYT_CONF0_RESTORE_MASK  (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
  70 #define BYT_VAL_RESTORE_MASK    (BYT_DIR_MASK | BYT_LEVEL)
  71
  72 /* BYT_DEBOUNCE_REG bits */
  73 #define BYT_DEBOUNCE_PULSE_MASK         GENMASK(2, 0)
  74 #define BYT_DEBOUNCE_PULSE_375US        1
  75 #define BYT_DEBOUNCE_PULSE_750US        2
  76 #define BYT_DEBOUNCE_PULSE_1500US       3
  77 #define BYT_DEBOUNCE_PULSE_3MS          4
  78 #define BYT_DEBOUNCE_PULSE_6MS          5
  79 #define BYT_DEBOUNCE_PULSE_12MS         6
  80 #define BYT_DEBOUNCE_PULSE_24MS         7
  81
  82 #define BYT_NGPIO_SCORE         102
  83 #define BYT_NGPIO_NCORE         28
  84 #define BYT_NGPIO_SUS           44
  85
  86 #define BYT_SCORE_ACPI_UID      "1"
  87 #define BYT_NCORE_ACPI_UID      "2"
  88 #define BYT_SUS_ACPI_UID        "3"
  89
  90 /*
  91  * This is the function value most pins have for GPIO muxing. If the value
  92  * differs from the default one, it must be explicitly mentioned. Otherwise, the
  93  * pin control implementation will set the muxing value to default GPIO if it
  94  * does not find a match for the requested function.
  95  */
  96 #define BYT_DEFAULT_GPIO_MUX    0
  97 #define BYT_ALTER_GPIO_MUX      1
  98
  99 struct intel_pad_context {
 100         u32 conf0;
 101         u32 val;
 102 };
 103
 104 #define COMMUNITY(p, n, map)            \
 105         {                               \
 106                 .pin_base       = (p),  \
 107                 .npins          = (n),  \
 108                 .pad_map        = (map),\
 109         }
 110
 111 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
 112 static const struct pinctrl_pin_desc byt_score_pins[] = {
 113         PINCTRL_PIN(0, "SATA_GP0"),
 114         PINCTRL_PIN(1, "SATA_GP1"),
 115         PINCTRL_PIN(2, "SATA_LED#"),
 116         PINCTRL_PIN(3, "PCIE_CLKREQ0"),
 117         PINCTRL_PIN(4, "PCIE_CLKREQ1"),
 118         PINCTRL_PIN(5, "PCIE_CLKREQ2"),
 119         PINCTRL_PIN(6, "PCIE_CLKREQ3"),
 120         PINCTRL_PIN(7, "SD3_WP"),
 121         PINCTRL_PIN(8, "HDA_RST"),
 122         PINCTRL_PIN(9, "HDA_SYNC"),
 123         PINCTRL_PIN(10, "HDA_CLK"),
 124         PINCTRL_PIN(11, "HDA_SDO"),
 125         PINCTRL_PIN(12, "HDA_SDI0"),
 126         PINCTRL_PIN(13, "HDA_SDI1"),
 127         PINCTRL_PIN(14, "GPIO_S0_SC14"),
 128         PINCTRL_PIN(15, "GPIO_S0_SC15"),
 129         PINCTRL_PIN(16, "MMC1_CLK"),
 130         PINCTRL_PIN(17, "MMC1_D0"),
 131         PINCTRL_PIN(18, "MMC1_D1"),
 132         PINCTRL_PIN(19, "MMC1_D2"),
 133         PINCTRL_PIN(20, "MMC1_D3"),
 134         PINCTRL_PIN(21, "MMC1_D4"),
 135         PINCTRL_PIN(22, "MMC1_D5"),
 136         PINCTRL_PIN(23, "MMC1_D6"),
 137         PINCTRL_PIN(24, "MMC1_D7"),
 138         PINCTRL_PIN(25, "MMC1_CMD"),
 139         PINCTRL_PIN(26, "MMC1_RST"),
 140         PINCTRL_PIN(27, "SD2_CLK"),
 141         PINCTRL_PIN(28, "SD2_D0"),
 142         PINCTRL_PIN(29, "SD2_D1"),
 143         PINCTRL_PIN(30, "SD2_D2"),
 144         PINCTRL_PIN(31, "SD2_D3_CD"),
 145         PINCTRL_PIN(32, "SD2_CMD"),
 146         PINCTRL_PIN(33, "SD3_CLK"),
 147         PINCTRL_PIN(34, "SD3_D0"),
 148         PINCTRL_PIN(35, "SD3_D1"),
 149         PINCTRL_PIN(36, "SD3_D2"),
 150         PINCTRL_PIN(37, "SD3_D3"),
 151         PINCTRL_PIN(38, "SD3_CD"),
 152         PINCTRL_PIN(39, "SD3_CMD"),
 153         PINCTRL_PIN(40, "SD3_1P8EN"),
 154         PINCTRL_PIN(41, "SD3_PWREN#"),
 155         PINCTRL_PIN(42, "ILB_LPC_AD0"),
 156         PINCTRL_PIN(43, "ILB_LPC_AD1"),
 157         PINCTRL_PIN(44, "ILB_LPC_AD2"),
 158         PINCTRL_PIN(45, "ILB_LPC_AD3"),
 159         PINCTRL_PIN(46, "ILB_LPC_FRAME"),
 160         PINCTRL_PIN(47, "ILB_LPC_CLK0"),
 161         PINCTRL_PIN(48, "ILB_LPC_CLK1"),
 162         PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
 163         PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
 164         PINCTRL_PIN(51, "PCU_SMB_DATA"),
 165         PINCTRL_PIN(52, "PCU_SMB_CLK"),
 166         PINCTRL_PIN(53, "PCU_SMB_ALERT"),
 167         PINCTRL_PIN(54, "ILB_8254_SPKR"),
 168         PINCTRL_PIN(55, "GPIO_S0_SC55"),
 169         PINCTRL_PIN(56, "GPIO_S0_SC56"),
 170         PINCTRL_PIN(57, "GPIO_S0_SC57"),
 171         PINCTRL_PIN(58, "GPIO_S0_SC58"),
 172         PINCTRL_PIN(59, "GPIO_S0_SC59"),
 173         PINCTRL_PIN(60, "GPIO_S0_SC60"),
 174         PINCTRL_PIN(61, "GPIO_S0_SC61"),
 175         PINCTRL_PIN(62, "LPE_I2S2_CLK"),
 176         PINCTRL_PIN(63, "LPE_I2S2_FRM"),
 177         PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
 178         PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
 179         PINCTRL_PIN(66, "SIO_SPI_CS"),
 180         PINCTRL_PIN(67, "SIO_SPI_MISO"),
 181         PINCTRL_PIN(68, "SIO_SPI_MOSI"),
 182         PINCTRL_PIN(69, "SIO_SPI_CLK"),
 183         PINCTRL_PIN(70, "SIO_UART1_RXD"),
 184         PINCTRL_PIN(71, "SIO_UART1_TXD"),
 185         PINCTRL_PIN(72, "SIO_UART1_RTS"),
 186         PINCTRL_PIN(73, "SIO_UART1_CTS"),
 187         PINCTRL_PIN(74, "SIO_UART2_RXD"),
 188         PINCTRL_PIN(75, "SIO_UART2_TXD"),
 189         PINCTRL_PIN(76, "SIO_UART2_RTS"),
 190         PINCTRL_PIN(77, "SIO_UART2_CTS"),
 191         PINCTRL_PIN(78, "SIO_I2C0_DATA"),
 192         PINCTRL_PIN(79, "SIO_I2C0_CLK"),
 193         PINCTRL_PIN(80, "SIO_I2C1_DATA"),
 194         PINCTRL_PIN(81, "SIO_I2C1_CLK"),
 195         PINCTRL_PIN(82, "SIO_I2C2_DATA"),
 196         PINCTRL_PIN(83, "SIO_I2C2_CLK"),
 197         PINCTRL_PIN(84, "SIO_I2C3_DATA"),
 198         PINCTRL_PIN(85, "SIO_I2C3_CLK"),
 199         PINCTRL_PIN(86, "SIO_I2C4_DATA"),
 200         PINCTRL_PIN(87, "SIO_I2C4_CLK"),
 201         PINCTRL_PIN(88, "SIO_I2C5_DATA"),
 202         PINCTRL_PIN(89, "SIO_I2C5_CLK"),
 203         PINCTRL_PIN(90, "SIO_I2C6_DATA"),
 204         PINCTRL_PIN(91, "SIO_I2C6_CLK"),
 205         PINCTRL_PIN(92, "GPIO_S0_SC92"),
 206         PINCTRL_PIN(93, "GPIO_S0_SC93"),
 207         PINCTRL_PIN(94, "SIO_PWM0"),
 208         PINCTRL_PIN(95, "SIO_PWM1"),
 209         PINCTRL_PIN(96, "PMC_PLT_CLK0"),
 210         PINCTRL_PIN(97, "PMC_PLT_CLK1"),
 211         PINCTRL_PIN(98, "PMC_PLT_CLK2"),
 212         PINCTRL_PIN(99, "PMC_PLT_CLK3"),
 213         PINCTRL_PIN(100, "PMC_PLT_CLK4"),
 214         PINCTRL_PIN(101, "PMC_PLT_CLK5"),
 215 };
 216
 217 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
 218         85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
 219         36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
 220         54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
 221         52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
 222         95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
 223         86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
 224         80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
 225         2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
 226         31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
 227         24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
 228         97, 100,
 229 };
 230
 231 /* SCORE groups */
 232 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
 233 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
 234
 235 static const unsigned int byt_score_pwm0_pins[] = { 94 };
 236 static const unsigned int byt_score_pwm1_pins[] = { 95 };
 237
 238 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
 239
 240 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
 241 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
 242 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
 243 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
 244 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
 245 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
 246 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
 247
 248 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
 249 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
 250 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
 251
 252 static const unsigned int byt_score_sdcard_pins[] = {
 253         7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
 254 };
 255 static const unsigned int byt_score_sdcard_mux_values[] = {
 256         2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 257 };
 258
 259 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
 260
 261 static const unsigned int byt_score_emmc_pins[] = {
 262         16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
 263 };
 264
 265 static const unsigned int byt_score_ilb_lpc_pins[] = {
 266         42, 43, 44, 45, 46, 47, 48, 49, 50,
 267 };
 268
 269 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
 270
 271 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
 272 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
 273 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
 274 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
 275 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
 276 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
 277
 278 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
 279
 280 static const struct intel_pingroup byt_score_groups[] = {
 281         PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
 282         PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
 283         PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
 284         PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
 285         PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
 286         PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
 287         PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
 288         PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
 289         PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
 290         PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
 291         PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
 292         PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
 293         PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
 294         PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
 295         PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
 296         PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
 297         PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
 298         PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
 299         PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
 300         PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
 301         PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
 302         PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
 303         PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
 304         PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
 305         PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
 306         PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
 307         PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
 308 };
 309
 310 static const char * const byt_score_uart_groups[] = {
 311         "uart1_grp", "uart2_grp",
 312 };
 313 static const char * const byt_score_pwm_groups[] = {
 314         "pwm0_grp", "pwm1_grp",
 315 };
 316 static const char * const byt_score_ssp_groups[] = {
 317         "ssp0_grp", "ssp1_grp", "ssp2_grp",
 318 };
 319 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
 320 static const char * const byt_score_i2c_groups[] = {
 321         "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
 322         "i2c6_grp",
 323 };
 324 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
 325 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
 326 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
 327 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
 328 static const char * const byt_score_sata_groups[] = { "sata_grp" };
 329 static const char * const byt_score_plt_clk_groups[] = {
 330         "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
 331         "plt_clk4_grp", "plt_clk5_grp",
 332 };
 333 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
 334 static const char * const byt_score_gpio_groups[] = {
 335         "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
 336         "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
 337         "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
 338         "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
 339         "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
 340         "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
 341 };
 342
 343 static const struct intel_function byt_score_functions[] = {
 344         FUNCTION("uart", byt_score_uart_groups),
 345         FUNCTION("pwm", byt_score_pwm_groups),
 346         FUNCTION("ssp", byt_score_ssp_groups),
 347         FUNCTION("spi", byt_score_spi_groups),
 348         FUNCTION("i2c", byt_score_i2c_groups),
 349         FUNCTION("sdcard", byt_score_sdcard_groups),
 350         FUNCTION("sdio", byt_score_sdio_groups),
 351         FUNCTION("emmc", byt_score_emmc_groups),
 352         FUNCTION("lpc", byt_score_lpc_groups),
 353         FUNCTION("sata", byt_score_sata_groups),
 354         FUNCTION("plt_clk", byt_score_plt_clk_groups),
 355         FUNCTION("smbus", byt_score_smbus_groups),
 356         FUNCTION("gpio", byt_score_gpio_groups),
 357 };
 358
 359 static const struct intel_community byt_score_communities[] = {
 360         COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
 361 };
 362
 363 static const struct intel_pinctrl_soc_data byt_score_soc_data = {
 364         .uid            = BYT_SCORE_ACPI_UID,
 365         .pins           = byt_score_pins,
 366         .npins          = ARRAY_SIZE(byt_score_pins),
 367         .groups         = byt_score_groups,
 368         .ngroups        = ARRAY_SIZE(byt_score_groups),
 369         .functions      = byt_score_functions,
 370         .nfunctions     = ARRAY_SIZE(byt_score_functions),
 371         .communities    = byt_score_communities,
 372         .ncommunities   = ARRAY_SIZE(byt_score_communities),
 373 };
 374
 375 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>]  */
 376 static const struct pinctrl_pin_desc byt_sus_pins[] = {
 377         PINCTRL_PIN(0, "GPIO_S50"),
 378         PINCTRL_PIN(1, "GPIO_S51"),
 379         PINCTRL_PIN(2, "GPIO_S52"),
 380         PINCTRL_PIN(3, "GPIO_S53"),
 381         PINCTRL_PIN(4, "GPIO_S54"),
 382         PINCTRL_PIN(5, "GPIO_S55"),
 383         PINCTRL_PIN(6, "GPIO_S56"),
 384         PINCTRL_PIN(7, "GPIO_S57"),
 385         PINCTRL_PIN(8, "GPIO_S58"),
 386         PINCTRL_PIN(9, "GPIO_S59"),
 387         PINCTRL_PIN(10, "GPIO_S510"),
 388         PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
 389         PINCTRL_PIN(12, "PMC_SUSCLK0"),
 390         PINCTRL_PIN(13, "GPIO_S513"),
 391         PINCTRL_PIN(14, "USB_ULPI_RST"),
 392         PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
 393         PINCTRL_PIN(16, "PMC_PWRBTN"),
 394         PINCTRL_PIN(17, "GPIO_S517"),
 395         PINCTRL_PIN(18, "PMC_SUS_STAT"),
 396         PINCTRL_PIN(19, "USB_OC0"),
 397         PINCTRL_PIN(20, "USB_OC1"),
 398         PINCTRL_PIN(21, "PCU_SPI_CS1"),
 399         PINCTRL_PIN(22, "GPIO_S522"),
 400         PINCTRL_PIN(23, "GPIO_S523"),
 401         PINCTRL_PIN(24, "GPIO_S524"),
 402         PINCTRL_PIN(25, "GPIO_S525"),
 403         PINCTRL_PIN(26, "GPIO_S526"),
 404         PINCTRL_PIN(27, "GPIO_S527"),
 405         PINCTRL_PIN(28, "GPIO_S528"),
 406         PINCTRL_PIN(29, "GPIO_S529"),
 407         PINCTRL_PIN(30, "GPIO_S530"),
 408         PINCTRL_PIN(31, "USB_ULPI_CLK"),
 409         PINCTRL_PIN(32, "USB_ULPI_DATA0"),
 410         PINCTRL_PIN(33, "USB_ULPI_DATA1"),
 411         PINCTRL_PIN(34, "USB_ULPI_DATA2"),
 412         PINCTRL_PIN(35, "USB_ULPI_DATA3"),
 413         PINCTRL_PIN(36, "USB_ULPI_DATA4"),
 414         PINCTRL_PIN(37, "USB_ULPI_DATA5"),
 415         PINCTRL_PIN(38, "USB_ULPI_DATA6"),
 416         PINCTRL_PIN(39, "USB_ULPI_DATA7"),
 417         PINCTRL_PIN(40, "USB_ULPI_DIR"),
 418         PINCTRL_PIN(41, "USB_ULPI_NXT"),
 419         PINCTRL_PIN(42, "USB_ULPI_STP"),
 420         PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
 421 };
 422
 423 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
 424         29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
 425         18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
 426         0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
 427         26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
 428         52, 53, 59, 40,
 429 };
 430
 431 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
 432 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
 433 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
 434
 435 static const unsigned int byt_sus_usb_ulpi_pins[] = {
 436         14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
 437 };
 438 static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
 439         2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 440 };
 441 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
 442         1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 443 };
 444
 445 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
 446 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
 447 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
 448
 449 static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 };
 450 static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 };
 451
 452 static const struct intel_pingroup byt_sus_groups[] = {
 453         PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
 454         PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
 455         PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
 456         PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
 457         PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
 458         PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
 459         PIN_GROUP("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1),
 460         PIN_GROUP("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1),
 461 };
 462
 463 static const char * const byt_sus_usb_groups[] = {
 464         "usb_oc_grp", "usb_ulpi_grp",
 465 };
 466 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
 467 static const char * const byt_sus_pmu_clk_groups[] = {
 468         "pmu_clk1_grp", "pmu_clk2_grp",
 469 };
 470 static const char * const byt_sus_gpio_groups[] = {
 471         "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
 472         "pmu_clk1_grp", "pmu_clk2_grp",
 473 };
 474
 475 static const struct intel_function byt_sus_functions[] = {
 476         FUNCTION("usb", byt_sus_usb_groups),
 477         FUNCTION("spi", byt_sus_spi_groups),
 478         FUNCTION("gpio", byt_sus_gpio_groups),
 479         FUNCTION("pmu_clk", byt_sus_pmu_clk_groups),
 480 };
 481
 482 static const struct intel_community byt_sus_communities[] = {
 483         COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
 484 };
 485
 486 static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
 487         .uid            = BYT_SUS_ACPI_UID,
 488         .pins           = byt_sus_pins,
 489         .npins          = ARRAY_SIZE(byt_sus_pins),
 490         .groups         = byt_sus_groups,
 491         .ngroups        = ARRAY_SIZE(byt_sus_groups),
 492         .functions      = byt_sus_functions,
 493         .nfunctions     = ARRAY_SIZE(byt_sus_functions),
 494         .communities    = byt_sus_communities,
 495         .ncommunities   = ARRAY_SIZE(byt_sus_communities),
 496 };
 497
 498 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
 499         PINCTRL_PIN(0, "HV_DDI0_HPD"),
 500         PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"),
 501         PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"),
 502         PINCTRL_PIN(3, "PANEL0_VDDEN"),
 503         PINCTRL_PIN(4, "PANEL0_BKLTEN"),
 504         PINCTRL_PIN(5, "PANEL0_BKLTCTL"),
 505         PINCTRL_PIN(6, "HV_DDI1_HPD"),
 506         PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"),
 507         PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"),
 508         PINCTRL_PIN(9, "PANEL1_VDDEN"),
 509         PINCTRL_PIN(10, "PANEL1_BKLTEN"),
 510         PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
 511         PINCTRL_PIN(12, "GP_INTD_DSI_TE1"),
 512         PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"),
 513         PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"),
 514         PINCTRL_PIN(15, "GP_CAMERASB00"),
 515         PINCTRL_PIN(16, "GP_CAMERASB01"),
 516         PINCTRL_PIN(17, "GP_CAMERASB02"),
 517         PINCTRL_PIN(18, "GP_CAMERASB03"),
 518         PINCTRL_PIN(19, "GP_CAMERASB04"),
 519         PINCTRL_PIN(20, "GP_CAMERASB05"),
 520         PINCTRL_PIN(21, "GP_CAMERASB06"),
 521         PINCTRL_PIN(22, "GP_CAMERASB07"),
 522         PINCTRL_PIN(23, "GP_CAMERASB08"),
 523         PINCTRL_PIN(24, "GP_CAMERASB09"),
 524         PINCTRL_PIN(25, "GP_CAMERASB10"),
 525         PINCTRL_PIN(26, "GP_CAMERASB11"),
 526         PINCTRL_PIN(27, "GP_INTD_DSI_TE2"),
 527 };
 528
 529 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
 530         19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
 531         14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
 532         3, 6, 10, 13, 2, 5, 9, 7,
 533 };
 534
 535 static const struct intel_community byt_ncore_communities[] = {
 536         COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
 537 };
 538
 539 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
 540         .uid            = BYT_NCORE_ACPI_UID,
 541         .pins           = byt_ncore_pins,
 542         .npins          = ARRAY_SIZE(byt_ncore_pins),
 543         .communities    = byt_ncore_communities,
 544         .ncommunities   = ARRAY_SIZE(byt_ncore_communities),
 545 };
 546
 547 static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
 548         &byt_score_soc_data,
 549         &byt_sus_soc_data,
 550         &byt_ncore_soc_data,
 551         NULL
 552 };
 553
 554 static DEFINE_RAW_SPINLOCK(byt_lock);
 555
 556 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
 557                                   int reg)
 558 {
 559         struct intel_community *comm = intel_get_community(vg, offset);
 560         u32 reg_offset;
 561
 562         if (!comm)
 563                 return NULL;
 564
 565         offset -= comm->pin_base;
 566         switch (reg) {
 567         case BYT_INT_STAT_REG:
 568                 reg_offset = (offset / 32) * 4;
 569                 break;
 570         case BYT_DEBOUNCE_REG:
 571                 reg_offset = 0;
 572                 break;
 573         default:
 574                 reg_offset = comm->pad_map[offset] * 16;
 575                 break;
 576         }
 577
 578         return comm->pad_regs + reg_offset + reg;
 579 }
 580
 581 static const struct pinctrl_ops byt_pinctrl_ops = {
 582         .get_groups_count       = intel_get_groups_count,
 583         .get_group_name         = intel_get_group_name,
 584         .get_group_pins         = intel_get_group_pins,
 585 };
 586
 587 static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
 588                                      const struct intel_pingroup group,
 589                                      unsigned int func)
 590 {
 591         unsigned long flags;
 592         int i;
 593
 594         raw_spin_lock_irqsave(&byt_lock, flags);
 595
 596         for (i = 0; i < group.grp.npins; i++) {
 597                 void __iomem *padcfg0;
 598                 u32 value;
 599
 600                 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
 601                 if (!padcfg0) {
 602                         dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
 603                                  group.grp.name, i);
 604                         continue;
 605                 }
 606
 607                 value = readl(padcfg0);
 608                 value &= ~BYT_PIN_MUX;
 609                 value |= func;
 610                 writel(value, padcfg0);
 611         }
 612
 613         raw_spin_unlock_irqrestore(&byt_lock, flags);
 614 }
 615
 616 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
 617                                     const struct intel_pingroup group,
 618                                     const unsigned int *func)
 619 {
 620         unsigned long flags;
 621         int i;
 622
 623         raw_spin_lock_irqsave(&byt_lock, flags);
 624
 625         for (i = 0; i < group.grp.npins; i++) {
 626                 void __iomem *padcfg0;
 627                 u32 value;
 628
 629                 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
 630                 if (!padcfg0) {
 631                         dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
 632                                  group.grp.name, i);
 633                         continue;
 634                 }
 635
 636                 value = readl(padcfg0);
 637                 value &= ~BYT_PIN_MUX;
 638                 value |= func[i];
 639                 writel(value, padcfg0);
 640         }
 641
 642         raw_spin_unlock_irqrestore(&byt_lock, flags);
 643 }
 644
 645 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
 646                        unsigned int group_selector)
 647 {
 648         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 649         const struct intel_function func = vg->soc->functions[func_selector];
 650         const struct intel_pingroup group = vg->soc->groups[group_selector];
 651
 652         if (group.modes)
 653                 byt_set_group_mixed_mux(vg, group, group.modes);
 654         else if (!strcmp(func.func.name, "gpio"))
 655                 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
 656         else
 657                 byt_set_group_simple_mux(vg, group, group.mode);
 658
 659         return 0;
 660 }
 661
 662 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
 663 {
 664         /* SCORE pin 92-93 */
 665         if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&
 666             offset >= 92 && offset <= 93)
 667                 return BYT_ALTER_GPIO_MUX;
 668
 669         /* SUS pin 11-21 */
 670         if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&
 671             offset >= 11 && offset <= 21)
 672                 return BYT_ALTER_GPIO_MUX;
 673
 674         return BYT_DEFAULT_GPIO_MUX;
 675 }
 676
 677 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
 678 {
 679         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 680         unsigned long flags;
 681         u32 value;
 682
 683         raw_spin_lock_irqsave(&byt_lock, flags);
 684         value = readl(reg);
 685
 686         /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
 687         if (!(value & BYT_DIRECT_IRQ_EN))
 688                 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
 689
 690         writel(value, reg);
 691         raw_spin_unlock_irqrestore(&byt_lock, flags);
 692 }
 693
 694 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
 695                                    struct pinctrl_gpio_range *range,
 696                                    unsigned int offset)
 697 {
 698         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 699         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 700         u32 value, gpio_mux;
 701         unsigned long flags;
 702
 703         raw_spin_lock_irqsave(&byt_lock, flags);
 704
 705         /*
 706          * In most cases, func pin mux 000 means GPIO function.
 707          * But, some pins may have func pin mux 001 represents
 708          * GPIO function.
 709          *
 710          * Because there are devices out there where some pins were not
 711          * configured correctly we allow changing the mux value from
 712          * request (but print out warning about that).
 713          */
 714         value = readl(reg) & BYT_PIN_MUX;
 715         gpio_mux = byt_get_gpio_mux(vg, offset);
 716         if (gpio_mux != value) {
 717                 value = readl(reg) & ~BYT_PIN_MUX;
 718                 value |= gpio_mux;
 719                 writel(value, reg);
 720
 721                 dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);
 722         }
 723
 724         raw_spin_unlock_irqrestore(&byt_lock, flags);
 725
 726         return 0;
 727 }
 728
 729 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
 730                                   struct pinctrl_gpio_range *range,
 731                                   unsigned int offset)
 732 {
 733         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 734
 735         byt_gpio_clear_triggering(vg, offset);
 736 }
 737
 738 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
 739                                       unsigned int offset)
 740 {
 741         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 742
 743         /*
 744          * Before making any direction modifications, do a check if gpio is set
 745          * for direct IRQ. On Bay Trail, setting GPIO to output does not make
 746          * sense, so let's at least inform the caller before they shoot
 747          * themselves in the foot.
 748          */
 749         if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
 750                 dev_info_once(vg->dev,
 751                               "Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n",
 752                               offset);
 753 }
 754
 755 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
 756                                   struct pinctrl_gpio_range *range,
 757                                   unsigned int offset,
 758                                   bool input)
 759 {
 760         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 761         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 762         unsigned long flags;
 763         u32 value;
 764
 765         raw_spin_lock_irqsave(&byt_lock, flags);
 766
 767         value = readl(val_reg);
 768         value &= ~BYT_DIR_MASK;
 769         if (input)
 770                 value |= BYT_OUTPUT_EN;
 771         else
 772                 byt_gpio_direct_irq_check(vg, offset);
 773
 774         writel(value, val_reg);
 775
 776         raw_spin_unlock_irqrestore(&byt_lock, flags);
 777
 778         return 0;
 779 }
 780
 781 static const struct pinmux_ops byt_pinmux_ops = {
 782         .get_functions_count    = intel_get_functions_count,
 783         .get_function_name      = intel_get_function_name,
 784         .get_function_groups    = intel_get_function_groups,
 785         .set_mux                = byt_set_mux,
 786         .gpio_request_enable    = byt_gpio_request_enable,
 787         .gpio_disable_free      = byt_gpio_disable_free,
 788         .gpio_set_direction     = byt_gpio_set_direction,
 789 };
 790
 791 static void byt_get_pull_strength(u32 reg, u16 *strength)
 792 {
 793         switch (reg & BYT_PULL_STR_MASK) {
 794         case BYT_PULL_STR_2K:
 795                 *strength = 2000;
 796                 break;
 797         case BYT_PULL_STR_10K:
 798                 *strength = 10000;
 799                 break;
 800         case BYT_PULL_STR_20K:
 801                 *strength = 20000;
 802                 break;
 803         case BYT_PULL_STR_40K:
 804                 *strength = 40000;
 805                 break;
 806         }
 807 }
 808
 809 static int byt_set_pull_strength(u32 *reg, u16 strength)
 810 {
 811         *reg &= ~BYT_PULL_STR_MASK;
 812
 813         switch (strength) {
 814         case 2000:
 815                 *reg |= BYT_PULL_STR_2K;
 816                 break;
 817         case 10000:
 818                 *reg |= BYT_PULL_STR_10K;
 819                 break;
 820         case 20000:
 821                 *reg |= BYT_PULL_STR_20K;
 822                 break;
 823         case 40000:
 824                 *reg |= BYT_PULL_STR_40K;
 825                 break;
 826         default:
 827                 return -EINVAL;
 828         }
 829
 830         return 0;
 831 }
 832
 833 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
 834                               unsigned long *config)
 835 {
 836         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 837         enum pin_config_param param = pinconf_to_config_param(*config);
 838         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 839         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 840         void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
 841         unsigned long flags;
 842         u32 conf, pull, val, debounce;
 843         u16 arg = 0;
 844
 845         raw_spin_lock_irqsave(&byt_lock, flags);
 846         conf = readl(conf_reg);
 847         pull = conf & BYT_PULL_ASSIGN_MASK;
 848         val = readl(val_reg);
 849         raw_spin_unlock_irqrestore(&byt_lock, flags);
 850
 851         switch (param) {
 852         case PIN_CONFIG_BIAS_DISABLE:
 853                 if (pull)
 854                         return -EINVAL;
 855                 break;
 856         case PIN_CONFIG_BIAS_PULL_DOWN:
 857                 /* Pull assignment is only applicable in input mode */
 858                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
 859                         return -EINVAL;
 860
 861                 byt_get_pull_strength(conf, &arg);
 862
 863                 break;
 864         case PIN_CONFIG_BIAS_PULL_UP:
 865                 /* Pull assignment is only applicable in input mode */
 866                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
 867                         return -EINVAL;
 868
 869                 byt_get_pull_strength(conf, &arg);
 870
 871                 break;
 872         case PIN_CONFIG_INPUT_DEBOUNCE:
 873                 if (!(conf & BYT_DEBOUNCE_EN))
 874                         return -EINVAL;
 875
 876                 raw_spin_lock_irqsave(&byt_lock, flags);
 877                 debounce = readl(db_reg);
 878                 raw_spin_unlock_irqrestore(&byt_lock, flags);
 879
 880                 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
 881                 case BYT_DEBOUNCE_PULSE_375US:
 882                         arg = 375;
 883                         break;
 884                 case BYT_DEBOUNCE_PULSE_750US:
 885                         arg = 750;
 886                         break;
 887                 case BYT_DEBOUNCE_PULSE_1500US:
 888                         arg = 1500;
 889                         break;
 890                 case BYT_DEBOUNCE_PULSE_3MS:
 891                         arg = 3000;
 892                         break;
 893                 case BYT_DEBOUNCE_PULSE_6MS:
 894                         arg = 6000;
 895                         break;
 896                 case BYT_DEBOUNCE_PULSE_12MS:
 897                         arg = 12000;
 898                         break;
 899                 case BYT_DEBOUNCE_PULSE_24MS:
 900                         arg = 24000;
 901                         break;
 902                 default:
 903                         return -EINVAL;
 904                 }
 905
 906                 break;
 907         default:
 908                 return -ENOTSUPP;
 909         }
 910
 911         *config = pinconf_to_config_packed(param, arg);
 912
 913         return 0;
 914 }
 915
 916 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
 917                               unsigned int offset,
 918                               unsigned long *configs,
 919                               unsigned int num_configs)
 920 {
 921         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 922         unsigned int param, arg;
 923         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 924         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 925         void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
 926         u32 conf, val, db_pulse, debounce;
 927         unsigned long flags;
 928         int i, ret = 0;
 929
 930         raw_spin_lock_irqsave(&byt_lock, flags);
 931
 932         conf = readl(conf_reg);
 933         val = readl(val_reg);
 934
 935         for (i = 0; i < num_configs; i++) {
 936                 param = pinconf_to_config_param(configs[i]);
 937                 arg = pinconf_to_config_argument(configs[i]);
 938
 939                 switch (param) {
 940                 case PIN_CONFIG_BIAS_DISABLE:
 941                         conf &= ~BYT_PULL_ASSIGN_MASK;
 942                         break;
 943                 case PIN_CONFIG_BIAS_PULL_DOWN:
 944                         /* Set default strength value in case none is given */
 945                         if (arg == 1)
 946                                 arg = 2000;
 947
 948                         /*
 949                          * Pull assignment is only applicable in input mode. If
 950                          * chip is not in input mode, set it and warn about it.
 951                          */
 952                         if (val & BYT_INPUT_EN) {
 953                                 val &= ~BYT_INPUT_EN;
 954                                 writel(val, val_reg);
 955                                 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
 956                         }
 957
 958                         conf &= ~BYT_PULL_ASSIGN_MASK;
 959                         conf |= BYT_PULL_ASSIGN_DOWN;
 960                         ret = byt_set_pull_strength(&conf, arg);
 961
 962                         break;
 963                 case PIN_CONFIG_BIAS_PULL_UP:
 964                         /* Set default strength value in case none is given */
 965                         if (arg == 1)
 966                                 arg = 2000;
 967
 968                         /*
 969                          * Pull assignment is only applicable in input mode. If
 970                          * chip is not in input mode, set it and warn about it.
 971                          */
 972                         if (val & BYT_INPUT_EN) {
 973                                 val &= ~BYT_INPUT_EN;
 974                                 writel(val, val_reg);
 975                                 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
 976                         }
 977
 978                         conf &= ~BYT_PULL_ASSIGN_MASK;
 979                         conf |= BYT_PULL_ASSIGN_UP;
 980                         ret = byt_set_pull_strength(&conf, arg);
 981
 982                         break;
 983                 case PIN_CONFIG_INPUT_DEBOUNCE:
 984                         if (arg) {
 985                                 conf |= BYT_DEBOUNCE_EN;
 986                         } else {
 987                                 conf &= ~BYT_DEBOUNCE_EN;
 988
 989                                 /*
 990                                  * No need to update the pulse value.
 991                                  * Debounce is going to be disabled.
 992                                  */
 993                                 break;
 994                         }
 995
 996                         switch (arg) {
 997                         case 375:
 998                                 db_pulse = BYT_DEBOUNCE_PULSE_375US;
 999                                 break;
1000                         case 750:
1001                                 db_pulse = BYT_DEBOUNCE_PULSE_750US;
1002                                 break;
1003                         case 1500:
1004                                 db_pulse = BYT_DEBOUNCE_PULSE_1500US;
1005                                 break;
1006                         case 3000:
1007                                 db_pulse = BYT_DEBOUNCE_PULSE_3MS;
1008                                 break;
1009                         case 6000:
1010                                 db_pulse = BYT_DEBOUNCE_PULSE_6MS;
1011                                 break;
1012                         case 12000:
1013                                 db_pulse = BYT_DEBOUNCE_PULSE_12MS;
1014                                 break;
1015                         case 24000:
1016                                 db_pulse = BYT_DEBOUNCE_PULSE_24MS;
1017                                 break;
1018                         default:
1019                                 if (arg)
1020                                         ret = -EINVAL;
1021                                 break;
1022                         }
1023
1024                         if (ret)
1025                                 break;
1026
1027                         debounce = readl(db_reg);
1028                         debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse;
1029                         writel(debounce, db_reg);
1030
1031                         break;
1032                 default:
1033                         ret = -ENOTSUPP;
1034                 }
1035
1036                 if (ret)
1037                         break;
1038         }
1039
1040         if (!ret)
1041                 writel(conf, conf_reg);
1042
1043         raw_spin_unlock_irqrestore(&byt_lock, flags);
1044
1045         return ret;
1046 }
1047
1048 static const struct pinconf_ops byt_pinconf_ops = {
1049         .is_generic     = true,
1050         .pin_config_get = byt_pin_config_get,
1051         .pin_config_set = byt_pin_config_set,
1052 };
1053
1054 static const struct pinctrl_desc byt_pinctrl_desc = {
1055         .pctlops        = &byt_pinctrl_ops,
1056         .pmxops         = &byt_pinmux_ops,
1057         .confops        = &byt_pinconf_ops,
1058         .owner          = THIS_MODULE,
1059 };
1060
1061 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1062 {
1063         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1064         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1065         unsigned long flags;
1066         u32 val;
1067
1068         raw_spin_lock_irqsave(&byt_lock, flags);
1069         val = readl(reg);
1070         raw_spin_unlock_irqrestore(&byt_lock, flags);
1071
1072         return !!(val & BYT_LEVEL);
1073 }
1074
1075 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1076 {
1077         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1078         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1079         unsigned long flags;
1080         u32 old_val;
1081
1082         if (!reg)
1083                 return;
1084
1085         raw_spin_lock_irqsave(&byt_lock, flags);
1086         old_val = readl(reg);
1087         if (value)
1088                 writel(old_val | BYT_LEVEL, reg);
1089         else
1090                 writel(old_val & ~BYT_LEVEL, reg);
1091         raw_spin_unlock_irqrestore(&byt_lock, flags);
1092 }
1093
1094 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1095 {
1096         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1097         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1098         unsigned long flags;
1099         u32 value;
1100
1101         if (!reg)
1102                 return -EINVAL;
1103
1104         raw_spin_lock_irqsave(&byt_lock, flags);
1105         value = readl(reg);
1106         raw_spin_unlock_irqrestore(&byt_lock, flags);
1107
1108         if (!(value & BYT_OUTPUT_EN))
1109                 return GPIO_LINE_DIRECTION_OUT;
1110         if (!(value & BYT_INPUT_EN))
1111                 return GPIO_LINE_DIRECTION_IN;
1112
1113         return -EINVAL;
1114 }
1115
1116 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1117 {
1118         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1119         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1120         unsigned long flags;
1121         u32 reg;
1122
1123         raw_spin_lock_irqsave(&byt_lock, flags);
1124
1125         reg = readl(val_reg);
1126         reg &= ~BYT_DIR_MASK;
1127         reg |= BYT_OUTPUT_EN;
1128         writel(reg, val_reg);
1129
1130         raw_spin_unlock_irqrestore(&byt_lock, flags);
1131         return 0;
1132 }
1133
1134 /*
1135  * Note despite the temptation this MUST NOT be converted into a call to
1136  * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this
1137  * MUST be done as a single BYT_VAL_REG register write.
1138  * See the commit message of the commit adding this comment for details.
1139  */
1140 static int byt_gpio_direction_output(struct gpio_chip *chip,
1141                                      unsigned int offset, int value)
1142 {
1143         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1144         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1145         unsigned long flags;
1146         u32 reg;
1147
1148         raw_spin_lock_irqsave(&byt_lock, flags);
1149
1150         byt_gpio_direct_irq_check(vg, offset);
1151
1152         reg = readl(val_reg);
1153         reg &= ~BYT_DIR_MASK;
1154         if (value)
1155                 reg |= BYT_LEVEL;
1156         else
1157                 reg &= ~BYT_LEVEL;
1158
1159         writel(reg, val_reg);
1160
1161         raw_spin_unlock_irqrestore(&byt_lock, flags);
1162         return 0;
1163 }
1164
1165 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1166 {
1167         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1168         int i;
1169         u32 conf0, val;
1170
1171         for (i = 0; i < vg->soc->npins; i++) {
1172                 const struct intel_community *comm;
1173                 void __iomem *conf_reg, *val_reg;
1174                 const char *pull_str = NULL;
1175                 const char *pull = NULL;
1176                 unsigned long flags;
1177                 unsigned int pin;
1178
1179                 pin = vg->soc->pins[i].number;
1180
1181                 conf_reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1182                 if (!conf_reg) {
1183                         seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin);
1184                         continue;
1185                 }
1186
1187                 val_reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1188                 if (!val_reg) {
1189                         seq_printf(s, "Pin %i: can't retrieve VAL\n", pin);
1190                         continue;
1191                 }
1192
1193                 raw_spin_lock_irqsave(&byt_lock, flags);
1194                 conf0 = readl(conf_reg);
1195                 val = readl(val_reg);
1196                 raw_spin_unlock_irqrestore(&byt_lock, flags);
1197
1198                 comm = intel_get_community(vg, pin);
1199                 if (!comm) {
1200                         seq_printf(s, "Pin %i: can't retrieve community\n", pin);
1201                         continue;
1202                 }
1203
1204                 char *label __free(kfree) = gpiochip_dup_line_label(chip, i);
1205                 if (IS_ERR(label))
1206                         continue;
1207
1208                 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1209                 case BYT_PULL_ASSIGN_UP:
1210                         pull = "up";
1211                         break;
1212                 case BYT_PULL_ASSIGN_DOWN:
1213                         pull = "down";
1214                         break;
1215                 }
1216
1217                 switch (conf0 & BYT_PULL_STR_MASK) {
1218                 case BYT_PULL_STR_2K:
1219                         pull_str = "2k";
1220                         break;
1221                 case BYT_PULL_STR_10K:
1222                         pull_str = "10k";
1223                         break;
1224                 case BYT_PULL_STR_20K:
1225                         pull_str = "20k";
1226                         break;
1227                 case BYT_PULL_STR_40K:
1228                         pull_str = "40k";
1229                         break;
1230                 }
1231
1232                 seq_printf(s,
1233                            " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1234                            pin,
1235                            label ?: "Unrequested",
1236                            val & BYT_INPUT_EN ? "  " : "in",
1237                            val & BYT_OUTPUT_EN ? "   " : "out",
1238                            str_hi_lo(val & BYT_LEVEL),
1239                            comm->pad_map[i], comm->pad_map[i] * 16,
1240                            conf0 & 0x7,
1241                            conf0 & BYT_TRIG_NEG ? " fall" : "     ",
1242                            conf0 & BYT_TRIG_POS ? " rise" : "     ",
1243                            conf0 & BYT_TRIG_LVL ? " level" : "      ");
1244
1245                 if (pull && pull_str)
1246                         seq_printf(s, " %-4s %-3s", pull, pull_str);
1247                 else
1248                         seq_puts(s, "          ");
1249
1250                 if (conf0 & BYT_IODEN)
1251                         seq_puts(s, " open-drain");
1252
1253                 seq_puts(s, "\n");
1254         }
1255 }
1256
1257 static const struct gpio_chip byt_gpio_chip = {
1258         .owner                  = THIS_MODULE,
1259         .request                = gpiochip_generic_request,
1260         .free                   = gpiochip_generic_free,
1261         .get_direction          = byt_gpio_get_direction,
1262         .direction_input        = byt_gpio_direction_input,
1263         .direction_output       = byt_gpio_direction_output,
1264         .get                    = byt_gpio_get,
1265         .set                    = byt_gpio_set,
1266         .set_config             = gpiochip_generic_config,
1267         .dbg_show               = byt_gpio_dbg_show,
1268 };
1269
1270 static void byt_irq_ack(struct irq_data *d)
1271 {
1272         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1273         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1274         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1275         void __iomem *reg;
1276
1277         reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG);
1278         if (!reg)
1279                 return;
1280
1281         raw_spin_lock(&byt_lock);
1282         writel(BIT(hwirq % 32), reg);
1283         raw_spin_unlock(&byt_lock);
1284 }
1285
1286 static void byt_irq_mask(struct irq_data *d)
1287 {
1288         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1289         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1290         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1291
1292         byt_gpio_clear_triggering(vg, hwirq);
1293         gpiochip_disable_irq(gc, hwirq);
1294 }
1295
1296 static void byt_irq_unmask(struct irq_data *d)
1297 {
1298         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1299         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1300         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1301         unsigned long flags;
1302         void __iomem *reg;
1303         u32 value;
1304
1305         gpiochip_enable_irq(gc, hwirq);
1306
1307         reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1308         if (!reg)
1309                 return;
1310
1311         raw_spin_lock_irqsave(&byt_lock, flags);
1312         value = readl(reg);
1313
1314         switch (irqd_get_trigger_type(d)) {
1315         case IRQ_TYPE_LEVEL_HIGH:
1316                 value |= BYT_TRIG_LVL;
1317                 fallthrough;
1318         case IRQ_TYPE_EDGE_RISING:
1319                 value |= BYT_TRIG_POS;
1320                 break;
1321         case IRQ_TYPE_LEVEL_LOW:
1322                 value |= BYT_TRIG_LVL;
1323                 fallthrough;
1324         case IRQ_TYPE_EDGE_FALLING:
1325                 value |= BYT_TRIG_NEG;
1326                 break;
1327         case IRQ_TYPE_EDGE_BOTH:
1328                 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1329                 break;
1330         }
1331
1332         writel(value, reg);
1333
1334         raw_spin_unlock_irqrestore(&byt_lock, flags);
1335 }
1336
1337 static int byt_irq_type(struct irq_data *d, unsigned int type)
1338 {
1339         struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1340         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1341         u32 value;
1342         unsigned long flags;
1343         void __iomem *reg;
1344
1345         reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1346         if (!reg)
1347                 return -EINVAL;
1348
1349         raw_spin_lock_irqsave(&byt_lock, flags);
1350         value = readl(reg);
1351
1352         WARN(value & BYT_DIRECT_IRQ_EN,
1353              "Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing");
1354
1355         /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1356          * are used to indicate high and low level triggering
1357          */
1358         value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1359                    BYT_TRIG_LVL);
1360         /* Enable glitch filtering */
1361         value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1362                  BYT_GLITCH_F_FAST_CLK;
1363
1364         writel(value, reg);
1365
1366         if (type & IRQ_TYPE_EDGE_BOTH)
1367                 irq_set_handler_locked(d, handle_edge_irq);
1368         else if (type & IRQ_TYPE_LEVEL_MASK)
1369                 irq_set_handler_locked(d, handle_level_irq);
1370
1371         raw_spin_unlock_irqrestore(&byt_lock, flags);
1372
1373         return 0;
1374 }
1375
1376 static const struct irq_chip byt_gpio_irq_chip = {
1377         .name           = "BYT-GPIO",
1378         .irq_ack        = byt_irq_ack,
1379         .irq_mask       = byt_irq_mask,
1380         .irq_unmask     = byt_irq_unmask,
1381         .irq_set_type   = byt_irq_type,
1382         .flags          = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
1383         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1384 };
1385
1386 static void byt_gpio_irq_handler(struct irq_desc *desc)
1387 {
1388         struct irq_data *data = irq_desc_get_irq_data(desc);
1389         struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
1390         struct irq_chip *chip = irq_data_get_irq_chip(data);
1391         u32 base, pin;
1392         void __iomem *reg;
1393         unsigned long pending;
1394
1395         /* check from GPIO controller which pin triggered the interrupt */
1396         for (base = 0; base < vg->chip.ngpio; base += 32) {
1397                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1398
1399                 if (!reg) {
1400                         dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
1401                         continue;
1402                 }
1403
1404                 raw_spin_lock(&byt_lock);
1405                 pending = readl(reg);
1406                 raw_spin_unlock(&byt_lock);
1407                 for_each_set_bit(pin, &pending, 32)
1408                         generic_handle_domain_irq(vg->chip.irq.domain, base + pin);
1409         }
1410         chip->irq_eoi(data);
1411 }
1412
1413 static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0)
1414 {
1415         int direct_irq, ioapic_direct_irq_base;
1416         u8 *match, direct_irq_mux[16];
1417         u32 trig;
1418
1419         memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG,
1420                       sizeof(direct_irq_mux));
1421         match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
1422         if (!match) {
1423                 dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin);
1424                 return false;
1425         }
1426
1427         direct_irq = match - direct_irq_mux;
1428         /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */
1429         ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67;
1430         dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin,
1431                 direct_irq, direct_irq + ioapic_direct_irq_base);
1432
1433         /*
1434          * Testing has shown that the way direct IRQs work is that the combination of the
1435          * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ
1436          * trigger block, which normally sets the status flag in the IRQ status reg at
1437          * 0x800, to one of the IO-APIC pins according to the mux registers.
1438          *
1439          * This means that:
1440          * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block
1441          * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly
1442          *    passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set,
1443          *    selecting edge mode operation then on the first edge the IO-APIC pin goes
1444          *    high, but since no write-to-clear write will be done to the IRQ status reg
1445          *    at 0x800, the detected edge condition will never get cleared.
1446          */
1447         trig = conf0 & BYT_TRIG_MASK;
1448         if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
1449             trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
1450                 dev_warn(vg->dev,
1451                          FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n",
1452                          pin, conf0);
1453                 return false;
1454         }
1455
1456         return true;
1457 }
1458
1459 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
1460                                     unsigned long *valid_mask,
1461                                     unsigned int ngpios)
1462 {
1463         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1464         void __iomem *reg;
1465         u32 value;
1466         int i;
1467
1468         /*
1469          * Clear interrupt triggers for all pins that are GPIOs and
1470          * do not use direct IRQ mode. This will prevent spurious
1471          * interrupts from misconfigured pins.
1472          */
1473         for (i = 0; i < vg->soc->npins; i++) {
1474                 unsigned int pin = vg->soc->pins[i].number;
1475
1476                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1477                 if (!reg) {
1478                         dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i);
1479                         continue;
1480                 }
1481
1482                 value = readl(reg);
1483                 if (value & BYT_DIRECT_IRQ_EN) {
1484                         if (byt_direct_irq_sanity_check(vg, i, value)) {
1485                                 clear_bit(i, valid_mask);
1486                         } else {
1487                                 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS |
1488                                            BYT_TRIG_NEG | BYT_TRIG_LVL);
1489                                 writel(value, reg);
1490                         }
1491                 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1492                         byt_gpio_clear_triggering(vg, i);
1493                         dev_dbg(vg->dev, "disabling GPIO %d\n", i);
1494                 }
1495         }
1496 }
1497
1498 static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
1499 {
1500         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1501         void __iomem *reg;
1502         u32 base, value;
1503
1504         /* clear interrupt status trigger registers */
1505         for (base = 0; base < vg->soc->npins; base += 32) {
1506                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1507
1508                 if (!reg) {
1509                         dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
1510                         continue;
1511                 }
1512
1513                 writel(0xffffffff, reg);
1514                 /* make sure trigger bits are cleared, if not then a pin
1515                    might be misconfigured in bios */
1516                 value = readl(reg);
1517                 if (value)
1518                         dev_err(vg->dev,
1519                                 "GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n",
1520                                 base / 32, value);
1521         }
1522
1523         return 0;
1524 }
1525
1526 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
1527 {
1528         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1529         struct device *dev = vg->dev;
1530         int ret;
1531
1532         ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
1533         if (ret)
1534                 dev_err(dev, "failed to add GPIO pin range\n");
1535
1536         return ret;
1537 }
1538
1539 static int byt_gpio_probe(struct intel_pinctrl *vg)
1540 {
1541         struct platform_device *pdev = to_platform_device(vg->dev);
1542         struct gpio_chip *gc;
1543         int irq, ret;
1544
1545         /* Set up gpio chip */
1546         vg->chip        = byt_gpio_chip;
1547         gc              = &vg->chip;
1548         gc->label       = dev_name(vg->dev);
1549         gc->base        = -1;
1550         gc->can_sleep   = false;
1551         gc->add_pin_ranges = byt_gpio_add_pin_ranges;
1552         gc->parent      = vg->dev;
1553         gc->ngpio       = vg->soc->npins;
1554
1555 #ifdef CONFIG_PM_SLEEP
1556         vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),
1557                                         GFP_KERNEL);
1558         if (!vg->context.pads)
1559                 return -ENOMEM;
1560 #endif
1561
1562         /* set up interrupts  */
1563         irq = platform_get_irq_optional(pdev, 0);
1564         if (irq > 0) {
1565                 struct gpio_irq_chip *girq;
1566
1567                 girq = &gc->irq;
1568                 gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip);
1569                 girq->init_hw = byt_gpio_irq_init_hw;
1570                 girq->init_valid_mask = byt_init_irq_valid_mask;
1571                 girq->parent_handler = byt_gpio_irq_handler;
1572                 girq->num_parents = 1;
1573                 girq->parents = devm_kcalloc(vg->dev, girq->num_parents,
1574                                              sizeof(*girq->parents), GFP_KERNEL);
1575                 if (!girq->parents)
1576                         return -ENOMEM;
1577                 girq->parents[0] = irq;
1578                 girq->default_type = IRQ_TYPE_NONE;
1579                 girq->handler = handle_bad_irq;
1580         }
1581
1582         ret = devm_gpiochip_add_data(vg->dev, gc, vg);
1583         if (ret) {
1584                 dev_err(vg->dev, "failed adding byt-gpio chip\n");
1585                 return ret;
1586         }
1587
1588         return ret;
1589 }
1590
1591 static int byt_set_soc_data(struct intel_pinctrl *vg,
1592                             const struct intel_pinctrl_soc_data *soc)
1593 {
1594         struct platform_device *pdev = to_platform_device(vg->dev);
1595         int i;
1596
1597         vg->soc = soc;
1598
1599         vg->ncommunities = vg->soc->ncommunities;
1600         vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,
1601                                        sizeof(*vg->communities), GFP_KERNEL);
1602         if (!vg->communities)
1603                 return -ENOMEM;
1604
1605         for (i = 0; i < vg->soc->ncommunities; i++) {
1606                 struct intel_community *comm = vg->communities + i;
1607
1608                 *comm = vg->soc->communities[i];
1609
1610                 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0);
1611                 if (IS_ERR(comm->pad_regs))
1612                         return PTR_ERR(comm->pad_regs);
1613         }
1614
1615         return 0;
1616 }
1617
1618 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1619         { "INT33B2", (kernel_ulong_t)byt_soc_data },
1620         { "INT33FC", (kernel_ulong_t)byt_soc_data },
1621         { }
1622 };
1623
1624 static int byt_pinctrl_probe(struct platform_device *pdev)
1625 {
1626         const struct intel_pinctrl_soc_data *soc_data;
1627         struct device *dev = &pdev->dev;
1628         struct intel_pinctrl *vg;
1629         int ret;
1630
1631         soc_data = intel_pinctrl_get_soc_data(pdev);
1632         if (IS_ERR(soc_data))
1633                 return PTR_ERR(soc_data);
1634
1635         vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
1636         if (!vg)
1637                 return -ENOMEM;
1638
1639         vg->dev = dev;
1640         ret = byt_set_soc_data(vg, soc_data);
1641         if (ret) {
1642                 dev_err(dev, "failed to set soc data\n");
1643                 return ret;
1644         }
1645
1646         vg->pctldesc            = byt_pinctrl_desc;
1647         vg->pctldesc.name       = dev_name(dev);
1648         vg->pctldesc.pins       = vg->soc->pins;
1649         vg->pctldesc.npins      = vg->soc->npins;
1650
1651         vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
1652         if (IS_ERR(vg->pctldev)) {
1653                 dev_err(dev, "failed to register pinctrl driver\n");
1654                 return PTR_ERR(vg->pctldev);
1655         }
1656
1657         ret = byt_gpio_probe(vg);
1658         if (ret)
1659                 return ret;
1660
1661         platform_set_drvdata(pdev, vg);
1662
1663         return 0;
1664 }
1665
1666 static int byt_gpio_suspend(struct device *dev)
1667 {
1668         struct intel_pinctrl *vg = dev_get_drvdata(dev);
1669         unsigned long flags;
1670         int i;
1671
1672         raw_spin_lock_irqsave(&byt_lock, flags);
1673
1674         for (i = 0; i < vg->soc->npins; i++) {
1675                 void __iomem *reg;
1676                 u32 value;
1677                 unsigned int pin = vg->soc->pins[i].number;
1678
1679                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1680                 if (!reg) {
1681                         dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
1682                         continue;
1683                 }
1684                 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1685                 vg->context.pads[i].conf0 = value;
1686
1687                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1688                 if (!reg) {
1689                         dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
1690                         continue;
1691                 }
1692                 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1693                 vg->context.pads[i].val = value;
1694         }
1695
1696         raw_spin_unlock_irqrestore(&byt_lock, flags);
1697         return 0;
1698 }
1699
1700 static int byt_gpio_resume(struct device *dev)
1701 {
1702         struct intel_pinctrl *vg = dev_get_drvdata(dev);
1703         unsigned long flags;
1704         int i;
1705
1706         raw_spin_lock_irqsave(&byt_lock, flags);
1707
1708         for (i = 0; i < vg->soc->npins; i++) {
1709                 void __iomem *reg;
1710                 u32 value;
1711                 unsigned int pin = vg->soc->pins[i].number;
1712
1713                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1714                 if (!reg) {
1715                         dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
1716                         continue;
1717                 }
1718                 value = readl(reg);
1719                 if ((value & BYT_CONF0_RESTORE_MASK) !=
1720                      vg->context.pads[i].conf0) {
1721                         value &= ~BYT_CONF0_RESTORE_MASK;
1722                         value |= vg->context.pads[i].conf0;
1723                         writel(value, reg);
1724                         dev_info(dev, "restored pin %d CONF0 %#08x", i, value);
1725                 }
1726
1727                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1728                 if (!reg) {
1729                         dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
1730                         continue;
1731                 }
1732                 value = readl(reg);
1733                 if ((value & BYT_VAL_RESTORE_MASK) !=
1734                      vg->context.pads[i].val) {
1735                         u32 v;
1736
1737                         v = value & ~BYT_VAL_RESTORE_MASK;
1738                         v |= vg->context.pads[i].val;
1739                         if (v != value) {
1740                                 writel(v, reg);
1741                                 dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v);
1742                         }
1743                 }
1744         }
1745
1746         raw_spin_unlock_irqrestore(&byt_lock, flags);
1747         return 0;
1748 }
1749
1750 static const struct dev_pm_ops byt_gpio_pm_ops = {
1751         LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1752 };
1753
1754 static struct platform_driver byt_gpio_driver = {
1755         .probe          = byt_pinctrl_probe,
1756         .driver         = {
1757                 .name                   = "byt_gpio",
1758                 .pm                     = pm_sleep_ptr(&byt_gpio_pm_ops),
1759                 .acpi_match_table       = byt_gpio_acpi_match,
1760                 .suppress_bind_attrs    = true,
1761         },
1762 };
1763
1764 static int __init byt_gpio_init(void)
1765 {
1766         return platform_driver_register(&byt_gpio_driver);
1767 }
1768 subsys_initcall(byt_gpio_init);
1769
1770 MODULE_IMPORT_NS(PINCTRL_INTEL);