1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2017 Broadcom
7 * This file contains the Broadcom Iproc GPIO driver that supports 3
8 * GPIO controllers on Iproc including the ASIU GPIO controller, the
9 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
10 * PINCONF such as bias pull up/down, and drive strength are also supported
13 * It provides the functionality where pins from the GPIO can be
14 * individually muxed to GPIO function, if individual pad
15 * configuration is supported, through the interaction with respective
16 * SoCs IOMUX controller.
19 #include <linux/gpio/driver.h>
20 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/kernel.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/slab.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/pinctrl/pinctrl.h>
33 #include "../pinctrl-utils.h"
35 #define IPROC_GPIO_DATA_IN_OFFSET 0x00
36 #define IPROC_GPIO_DATA_OUT_OFFSET 0x04
37 #define IPROC_GPIO_OUT_EN_OFFSET 0x08
38 #define IPROC_GPIO_INT_TYPE_OFFSET 0x0c
39 #define IPROC_GPIO_INT_DE_OFFSET 0x10
40 #define IPROC_GPIO_INT_EDGE_OFFSET 0x14
41 #define IPROC_GPIO_INT_MSK_OFFSET 0x18
42 #define IPROC_GPIO_INT_STAT_OFFSET 0x1c
43 #define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
44 #define IPROC_GPIO_INT_CLR_OFFSET 0x24
45 #define IPROC_GPIO_PAD_RES_OFFSET 0x34
46 #define IPROC_GPIO_RES_EN_OFFSET 0x38
48 /* drive strength control for ASIU GPIO */
49 #define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
51 /* pinconf for CCM GPIO */
52 #define IPROC_GPIO_PULL_DN_OFFSET 0x10
53 #define IPROC_GPIO_PULL_UP_OFFSET 0x14
55 /* pinconf for CRMU(aon) GPIO and CCM GPIO*/
56 #define IPROC_GPIO_DRV_CTRL_OFFSET 0x00
58 #define GPIO_BANK_SIZE 0x200
59 #define NGPIOS_PER_BANK 32
60 #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
62 #define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
63 #define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
65 #define GPIO_DRV_STRENGTH_BIT_SHIFT 20
66 #define GPIO_DRV_STRENGTH_BITS 3
67 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
69 enum iproc_pinconf_param {
70 IPROC_PINCONF_DRIVE_STRENGTH = 0,
71 IPROC_PINCONF_BIAS_DISABLE,
72 IPROC_PINCONF_BIAS_PULL_UP,
73 IPROC_PINCONF_BIAS_PULL_DOWN,
77 enum iproc_pinconf_ctrl_type {
86 * @dev: pointer to device
87 * @base: I/O register base for Iproc GPIO controller
88 * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that
89 * has the PINCONF support implemented outside of the GPIO block
90 * @lock: lock to protect access to I/O registers
92 * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
93 * @pinmux_is_supported: flag to indicate this GPIO controller contains pins
94 * that can be individually muxed to GPIO
95 * @pinconf_disable: contains a list of PINCONF parameters that need to be
97 * @nr_pinconf_disable: total number of PINCONF parameters that need to be
99 * @pctl: pointer to pinctrl_dev
100 * @pctldesc: pinctrl descriptor
106 void __iomem *io_ctrl;
107 enum iproc_pinconf_ctrl_type io_ctrl_type;
111 struct irq_chip irqchip;
115 bool pinmux_is_supported;
117 enum pin_config_param *pinconf_disable;
118 unsigned int nr_pinconf_disable;
120 struct pinctrl_dev *pctl;
121 struct pinctrl_desc pctldesc;
125 * Mapping from PINCONF pins to GPIO pins is 1-to-1
127 static inline unsigned iproc_pin_to_gpio(unsigned pin)
133 * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
134 * Iproc GPIO register
136 * @chip: Iproc GPIO device
137 * @reg: register offset
141 static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg,
142 unsigned gpio, bool set)
144 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
145 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
148 val = readl(chip->base + offset);
153 writel(val, chip->base + offset);
156 static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg,
159 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
160 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
162 return !!(readl(chip->base + offset) & BIT(shift));
165 static void iproc_gpio_irq_handler(struct irq_desc *desc)
167 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
168 struct iproc_gpio *chip = gpiochip_get_data(gc);
169 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
172 chained_irq_enter(irq_chip, desc);
174 /* go through the entire GPIO banks and handle all interrupts */
175 for (i = 0; i < chip->num_banks; i++) {
176 unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
177 IPROC_GPIO_INT_MSTAT_OFFSET);
179 for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
180 unsigned pin = NGPIOS_PER_BANK * i + bit;
183 * Clear the interrupt before invoking the
184 * handler, so we do not leave any window
186 writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
187 IPROC_GPIO_INT_CLR_OFFSET);
189 generic_handle_domain_irq(gc->irq.domain, pin);
193 chained_irq_exit(irq_chip, desc);
197 static void iproc_gpio_irq_ack(struct irq_data *d)
199 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
200 struct iproc_gpio *chip = gpiochip_get_data(gc);
201 unsigned gpio = d->hwirq;
202 unsigned int offset = IPROC_GPIO_REG(gpio,
203 IPROC_GPIO_INT_CLR_OFFSET);
204 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
205 u32 val = BIT(shift);
207 writel(val, chip->base + offset);
211 * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt
214 * @unmask: mask/unmask GPIO interrupt
216 static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask)
218 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
219 struct iproc_gpio *chip = gpiochip_get_data(gc);
220 unsigned gpio = d->hwirq;
222 iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask);
225 static void iproc_gpio_irq_mask(struct irq_data *d)
227 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
228 struct iproc_gpio *chip = gpiochip_get_data(gc);
231 raw_spin_lock_irqsave(&chip->lock, flags);
232 iproc_gpio_irq_set_mask(d, false);
233 raw_spin_unlock_irqrestore(&chip->lock, flags);
236 static void iproc_gpio_irq_unmask(struct irq_data *d)
238 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
239 struct iproc_gpio *chip = gpiochip_get_data(gc);
242 raw_spin_lock_irqsave(&chip->lock, flags);
243 iproc_gpio_irq_set_mask(d, true);
244 raw_spin_unlock_irqrestore(&chip->lock, flags);
247 static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
249 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
250 struct iproc_gpio *chip = gpiochip_get_data(gc);
251 unsigned gpio = d->hwirq;
252 bool level_triggered = false;
253 bool dual_edge = false;
254 bool rising_or_high = false;
257 switch (type & IRQ_TYPE_SENSE_MASK) {
258 case IRQ_TYPE_EDGE_RISING:
259 rising_or_high = true;
262 case IRQ_TYPE_EDGE_FALLING:
265 case IRQ_TYPE_EDGE_BOTH:
269 case IRQ_TYPE_LEVEL_HIGH:
270 level_triggered = true;
271 rising_or_high = true;
274 case IRQ_TYPE_LEVEL_LOW:
275 level_triggered = true;
279 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
284 raw_spin_lock_irqsave(&chip->lock, flags);
285 iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
287 iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
288 iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
291 if (type & IRQ_TYPE_EDGE_BOTH)
292 irq_set_handler_locked(d, handle_edge_irq);
294 irq_set_handler_locked(d, handle_level_irq);
296 raw_spin_unlock_irqrestore(&chip->lock, flags);
299 "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
300 gpio, level_triggered, dual_edge, rising_or_high);
306 * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
308 static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
310 struct iproc_gpio *chip = gpiochip_get_data(gc);
311 unsigned gpio = gc->base + offset;
313 /* not all Iproc GPIO pins can be muxed individually */
314 if (!chip->pinmux_is_supported)
317 return pinctrl_gpio_request(gpio);
320 static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
322 struct iproc_gpio *chip = gpiochip_get_data(gc);
323 unsigned gpio = gc->base + offset;
325 if (!chip->pinmux_is_supported)
328 pinctrl_gpio_free(gpio);
331 static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
333 struct iproc_gpio *chip = gpiochip_get_data(gc);
336 raw_spin_lock_irqsave(&chip->lock, flags);
337 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
338 raw_spin_unlock_irqrestore(&chip->lock, flags);
340 dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
345 static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
348 struct iproc_gpio *chip = gpiochip_get_data(gc);
351 raw_spin_lock_irqsave(&chip->lock, flags);
352 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
353 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
354 raw_spin_unlock_irqrestore(&chip->lock, flags);
356 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
361 static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
363 struct iproc_gpio *chip = gpiochip_get_data(gc);
364 unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET);
365 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
367 if (readl(chip->base + offset) & BIT(shift))
368 return GPIO_LINE_DIRECTION_OUT;
370 return GPIO_LINE_DIRECTION_IN;
373 static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
375 struct iproc_gpio *chip = gpiochip_get_data(gc);
378 raw_spin_lock_irqsave(&chip->lock, flags);
379 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
380 raw_spin_unlock_irqrestore(&chip->lock, flags);
382 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
385 static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
387 struct iproc_gpio *chip = gpiochip_get_data(gc);
388 unsigned int offset = IPROC_GPIO_REG(gpio,
389 IPROC_GPIO_DATA_IN_OFFSET);
390 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
392 return !!(readl(chip->base + offset) & BIT(shift));
396 * Mapping of the iProc PINCONF parameters to the generic pin configuration
399 static const enum pin_config_param iproc_pinconf_disable_map[] = {
400 [IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH,
401 [IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE,
402 [IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP,
403 [IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN,
406 static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip,
407 enum pin_config_param param)
411 if (!chip->nr_pinconf_disable)
414 for (i = 0; i < chip->nr_pinconf_disable; i++)
415 if (chip->pinconf_disable[i] == param)
421 static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip,
422 unsigned long disable_mask)
424 unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map);
425 unsigned int bit, nbits = 0;
427 /* figure out total number of PINCONF parameters to disable */
428 for_each_set_bit(bit, &disable_mask, map_size)
435 * Allocate an array to store PINCONF parameters that need to be
438 chip->pinconf_disable = devm_kcalloc(chip->dev, nbits,
439 sizeof(*chip->pinconf_disable),
441 if (!chip->pinconf_disable)
444 chip->nr_pinconf_disable = nbits;
446 /* now store these parameters */
448 for_each_set_bit(bit, &disable_mask, map_size)
449 chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit];
454 static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
460 * Only one group: "gpio_grp", since this local pinctrl device only performs
461 * GPIO specific PINCONF configurations
463 static const char *iproc_get_group_name(struct pinctrl_dev *pctldev,
469 static const struct pinctrl_ops iproc_pctrl_ops = {
470 .get_groups_count = iproc_get_groups_count,
471 .get_group_name = iproc_get_group_name,
472 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
473 .dt_free_map = pinctrl_utils_free_map,
476 static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
477 bool disable, bool pull_up)
484 raw_spin_lock_irqsave(&chip->lock, flags);
485 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
486 base = chip->io_ctrl;
487 shift = IPROC_GPIO_SHIFT(gpio);
489 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET);
490 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET);
492 /* no pull-up or pull-down */
493 val_1 &= ~BIT(shift);
494 val_2 &= ~BIT(shift);
495 } else if (pull_up) {
497 val_2 &= ~BIT(shift);
499 val_1 &= ~BIT(shift);
502 writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
503 writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
506 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
509 iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
511 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
516 raw_spin_unlock_irqrestore(&chip->lock, flags);
517 dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
522 static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
523 bool *disable, bool *pull_up)
530 raw_spin_lock_irqsave(&chip->lock, flags);
531 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
532 base = chip->io_ctrl;
533 shift = IPROC_GPIO_SHIFT(gpio);
535 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift);
536 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift);
538 *pull_up = val_1 ? true : false;
539 *disable = (val_1 | val_2) ? false : true;
542 *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
543 *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
545 raw_spin_unlock_irqrestore(&chip->lock, flags);
548 #define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \
549 ((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
550 ((type) == IOCTRL_TYPE_CDRU) ? \
551 ((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
552 ((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
554 static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
558 unsigned int i, offset, shift;
562 /* make sure drive strength is supported */
563 if (strength < 2 || strength > 16 || (strength % 2))
567 base = chip->io_ctrl;
572 shift = IPROC_GPIO_SHIFT(gpio);
574 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
577 raw_spin_lock_irqsave(&chip->lock, flags);
578 strength = (strength / 2) - 1;
579 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
580 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
581 val = readl(base + offset);
583 val |= ((strength >> i) & 0x1) << shift;
584 writel(val, base + offset);
586 raw_spin_unlock_irqrestore(&chip->lock, flags);
591 static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
595 unsigned int i, offset, shift;
600 base = chip->io_ctrl;
605 shift = IPROC_GPIO_SHIFT(gpio);
607 raw_spin_lock_irqsave(&chip->lock, flags);
609 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
610 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
611 val = readl(base + offset) & BIT(shift);
613 *strength += (val << i);
617 *strength = (*strength + 1) * 2;
618 raw_spin_unlock_irqrestore(&chip->lock, flags);
623 static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
624 unsigned long *config)
626 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
627 enum pin_config_param param = pinconf_to_config_param(*config);
628 unsigned gpio = iproc_pin_to_gpio(pin);
630 bool disable, pull_up;
633 if (iproc_pinconf_param_is_disabled(chip, param))
637 case PIN_CONFIG_BIAS_DISABLE:
638 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
644 case PIN_CONFIG_BIAS_PULL_UP:
645 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
646 if (!disable && pull_up)
651 case PIN_CONFIG_BIAS_PULL_DOWN:
652 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
653 if (!disable && !pull_up)
658 case PIN_CONFIG_DRIVE_STRENGTH:
659 ret = iproc_gpio_get_strength(chip, gpio, &arg);
662 *config = pinconf_to_config_packed(param, arg);
673 static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
674 unsigned long *configs, unsigned num_configs)
676 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
677 enum pin_config_param param;
679 unsigned i, gpio = iproc_pin_to_gpio(pin);
682 for (i = 0; i < num_configs; i++) {
683 param = pinconf_to_config_param(configs[i]);
685 if (iproc_pinconf_param_is_disabled(chip, param))
688 arg = pinconf_to_config_argument(configs[i]);
691 case PIN_CONFIG_BIAS_DISABLE:
692 ret = iproc_gpio_set_pull(chip, gpio, true, false);
697 case PIN_CONFIG_BIAS_PULL_UP:
698 ret = iproc_gpio_set_pull(chip, gpio, false, true);
703 case PIN_CONFIG_BIAS_PULL_DOWN:
704 ret = iproc_gpio_set_pull(chip, gpio, false, false);
709 case PIN_CONFIG_DRIVE_STRENGTH:
710 ret = iproc_gpio_set_strength(chip, gpio, arg);
716 dev_err(chip->dev, "invalid configuration\n");
719 } /* for each config */
725 static const struct pinconf_ops iproc_pconf_ops = {
727 .pin_config_get = iproc_pin_config_get,
728 .pin_config_set = iproc_pin_config_set,
732 * Iproc GPIO controller supports some PINCONF related configurations such as
733 * pull up, pull down, and drive strength, when the pin is configured to GPIO
735 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
738 static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
740 struct pinctrl_desc *pctldesc = &chip->pctldesc;
741 struct pinctrl_pin_desc *pins;
742 struct gpio_chip *gc = &chip->gc;
745 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
749 for (i = 0; i < gc->ngpio; i++) {
751 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
757 pctldesc->name = dev_name(chip->dev);
758 pctldesc->pctlops = &iproc_pctrl_ops;
759 pctldesc->pins = pins;
760 pctldesc->npins = gc->ngpio;
761 pctldesc->confops = &iproc_pconf_ops;
763 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
764 if (IS_ERR(chip->pctl)) {
765 dev_err(chip->dev, "unable to register pinctrl device\n");
766 return PTR_ERR(chip->pctl);
772 static const struct of_device_id iproc_gpio_of_match[] = {
773 { .compatible = "brcm,iproc-gpio" },
774 { .compatible = "brcm,cygnus-ccm-gpio" },
775 { .compatible = "brcm,cygnus-asiu-gpio" },
776 { .compatible = "brcm,cygnus-crmu-gpio" },
777 { .compatible = "brcm,iproc-nsp-gpio" },
778 { .compatible = "brcm,iproc-stingray-gpio" },
782 static int iproc_gpio_probe(struct platform_device *pdev)
784 struct device *dev = &pdev->dev;
785 struct resource *res;
786 struct iproc_gpio *chip;
787 struct gpio_chip *gc;
788 u32 ngpios, pinconf_disable_mask = 0;
790 bool no_pinconf = false;
791 enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID;
793 /* NSP does not support drive strength config */
794 if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
795 pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH);
796 /* Stingray does not support pinconf in this controller */
797 else if (of_device_is_compatible(dev->of_node,
798 "brcm,iproc-stingray-gpio"))
801 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
806 platform_set_drvdata(pdev, chip);
808 chip->base = devm_platform_ioremap_resource(pdev, 0);
809 if (IS_ERR(chip->base)) {
810 dev_err(dev, "unable to map I/O memory\n");
811 return PTR_ERR(chip->base);
814 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
816 chip->io_ctrl = devm_ioremap_resource(dev, res);
817 if (IS_ERR(chip->io_ctrl))
818 return PTR_ERR(chip->io_ctrl);
819 if (of_device_is_compatible(dev->of_node,
820 "brcm,cygnus-ccm-gpio"))
821 io_ctrl_type = IOCTRL_TYPE_CDRU;
823 io_ctrl_type = IOCTRL_TYPE_AON;
826 chip->io_ctrl_type = io_ctrl_type;
828 if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
829 dev_err(&pdev->dev, "missing ngpios DT property\n");
833 raw_spin_lock_init(&chip->lock);
838 chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
839 gc->label = dev_name(dev);
841 gc->request = iproc_gpio_request;
842 gc->free = iproc_gpio_free;
843 gc->direction_input = iproc_gpio_direction_input;
844 gc->direction_output = iproc_gpio_direction_output;
845 gc->get_direction = iproc_gpio_get_direction;
846 gc->set = iproc_gpio_set;
847 gc->get = iproc_gpio_get;
849 chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
852 /* optional GPIO interrupt support */
853 irq = platform_get_irq_optional(pdev, 0);
855 struct irq_chip *irqc;
856 struct gpio_irq_chip *girq;
858 irqc = &chip->irqchip;
859 irqc->name = dev_name(dev);
860 irqc->irq_ack = iproc_gpio_irq_ack;
861 irqc->irq_mask = iproc_gpio_irq_mask;
862 irqc->irq_unmask = iproc_gpio_irq_unmask;
863 irqc->irq_set_type = iproc_gpio_irq_set_type;
864 irqc->irq_enable = iproc_gpio_irq_unmask;
865 irqc->irq_disable = iproc_gpio_irq_mask;
869 girq->parent_handler = iproc_gpio_irq_handler;
870 girq->num_parents = 1;
871 girq->parents = devm_kcalloc(dev, 1,
872 sizeof(*girq->parents),
876 girq->parents[0] = irq;
877 girq->default_type = IRQ_TYPE_NONE;
878 girq->handler = handle_bad_irq;
881 ret = gpiochip_add_data(gc, chip);
883 dev_err(dev, "unable to add GPIO chip\n");
888 ret = iproc_gpio_register_pinconf(chip);
890 dev_err(dev, "unable to register pinconf\n");
891 goto err_rm_gpiochip;
894 if (pinconf_disable_mask) {
895 ret = iproc_pinconf_disable_map_create(chip,
896 pinconf_disable_mask);
899 "unable to create pinconf disable map\n");
900 goto err_rm_gpiochip;
913 static struct platform_driver iproc_gpio_driver = {
915 .name = "iproc-gpio",
916 .of_match_table = iproc_gpio_of_match,
918 .probe = iproc_gpio_probe,
921 static int __init iproc_gpio_init(void)
923 return platform_driver_register(&iproc_gpio_driver);
925 arch_initcall_sync(iproc_gpio_init);