1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2017 Broadcom
7 * This file contains the Broadcom Iproc GPIO driver that supports 3
8 * GPIO controllers on Iproc including the ASIU GPIO controller, the
9 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
10 * PINCONF such as bias pull up/down, and drive strength are also supported
13 * It provides the functionality where pins from the GPIO can be
14 * individually muxed to GPIO function, if individual pad
15 * configuration is supported, through the interaction with respective
16 * SoCs IOMUX controller.
19 #include <linux/gpio/driver.h>
20 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/kernel.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/seq_file.h>
27 #include <linux/slab.h>
29 #include <linux/pinctrl/consumer.h>
30 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/pinctrl/pinconf.h>
32 #include <linux/pinctrl/pinctrl.h>
34 #include "../pinctrl-utils.h"
36 #define IPROC_GPIO_DATA_IN_OFFSET 0x00
37 #define IPROC_GPIO_DATA_OUT_OFFSET 0x04
38 #define IPROC_GPIO_OUT_EN_OFFSET 0x08
39 #define IPROC_GPIO_INT_TYPE_OFFSET 0x0c
40 #define IPROC_GPIO_INT_DE_OFFSET 0x10
41 #define IPROC_GPIO_INT_EDGE_OFFSET 0x14
42 #define IPROC_GPIO_INT_MSK_OFFSET 0x18
43 #define IPROC_GPIO_INT_STAT_OFFSET 0x1c
44 #define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
45 #define IPROC_GPIO_INT_CLR_OFFSET 0x24
46 #define IPROC_GPIO_PAD_RES_OFFSET 0x34
47 #define IPROC_GPIO_RES_EN_OFFSET 0x38
49 /* drive strength control for ASIU GPIO */
50 #define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
52 /* pinconf for CCM GPIO */
53 #define IPROC_GPIO_PULL_DN_OFFSET 0x10
54 #define IPROC_GPIO_PULL_UP_OFFSET 0x14
56 /* pinconf for CRMU(aon) GPIO and CCM GPIO*/
57 #define IPROC_GPIO_DRV_CTRL_OFFSET 0x00
59 #define GPIO_BANK_SIZE 0x200
60 #define NGPIOS_PER_BANK 32
61 #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
63 #define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
64 #define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
66 #define GPIO_DRV_STRENGTH_BIT_SHIFT 20
67 #define GPIO_DRV_STRENGTH_BITS 3
68 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
70 enum iproc_pinconf_param {
71 IPROC_PINCONF_DRIVE_STRENGTH = 0,
72 IPROC_PINCONF_BIAS_DISABLE,
73 IPROC_PINCONF_BIAS_PULL_UP,
74 IPROC_PINCONF_BIAS_PULL_DOWN,
78 enum iproc_pinconf_ctrl_type {
87 * @dev: pointer to device
88 * @base: I/O register base for Iproc GPIO controller
89 * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that
90 * has the PINCONF support implemented outside of the GPIO block
91 * @lock: lock to protect access to I/O registers
93 * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
94 * @pinmux_is_supported: flag to indicate this GPIO controller contains pins
95 * that can be individually muxed to GPIO
96 * @pinconf_disable: contains a list of PINCONF parameters that need to be
98 * @nr_pinconf_disable: total number of PINCONF parameters that need to be
100 * @pctl: pointer to pinctrl_dev
101 * @pctldesc: pinctrl descriptor
107 void __iomem *io_ctrl;
108 enum iproc_pinconf_ctrl_type io_ctrl_type;
115 bool pinmux_is_supported;
117 enum pin_config_param *pinconf_disable;
118 unsigned int nr_pinconf_disable;
120 struct pinctrl_dev *pctl;
121 struct pinctrl_desc pctldesc;
125 * Mapping from PINCONF pins to GPIO pins is 1-to-1
127 static inline unsigned iproc_pin_to_gpio(unsigned pin)
133 * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
134 * Iproc GPIO register
136 * @chip: Iproc GPIO device
137 * @reg: register offset
141 static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg,
142 unsigned gpio, bool set)
144 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
145 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
148 val = readl(chip->base + offset);
153 writel(val, chip->base + offset);
156 static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg,
159 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
160 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
162 return !!(readl(chip->base + offset) & BIT(shift));
165 static void iproc_gpio_irq_handler(struct irq_desc *desc)
167 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
168 struct iproc_gpio *chip = gpiochip_get_data(gc);
169 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
172 chained_irq_enter(irq_chip, desc);
174 /* go through the entire GPIO banks and handle all interrupts */
175 for (i = 0; i < chip->num_banks; i++) {
176 unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
177 IPROC_GPIO_INT_MSTAT_OFFSET);
179 for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
180 unsigned pin = NGPIOS_PER_BANK * i + bit;
183 * Clear the interrupt before invoking the
184 * handler, so we do not leave any window
186 writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
187 IPROC_GPIO_INT_CLR_OFFSET);
189 generic_handle_domain_irq(gc->irq.domain, pin);
193 chained_irq_exit(irq_chip, desc);
197 static void iproc_gpio_irq_ack(struct irq_data *d)
199 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
200 struct iproc_gpio *chip = gpiochip_get_data(gc);
201 unsigned gpio = d->hwirq;
202 unsigned int offset = IPROC_GPIO_REG(gpio,
203 IPROC_GPIO_INT_CLR_OFFSET);
204 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
205 u32 val = BIT(shift);
207 writel(val, chip->base + offset);
211 * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt
214 * @unmask: mask/unmask GPIO interrupt
216 static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask)
218 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
219 struct iproc_gpio *chip = gpiochip_get_data(gc);
220 unsigned gpio = irqd_to_hwirq(d);
222 iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask);
225 static void iproc_gpio_irq_mask(struct irq_data *d)
227 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
228 struct iproc_gpio *chip = gpiochip_get_data(gc);
231 raw_spin_lock_irqsave(&chip->lock, flags);
232 iproc_gpio_irq_set_mask(d, false);
233 raw_spin_unlock_irqrestore(&chip->lock, flags);
234 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
237 static void iproc_gpio_irq_unmask(struct irq_data *d)
239 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
240 struct iproc_gpio *chip = gpiochip_get_data(gc);
243 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
244 raw_spin_lock_irqsave(&chip->lock, flags);
245 iproc_gpio_irq_set_mask(d, true);
246 raw_spin_unlock_irqrestore(&chip->lock, flags);
249 static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
251 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
252 struct iproc_gpio *chip = gpiochip_get_data(gc);
253 unsigned gpio = d->hwirq;
254 bool level_triggered = false;
255 bool dual_edge = false;
256 bool rising_or_high = false;
259 switch (type & IRQ_TYPE_SENSE_MASK) {
260 case IRQ_TYPE_EDGE_RISING:
261 rising_or_high = true;
264 case IRQ_TYPE_EDGE_FALLING:
267 case IRQ_TYPE_EDGE_BOTH:
271 case IRQ_TYPE_LEVEL_HIGH:
272 level_triggered = true;
273 rising_or_high = true;
276 case IRQ_TYPE_LEVEL_LOW:
277 level_triggered = true;
281 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
286 raw_spin_lock_irqsave(&chip->lock, flags);
287 iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
289 iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
290 iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
293 if (type & IRQ_TYPE_EDGE_BOTH)
294 irq_set_handler_locked(d, handle_edge_irq);
296 irq_set_handler_locked(d, handle_level_irq);
298 raw_spin_unlock_irqrestore(&chip->lock, flags);
301 "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
302 gpio, level_triggered, dual_edge, rising_or_high);
307 static void iproc_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
309 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
310 struct iproc_gpio *chip = gpiochip_get_data(gc);
312 seq_printf(p, dev_name(chip->dev));
315 static const struct irq_chip iproc_gpio_irq_chip = {
316 .irq_ack = iproc_gpio_irq_ack,
317 .irq_mask = iproc_gpio_irq_mask,
318 .irq_unmask = iproc_gpio_irq_unmask,
319 .irq_set_type = iproc_gpio_irq_set_type,
320 .irq_enable = iproc_gpio_irq_unmask,
321 .irq_disable = iproc_gpio_irq_mask,
322 .irq_print_chip = iproc_gpio_irq_print_chip,
323 .flags = IRQCHIP_IMMUTABLE,
324 GPIOCHIP_IRQ_RESOURCE_HELPERS,
328 * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
330 static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
332 struct iproc_gpio *chip = gpiochip_get_data(gc);
333 unsigned gpio = gc->base + offset;
335 /* not all Iproc GPIO pins can be muxed individually */
336 if (!chip->pinmux_is_supported)
339 return pinctrl_gpio_request(gpio);
342 static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
344 struct iproc_gpio *chip = gpiochip_get_data(gc);
345 unsigned gpio = gc->base + offset;
347 if (!chip->pinmux_is_supported)
350 pinctrl_gpio_free(gpio);
353 static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
355 struct iproc_gpio *chip = gpiochip_get_data(gc);
358 raw_spin_lock_irqsave(&chip->lock, flags);
359 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
360 raw_spin_unlock_irqrestore(&chip->lock, flags);
362 dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
367 static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
370 struct iproc_gpio *chip = gpiochip_get_data(gc);
373 raw_spin_lock_irqsave(&chip->lock, flags);
374 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
375 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
376 raw_spin_unlock_irqrestore(&chip->lock, flags);
378 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
383 static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
385 struct iproc_gpio *chip = gpiochip_get_data(gc);
386 unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET);
387 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
389 if (readl(chip->base + offset) & BIT(shift))
390 return GPIO_LINE_DIRECTION_OUT;
392 return GPIO_LINE_DIRECTION_IN;
395 static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
397 struct iproc_gpio *chip = gpiochip_get_data(gc);
400 raw_spin_lock_irqsave(&chip->lock, flags);
401 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
402 raw_spin_unlock_irqrestore(&chip->lock, flags);
404 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
407 static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
409 struct iproc_gpio *chip = gpiochip_get_data(gc);
410 unsigned int offset = IPROC_GPIO_REG(gpio,
411 IPROC_GPIO_DATA_IN_OFFSET);
412 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
414 return !!(readl(chip->base + offset) & BIT(shift));
418 * Mapping of the iProc PINCONF parameters to the generic pin configuration
421 static const enum pin_config_param iproc_pinconf_disable_map[] = {
422 [IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH,
423 [IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE,
424 [IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP,
425 [IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN,
428 static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip,
429 enum pin_config_param param)
433 if (!chip->nr_pinconf_disable)
436 for (i = 0; i < chip->nr_pinconf_disable; i++)
437 if (chip->pinconf_disable[i] == param)
443 static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip,
444 unsigned long disable_mask)
446 unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map);
447 unsigned int bit, nbits = 0;
449 /* figure out total number of PINCONF parameters to disable */
450 for_each_set_bit(bit, &disable_mask, map_size)
457 * Allocate an array to store PINCONF parameters that need to be
460 chip->pinconf_disable = devm_kcalloc(chip->dev, nbits,
461 sizeof(*chip->pinconf_disable),
463 if (!chip->pinconf_disable)
466 chip->nr_pinconf_disable = nbits;
468 /* now store these parameters */
470 for_each_set_bit(bit, &disable_mask, map_size)
471 chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit];
476 static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
482 * Only one group: "gpio_grp", since this local pinctrl device only performs
483 * GPIO specific PINCONF configurations
485 static const char *iproc_get_group_name(struct pinctrl_dev *pctldev,
491 static const struct pinctrl_ops iproc_pctrl_ops = {
492 .get_groups_count = iproc_get_groups_count,
493 .get_group_name = iproc_get_group_name,
494 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
495 .dt_free_map = pinctrl_utils_free_map,
498 static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
499 bool disable, bool pull_up)
506 raw_spin_lock_irqsave(&chip->lock, flags);
507 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
508 base = chip->io_ctrl;
509 shift = IPROC_GPIO_SHIFT(gpio);
511 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET);
512 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET);
514 /* no pull-up or pull-down */
515 val_1 &= ~BIT(shift);
516 val_2 &= ~BIT(shift);
517 } else if (pull_up) {
519 val_2 &= ~BIT(shift);
521 val_1 &= ~BIT(shift);
524 writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
525 writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
528 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
531 iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
533 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
538 raw_spin_unlock_irqrestore(&chip->lock, flags);
539 dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
544 static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
545 bool *disable, bool *pull_up)
552 raw_spin_lock_irqsave(&chip->lock, flags);
553 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
554 base = chip->io_ctrl;
555 shift = IPROC_GPIO_SHIFT(gpio);
557 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift);
558 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift);
560 *pull_up = val_1 ? true : false;
561 *disable = (val_1 | val_2) ? false : true;
564 *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
565 *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
567 raw_spin_unlock_irqrestore(&chip->lock, flags);
570 #define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \
571 ((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
572 ((type) == IOCTRL_TYPE_CDRU) ? \
573 ((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
574 ((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
576 static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
580 unsigned int i, offset, shift;
584 /* make sure drive strength is supported */
585 if (strength < 2 || strength > 16 || (strength % 2))
589 base = chip->io_ctrl;
594 shift = IPROC_GPIO_SHIFT(gpio);
596 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
599 raw_spin_lock_irqsave(&chip->lock, flags);
600 strength = (strength / 2) - 1;
601 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
602 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
603 val = readl(base + offset);
605 val |= ((strength >> i) & 0x1) << shift;
606 writel(val, base + offset);
608 raw_spin_unlock_irqrestore(&chip->lock, flags);
613 static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
617 unsigned int i, offset, shift;
622 base = chip->io_ctrl;
627 shift = IPROC_GPIO_SHIFT(gpio);
629 raw_spin_lock_irqsave(&chip->lock, flags);
631 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
632 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
633 val = readl(base + offset) & BIT(shift);
635 *strength += (val << i);
639 *strength = (*strength + 1) * 2;
640 raw_spin_unlock_irqrestore(&chip->lock, flags);
645 static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
646 unsigned long *config)
648 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
649 enum pin_config_param param = pinconf_to_config_param(*config);
650 unsigned gpio = iproc_pin_to_gpio(pin);
652 bool disable, pull_up;
655 if (iproc_pinconf_param_is_disabled(chip, param))
659 case PIN_CONFIG_BIAS_DISABLE:
660 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
666 case PIN_CONFIG_BIAS_PULL_UP:
667 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
668 if (!disable && pull_up)
673 case PIN_CONFIG_BIAS_PULL_DOWN:
674 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
675 if (!disable && !pull_up)
680 case PIN_CONFIG_DRIVE_STRENGTH:
681 ret = iproc_gpio_get_strength(chip, gpio, &arg);
684 *config = pinconf_to_config_packed(param, arg);
695 static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
696 unsigned long *configs, unsigned num_configs)
698 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
699 enum pin_config_param param;
701 unsigned i, gpio = iproc_pin_to_gpio(pin);
704 for (i = 0; i < num_configs; i++) {
705 param = pinconf_to_config_param(configs[i]);
707 if (iproc_pinconf_param_is_disabled(chip, param))
710 arg = pinconf_to_config_argument(configs[i]);
713 case PIN_CONFIG_BIAS_DISABLE:
714 ret = iproc_gpio_set_pull(chip, gpio, true, false);
719 case PIN_CONFIG_BIAS_PULL_UP:
720 ret = iproc_gpio_set_pull(chip, gpio, false, true);
725 case PIN_CONFIG_BIAS_PULL_DOWN:
726 ret = iproc_gpio_set_pull(chip, gpio, false, false);
731 case PIN_CONFIG_DRIVE_STRENGTH:
732 ret = iproc_gpio_set_strength(chip, gpio, arg);
738 dev_err(chip->dev, "invalid configuration\n");
741 } /* for each config */
747 static const struct pinconf_ops iproc_pconf_ops = {
749 .pin_config_get = iproc_pin_config_get,
750 .pin_config_set = iproc_pin_config_set,
754 * Iproc GPIO controller supports some PINCONF related configurations such as
755 * pull up, pull down, and drive strength, when the pin is configured to GPIO
757 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
760 static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
762 struct pinctrl_desc *pctldesc = &chip->pctldesc;
763 struct pinctrl_pin_desc *pins;
764 struct gpio_chip *gc = &chip->gc;
767 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
771 for (i = 0; i < gc->ngpio; i++) {
773 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
779 pctldesc->name = dev_name(chip->dev);
780 pctldesc->pctlops = &iproc_pctrl_ops;
781 pctldesc->pins = pins;
782 pctldesc->npins = gc->ngpio;
783 pctldesc->confops = &iproc_pconf_ops;
785 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
786 if (IS_ERR(chip->pctl)) {
787 dev_err(chip->dev, "unable to register pinctrl device\n");
788 return PTR_ERR(chip->pctl);
794 static const struct of_device_id iproc_gpio_of_match[] = {
795 { .compatible = "brcm,iproc-gpio" },
796 { .compatible = "brcm,cygnus-ccm-gpio" },
797 { .compatible = "brcm,cygnus-asiu-gpio" },
798 { .compatible = "brcm,cygnus-crmu-gpio" },
799 { .compatible = "brcm,iproc-nsp-gpio" },
800 { .compatible = "brcm,iproc-stingray-gpio" },
804 static int iproc_gpio_probe(struct platform_device *pdev)
806 struct device *dev = &pdev->dev;
807 struct resource *res;
808 struct iproc_gpio *chip;
809 struct gpio_chip *gc;
810 u32 ngpios, pinconf_disable_mask = 0;
812 bool no_pinconf = false;
813 enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID;
815 /* NSP does not support drive strength config */
816 if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
817 pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH);
818 /* Stingray does not support pinconf in this controller */
819 else if (of_device_is_compatible(dev->of_node,
820 "brcm,iproc-stingray-gpio"))
823 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
828 platform_set_drvdata(pdev, chip);
830 chip->base = devm_platform_ioremap_resource(pdev, 0);
831 if (IS_ERR(chip->base)) {
832 dev_err(dev, "unable to map I/O memory\n");
833 return PTR_ERR(chip->base);
836 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
838 chip->io_ctrl = devm_ioremap_resource(dev, res);
839 if (IS_ERR(chip->io_ctrl))
840 return PTR_ERR(chip->io_ctrl);
841 if (of_device_is_compatible(dev->of_node,
842 "brcm,cygnus-ccm-gpio"))
843 io_ctrl_type = IOCTRL_TYPE_CDRU;
845 io_ctrl_type = IOCTRL_TYPE_AON;
848 chip->io_ctrl_type = io_ctrl_type;
850 if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
851 dev_err(&pdev->dev, "missing ngpios DT property\n");
855 raw_spin_lock_init(&chip->lock);
860 chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
861 gc->label = dev_name(dev);
863 gc->request = iproc_gpio_request;
864 gc->free = iproc_gpio_free;
865 gc->direction_input = iproc_gpio_direction_input;
866 gc->direction_output = iproc_gpio_direction_output;
867 gc->get_direction = iproc_gpio_get_direction;
868 gc->set = iproc_gpio_set;
869 gc->get = iproc_gpio_get;
871 chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
874 /* optional GPIO interrupt support */
875 irq = platform_get_irq_optional(pdev, 0);
877 struct gpio_irq_chip *girq;
880 gpio_irq_chip_set_chip(girq, &iproc_gpio_irq_chip);
881 girq->parent_handler = iproc_gpio_irq_handler;
882 girq->num_parents = 1;
883 girq->parents = devm_kcalloc(dev, 1,
884 sizeof(*girq->parents),
888 girq->parents[0] = irq;
889 girq->default_type = IRQ_TYPE_NONE;
890 girq->handler = handle_bad_irq;
893 ret = gpiochip_add_data(gc, chip);
895 dev_err(dev, "unable to add GPIO chip\n");
900 ret = iproc_gpio_register_pinconf(chip);
902 dev_err(dev, "unable to register pinconf\n");
903 goto err_rm_gpiochip;
906 if (pinconf_disable_mask) {
907 ret = iproc_pinconf_disable_map_create(chip,
908 pinconf_disable_mask);
911 "unable to create pinconf disable map\n");
912 goto err_rm_gpiochip;
925 static struct platform_driver iproc_gpio_driver = {
927 .name = "iproc-gpio",
928 .of_match_table = iproc_gpio_of_match,
930 .probe = iproc_gpio_probe,
933 static int __init iproc_gpio_init(void)
935 return platform_driver_register(&iproc_gpio_driver);
937 arch_initcall_sync(iproc_gpio_init);