2 * Copyright (C) 2014-2017 Broadcom
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 * This file contains the Broadcom Iproc GPIO driver that supports 3
16 * GPIO controllers on Iproc including the ASIU GPIO controller, the
17 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
18 * PINCONF such as bias pull up/down, and drive strength are also supported
21 * It provides the functionality where pins from the GPIO can be
22 * individually muxed to GPIO function, if individual pad
23 * configuration is supported, through the interaction with respective
24 * SoCs IOMUX controller.
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
31 #include <linux/gpio/driver.h>
32 #include <linux/ioport.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinconf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
39 #include "../pinctrl-utils.h"
41 #define IPROC_GPIO_DATA_IN_OFFSET 0x00
42 #define IPROC_GPIO_DATA_OUT_OFFSET 0x04
43 #define IPROC_GPIO_OUT_EN_OFFSET 0x08
44 #define IPROC_GPIO_INT_TYPE_OFFSET 0x0c
45 #define IPROC_GPIO_INT_DE_OFFSET 0x10
46 #define IPROC_GPIO_INT_EDGE_OFFSET 0x14
47 #define IPROC_GPIO_INT_MSK_OFFSET 0x18
48 #define IPROC_GPIO_INT_STAT_OFFSET 0x1c
49 #define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
50 #define IPROC_GPIO_INT_CLR_OFFSET 0x24
51 #define IPROC_GPIO_PAD_RES_OFFSET 0x34
52 #define IPROC_GPIO_RES_EN_OFFSET 0x38
54 /* drive strength control for ASIU GPIO */
55 #define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
57 /* pinconf for CCM GPIO */
58 #define IPROC_GPIO_PULL_DN_OFFSET 0x10
59 #define IPROC_GPIO_PULL_UP_OFFSET 0x14
61 /* pinconf for CRMU(aon) GPIO and CCM GPIO*/
62 #define IPROC_GPIO_DRV_CTRL_OFFSET 0x00
64 #define GPIO_BANK_SIZE 0x200
65 #define NGPIOS_PER_BANK 32
66 #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
68 #define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
69 #define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
71 #define GPIO_DRV_STRENGTH_BIT_SHIFT 20
72 #define GPIO_DRV_STRENGTH_BITS 3
73 #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
75 enum iproc_pinconf_param {
76 IPROC_PINCONF_DRIVE_STRENGTH = 0,
77 IPROC_PINCONF_BIAS_DISABLE,
78 IPROC_PINCONF_BIAS_PULL_UP,
79 IPROC_PINCONF_BIAS_PULL_DOWN,
83 enum iproc_pinconf_ctrl_type {
92 * @dev: pointer to device
93 * @base: I/O register base for Iproc GPIO controller
94 * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that
95 * has the PINCONF support implemented outside of the GPIO block
96 * @lock: lock to protect access to I/O registers
98 * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
99 * @pinmux_is_supported: flag to indicate this GPIO controller contains pins
100 * that can be individually muxed to GPIO
101 * @pinconf_disable: contains a list of PINCONF parameters that need to be
103 * @nr_pinconf_disable: total number of PINCONF parameters that need to be
105 * @pctl: pointer to pinctrl_dev
106 * @pctldesc: pinctrl descriptor
112 void __iomem *io_ctrl;
113 enum iproc_pinconf_ctrl_type io_ctrl_type;
117 struct irq_chip irqchip;
121 bool pinmux_is_supported;
123 enum pin_config_param *pinconf_disable;
124 unsigned int nr_pinconf_disable;
126 struct pinctrl_dev *pctl;
127 struct pinctrl_desc pctldesc;
131 * Mapping from PINCONF pins to GPIO pins is 1-to-1
133 static inline unsigned iproc_pin_to_gpio(unsigned pin)
139 * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
140 * Iproc GPIO register
142 * @iproc_gpio: Iproc GPIO device
143 * @reg: register offset
147 static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg,
148 unsigned gpio, bool set)
150 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
151 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
154 val = readl(chip->base + offset);
159 writel(val, chip->base + offset);
162 static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg,
165 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
166 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
168 return !!(readl(chip->base + offset) & BIT(shift));
171 static void iproc_gpio_irq_handler(struct irq_desc *desc)
173 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
174 struct iproc_gpio *chip = gpiochip_get_data(gc);
175 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
178 chained_irq_enter(irq_chip, desc);
180 /* go through the entire GPIO banks and handle all interrupts */
181 for (i = 0; i < chip->num_banks; i++) {
182 unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
183 IPROC_GPIO_INT_MSTAT_OFFSET);
185 for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
186 unsigned pin = NGPIOS_PER_BANK * i + bit;
187 int child_irq = irq_find_mapping(gc->irq.domain, pin);
190 * Clear the interrupt before invoking the
191 * handler, so we do not leave any window
193 writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
194 IPROC_GPIO_INT_CLR_OFFSET);
196 generic_handle_irq(child_irq);
200 chained_irq_exit(irq_chip, desc);
204 static void iproc_gpio_irq_ack(struct irq_data *d)
206 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
207 struct iproc_gpio *chip = gpiochip_get_data(gc);
208 unsigned gpio = d->hwirq;
209 unsigned int offset = IPROC_GPIO_REG(gpio,
210 IPROC_GPIO_INT_CLR_OFFSET);
211 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
212 u32 val = BIT(shift);
214 writel(val, chip->base + offset);
218 * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt
221 * @unmask: mask/unmask GPIO interrupt
223 static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask)
225 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
226 struct iproc_gpio *chip = gpiochip_get_data(gc);
227 unsigned gpio = d->hwirq;
229 iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask);
232 static void iproc_gpio_irq_mask(struct irq_data *d)
234 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
235 struct iproc_gpio *chip = gpiochip_get_data(gc);
238 raw_spin_lock_irqsave(&chip->lock, flags);
239 iproc_gpio_irq_set_mask(d, false);
240 raw_spin_unlock_irqrestore(&chip->lock, flags);
243 static void iproc_gpio_irq_unmask(struct irq_data *d)
245 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
246 struct iproc_gpio *chip = gpiochip_get_data(gc);
249 raw_spin_lock_irqsave(&chip->lock, flags);
250 iproc_gpio_irq_set_mask(d, true);
251 raw_spin_unlock_irqrestore(&chip->lock, flags);
254 static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
256 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
257 struct iproc_gpio *chip = gpiochip_get_data(gc);
258 unsigned gpio = d->hwirq;
259 bool level_triggered = false;
260 bool dual_edge = false;
261 bool rising_or_high = false;
264 switch (type & IRQ_TYPE_SENSE_MASK) {
265 case IRQ_TYPE_EDGE_RISING:
266 rising_or_high = true;
269 case IRQ_TYPE_EDGE_FALLING:
272 case IRQ_TYPE_EDGE_BOTH:
276 case IRQ_TYPE_LEVEL_HIGH:
277 level_triggered = true;
278 rising_or_high = true;
281 case IRQ_TYPE_LEVEL_LOW:
282 level_triggered = true;
286 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
291 raw_spin_lock_irqsave(&chip->lock, flags);
292 iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
294 iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
295 iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
297 raw_spin_unlock_irqrestore(&chip->lock, flags);
300 "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
301 gpio, level_triggered, dual_edge, rising_or_high);
307 * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
309 static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
311 struct iproc_gpio *chip = gpiochip_get_data(gc);
312 unsigned gpio = gc->base + offset;
314 /* not all Iproc GPIO pins can be muxed individually */
315 if (!chip->pinmux_is_supported)
318 return pinctrl_gpio_request(gpio);
321 static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
323 struct iproc_gpio *chip = gpiochip_get_data(gc);
324 unsigned gpio = gc->base + offset;
326 if (!chip->pinmux_is_supported)
329 pinctrl_gpio_free(gpio);
332 static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
334 struct iproc_gpio *chip = gpiochip_get_data(gc);
337 raw_spin_lock_irqsave(&chip->lock, flags);
338 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
339 raw_spin_unlock_irqrestore(&chip->lock, flags);
341 dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
346 static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
349 struct iproc_gpio *chip = gpiochip_get_data(gc);
352 raw_spin_lock_irqsave(&chip->lock, flags);
353 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
354 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
355 raw_spin_unlock_irqrestore(&chip->lock, flags);
357 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
362 static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
364 struct iproc_gpio *chip = gpiochip_get_data(gc);
365 unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET);
366 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
368 return !(readl(chip->base + offset) & BIT(shift));
371 static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
373 struct iproc_gpio *chip = gpiochip_get_data(gc);
376 raw_spin_lock_irqsave(&chip->lock, flags);
377 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
378 raw_spin_unlock_irqrestore(&chip->lock, flags);
380 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
383 static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
385 struct iproc_gpio *chip = gpiochip_get_data(gc);
386 unsigned int offset = IPROC_GPIO_REG(gpio,
387 IPROC_GPIO_DATA_IN_OFFSET);
388 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
390 return !!(readl(chip->base + offset) & BIT(shift));
394 * Mapping of the iProc PINCONF parameters to the generic pin configuration
397 static const enum pin_config_param iproc_pinconf_disable_map[] = {
398 [IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH,
399 [IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE,
400 [IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP,
401 [IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN,
404 static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip,
405 enum pin_config_param param)
409 if (!chip->nr_pinconf_disable)
412 for (i = 0; i < chip->nr_pinconf_disable; i++)
413 if (chip->pinconf_disable[i] == param)
419 static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip,
420 unsigned long disable_mask)
422 unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map);
423 unsigned int bit, nbits = 0;
425 /* figure out total number of PINCONF parameters to disable */
426 for_each_set_bit(bit, &disable_mask, map_size)
433 * Allocate an array to store PINCONF parameters that need to be
436 chip->pinconf_disable = devm_kcalloc(chip->dev, nbits,
437 sizeof(*chip->pinconf_disable),
439 if (!chip->pinconf_disable)
442 chip->nr_pinconf_disable = nbits;
444 /* now store these parameters */
446 for_each_set_bit(bit, &disable_mask, map_size)
447 chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit];
452 static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
458 * Only one group: "gpio_grp", since this local pinctrl device only performs
459 * GPIO specific PINCONF configurations
461 static const char *iproc_get_group_name(struct pinctrl_dev *pctldev,
467 static const struct pinctrl_ops iproc_pctrl_ops = {
468 .get_groups_count = iproc_get_groups_count,
469 .get_group_name = iproc_get_group_name,
470 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
471 .dt_free_map = pinctrl_utils_free_map,
474 static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
475 bool disable, bool pull_up)
482 raw_spin_lock_irqsave(&chip->lock, flags);
483 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
484 base = chip->io_ctrl;
485 shift = IPROC_GPIO_SHIFT(gpio);
487 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET);
488 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET);
490 /* no pull-up or pull-down */
491 val_1 &= ~BIT(shift);
492 val_2 &= ~BIT(shift);
493 } else if (pull_up) {
495 val_2 &= ~BIT(shift);
497 val_1 &= ~BIT(shift);
500 writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
501 writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
504 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
507 iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
509 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
514 raw_spin_unlock_irqrestore(&chip->lock, flags);
515 dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
520 static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
521 bool *disable, bool *pull_up)
528 raw_spin_lock_irqsave(&chip->lock, flags);
529 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
530 base = chip->io_ctrl;
531 shift = IPROC_GPIO_SHIFT(gpio);
533 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift);
534 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift);
536 *pull_up = val_1 ? true : false;
537 *disable = (val_1 | val_2) ? false : true;
540 *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
541 *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
543 raw_spin_unlock_irqrestore(&chip->lock, flags);
546 #define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \
547 ((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
548 ((type) == IOCTRL_TYPE_CDRU) ? \
549 ((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
550 ((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
552 static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
556 unsigned int i, offset, shift;
560 /* make sure drive strength is supported */
561 if (strength < 2 || strength > 16 || (strength % 2))
565 base = chip->io_ctrl;
570 shift = IPROC_GPIO_SHIFT(gpio);
572 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
575 raw_spin_lock_irqsave(&chip->lock, flags);
576 strength = (strength / 2) - 1;
577 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
578 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
579 val = readl(base + offset);
581 val |= ((strength >> i) & 0x1) << shift;
582 writel(val, base + offset);
584 raw_spin_unlock_irqrestore(&chip->lock, flags);
589 static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
593 unsigned int i, offset, shift;
598 base = chip->io_ctrl;
603 shift = IPROC_GPIO_SHIFT(gpio);
605 raw_spin_lock_irqsave(&chip->lock, flags);
607 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
608 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
609 val = readl(base + offset) & BIT(shift);
611 *strength += (val << i);
615 *strength = (*strength + 1) * 2;
616 raw_spin_unlock_irqrestore(&chip->lock, flags);
621 static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
622 unsigned long *config)
624 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
625 enum pin_config_param param = pinconf_to_config_param(*config);
626 unsigned gpio = iproc_pin_to_gpio(pin);
628 bool disable, pull_up;
631 if (iproc_pinconf_param_is_disabled(chip, param))
635 case PIN_CONFIG_BIAS_DISABLE:
636 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
642 case PIN_CONFIG_BIAS_PULL_UP:
643 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
644 if (!disable && pull_up)
649 case PIN_CONFIG_BIAS_PULL_DOWN:
650 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
651 if (!disable && !pull_up)
656 case PIN_CONFIG_DRIVE_STRENGTH:
657 ret = iproc_gpio_get_strength(chip, gpio, &arg);
660 *config = pinconf_to_config_packed(param, arg);
671 static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
672 unsigned long *configs, unsigned num_configs)
674 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
675 enum pin_config_param param;
677 unsigned i, gpio = iproc_pin_to_gpio(pin);
680 for (i = 0; i < num_configs; i++) {
681 param = pinconf_to_config_param(configs[i]);
683 if (iproc_pinconf_param_is_disabled(chip, param))
686 arg = pinconf_to_config_argument(configs[i]);
689 case PIN_CONFIG_BIAS_DISABLE:
690 ret = iproc_gpio_set_pull(chip, gpio, true, false);
695 case PIN_CONFIG_BIAS_PULL_UP:
696 ret = iproc_gpio_set_pull(chip, gpio, false, true);
701 case PIN_CONFIG_BIAS_PULL_DOWN:
702 ret = iproc_gpio_set_pull(chip, gpio, false, false);
707 case PIN_CONFIG_DRIVE_STRENGTH:
708 ret = iproc_gpio_set_strength(chip, gpio, arg);
714 dev_err(chip->dev, "invalid configuration\n");
717 } /* for each config */
723 static const struct pinconf_ops iproc_pconf_ops = {
725 .pin_config_get = iproc_pin_config_get,
726 .pin_config_set = iproc_pin_config_set,
730 * Iproc GPIO controller supports some PINCONF related configurations such as
731 * pull up, pull down, and drive strength, when the pin is configured to GPIO
733 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
736 static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
738 struct pinctrl_desc *pctldesc = &chip->pctldesc;
739 struct pinctrl_pin_desc *pins;
740 struct gpio_chip *gc = &chip->gc;
743 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
747 for (i = 0; i < gc->ngpio; i++) {
749 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
755 pctldesc->name = dev_name(chip->dev);
756 pctldesc->pctlops = &iproc_pctrl_ops;
757 pctldesc->pins = pins;
758 pctldesc->npins = gc->ngpio;
759 pctldesc->confops = &iproc_pconf_ops;
761 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
762 if (IS_ERR(chip->pctl)) {
763 dev_err(chip->dev, "unable to register pinctrl device\n");
764 return PTR_ERR(chip->pctl);
770 static const struct of_device_id iproc_gpio_of_match[] = {
771 { .compatible = "brcm,iproc-gpio" },
772 { .compatible = "brcm,cygnus-ccm-gpio" },
773 { .compatible = "brcm,cygnus-asiu-gpio" },
774 { .compatible = "brcm,cygnus-crmu-gpio" },
775 { .compatible = "brcm,iproc-nsp-gpio" },
776 { .compatible = "brcm,iproc-stingray-gpio" },
780 static int iproc_gpio_probe(struct platform_device *pdev)
782 struct device *dev = &pdev->dev;
783 struct resource *res;
784 struct iproc_gpio *chip;
785 struct gpio_chip *gc;
786 u32 ngpios, pinconf_disable_mask = 0;
788 bool no_pinconf = false;
789 enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID;
791 /* NSP does not support drive strength config */
792 if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
793 pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH);
794 /* Stingray does not support pinconf in this controller */
795 else if (of_device_is_compatible(dev->of_node,
796 "brcm,iproc-stingray-gpio"))
799 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
804 platform_set_drvdata(pdev, chip);
806 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
807 chip->base = devm_ioremap_resource(dev, res);
808 if (IS_ERR(chip->base)) {
809 dev_err(dev, "unable to map I/O memory\n");
810 return PTR_ERR(chip->base);
813 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
815 chip->io_ctrl = devm_ioremap_resource(dev, res);
816 if (IS_ERR(chip->io_ctrl)) {
817 dev_err(dev, "unable to map I/O memory\n");
818 return PTR_ERR(chip->io_ctrl);
820 if (of_device_is_compatible(dev->of_node,
821 "brcm,cygnus-ccm-gpio"))
822 io_ctrl_type = IOCTRL_TYPE_CDRU;
824 io_ctrl_type = IOCTRL_TYPE_AON;
827 chip->io_ctrl_type = io_ctrl_type;
829 if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
830 dev_err(&pdev->dev, "missing ngpios DT property\n");
834 raw_spin_lock_init(&chip->lock);
839 chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
840 gc->label = dev_name(dev);
842 gc->of_node = dev->of_node;
843 gc->request = iproc_gpio_request;
844 gc->free = iproc_gpio_free;
845 gc->direction_input = iproc_gpio_direction_input;
846 gc->direction_output = iproc_gpio_direction_output;
847 gc->get_direction = iproc_gpio_get_direction;
848 gc->set = iproc_gpio_set;
849 gc->get = iproc_gpio_get;
851 chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
854 /* optional GPIO interrupt support */
855 irq = platform_get_irq(pdev, 0);
857 struct irq_chip *irqc;
858 struct gpio_irq_chip *girq;
860 irqc = &chip->irqchip;
861 irqc->name = dev_name(dev);
862 irqc->irq_ack = iproc_gpio_irq_ack;
863 irqc->irq_mask = iproc_gpio_irq_mask;
864 irqc->irq_unmask = iproc_gpio_irq_unmask;
865 irqc->irq_set_type = iproc_gpio_irq_set_type;
866 irqc->irq_enable = iproc_gpio_irq_unmask;
867 irqc->irq_disable = iproc_gpio_irq_mask;
871 girq->parent_handler = iproc_gpio_irq_handler;
872 girq->num_parents = 1;
873 girq->parents = devm_kcalloc(dev, 1,
874 sizeof(*girq->parents),
878 girq->parents[0] = irq;
879 girq->default_type = IRQ_TYPE_NONE;
880 girq->handler = handle_simple_irq;
883 ret = gpiochip_add_data(gc, chip);
885 dev_err(dev, "unable to add GPIO chip\n");
890 ret = iproc_gpio_register_pinconf(chip);
892 dev_err(dev, "unable to register pinconf\n");
893 goto err_rm_gpiochip;
896 if (pinconf_disable_mask) {
897 ret = iproc_pinconf_disable_map_create(chip,
898 pinconf_disable_mask);
901 "unable to create pinconf disable map\n");
902 goto err_rm_gpiochip;
915 static struct platform_driver iproc_gpio_driver = {
917 .name = "iproc-gpio",
918 .of_match_table = iproc_gpio_of_match,
920 .probe = iproc_gpio_probe,
923 static int __init iproc_gpio_init(void)
925 return platform_driver_register(&iproc_gpio_driver);
927 arch_initcall_sync(iproc_gpio_init);